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U6809B
Fail-Safe IC with Relay Driver and Lamp Driver
Description
The U6809B is designed to support the fail-safe function of a safety-critical system e.g., ABS. It includes a relay driver, two independent short-circuit-protected lamp drivers which are supplied by redundant ground lines, two monitoring circuits of the lamp driver output voltage and output current, a watchdog controlled by an external R/Cnetwork and a reset circuit initiated by an over- and undervoltage condition of the 5-V supply providing a positive and a negative reset signal.
Features
D Digital self-supervising watchdog with hysteresis D Three 250-mA output drivers D One relay driver, two lamp drivers D Lamp drivers with auxiliary ground D Lamp drivers short-circuit protected D Lamp drivers with status feedback D Enable output D Over-/undervoltage detection and reset D All power outputs protected against standard transients D All power outputs protected against 40-V load dump D Automatically activated lamp drivers if VS is disconnected D Automatically activated lamp drivers via AUX GND if standard ground is disconnected
Ordering Information
Extended Type Number U6809B Package SO20 special lead frame Remarks
Block Diagram
VS
LA1I LA2I RELI WDI
Digital input lamp 1 Digital input lamp 2 Digital input relay Digital input wd
Logic Short-circuit detection and temperature monitor
Open-collector 250 mA lamp driver 1 Temperature Open-collector 250 mA lamp driver 2
LA1O
LA2O
Microcontroller
FBLA1 FBLA2
Watchdog
Feedback lamp 1 Feedback lamp 2
Loads
Debouncing of over- and undervoltage detection Oscillator monitoring RC-oscillator
Open-collector 250 mA relay driver
RELO
PRES NRES
p reset n reset
Open-collector 25 mA enable driver
ENO
OSC
GND
AUX GND
13939
Figure 1.
Rev.A1, 08-Feb-00
1 (14)
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Table 1. Pining and circuit description
Pin Description
U6809B
2 (14) 19 20 13 14 10 11 12 9 5, 6 7 8 4 3 2 1 Pin
15, 16, 17 18
VS WDI
LA1O
GND
AUX GND LA2O
FBLA2 OSC ENO
PRES
GND FBLA1 NRES
RELO
LA2I
LA1I
Name RELI
Supply Digital input
Open collector driver output
Supply Open collector driver output Supply
Digital output Analog input Open collector output
Digital output
Open collector driver output Supply Digital output Digital output
Digital input
Digital input
Type Digital input
REL1
GND
RELO
LA2I
LA1I
FBLA2
PRES
NRES
FBLA1
GND
10
8
5
3
1
7
6
4
2
9
U6809B
5 V supply Watchdog trigger signal
Warning lamp driver
Standard ground
Auxiliary ground of lamp drivers Warning lamp driver
Feedback lamp 2 Ext. RC for watchdog timer Watchdog disable output
Positive reset signal
Standard ground Feedback lamp1 Negative reset signal
Fail-safe relay driver
Activation of lamp 2 driver
Activation of lamp 1 driver
Function Activation of relay driver
17 GND
11 OSC
13 AUX GND 12 ENO
14 LA2O
15 GND
18 LA1O
19 VS
20 WDI
16 GND
Pulse sequence
Driver off: --- driver on: L
Driver off: --- driver on: L
Watchdog ok: --- watchdog n ok: L
See table 2 and 3 Reset: L no reset:H Reset: H no reset:L See table 2 and 3
Logic L: driver on H: driver off L: driver off H: driver on L: driver off H: driver on Driver off:--- driver on: L
Rev.A1, 08-Feb-00
U6809B
Detailed Block Diagram with External Components
19 VRef 4 + - Reset delay + - VRef 5 RELI 1 + -
Debouncing
VS
Reset debouncing
Push pull R+ Push pull R-
9
+ PRES
8
- NRES VBatt
A Temperature shut down Push pull L1 VS
4 RELO
7
FBLA1 VBatt
LA1I
2 + -
Failure detection lamp 1
VRef2 + - C VRef3 + - VS 18 LA1O
LA2I
3 + -
Debouncing
VBatt
WDI
20 VRef 1 + - A B C
Failure detection lamp 2 D
VRef2 + - D VRef3 E 14 LA2O
VS
Watchdog Ground backup
GND AUX GND
E
+ -
11 OSC
Oscillator D Integrated oscillator Internal timing C Push pull L2 E 10 FBLA2
Short circuit protection B 12 ENO
5 6 15 16 17 GND
13
95 11304
AUX GND Figure 2.
Rev.A1, 08-Feb-00
3 (14)
U6809B
Table 2. Thruth table for lamp drivers and lamp feedback
Lamp (I)
Inputs Lamp Lamp Voltage Current 1 1 0 0 0 1 1 0 0 1 1 0 1 1 0 0
Lamp Driver Current off on on
Outputs Lamp Current off off on
Feedback Lamp 1 1 0 0 0 1 1 1
Comment
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0 0 0 1 1 1 1 off on on off off on on off off on/off Explanation: Lamp voltage is logic 1 if output voltage u threshold voltage detection Lamp voltage is logic 0 if output voltage t threshold voltage detection Lamp current is logic 1 if output current u threshold current detection Lamp current is logic 0 if output current t threshold current detection
Table 3. Table of fault detection
0
Output ok or open (internal pull up) or shorted to VBatt Output shorted to VBatt and faulty input level Internal driver activated caused by internal failure Output shorted to GND Output ok Output shorted to VBatt Internal driver deactivated caused by internal failure or thermal shutdown Output shorted to GND or open
Condition Normal operation Lamp output shorted to GND Lamp output shorted to VBat Lamp output open Feedback shorted to GND Feedback shorted to Vs Lamp input shorted to GND Lamp input shorted to Vs 1 0 1 1 0 1 1 0
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Fail-Safe Functions
A fail-safe IC has to maintain its monitoring function even if there is a fault condition at one of the pins (e.g. short circuit). This ensures that a microcontroller system would not be brought into a critical status. A critical status is reached if the system is not able to actuate a warning lamp and switch off the relay. The following table shows fault conditions for different pins during which the IC still works as a fail-safe device. 4 (14) Rev.A1, 08-Feb-00
Feedback Lamp Lamp Input is 0 (Lamp off) Lamp Input is 1 (Lamp on) 0 (= detection) 1 (= detection) (= no detection) 1 (= detection) (= no detection) 1 (= detection) (= detection) 0 (= no detection) (= no detection) 1 (= detection) (= no detection) 1 (= detection) (= detection) 0 (= no detection)
U6809B
Table 4. Table of fault conditions
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LA2I LA2O on LA2O on LA2O off LA2O on FBLA2 LA1O Faulty feedback LA1O partly on Faulty feedback LA1O off Faulty feedback LA1O on Faulty feedback LA1O off LA1I LA1O on LA1O on LA1O off LA1O on FBLA1 RELI Faulty feedback Relay off Faulty feedbackAAAAAAA Faulty feedback Faulty feedback Relay off Relay on Relay off WDI OSC Watchdog reset Watchdog reset Watchdog reset Watchdog reset Watchdog reset Watchdog reset Watchdog reset Watchdog reset
Pin LA2O
Function Short-circuit proof driver for warning lamp Digital input to activate warning lamp Digital feedback of warning lamp Short-circuit proof driver for warning lamp Digital input to activate warning lamp Digital feedback of warning lamp Digital input to activate the failsafe relay Watchdog trigger input Capacitor and resistor of watchdog
Short to Vs LA2O partly on
Short to VBat LA2O off
Short to GND LA2O on
Open Circuit LA2O off
Description of the Watchdog
Abstract
a constant frequency for correct operation. The frequency of the trigger signal can be varied in a broad range as the watchdog`s time window is determined by external R/C components. The following description refers to the block diagram (Fig. 2)
The microcontroller is monitored by a digital window watchdog which accepts an incomming trigger signal of
RCOSC
Binary counter
Dual MUX
WDI RESET OSCERR
Slope detector
Up/down counter
RS-FF
WD-OK
13949
Figure 3. Watchdog block diagram
Rev.A1, 08-Feb-00
5 (14)
U6809B
WDI Input (Pin 20)
The microcontroller has to provide a trigger signal with the frequency fWDI which is fed to the WDI input. A positive edge of fWDI detected by a slope detector resets the binary counter and clocks the up/down counter additionally. The latter one counts only from 0 to 3 or reverse. Each correct trigger increments the up/down counter by 1, each wrong trigger decrements it by 1. As soon as the counter reaches status 3 the RS flip-flop is set; see Fig. 4 (Watchdog state diagram). A missing incoming trigger signal is detected after 250 clocks of the internal watchdog frequency fRC (see WD-OK output) and resets the up-/down counter directly.
Watchdog State Diagram
Initial status bad bad O/F bad good 1/F good Figure 4. Watchdog state diagram bad 2/F good good 1/NF bad bad 3/NF 2/NF good good
RCOSC Input
With an external R/C circuitry the IC generates a time base (frequency fRC) independent from the microcontroller. The watchdog`s time window refers to a frequency of fRC = 100 fWDI
Explanation In each block, the first character represents the state of the counter. The second notation indicates the fault status of the counter. A fault status is indicated by an "F" and a no fault status is indicated by an "NF". When the watchdog is powered up initially, the counter starts out at the 0/F block (initial state). "good" indicates that a pulse has been received whose width resides within the timing window. "bad" indicates that a pulse has been received whose width is either too short or too long.
Reset Input
During power-on and under-/overvoltage detection a reset signal is fed to this pin. It resets the watchdog timer and sets the initial state. During power on and under/overvoltage detection a reset signal is fed to this pin. It resets the watchdog timer and sets the initial state.
Watchdog-Window Calculation
Example with recommended values Cosc = 3.3 nF (should be preferably 10%, NPO) Rosc= 39 kW (may be 5%, Rosc <100 kW due to leakage current and humidity)
WD - OK Output
After the up/down counter is incremented to status 3 (see Fig. 4, WD state diagram) the RS flip-flop is set and the WD-OK output becomes logic "1". This information is available for the microcontroller at the open collector output ENO. If on the other hand the up/down counter is decremented to 0 the RS flip flop is reset, the WD OK output and the ENO output are disabled. The WD OK output also controls a dual MUX stage which shifts the time window by one clock after a successful trigger thus forming a hysteresis to provide stable conditions for the evaluation of the trigger signal "good or false". The WD OK signal is also reset in the case the watchdog counter is not reset after 250 clocks (missing trigger signal).
RC Oscillator tWDC (s) = 10-3 [Cosc (nF) 0.0005]] fWDC (Hz) = 1 / (tWDC) Watchdog WDI fWDI (Hz) =0.01 tWDC = 100 ms fWDI = 100 Hz fWDC -> fWDC = 10 kHz -> tWDI = 10 ms [(0.00078 Rosc (kW)) +
6 (14)
Rev.A1, 08-Feb-00
U6809B
WDI pulse width for fault detection after 3 pulses: Upper watchdog window Minimum: 169/ fWDC = 16.9 ms -> fWDC / 169 = 59.1 Hz Maximum: 170/ fWDC = 17.0 ms -> fWDC / 170 = 58.8 Hz Lower watchdog window Minimum: 79/ fWDC = 7.9 ms -> fWDC / 79 = 126.6 Hz Maximum: 80/ fWDC = 8.0 ms -> fWDC / 80 = 125.0 Hz WDI dropouts for immediate fault detection: Minimum: Maximum: 250/ fWDC = 25 ms 251/ fWDC = 25.1 ms
Time/s
79/ fWDC
80/ fWDC
169/ fWDC
170/ fWDC
250/ fWDC
251/ fWDC
Watchdog window update rate is good
Update rate is too fast Update rate is either too fast or good Update rate is ei- Update rate ther too slow or is too slow good Update rate is Pulse has either too dropped out slow or pulse has dropped out
Figure 5. Watchdog timing diagram with tolerances
Remark to reset delay The duration of the over- or undervoltage pulses determines the enable- and reset output. A pulse duration shorter than the debounce time has no effect on the
outputs. A pulse longer than the debounce time results in the first reset delay. If a pulse appears during this delay, a 2nd delay time is triggered. Therefore, the total reset delay time can be longer than specified in the data sheet.
Absolute Maximum Ratings
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Rev.A1, 08-Feb-00 7 (14)
Parameters Supply voltage range AUX GND offset voltage to GND AUX GND offset current to GND Power dissipation VS = 5 V; Tamb = 125C Thermal resistance Junction temperature Ambient temperature range Storage temperature range
Symbol VS VAUX IAUX Ptot Rthjc Tj Tamb Tstg
Value - 0.2 to 16 +/- 1.5 - 600 700 25 150 -40 to 125 -55 to 155
Unit V V mA mW K/W C C C
U6809B
Electrical Characteristics
VS = 5 V, Tamb = -40 to + 125C; reference pin is GND; fintern = 100 kHz "50% , fWDC = 10 kHz "10%; fWDI = 100 Hz Parameters Supply voltage Operation range general Operation range reset Supply current Lamp driver on, relay off Test Conditions / Pins Symbol VS VS Min. 4.5 1.5 Typ. Max. 5.5 16.0 40 35 25 20 15 10 -1.2 -0.65 -0.5 -1.7 1.2 1.0 0.8 3.0 Unit V V mA mA mA mA mA mA V V V V
Tamb = - 40C Tamb = 125C Lamp driver off, relay on Tamb = - 40C Tamb = 125C Lamp driver off, relay off Tamb = - 40C Tamb = 125C Auxiliary ground (AUX GND) AUX GND offset voltage Tamb = - 40C operation range Tamb = 90C Tamb = 125C AUX GND offset voltage IAUX = - 600 mA to GND Digital inputs (LA1I, LA2I, REL1 and WDI) Detection low Detection high Resistance to VS Input current low Input voltage = 0 V Input current high Input voltage = VS Digital outputs; lamp driver feedbacks (FBLA1, FBLA2) Voltage low I v 1.6 mA Voltage high I v 10 A 10 A v I v 1.6mA Threshold voltage detection Threshold current detection Digital outputs (PRES and NRES) Voltage high I v 100A Voltage low I v 1 mA Digital output (ENO) with open collector Saturation voltage low I v 25 mA Clamping voltage Current limit low Leakage current VENO = 5 V VENO = 16 V VENO = 26 V
-0.2 0.7 VS 10 100 -5 0
0.8 VS 0.7 VS + 0.1
0.2
VS
VS+0.5 V
40 550 5 0.5 VS VS 0.5 VS 50 VS 0.3 0.3 30 20 100 200
V V kW mA mA V V V V mA V V V V mA mA mA mA
0.4 VS 10 0.7 VS+0.1 0 0 26 25
8 (14)
Rev.A1, 08-Feb-00
U6809B
Parameters Test Conditions / Pins Symbol Lamp drivers (LA1O and LA2O) with integrated pull-up resistor Saturation voltage I v 125 mA; VS = 5 V I v 125 mA; VS = 0 V Saturation voltage I v 250 mA; VS = 5 V 250mA requires enhanced I v 250 mA; VS = 0 V heat sink I v 250 mA; no GND Maximum load current Tamb = 90C Tamb = 125C Clamping voltage Leakage current VLA1O, LA2O = 16 V VLA1O, LA2O = 26 V Threshold current limitation Pull-up resistor Relay driver (RELO) Saturation voltage I v 250 mA Maximum load current Tamb = 90C Tamb = 125C Clamping voltage Leakage current VBat = 16 V VBat = 26 V Reset and VS control Lower reset level VS Upper reset level VS Hysteresis Reset debounce time Reset delay Watchdog timing Feedback reaction time no fault, tFB (FBLA1, FBLA2) edge at LA1I, LA2I Minimum lamp input no fault, tP,FB toggle time for a securely pulse at LA1I, LA2I feedback reaction Power-on-reset prolongatPOR tion time Detection time for VRC = const. tRCerror RC-oscillator fault Time interval for over-/ tD,OUV under voltage detection Reaction time of NRES tR,OUV output on over-/under voltage Minimum toggle time for a tP,BGND securely broken ground detection Maximum reaction time for tR,BGND broken ground detection Nominal frequency for fRC = 100 fWDI fWDI WDI Nominal frequency for RC fWDI = 1/100 fRC fRC Min. Typ. Max. 0.5 1.5 1.0 2.0 3.0 250 180 26 Unit V V V V V mA mA V mA mA A kW V mA mA V mA mA V V mV ms ms ms ms
0.5 2
30 1 3 1.0 17 0.5
250 200 26
30 20 200 4.8 5.5 500 80 12.8
4.5 5.2 25 120 20 2.56 10.24
34 .3 81.9 0.16 0.187
103.1 246 0.64 0.72
ms ms ms ms s s Hz kHz
13.3
100 10 1 500 50
Rev.A1, 08-Feb-00
9 (14)
U6809B
Parameters Test Conditions / Pins Minimum pulse duration for a securely WDI input pulse detection Frequency range for a correct WDI signal Number of incorrect WDI trigger counts for locking the outputs Number of correct WDI trigger counts for releasing the outputs Detection time for a VWDI = const. stucked WDI signal Watchdog timing relative to fRC Minimum pulse duration for a securely WDI input pulse detection Frequency range for a correct WDI signal Hysteresis range at the WDI ok margins Detection time for a VWDI = const. stucked WDI signal Symbol tP,WDI Min. 182 Typ. Max. Unit s
fWDI nlock
64.7 3
112.5
Hz
nrelease
3
tWDIerror
24.5
25.5
ms
2
cycles
80 1 250
170
cycles cycle
251
cycles
Protection against transient voltages according to ISO TR 7637-3 level 4 (except pulse 5)
Pulse 1 2 3a 3b 5 Voltage - 110 V + 110 V - 160 V + 150 V 40 V
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100 V/s 100 V/s 30 V/ns 20 V/ns 10 V/ms 2 ms 0.05 ms 0.1 s 0.1 s 250 ms 15.000 15.000 1h 1h 20 * Lamp drivers: Relay driver: 1.2 W lamps to be added to the source resistance relay coil with Rmin = 70 W to be added to the source resistance.
Source Resistance * 10 W 10 W 50 W 50 W 2W
Rise Time
Duration
Amount
Application Hints
a.) The lamp output pins LA1O and LA2O may need to be protected by external protection diodes against reversed battery (e.g. BAV 202) in order to avoid a reset during negative pulses. b.) If pilot lamps with a wattage of P > 1.2 W are connected external Zener diodes are mandatory.
10 (14)
Rev.A1, 08-Feb-00
U6809B
Timing Diagrams
Normal operation 5V WDI 0V V Batt RELO 0V 5V ENO 0V V Batt LAXO 0V Don't care
13940
WDI too fast
Normal operation
Figure 6. Watchdog in too fast condition
Normal operation 5V WDI 0V V Batt RELO 0V 5V ENO 0V V Batt LAXO 0V
WDI too low
Normal operation
Don't care
13941
Figure 7. Watchdog in too slow condition
Rev.A1, 08-Feb-00
11 (14)
U6809B
Overvoltage condition > 120 ms w5.5 V 5V VS 0V V Batt RELO 0V 5V ENO 0V 5V NRES 0V V Batt LAXO 0V Reset debounce time 1st Reset delay 2nd Reset delay
13942
t 120 ms
w5.5 V
3 good WDI pulses
Don't care
Figure 8. Overvoltage condition
Undervoltage condition 5V VS 0V V Batt RELO 0V 5V ENO 0V 5V NRES 0V V Batt LAXO 0V Reset debounce time 1st Reset delay
> 120 ms
t 120 ms v4.5 V
v4.5 V
3 good WDI pulses
Don't care
2nd Reset delay
13943
Figure 9. Undervoltage condition
12 (14)
Rev.A1, 08-Feb-00
U6809B
Package Information
Package SO20
Dimensions in mm
12.95 12.70 9.15 8.65 7.5 7.3
2.35
0.4 1.27 11.43 20 11
0.25 0.10 10.50 10.20
0.25
technical drawings according to DIN specifications 13038
1
10
Rev.A1, 08-Feb-00
13 (14)
U6809B
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify TEMIC Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Data sheets can also be retrieved from the Internet: http://www.temic-semi.com
TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423
14 (14)
Rev.A1, 08-Feb-00

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