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ILX523A
2700 pixel CCD Linear Sensor (B/W)
Description The ILX523A is a reduction type CCD linear sensor designed for facsimile, scanner and OCR use. This sensor reads A3 size documents at a density of 200 DPI (Dot Per Inch). In addition, this can be directly driven at 5V logic and operate on single 12V power supply for easy use. Features * Number of effective pixels: 2700 pixels * Pixel size: 11m x 11m (11m pitch) * Ultra low lag/High Sensitivity * Built-in Feed through suppression circuit * Built-in Sample-and-hold circuit * Maximum data rate: 5MHz * Single 12V power supply Absolute Maximum Ratings 15 * Supply voltage VDD * Operating temperature -10 to +60 * Storage temperature -30 to +80 Pin Configuration (Top View) 22 pin DIP (Cer-DIP)
Block Diagram
Timing Generator
Read Out gate CCD Analog Shift Register
VOUT 1 VSS 2 NC 3 S/H 4 NC 5 NC 6 NC 7 NC 8 1 9 NC 10 ROG 11 2700 1
22 NC 21 NC 20 VDD RS 19 T1 18 RS 17 NC 16 NC T1 15 NC 14 2 13 NC 12 NC 19 Timing Generator 18
* Output Amplifier * Sample-and-Hold Circuit * Feed Through Level Clamp Circuit
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
S/H
4
E97442A78
VOUT
1
GND
2
VDD
20
D33 S1 S2
V C C
14
2
1
9
ROG
11
S2699 S2700 D34
D39 D14 D15
ILX523A
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 Symbol VOUT GND NC S/H NC NC NC NC 1 NC ROG Description Signal output GND NC Sample-and-Hold pulse NC NC NC NC Transfer pulse 1 NC Read out gate pulse Pin No. 12 13 14 15 16 17 18 19 20 21 22 Symbol NC NC 2 NC NC NC RS T1 VDD NC NC NC NC Transfer pulse 2 NC NC NC Reset gate pulse Test pin (Open) 12V power supply NC NC Description
Note) Connect Pin 4 to GND when not using internal sample-and-hold circuit.
Recommended Pin Voltage Item VDD Min. 11.4 Typ. 12.0 Max. 12.6 Unit V
Clock Characteristics Item Input capacitance of 1 Input capacitance of 2 Input capacitance of ROG Input capacitance of RS Input capacitance of S/H Data Rate Symbol C1 C2 CROG CRS CS/H -- Min. -- -- -- -- -- -- Typ. 300 300 10 10 10 1.0 Max. -- -- -- -- -- 5.0 Unit pF pF pF pF pF MHz
-2-
ILX523A
Electrooptical Characteristics (Ta = 25C, VDD = 12V, data rate = 1MHz, mode without S/H (Pin 4 = GND), light source = 3200K, IR cut filter CM-500S (t = 1.0mm) used) Item Sensitivity Sencitivity nonuniformity Saturation output voltage Dark voltage average Dark signal nonuniformity Image Lag Dynamic range Saturation exposure Supply current Total transfer efficiency Output impedance Offset level Symbol R1 PRNU VSAT VDRK DSNU IL DR SE IVDD TTE ZO VOS Min. 66.5 -- 2.0 -- -- -- -- -- -- 92.0 -- -- Typ. 95 2.0 2.5 2.0 7.0 0.02 1250 0.02 15.0 98.0 300 7.4 Max. 123.5 10.0 -- 8.0 14.0 -- -- -- 25.0 -- -- -- Unit V/(lx * s) % V mV mV % -- lx * s mA % V Remarks Note 1 Note 2 -- Note 3 Note 3 Note 4 Note 5 Note 6 -- -- -- Note 7
Notes) 1. For the sensitivity test, light is applied with a uniform intensity of illumination. 2. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 1. The output signal amplitude for test is 1V. PRNU = (VMAX - VMIN)/2 VAVE x 100 [%]
The maximum output of all the valid pixels is set to VMAX, the minimum output to VMIN and the average output to VAVE. 3. Optical signal accumulated time stands at 10ms. 4. Output signal amplitude VOUT = 500mV. 5. Dynamic range is defined as follows. DR = VSAT VDRK
When the optical signal accumulated time is shorter, the dynamic range gets wider because the optical signal accumulated time is in proportion to the dark voltage. 6. Saturation exposure is defined as follows. SE = VSAT R1
7. VOS is defined as indicated below.
VOUT D29 D30 D31 D32 D33 S1
VOS
GND
-3-
Clock Timing Diagram (without internal sample-and-hold circuit)
5
ROG
0
5
2739
1
23
4
5
6
1
2
1
0
5
2
0
D33
D4
D13
D32
S2
S2699
D35
D3
D6
D12
D15
D31
S1
S4
S2698
D34
D37
D38 D36
D1
D2
D5
D11
D14
VOUT
Optical black (18 pixels) Effective picture elements signal Dummy signal (6 pixels) (2700 pixels)
Dummy signal (33 pixels)
1-line output period (2739 pixels) ILX523A Note) 2750 or more clock pulses (1, 2, RS) are required.
S3
S2697
S2700
D39
-4-
5
RS
0
Clock Timing Diagram (using internal sample-and-hold circuit)
5
ROG
0
5
2739
1
1
2
3
4
5
6
1
2
0
5
2
0
5
S3
D1
D4
D13
D33
S2699
S2
D32
S2698
D34
D37
D3
D6
D12
D15
S1
S4
D2
D5
D11
D14
D31
S2697
S2700
D36
VOUT Optical black (18 pixels) Dummy signal (33 pixels) Effective picture elements signal Dummy signal (6 pixels) (2700 pixels)
1-line output period (2739 pixels)
ILX523A
Note) 2750 or more clock pulses (1, 2, RS, S/H) are required.
D35
D38
D39
-5-
RS
0
5
S/H
0
ILX523A
Input Clock Waveform Conditions 1, 2, RS, S/H pulses related
t1 5V 1 0V 10% 90% t2
5V 2 0V t4 5V RS 0V
90% 10% t5 90% 50% 10% t3 t8 t9 90% 50% 10% t7 t10 t11 t6
5V S/H 0V
VOUT (without internal sample-and-hold circuit) t13
10%
t12
t19 VOUT (using internal sample-and-hold circuit)
ROG, 1 pulses related
t17 5V ROG 0V 10% t16 5V 1 0V 50% 90% 50% t14
t18
t15
-6-
ILX523A
Cross point 1 and 2
1
5V 2.0V (Min.) 0V 2.0V (Min.)
2
Input Clock Waveform Conditions Item 1, 2 rise/fall time RS pulse low level period 1, 2 - RS pulse timing RS rise/fall time S/H pulse low level period 1, 2 - S/H pulse timing RS - S/H pulse timing S/H rise/fall time Symbol t1, t2 t3 t4 t5, t6 t7 t8 t9 t10, t11 t12 Signal output delay time ROG pulse high level period 1 - ROG pulse timing ROG rise/fall time Inpuyt clock pulse voltage High level Low level t13 t19 t14 t15, t16 t17, t18 Min. 0 20 25 0 20 70 15 0 -- -- -- 500 500 0 4.5 0 Typ. 50 801 2001 10 801 2001 -- 10 40 20 20 1000 1000 50 5 -- Max. 100 200 350 40 200 350 -- 40 -- -- -- -- -- 100 5.5 0.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns V V
1 Recommended conditions for data rate = 1MHz.
-7-
Application Circuit
5V
12V
10/16V 0.01 10/16V
0.01
74HC04
RS 22 20 21 19 18 17 16 15 14 13 12
T1
2
NC
NC
NC
VDD
1
S/H
NC
VOUT
NC
NC
GND
NC
2 1 2 3 4 5 6
NC
7
1
8
9
10
NC
Connect Pin 4 to GND or ROG when not using internal sample-and-hold circuit. 2SC2785
Output signal 10k
ILX523A
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
ROG
11
-8-
ROG
RS
NC
NC
NC
NC
S/H
ILX523A
Example of Representative Characteristics (VDD = 12V, Ta = 25C)
Spectral sensitivity characteristics (Standard characteristics)
10 9 8 7
Relative sensitivity
6 5 4 3 2 1 0 400
500
600
700 Wavelength [nm]
800
900
1000
Dark signal output temperature characteristics (standard characteristics)
100 50
10
Output voltage rate
5
1 0.5
0.1 0.05
0.01 -10
0
10
20
30
40
50
60
Ta - Ambient temperature [C]
-9-
ILX523A
Offset level vs. Temperature characteristics (Standard characteristics)
12 12
Offset level vs. VDD characteristics (Standard characteristics)
10
10
VOS - Offset level [V]
8 Vos Ta
VOS - Offset level [V]
8
6
-5mV/ C
6 Vos VDD 4 0.8
4
2 0 -10
2 0 11.4
0
10
20
30
40
50
60
11.6
11.8
12.0 VDD [V]
12.2
12.4
12.6
Ta - Ambient temperature [C]
Supply current vs. VDD characteristics (Standard characteristics)
20 10
Output voltage vs. Integration time (Standard characteristics)
IvDD - Supply current [mA]
15
10
5
Output voltage rate
11.4 11.6 12.2 12.4 12.6
5
0 11.8 12.0 VDD [V]
1 10 50 - Integration time [ms] 100
- 10 -
ILX523A
Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for prevention of static charges. 2) Notes on Handling CCD Cer-DIP Packages The following points should be observed when handling and installing Cer-DIP packages. a) Remain within the following limits when applying static load to the ceramic portion of the package: (1) Compressive strength: 39N/surface (Do not apply load more than 0.7mm inside the outer perimeter of the glass portion.) (2) Shearing strength: 29N/surface (3) Tensile strength: 29N/surface (4) Torsional strength: 0.9Nm
Upper ceramic layer 39N 29N 29N 0.9Nm
Lower ceramic layer
(1)
Low-melting glass
(2)
(3)
(4)
b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive. c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic layers are shielded by low-melting glass, (1) Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with soldering iron. (3) Rapid cooling or heating. (4) Rapid cooling or impact to a limited portion of the low-melting glass with a small-tipped tool such as tweezers. (5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. 3) Soldering a) Make sure the package temperature does not exceed 80C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an imaging device, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. - 11 -
ILX523A
4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. 7) Normal output signal is not obtained immediately after device switch on.
- 12 -
Package Outline
Unit: mm
22pin DIP (400mil)
41.6 0.5 12
22
5.0 0.5
1 40.2
11
4.0 0.5
2.54 0.3
M
0.51
PACKAGE STRUCTURE
PACKAGE MATERIAL
Cer-DIP
LEAD TREATMENT
TIN PLATING
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
5.2g
3.65 4.45 0.5
- 13 -
1. The height from the bottom to the sensor surface is 2.45 0.3mm. 2. The thickness of the cover glass is 0.8mm, and the refractive index is 1.5.
(AT STAND OFF) 10.16
0.25
H
No.1 Pixel
10.0 0.5
V
9.0
0 to 9
6.73 0.8
29.7 (11m x 2700Pixels)
ILX523A

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