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ILX526A 3000-pixel CCD Linear Image Sensor (B/W) Description The ILX526A is a rectangular reduction type CCD linear image sensor designed for bar code POS hand scanner and optical measuring equipment use. A built-in timing generator and clock-drivers ensure single 5V power supply for easy use. Features * Number of effective pixels: 3000 pixels * Pixel size: 7m x 200m (7m pitch) * Single 5V power supply * High sensitivity: 300V/(lx * s) * Built-in timing generator and clock-drivers * Built-in sample-and-hold circuit * Electrical shutter function * Clock frequency: 100kHz (Min), 1MHz (Max) Absolute Maximum Ratings * Supply voltage VDD * Operating temperature * Storage temperature 22 pin DIP (Cer-DIP) Internal Structure GND 8 Readout gate pulse generator Shutter pulse generator VDD 9 Clock pulse generator VDD 14 CCD analog shift register Readout gate Clock-drivers Clock-drivers Pin Configuration (Top View) VDD 22 Readout gate CCD analog shift register Vgg 1 CLK 2 NC 3 NC 4 NC 5 ROG 6 SHUT 7 GND 8 VDD 9 T1 10 NC 11 3000 1 22 VDD 21 21 GND 20 VOUT 19 NC 18 NC 17 NC 16 NC 15 NC GND Vgg 13 GND 12 S/HSW Output Amplifier S/H circuit 14 VDD 1 10 12 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- VOUT 20 E97803-PS S/HSW T1 CLK S2999 S3000 D56 2 D54 D55 S1 S2 S3 D24 D25 D65 6 -10 to +60 -30 to +80 V C C GND 13 ROG 6 SHUT 7 ILX526A Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Symbol Vgg CLK NC NC NC ROG SHUT GND VDD T1 NC S/HSW GND VDD NC NC NC NC NC VOUT GND VDD Output circuit gate bias Clock pulse input NC NC NC Readout gate pulse input Electrical Shutter pulse input GND 5V TEST NC Switch (with S/H or without S/H) GND 5V NC NC NC NC NC Signal output GND 5V Description Mode Description Mode in Use With S/H Without S/H 12 pin S/HSW GND VDD Recommended Voltage Item VDD Min. 4.5 Typ. 5.0 Max. 5.5 Unit V Input Pin Capacity Item Input capacity of CLK pin Input capacity of ROG pin Input capacity of SHUT pin Symbol CCLK CROG CROG Min. -- -- -- -2- Typ. 10 10 10 Max. -- -- -- Unit pF pF pF ILX526A Electro-optical Characteristics (Note 1) Ta = 25C, VDD = 5V, Clock frequency: 500kHz, Light source = 3200K, IR cut filter: CM-500S (t = 1.0mm), Without S/H mode Item Sensitivity 1 Sensitivity 2 Sensitivity nonuniformity Saturation output voltage Dark voltage average Dark signal nonuniformity Image lag Dynamic range Saturation exposure 5V current consumption Total transfer efficiency Output impedance Offset level Symbol R1 R2 PRNU VSAT VDRK DSNU IL DR SE IVDD TTE ZO VOS Min. 210 -- -- 0.6 -- -- -- -- -- -- 92.0 -- -- Typ. 300 3700 5.0 0.8 2.5 5.0 5.0 320 0.003 7.0 97.0 250 2.5 Max. 390 -- 10.0 -- 6.0 12.0 -- -- -- 17.0 -- -- -- Unit V/(lx * s) V/(lx * s) % V mV mV % -- lx * s mA % V Remarks Note 2 Note 3 Note 4 -- Note 5 Note 6 Note 7 Note 8 Note 9 -- -- -- Note 10 Note) 1. In accordance with the given electrooptical characteristics, the even black level is defined as the average value of D24, D26 to D52. The odd black level is defined as the average value of D25 , D27 to D53. 2. For the sensitivity test light is applied with a uniform intensity of illumination. 3. Light source: LED = 660nm 4. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2. PRNU = (VMAX - VMIN)/2 VAVE x 100 [%] 5. 6. 7. 8. Where the 3000 pixels are divided into blocks of even and odd pixels, respectively, the maximum output of each block is set to VMAX, the minimum output to VMIN and the average output to VAVE. Integration time is 10ms. The difference between the maximum and average values of the dark output voltage is calculated for even and odd respectively. Integration time is 10ms. Typical value is used for clock pulse and readout pulse. VOUT = 500mV. VSAT DR = VDRK When optical integration time is shorter, the dynamic range sets wider because dark voltage is in proportion to optical integration time. VSAT 9. SE = R1 10. Vos is defined as indicated below. VOUT D51 D52 D53 D54 D55 S1 VOS GND -3- Clock Timing Diagram (With S/H mode) 5 ROG 0 5 SHUT 0 0 1 5 CLK 0 -1 2 D1 D23 S1 S2 D3 D53 S4 D21 S2998 D56 D61 D55 S2999 D64 D58 D60 D57 D59 D62 D0 D2 D24 D4 D22 D54 S3 S2997 S3000 VOUT Optical black (30 pixels) Dummy signal (55 pixels) Effective picture elements signal (3000 pixels) Dummy signal (10 pixels) 1-Line output period (3066 pixels) 3100 or more clock pulses are required. D63 D65 -4- ILX526A Clock Timing Diagram (Without S/H mode) 5 ROG 0 5 SHUT 0 2 0 5 CLK 0 -1 1 S2997 D57 D59 D23 S1 D2 S2 D61 D63 D56 D52 D21 S2998 D4 D53 D55 S2999 D64 D58 D60 D0 D1 D24 D3 D22 S3 D54 VOUT Optical black (30 pixels) Dummy signal (55 pixels) S3000 Effective picture elements signal (3000 pixels) Dummy signal (10 pixels) 1-Line output period (3066 pixels) 3100 or more clock pulses are required. D62 D65 -5- ILX526A ILX526A Input Clock Voltage Condition Item VIH VIL Min. 4.5 0.0 Typ. VDD -- Max. 5.5 0.1 Unit V V This is applied to the all external pulses. (CLK, ROG, SHUT) CLK Timing (For all modes) t1 CLK t2 t3 t4 Item CLK pulse rise/fall time CLK pulse Duty1 1 100 x t4/ (t3 + t4) Symbol Min. 0 Typ. 10 50 Max. 100 60 Unit ns % t1, t2 -- 40 ROG, CLK Timing ROG t6 t7 t8 CLK t5 t9 Item ROG, CLKpulse timing 1 ROG, CLKpulse timing 2 ROG pulse rise/fall time ROG pulse period Note) is the period of CLK. Symbol Min. (1/8) (1/8) 0 6 Typ. (1/4) (1/4) 10 10 Max. (3/8) (3/8) 100 20 Unit ns ns ns ns t5 t9 t6, t8 t7 -6- ILX526A SHUT, CLK Timing SHUT t11 t12 t13 CLK t14 t15 Item SHUT pulse rise/fall time SHUT pulse period SHUT, CLK pulse timing 1 SHUT, CLK pulse timing 2 Symbol Min. 0 4000 150 150 Typ. 10 5000 200 200 Max. 100 -- 250 250 Unit ns ns ns ns t11, t13 t12 t14 t15 ROG, SHUT Timing ROG t16 t17 SHUT Item ROG, SHUT pulse timing Symbol Min. 10 Typ. -- Max. -- Unit ns t16, t17 -7- ILX526A CLK-VOUT Timing 1 2 CLK t18 VOUT3 t19 VOUT Item CLK-VOUT output delay time1 CLK-VOUT output delay time2 Symbol Min. -- -- Typ. 230 210 Max. -- -- Unit ns ns t18 t19 1 fck = 500kHz, CLK Duty = 50%, CLK rise/fall time = 10ns 2 is data period 3 Using internal sample-and-hold circuit Application Circuit (Without S/H mode (Note)) 5V 0.01 22/10V 3k 1 Vgg VDD 22 GND 21 VOUT 20 NC 19 NC 18 NC 17 NC 16 NC 15 VDD 14 GND 13 S/HSW 12 2 CLK 3 NC CLK 4 NC 5 NC 6 ROG 7 ROG SHUT 8 SHUT GND 2SA1175 9 VDD 10 T1 11 NC Note) This circuit diagram is the case when internal S/H is not used. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. -8- ILX526A Example of Representative Characteristics (VDD = 5V, Ta = 25C) Spectral sensitivity characteristics (Standard characteristics) 10 9 8 Relative sensitivity 7 6 5 4 3 2 1 0 400 500 600 700 Wavelength [nm] 800 900 1000 Dark signal output temperature characteristics (Standard characteristics) 10 5 Output voltage rate 1 0.5 0.1 0.05 0.01 -10 0 10 20 30 40 50 60 Ta - Ambient temperature [C] -9- ILX526A Offset level vs. Temperature characteristics (Standard characteristics) 5 VOS Ta 4 -2.1mV/C 4 5 Offset level vs. VDD characteristics (Standard characteristics) Ta = 25C VOS - Offset level [V] 3 VOS - Offset level [V] 3 2 2 1 1 VOS VDD 0.49 5.5 0 -10 0 10 20 30 40 50 60 0 4.5 5 VDD [V] Ta - Ambient temperature [C] Supply current vs. VDD characteristics (Standard characteristics) 14 Ta = 25C 12 10 Output voltage vs. Integration time (Standard characteristics) IVDD - Supply current [mA] 8 6 4 2 0 4.5 Output voltage rate 10 5 5 VDD [V] 5.5 1 10 50 - Integration time [ms] 100 - 10 - ILX526A Notes of Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for prevention of static charges. 2) Notes on Handling CCD Cer-DIP Packages The following points should be observed when handling and installing cer-DIP packages. a) Remain within the following limits when applying static load to the ceramic portion of the package: (1) Compressive strength: 39N/surface (Do not apply load more than 0.7mm inside the outer perimeter of the glass portion.) (2) Shearing strength: 29N/surface (3) Tensile strength: 29N/surface (4) Torsional strength: 0.9Nm Upper ceramic layer 39N 29N 29N 0.9Nm Lower ceramic layer (1) Low-melting glass (2) (3) (4) b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive. c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic layers are shielded by low-melting glass, (1) Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with soldering iron. (3) Rapid cooling or heating. (4) Applying a load or impact to a limited portion of the low-melting glass with a small-tipped tool such as tweezers. (5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. 3) Soldering a) Make sure the package temperature does not exceed 80C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an imaging device, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. - 11 - ILX526A 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. 7) Normal output signal is not obtained immediately after device switch on. - 12 - Package Outline Unit: mm 22pin DIP (400mil) 32.0 0.5 22 12 9.0 5.0 0.5 1 4.0 0.5 2.7 2.54 0.51 3.4 0.5 - 13 - 0.3 M 1. The height from the bottom to the sensor surface is 1.61 0.3mm. 2. The thickness of the cover glass is 0.7mm, and the refractive index is 1.5. PACKAGE STRUCTURE PACKAGE MATERIAL Cer-DIP LEAD TREATMENT TIN PLATING LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 3.0g ILX526A 0.25 30.6 11 (AT STAND OFF) H No.1 Pixel 10.0 0.5 V 10.16 0 to 9 5.5 0.8 21.0 (7m x 3000Pixels) |
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