View STV6889_248164.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

STV6889
HIGH-END IC CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR
PRODUCT PREVIEW
FEATURES General * Advanced I2C-bus controlled deflection processor dedicated for high-end CRT monitors * Single supply voltage 12V * Very low jitter * DC/DC converter controller * Advanced EW drive * Advanced asymmetry corrections * Automatic multistandard synchronization * Vertical dynamic correction waveform output * X-ray protection and Soft-start & stop on horizontal and DC/DC drive outputs * I2C-bus status register Horizontal section * 150 kHz maximum frequency * Corrections of geometric asymmetry: Pin cushion asymmetry, Parallelogram, separate Top/Bottom corner asymmetry * Tracking of asymmetry corrections with vertical size and position * Fully integrated horizontal moire cancellation Vertical section * 200 Hz maximum frequency * Vertical ramp for DC-coupled output stage with adjustments of: C-correction, S-correction for super-flat CRT, Vertical size, Vertical position * Vertical size and position prescales for factory adjustment * Vertical moire cancellation through vertical ramp waveform * Compensation of vertical breathing with EHT variation; I2C-bus gain adjustment EW section * Symmetrical geometry corrections: Pin cushion, Keystone, Top/Bottom corners separately, Sand W-corrections * Horizontal size adjustment * Tracking of EW waveform with Vertical size and position, horizontal size and frequency
* Compensation of horizontal breathing with EHT variation, I2C-bus gain adjustment Dynamic correction section * Generates vertical waveform for dynamic corrections like focus, brightness uniformity, ... * 1 output with vertical dynamic correction waveform, both polarities, tracking with vertical size and position DC/DC controller section * Step-up and step-down conversion modes * External sawtooth configuration * I2C-bus-controlled output voltage * Synchronized on hor. frequency with phase selection * Selectable polarity of drive signal * Protection at H unlock condition DESCRIPTION The STV6889 is a monolithic integrated circuit assembled in a 32-pin shrink dual-in-line plastic package. This IC controls all the functions related to horizontal and vertical deflection in multimode or multi-frequency computer display monitors. Combined with other ST components dedicated for CRT monitors (microcontroller, video preamplifier, video amplifier, OSD controller), the STV6889 allows fully I2C bus-controlled computer display monitors to be built with a reduced number of external components.
SDIP 32 (Shrink DIP package) ORDER CODE: STV6889
Version 1.1 May 2004
This is preliminary information on a new product now in development. Details are subject to change without notice.
1/56
1
Table of Contents
1 2 3 4 5 6 PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PIN FUNCTION REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 QUICK REFERENCE DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ELECTRICAL PARAMETERS AND OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . 9 6.1 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.2 Supply and Reference voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.3 Synchronization inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.4 Horizontal section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.5 Vertical section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.6 EW drive section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.7 Dynamic correction outputs section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.8 DC/DC controller section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.9 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 8 9 TYPICAL OUTPUT WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 IC-BUS CONTROL REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 OPERATING DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.1 Supply and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.1.1 Power supply and voltage references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.1.2 IC-bus control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.2 Synchronization processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.2.1 Synchronization signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.2.2 Sync. presence detection flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.2.3 MCU controlled sync. selection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.2.4 Automatic sync. selection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.3 Horizontal section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.3.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.3.2 PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.3.3 Voltage controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . . . 33 . 9.3.4 PLL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2/56
1
STV6889
9.3.5 Dynamic PLL2 phase control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.3.6 Output Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.3.7 Soft-start and soft-stop on H-drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.3.8 Horizontal moire cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.4 Vertical section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.4.2 S and C corrections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.4.3 Vertical breathing compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.4.4 Vertical after-gain and offset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.4.5 Vertical moire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.4.6 Biasing of vertical booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.5 EW drive section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.6 Dynamic correction outputs section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.6.1 Vertical dynamic correction output VDyCor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.7 DC/DC controller section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.7.1 Synchronization of DC/DC controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.7.2 Soft-start and soft-stop on B-drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.8 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.8.1 Safety functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.8.2 Composite output HLckVBk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10 INTERNAL SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 12 GLOSSARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3/56
1
STV6889
1 PIN CONFIGURATION
H/HVSyn VSyn HLckVBk HOscF HPLL2C CO HGND RO HPLL1F HPosF IC HFly RefOut BComp BRegIn BISense
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VDyCor SDA SCL Vcc BOut GND HOut XRay EWOut VOut VCap VGND VAGCCap VOscF VEHTIn HEHTIn
4/56
2
HGND
7 10 9 8 6 12 5 4
HPosF
HPLL1F
RO CO HOscF
HFly
HPLL2C
H/HVSyn
Horizontal position PLL1 speed
1
H-sync detection Polarity handling Phase/frequency comparator Horizontal VCO
25
Phase comparator Phase shifter H duty controller Safety processor
H-drive buffer
26
HOut
2 BLOCK DIAGRAM
XRay
Lock detection
PLL1
H-moire controller
H-moire amplitude
HLckVBk
3
Pin cushion asymm. Parallelogram Top corner asymm. Bottom corner asymm. Hor. duty cycle
28
V-blank H-lock
BOut
16 15
PLL2
BISense BRegIn
B+ ref.
14
SDA
IC-bus control registers
: Multiple bit djustments
31
B+ DC/DC converter controller
SCL
30
IC-bus interface
BComp
Vcc
V-dynamic correction Tracking
(focus, brightness)
29
RefOut
VDyCor amplitude
13
Supply supervision Reference generation V-sync extraction & detection
11
IC
EW generator
Internal ref.
GND
Vertical oscillator with AGC
27
V-ramp control
Vertical size & pos. Prescale size & pos. S- & C-correction Vertical moire Breathing gain
V-sync detection Input selection Polarity handling
H size Pin cushion Keystone Top corners Bottom corners S-correction W-correction Breathing gain
24
EWOut
2
21
19
20
22
32
23
18
17
STV6889
VOut VEHTIn HEHTIn
VSyn VAGCCap
VGND
VOscF
VCap VDyCor
STV6889
5/56
STV6889
3 PIN FUNCTION REFERENCE
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name H/HVSyn VSyn HLckVBk HOscF HPLL2C CO HGND RO HPLL1F HPosF IC HFly RefOut BComp BRegIn BISense HEHTIn VEHTIn VOscF VAGCCap VGND VCap VOut EWOut XRay HOut GND BOut Vcc SCL SDA VDyCor TTL compatible Vertical Sync. input Horizontal PLL1 Lock detection and Vertical early Blanking composite output High Horizontal Oscillator sawtooth threshold level Filter input Horizontal PLL2 loop Capacitive filter input Horizontal Oscillator Capacitor input Horizontal section GrouND Horizontal Oscillator Resistor input Horizontal PLL1 loop Filter input Horizontal Position Filter and soft-start time constant capacitor input Internally Connected (to be left open) Horizontal Flyback input Reference voltage Output B+ DC/DC error amplifier (Compensation) output Regulation feedback Input of the B+ DC/DC converter controller B+ DC/DC converter current (I) Sense input Input for compensation of Horizontal amplitude versus EHT variation Input for compensation of Vertical amplitude versus EHT variation Vertical Oscillator sawtooth low threshold Filter (capacitor to be connected to VGND) Input for storage Capacitor for Automatic Gain Control loop in Vertical oscillator Vertical section GrouND Vertical sawtooth generator Capacitor Vertical deflection drive Output for a DC-coupled output stage E/W Output X-Ray protection input Horizontal drive Output Main GrouND B+ DC/DC converter controller Output Supply voltage IC-bus Serial CLock Input IC-bus Serial DAta input/output Vertical Dynamic Correction output Function TTL compatible Horizontal / Horizontal and Vertical Sync. input
6/56
STV6889
4 QUICK REFERENCE DATA
Characteristic General Package Supply voltage Supply current Application category Means of control * Maximum clock frequency EW drive DC/DC converter controller Horizontal section Frequency range Autosync frequency ratio (can be enlarged in application) Positive * Negative polarity of horizontal sync signal * Automatic adaptation Duty cycle range of the drive signal Position adjustment range with respect to H period Soft start * Soft stop feature Hardware * Software PLL lock indication Parallelogram Pin cushion asymmetry correction (also called Side pin balance) Top * Bottom * Common corner asymmetry correction Tracking of asymmetry corrections with vertical size & position Horizontal moire cancellation (int.) for Combined * Separated architecture Vertical section Frequency range Autosync frequency range (150nF at VCap and 470nF at VAGCCap) Positive * Negative polarity of vertical sync signal * Automatic adaptation S-correction * C-correction * Super-flat tube characteristic Vertical size * Vertical position * Prescale adjustments Vertical moire cancellation (internal) EHT breathing compensation * With IC-bus gain control EW section Pin cushion correction Keystone correction Top * Bottom * Common corner correction S-correction * W-correction Horizontal size adjustment Tracking of EW waveform with Frequency * Vertical size & position EHT breathing compensation * With IC-bus gain control Dynamic correction section (dyn. focus, dyn. brightness,...) Vertical dynamic correction output VDyCor * Positive or negative polarity Horizontal dynamic correction output HDyCor Composite HV dynamic correction output HVDyCor * Positive or negative polarity Shape control on H waveform component of HVDyCor output Tracking of horizontal waveform component with Horizontal size * EHT Tracking of vertical waveforms (component) with V. size & position DC * DC controller section Step-up * Step-down conversion mode Internal * External sawtooth configuration Bus-controlled output voltage * Inhibition at H unlock Mute * Soft start * Soft stop feature Positive (N-MOS) * Negative(P-MOS) polarity of BOut signal Phase selection * Max current selection * Frequency selection Value SDIP 32 12 65 High-end IC-bus * 400 Yes Yes 15 to 150 4.28 Yes * Yes * Yes 30 to 65 10 Yes * Yes Yes * Yes Yes Yes Yes * Yes * No Yes Yes * Yes 35 to 200 50 to 180 Yes * Yes * Yes Yes * Yes * Yes Yes * Yes * Yes Yes Yes * Yes Yes Yes Yes * Yes * No Yes * Yes Yes Yes * Yes Yes * Yes Yes * Yes No No * No No No * No Yes Yes * Yes No * Yes Yes * Yes Yes * Yes * Yes Yes * Yes Yes * Yes * Yes Unit
V mA kHz
kHz
% %
Hz Hz
7/56
STV6889
5 ABSOLUTE MAXIMUM RATINGS
All voltages are given with respect to ground. Currents flowing from the device (sourced) are signed negative. Currents flowing to the device are signed positive.
Symbol VCC Supply voltage (pin Vcc) Pins HEHTIn, VEHTIn, XRay, HOut, BOut Pins H/HVSyn, VSyn, SCL, SDA Pins HLckVBk, CO, RO, HPLL1F, HPosF, BRegIn, BISense, VAGCCap, VCap, VDyCor, HOscF, VOscF Pin HPLL2C Pin HFly Latch-up current All pins except XRay Pin XRay ESD susceptibility (human body model: discharge of 100pF through 1.5kW) Storage temperature Junction temperature Parameter Value Min -0.4 -0.4 -0.4 -0.4 -0.4 -0.4 -200 -100 Max 13.5 VCC 5.5 VRefO VRefO/2 VRefO 200 200 Unit V V V V V V mA mA
V(pin)
Ilatch(pin)
VESD Tstg Tj
-2000 -40
2000 150 150
V C C
8/56
STV6889
6 ELECTRICAL PARAMETERS AND OPERATING CONDITIONS
Medium (middle) value of an IC-bus control or adjustment register composed of bits D0, D1,...,Dn is the one having Dn at "1" and all other bits at "0". Minimum value is the one with all bits at 0, maximum value is the one with all at "1". Currents flowing from the device (sourced) are signed negative. Currents flowing to the device are signed positive. TH is period of horizontal deflection.
6.1 Thermal data
Symbol Tamb Rth(j-a) Parameter Operating ambient temperature Junction-ambience thermal resistance Value Min. 0 65 Typ. Max. 70 Unit C C/W
6.2 Supply and Reference voltages
Tamb = 25C
Symbol VCC ICC VRefO IRefO Parameter Supply voltage at Vcc pin Supply current to Vcc pin Reference output voltage at RefOut pin Current capability of RefOut output VCC = 12V VCC = 12V, IRefO= -2mA 7.65 -5 Test Conditions Value Min. 10.8 Typ. 12 65 7.9 8.2 0 Max. 13.2 Units V mA V mA
6.3 Synchronization inputs
Vcc = 12V, Tamb = 25C
Symbol VLoH/HVSyn VHiH/HVSyn VLoVSyn VHiVSyn RPdSyn tPulseHSyn tPulseHSyn /TH tPulseVSyn tPulseVSyn /TV textrV /TH tHPolDet Parameter LOW level voltage on H/HVSyn HIGH level voltage on H/HVSyn LOW level voltage on VSyn HIGH level voltage on VSyn Internal pull-down on H/HVSyn, VSyn H sync. pulse duration on H/HVSyn pin Proportion of H sync pulse to H period V sync. pulse duration Proportion of V sync pulse to V period Pin H/HVSyn Pins H/HVSyn, VSyn Pins H/HVSyn, VSyn 0.21 0.75 0.35 ms 0.5 Test Conditions Value Min. 0 2.2 0 2.2 100 0.5 0.2 750 0.15 ms 175 Typ. Max. 0.8 5 0.8 5 250 Units V V V V kW ms
Proportion of H sync pulse length to H pe- Pin H/HVSyn, riod for extraction as V sync pulse cap. on pin CO = 820pF Polarity detection time (after change) Pin H/HVSyn
9/56
STV6889
6.4 Horizontal section
Table 1. Horizontal section
Symbol PLL1 IRO CCO fHO fHO(0) fHOCapt Df HO ( 0 ) ------------------------f HO ( 0 ) x DT DfHO/DVHO VHO VHOThrfr Current load on RO pin Capacitance on CO pin Frequency of hor. oscillator Free-running frequency of hor. oscill. (1) Hor. PLL1 capture frequency (4) Temperature drift of free-running freq. (3) RRO=5.23kW, CCO=820pF fHO(0) = 28.5kHz 27 29 28.5 390 150 29.9 122 1.5 mA pF kHz kHz kHz Parameter
( Vcc = 12V, Tamb = 25C)
Test Conditions Value Min. Typ. Max. Units
-150
ppm/C
Average horizontal oscillator sensitivity H. oscill. control voltage on pin HPLL1F
fHO(0) = 28.5kHz VRefO=8V 1.4
20.2 6.0 5.0 2.8 3.4 4.0 1.6 6.4
kHz/V V V V V V V V 700 5 W mA V V V V % %
Threshold on H. oscill. control voltage on =8V V HPLL1F pin for tracking of EW with freq. RefO Control voltage on HPosF pin Bottom of hor. oscillator sawtooth(6) Top of hor. oscillator sawtooth(6) Input impedance on HFly input Current into HFly input Voltage threshold on HFly input H flyback lock middle point(6) Low clamping voltage on HPLL2C pin(5) High clamping voltage on HPLL2C pin(5) Min. advance of H-drive OFF before middle of H flyback(7) Max. advance of H-drive OFF before middle of H flyback(8) Current into HOut output Null asym. correction Null asym. correction No PLL2 phase modulation V(HFly) >VThrHFly (2) At top of H flyback pulse 0.5 300 HPOS (Sad01h): 11111111b 10000000b 00000000b
VHPosF VHOThrLo VHOThrHi PLL2 RIn(HFly) IInHFly VThrHFly VS(0) VBotHPLL2C VTopHPLL2C tph(min) /TH tph(max) /TH IHOut
500 0.6 4.0 1.6 4.0 0 44
H-drive output on pin HOut Output driven LOW fH = 31kHz; HDUTY (Sad00h): x1111111b x0000000b Soft-start/Soft-stop value 30 mA
tHoff /TH
Duty cycle of H-drive signal
27 65 85
% % %
10/56
STV6889
Table 1. Horizontal section
Symbol Parameter
( Vcc = 12V, Tamb = 25C)
Test Conditions Value Min. Typ. Max. Units
Picture geometry corrections through PLL1 & PLL2 tHph /TH Hor. VCO phase vs. sync signal (via PLL1), see Figure 7 HPOS (Sad01h): 11111111b 10000000b 00000000b PCAC (Sad11h) full span
(9)
+11 0 -11
% % %
tPCAC /TH
Contribution of pin cushion asymmetry correction to phase of H-drive vs. static phase (via PLL2), measured in corners
VPOS at medium VSIZE at minimum VSIZE at medium VSIZE at maximum PARAL (Sad12h) full span
(9)
0.9 1.6 2.6
% % %
tParalC /TH
Contribution of parallelogram correction to phase of H-drive vs. static phase (via PLL2), measured in corners
VPOS at medium VSIZE at minimum VSIZE at medium VSIZE at maximum TCAC (Sad13h) full span
(9)
1.4 1.9 2.4
% % %
tTCAC /TH
Contribution of top corner asymmetry correction to phase of H-drive vs. static phase (via PLL2), measured in corners
VPOS at medium VSIZE at minimum VSIZE at medium VSIZE at maximum BCAC (Sad14h) full span
(9)
0.4 1.4 3.5
% % %
tBCAC /TH
Contribution of bottom corner asymmetry correction to phase of H-drive vs. static VPOS at medium phase (via PLL2), measured in corners VSIZE at minimum VSIZE at medium VSIZE at maximum
0.4 1.4 3.5
% % %
Notes about horizontal section
Note 1: Frequency at no sync signal condition. For correct operation, the frequency of the sync signal applied must always be higher than the free-running frequency. The application must consider the spread of values of real electrical components in RRO and CCO positions so as to always meet this condition. The formula to calculate the free-running frequency is fHO(0)=0.122/(RRO CCO) Note 2: Base of NPN transistor with emitter to ground is internally connected on pin HFly through a series resistance of about 500W and a resistance to ground of about 20kW. Note 3: Evaluated and figured out during the device qualification phase. Informative. Not tested on every single unit. Note 4: This capture range can be enlarged by external circuitry. Note 5: The voltage on HPLL2C pin corresponds to immediate phase of leading edge of H-drive signal on HOut pin with respect to internal horizontal oscillator sawtooth. It must be between the two clamping levels given. Voltage equal to one of the clamping values indicates a marginal operation of PLL2 or non-locked state. Note 6: Internal threshold. See Figure 6. Note 7: The tph(min) parameter is fixed by the application. For correct operation of asymmetry corrections through dynamic phase modulation, this minimum must be increased by maximum of the total dynamic phase required in the direction leading to bending of corners to the left. Marginal situation is indicated by reach of VTopHPLL2C high clamping level by waveform on pin HPLL2C. Also refer to Note 5 and Figure 6.
11/56
STV6889
Notes about horizontal section (continued)
Note 8: The tph(max) parameter is fixed by the application. For correct operation of asymmetry corrections through dynamic phase modulation, this maximum must be reduced by maximum of the total dynamic phase required in the direction leading to bending of corners to the right. Marginal situation is indicated by reach of VBotHPLL2C low clamping level by waveform on pin HPLL2C. Also refer to Note 5 and Figure 6. Note 9: All other dynamic phase corrections of picture asymmetry set to their neutral (medium) positions.
6.5 Vertical section
Table 2. Vertical section (Vcc = 12V, Tamb = 25C)
Symbol Parameter Test Conditions Value Min. Typ. Max. Units
AGC-controlled vertical oscillator sawtooth; VRefO = 8V RL(VAGCCap) VVOB VVOTref VVOT tVODis fVO(0) fVOCapt DVVOdev ------------------VVOamp DVVOamp --------------------------------VVOamp x DfVO Ext. load resistance on VAGCCap pin(10) Sawtooth bottom voltage on VCap pin(11) Sawtooth top voltage internal reference Sawtooth top voltage on VCap pin Sawtooth Discharge time Free-running frequency AGC loop capture frequency Sawtooth non-linearity(12)(17) AGC loop stabilized CVCap=150nF CVCap=150nF CVCap=150nF AGC loop stabilized (12) 50 0.5 DVamp/Vamp(R=) 1% No load on VOscF pin(11) 65 2 5 5 80 100 185 MW V V V ms Hz Hz %
Frequency drift of sawtooth amplitude(18)(19)
AGC loop stabilized fVOCapt(min)fVOfVOCapt(max)
200
ppm/Hz
Vertical output drive signal (on pin VOut); VRefO = 8V Vmidref Internal reference for vertical sawtooth middle point VPOS (Sad08h):(22) x0000000b x1000000b x1111111b VPOF (Sad1Eh):(21) x0000000b x1000000b x1111111b VSIZE (Sad07h):(23) x0000000b x1000000b x1111111b VSAG (Sad1Dh):(20) x0000000b x1000000b x1111111b 3.5 3.1 3.45 3.8 3.3 3.45 3.6 2.25 3.0 3.75 2 2.5 3.0 4.0 2.5 3.3 V V V V V V V V V V V V V V
Vmid(VOut)
Middle point on VOut sawtooth
3.65
Vamp
Amplitude of VOut sawtooth (peak-to-peak voltage)
3.5
VoffVOut
Level on VOut pin at V-drive "off" IC-bus bit VOutEn at 0
12/56
STV6889
Table 2. Vertical section (Vcc = 12V, Tamb = 25C)
Symbol IVOut VSCor /Vamp Parameter Current delivered by VOut output
(13)(20)(21)
Test Conditions
Value Min. -5 Typ. Max. 0.25
Units mA
S-correction range
AGC loop stabilized tVR=1/4 TVR(15) tVR=3/4 TVR
(14)(20)(21)
-4.5 +4.5
% %
VCCor /Vamp
C-correction range
AGC loop stabilized tVR=1/2 TVR(15) CCOR(Sad0Ah): x0000000b x1000000b x1111111b 1
-2.5 0 +2.5 4 4.0 6
% % % V V %/V
VVEHT VVEHTnull
Control input voltage range onVEHTIn pin Neutral point on breathing characteristics(16) VRefO < VVEHT < VCC VVEHT(min)VVEHTVVE-
0
DVamp ---------------------------------Vamp x DVVEHT
HT(max):
Breathing compensation
VEHTG (Sad1Ch): x0000000b x1000000b x1111111b
5 0 -5
%/V %/V %/V
Notes about vertical section
Note 10: Value of acceptable cumulated parasitic load resistance due to humidity, AGC storage capacitor leakage, etc., for less than 1% of Vamp change. Note 11: The threshold for VVOB is generated internally and routed to VOscF pin. Any DC current on this pin will influence the value of VVOB. Note 12: Maximum of deviation from an ideally linear sawtooth ramp at null S-correction (SCOR at 0000000b) and null C-correction (CCOR at 1000000b). The same rate applies to V-drive signal on VOut pin, no effect on EWOut. Note 13: Maximum S-correction (SCOR at x1111111b), null C-correction (CCOR at 1000000b). Note 14: Null S-correction (SCOR at 0000000b). Note 15: "tVR" is time from the beginning of vertical ramp of V-drive signal on VOut pin. "TVR" is the duration of this ramp, see Chapter 7 - page 21 and Figure 17. Note 16: If VVEHT=VVEHTnull or VHEHT=VHEHTnull, respectively, the influence of VVEHT on vertical drive amplitude or the influence of VHEHT on EW drive signal, respectively, is null. Note 17: VVOamp = VVOT -VVOB Note 18: Only the top of the saw tooth drifts. The same rate applies to V-drive signal on VOut pin. Note 19: Informative, not tested on each unit. Note 20: VSIZE at medium value 1000000b. Note 21: VPOS at medium value 1000000b. Note 22: VPOF at medium value 1000000b. Note 23: VSAG at maximum value 1111111b.
13/56
STV6889
6.6 EW drive section
Table 3. EW drive section (VCC = 12V, Tamb = 25C)
Symbol VEW IEWOut VHEHT VHEHTnull Parameter Output voltage on EWOut pin Current delivered by EWOut output Control voltage range on HEHTIn pin Neutral point on breathing characteristics. See Figure 15.(16)
(24)(25)(26)(27)(28)(36)(42)(43)
Test Conditions
Value Min. 1.8 -1.5 1 4.0 Typ. Max. 6.5 0.1 6
Units V mA V V
EWTrHFr=0 or VHO>VHOThrfr
VEW-DC
DC component of the EW-drive signal on EWOut pin(30)
HSIZE (Sad10h): 00000000b 10000000b 11111111b
2 3.25 4.5 2
V V V V
VEW-base
DC reference for the EW-drive signal on EWOut pin
(24)(25)(26)(27)(42)(43)
DVEW - DC ---------------------DVHEHT
VRefO < VHEHT < VCC VHEHT(min)VHEHTVHEBreathing compensation on DC (max): component of the EW-drive sig- HT HEHTG (Sad1Bh): (30) nal x0000000b x1000000b x1111111b Temperature drift of DC component of the EW-drive signal(30)
(24)(25)(26)(27)(28)(36)(42)(43) (44)
0 0 -0.25 0 +0.25 100
V/V V/V V/V V/V V/V ppm/C
DVEW - DC ------------------------------V EW -DC x DT
(24)(25)(26)(28)(29)(31) (32)(36)(42)(43)
VEW-PCC
Pin cushion correction component of the EW-drive signal
VSIZE at maximum PCC (Sad0Ch): x0000000b x1000000b x1111111b Tracking with VSIZE: PCC at x1000000b VSIZE (Sad07h): x0000000b x1000000b
(24)(25)(26)(29)(33)(35)(36)(42)(43)
0 0.75 1.5
V V V
0.25 0.5
V V
VEW - PCC [ t vr= 0 ] ------------------------------------------VEW - PCC [ t vr= TVR]
Tracking of PCC component of the EW-drive signal with vertical position adjustment
PCC at x1111111b VPOS (Sad08h): x0000000b x1111111b
(25)(26)(27)(28)(29)(33)(34)(36)(42)(
0.5 2.0
43)
VEW-Key
Keystone correction component KEYST (Sad0Dh): of the EW-drive signal x0000000b x1111111b
0.4 -0.4
V V
14/56
STV6889
Table 3. EW drive section (VCC = 12V, Tamb = 25C)
Symbol Parameter
(43)
Test Conditions
(24)(26)(27)(28)(29)(31)(33)(36)(42)
Value Min. Typ. Max.
Units
VEW-TCor
Top corner correction component of the EW-drive signal
TCC (Sad0Eh): x0000000b x1000000b x1111111b
(24)(25)(27)(28)(29)(32)(33)(36)(42) (43)
-1.4 0 +1.4
V V V
VEW-BCor
Bottom corner correction compo- BCC (Sad0Fh): nent of the EW-drive signal x0000000b x1000000b x1111111b
(24)(25)(26)(27)(28)(29)(33)(36)(41) (43)
-1.4 0 +1.4
V V V
VEW-S
Pin Cushion S correction compo- EWSC (Sad19h): nent of EW-drive signal x0000000b x1000000b x1111111b
(24)(25)(26)(27)(28)(29)(33)(36)(41) (42)
-0.3 0 0.3
V V V
VEW-W
Pin Cushion W correction component of EW-drive signal
EWWC (Sad1Ah): x0000000b x1000000b x1111111b IC bit EWTrHFr=1 VHO>VHOThrfr VHO(min)VHOVHOThrfr IC bit EWTrHFr=1 VHO>VHOThrfr VHO(min)VHOVHOThrfr IC bit EWTrHSize=1 HSIZE (Sad10h): 00000000b 10000000b 11111111b VRefO < VHEHT < VCC VHEHT(min)VHEHTVHE-
-0.1 0 0.1 0 20 0 20
V V V %/V %/V %/V %/V
DV EW-AC ----------------------------------------------------V EW-AC [ f max ] x DV HO DV EW- DC ---------------------------------------------------V EW- DC [span] x DV HO VEW-AC -------------------------------------------------VEW - AC [ HSIZE max ]
Tracking of AC component of EW-drive signal with horizontal frequency(37)(38)(39) Tracking of DC component of EW-drive signal with horizontal frequency(30)(38)(39) Tracking of AC component of EW-drive signal with horizontal size(37)
138 119 100 0
% % % %/V
DVEW - AC -----------------------------------------VEW - AC x DVHEHT
Breathing compensation on AC HT(max): component of the EW-drive sig- HEHTG (Sad1Bh): nal(37) 0000000b 1000000b 1111111b
3.5 0 -3.5
%/V %/V %/V
15/56
STV6889
Notes about EW drive section
Note 24: KEYST at medium (neutral) value. Note 25: TCC at medium (neutral) value. Note 26: BCC at medium (neutral) value. Note 27: PCC at minimum value. Note 28: VPOS at medium (neutral) value. Note 29: HSIZE IC field at maximum value. Note 30: VEW-DC is defined as voltage at tVR=1/2 TVR. Note 31: Defined as difference of (voltage at tVR=0) minus (voltage at tVR=1/2 TVR). Note 32: Defined as difference of (voltage at tVR=TVR) minus (voltage at tVR=1/2 TVR). Note 33: VSIZE at maximum value. Note 34: Difference (voltage at tVR=0) minus (voltage at tVR=TVR). Note 35: Ratio "A/B"of parabola component voltage at tVR=0 versus parabola component voltage at tVR=TVR. See Figure 2. Note 36: VHEHT>VRefO, VVEHT>VRefO Note 37: VEW-AC is defined as overall peak-to-peak value between tVR=0 and tVR=TVR of all components other than VEWDC (contribution of PCC, keystone correction, corner corrections and S- and W-corrections). Note 38: More precisely tracking with voltage on HPLL1F pin which itself depends on frequency at a rate given by external components on PLL1 pins Note 39: VEW-DC[span] = VEW-DC[VHO>VHOThrfr] - VEW-DC[HSIZE=0000000b]. VEW-AC[fmax] = VEW-AC[VHO>VHOThrfr]. Note 40: Defined as difference of (voltage at tVR=1/4 TVR) minus (voltage at tVR=3/4 TVR). Note 41: Defined as difference of (voltage at tVR=1/2 TVR) minus (voltage at tVR=1/4 TVR). Note 42: EWSC at medium (neutral) value. Note 43: EWWC at medium (neutral) value. Note 44: Informative, not tested on each unit.
16/56
STV6889
6.7 Dynamic correction outputs section
Table 4. Dynamic correction outputs section
Symbol Parameter
(VCC = 12V, Tamb = 25C)
Value Min. -1.5 Typ. Max. 0.1 4 Units
Test Conditions
Vertical Dynamic Correction output VDyCor IVDyCor VVD-DC Current delivered by VDyCor output DC component of the drive signal on VDyCor output RL(VDyCor)=10kW
(28)
mA V
VVD-V
VSIZE at medium VDC-AMP (Sad15h): x0000000b Amplitude of V-parabola on VDyCor x1000000b output x1111111b VDC-AMP at maximum VSIZE (Sad07h): x0000000b x1111111b VDC-AMP at maximum Tracking of V-parabola on VDyCor VPOS (Sad08h): x0000000b output with vertical position (45) x1111111b
0 0.5 1
V V V
0.6 1.6
V V
VVD - V [t VR= 0] ------------------------------------------------------VVD -V [t VR= TVR]
0.5 2.0
Notes about dynamic output section
Note 45: Ratio "A/B"of vertical parabola component voltage at tVR=0 versus vertical parabola component voltage at tVR=TVR.
17/56
STV6889
6.8 DC/DC controller section
Table 5. DC/DC controller section
Symbol RB+FB AOLG fUGBW IRI IBComp ABISense VThrBIsCurr IBISense tBOn IBOut VBOSat Parameter Ext. resistance applied between BComp output and BRegIn input Open loop gain of error amplifier on BRegIn input Unity gain bandwidth of error amplifier on BRegIn input Bias current delivered by BRegIn Output current capability of BComp out- BOut enabled put. BOut disabled(46) Voltage gain on BISense input Threshold voltage on BISense input corresponding to current limitation Bias current delivered by BISense Conduction time of the power transistor Output current capability of BOut output Saturation voltage of the internal output IBOut=10mA transistor on BOut Regulation reference for BRegIn voltage(47) Delay of BOut "Off-to-On" edge after middle of flyback pulse (48) VRefO=8V BREF (Sad03h): x0000000b x1000000b x1111111b BOutPh = 0 and BOHEdge = 0 0 0.25 ThrBlsense = 0 ThrBlsense = 1 TBD TBD -0.5 0.5 3 2.1 1.2 -1 10 V mA TH - 300ns mA V Low frequency(19)
(19)
(VCC = 12V, Tamb = 25C)
Test Conditions Value Min. 5 100 6 -0.2 2.0 Typ. Max. Units kW dB MHz mA mA mA
VBReg
3.8 4.9 6.0 16
V V V %
tBTrigDel /TH
Note 46: A current sink is provided by the BComp output while BOut is disabled. Note 47: Internal reference related to VRefO. The same values to be found on pin BRegIn, while regulation loop is stabilized. Note 48: Only applies to configuration specified in "Test conditions" column, i.e. synchronization of BOut "Off-to-On" edge with horizontal fly-back signal. Refer to chapter "DC/DC controller" for more details.
18/56
STV6889
6.9 Miscellaneous
Table 6. Miscellaneous
Symbol Parameter
(VCC = 12V, Tamb = 25C)
Test Conditions Value Min. Typ. 100 H. lock Yes Yes No No 0.1 1.1 5 6 Max. Units
Vertical blanking and horizontal lock indication composite output HLckVBk ISinkLckBk Sink current to HLckVBk pin
(49)
mA V V V V
VOLckBk
Output voltage on HLckVBk output
V. blank No Yes No Yes
Horizontal moire canceller HMoireMode = 0 HMOIRE (Sad02h): x0000000b x1111111b HMoireMode = 1 HMOIRE (Sad02h): x0000000b x1111111b VMOIRE (Sad0Bh): x0000000b x1111111b
DTH ( H - moire) ---------------------------TH
Modulation of TH by H. moire function
0 0.02
% %
0 0.04
% %
Vertical moire canceller VV-moire Amplitude of modulation of V-drive signal on VOut pin by vertical moire. 0 3 VRefO VRefO VRefO -10mV +10mV TH 10.2 8.0 6.8 2TH 10.8 V V V mV mV
Protection functions VThrXRay tXRayDelay VCCXRayEn VCCEn VCCDis Input threshold on XRay input(50) Delay time between XRay detection event and protection action Minimum VCC value for operation of XRay detection and protection(53) VCC value for start of operation at VCC ramp-up(51) VCC value for stop of operation at VCC ramp-down(51) Threshold for start/stop of H-drive signal Threshold for start/stop of B-drive signal Threshold for full operation duty cycle of H-drive and B-drive signals Minimum supply voltage when voltage on HPosF pin reaches VHOn threshold(54)
Control voltages on HPosF pin and VCC for Soft start/stop operation(19)(52) VHOn VBOn VHBNorm VCCStop 1 1.7 2.4 4.8 V V
19/56
STV6889
Notes about Miscellaneous section
Note 49: Current sunk by the pin if the external voltage is higher than one the circuit tries to force. Note 50: See VRefO in Section 6.2. Note 51: In the regions of VCC where the device's operation is disabled, the H-drive, V-drive and B+-drive signals on HOut, VOut and BOut pins, resp., are inhibited, the IC-bus does not accept any data and the XRayAlarm flag is reset. Also see Figure 10. Note 52: See Figure 10. Note 53: When VCC is below VCCXRayEn XRay detection and protection are disabled. Note 54: Minimum momentary supply voltage to ensure a correct performance of Soft stop function at VCC fall down is defined at the moment when the voltage on HPosF pin reaches VHOn threshold.
20/56
STV6889
7 TYPICAL OUTPUT WAVEFORMS
Table 7. Typical output waveforms - Note 55
Function Sad Pin Byte x0000000 Vertical Size 07 VOut (23) x1111111 Vamp Vmid(VOut) Vamp Waveform Effect on Screen
Vmid(VOut)
x0000000 Vertical Size After Gain 1D VOut (23) x1111111
Vamp
Vmid(VOut)
Vamp
Vmid(VOut)
x0000000
Vmid(VOut)
Vmidref
Vertical Position
08
VOut (23)
x1000000
Vmid(VOut) Vmid(VOut)
Vmidref
x1111111
Vmidref
x0000000
Vmid(VOut)
Vmidref
Vertical Position Offset
1E
VOut (23)
x1000000
Vmid(VOut) Vmid(VOut)
Vmidref
x1111111
Vmidref
x0000000: Null S-correction 09 VOut (23) x1111111: Max.
Vamp
0 1/2TVR TVR t VR
VSCor Vamp
0 1/4TVR 3/4TVR TVR
tVR
21/56
STV6889
Table 7. Typical output waveforms - Note 55
Function Sad Pin Byte Vamp x0000000
0
Waveform
Effect on Screen
VCCor
1/2TVR TVR tVR
C-correction
0A
VOut (23)
x1000000 : Null
Vamp
0 1/2TVR TVR t VR
Vamp x1111111
0
VCCor
1/2TVR TVR tVR
x0000000: Vamp Null Vertical moire amplitude 0B VOut (23)
(n-1)TV nTV (n+1)TV VV-moire t
x1111111: Vamp Max.
(n-1)TV nTV (n+1)TV t
00000000 Horizontal size 10h EWOut (24) 11111111
VEW-DC
0 1/2TVR TVR t VR
VEW-DC
0 1/2TVR TVR t VR
x0000000 Keystone correction 0D EWOut (24) x1111111
VEW-Key
0
VEW-DC
1/2TVR TVR tVR
VEW-Key
VEW-DC
VEW-PCC x0000000 Pin cushion correction 0C EWOut (24) x1111111
0 1/2TVR TVR t VR 0 1/2TVR TVR t VR
VEW-PCC
22/56
STV6889
Table 7. Typical output waveforms - Note 55
Function Sad Pin Byte Waveform VEW-TCor x1111111 Top corner correction 0E EWOut (24) x0000000
0 1/2TVR TVR t VR 0 1/2TVR TVR t VR
Effect on Screen
VEW-TCor
VEW-BCor x1111111 Bottom corner correction 0F EWOut (24) x0000000
0 1/2TVR TVR t VR 0 1/2TVR TVR t VR
VEW-BCor
x1111111 Pin Cushion S-correction 19 EWOut (24) x0000000
VEW-S
0 1/2TVR TVR tVR
VEW-S
0 1/2TVR TVR tVR
x1111111 Pin Cushion W-correction 1A EWOut (24)
VEW-W
0 1/2TVR TVR tVR
x0000000 VEW-W
0 1/2TVR TVR tVR
tParalC x0000000 Parallelogram correction 12h Internal
0
static H-phase
1/2TVR
TVR t VR
tParalC x1111111
0
static H-phase
1/2TVR
TVR t VR
static H-phase
x0000000 11h Internal Pin cushion asymmetry correction
tPCAC
0 1/2TVR
TVR t VR
tPCAC x1111111
0 1/2TVR
static H-phase
TVR t VR
23/56
STV6889
Table 7. Typical output waveforms - Note 55
Function Sad Pin Byte tTCAC x0000000 Internal Top corner asymmetry correction
0 1/2TVR
Waveform
static H-phase
Effect on Screen
TVR
13h
tVR
x1111111
tTCAC
0 1/2TVR
static H-phase
TVR t VR
static H-phase
tBCAC x0000000 Internal Bottom corner asymmetry correction 14h
0 1/2TVR
TVR t VR
static H-phase
x1111111
tBCAC
0 1/2TVR
TVR t VR
VDyCorPol=0
01111111
VVD-V
0 1/2TVR
VVD-DC
TVR t VR
Vertical dynamic correction amplitude
15h
VDyCor (32)
x0000000
VVD-V
0 1/2TVR
VVD-DC
TVR t VR
VDyCorPol=1
Application dependent
11111111
VVD-V
0 1/2TVR
VVD-DC
TVR t VR
Note 55: For any H and V correction component of the waveforms on EWOut and VOut pins and internal waveform for corrections of H asymmetry, displayed in the table, the weight of the other relevant components is nullified (minimum for parabola, S-correction, medium for keystone, all corner corrections, C-correction, S- and W-pin cushion corrections, parallelogram, pin cushion asymmetry correction, written in corresponding registers).
24/56
STV6889
8 IC-BUS CONTROL REGISTER MAP
The device slave address is 8C in write mode and 8D in read mode. The control register map is given in Table . Bold weight denotes default value at Power-On-Reset. IC-bus data in the adjustment register is buffered and internally applied with discharge of the vertical oscillator (56).
In order to ensure compatibility with future devices, all "Reserved" bits should be set to 0.
Table 8. IC-bus control registers
Sad D7 HDutySyncV 1: Synchro. 0: Asynchro. 1 HMoireMode 1: Separated 0: Combined B+SyncV 0: Asynchro. D6 D5 D4 HDUTY 0 0 0 HPOS 0 0 0 HMOIRE 0 0 0 BREF 1 0 0 Reserved Reserved BOutPol 0: Type N BOutPh 0: H-flyback 1: H-drive EWTrHFr 0: No tracking Reserved Reserved Reserved Reserved Reserved Reserved Reserved VSIZE 1 0 0 VPOS 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 SCOR 0 CCOR 0 VMOIRE 0 PCC 0 KEYST 0 TCC 0 BCC 0 HSIZE 1 0 Reserved Vertical size 0 Vertical position 0 S-correction 0 C-correction 0 0 0 0 0 0 Horizontal size 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Vertical moire amplitude Pin cushion correction Keystone correction Top corner correction Bottom corner correction 0 0 0 0 0 0 0 0 0 D3 D2 D1 D0
WRITE MODE (SLAVE ADDRESS = 8C) Horizontal duty cycle 0 0 0 0 00
01
Horizontal position 0 0 0 0 Horizontal moire amplitude 0 B+reference 0 0 0 0 0 0 0
02
03 04 05 06
07
08 09 0A 0B 0C 0D 0E 0F 10
25/56
STV6889
Table 8. IC-bus control registers
Sad 11 12 13 14 15 D7 Reserved Reserved Reserved Reserved VDyCorPol 0: "E" XRayReset 0: No effect 1: Reset TV 0: Off(58) Reserved 0: Reserved 0: Reserved 0: Reserved 0: Reserved 0: Reserved 0: ThrBlsense 0: High D6 1 1 1 1 1 VSyncAuto 1: On TH 0: Off(58) D5 0 0 0 0 0 VSyncSel 0:Comp 1:Sep TVM 0: Off(58) D4 PCAC 0 PARAL 0 TCAC 0 BCAC 0 VDC-AMP 0 SDetReset 0: No effect 1: Reset THM 0: Off(58) EWSC 1 1 0 0 1 1 BMute 0: Off VLock 0: Locked 1: Not lock. 0 0 0 0 1 0 BSafeEn 0: Disable 0 EWWC 0 HEHTG 0 VEHTG 0 VSAG 1 VPOF 0 D3 0 0 0 0 0 PLL1Pump 1,1: Fastest 0,0: Slowest BOHEdge 0: Falling HBOutEn 0: Disable D2 0 0 0 0 0 D1 0 0 0 0 0 PLL1InhEn 1: On VOutEn 0: Disable D0 0 0 0 0 0 HLockEn 1: On BlankMode 1: Perm.
Pin cushion asymmetry correction Parallelogram correction Top corner asymmetry correction Bottom corner asymmetry correction Vertical dynamic correction
16
17 18 19 1A 1B 1C 1D 1E 1F
Reserved East-West S-correction 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved 0 0 0 0 0 0 Reserved East-West W-correction Horizontal EHT compensation gain Vertical EHT compensation gain Vertical size after-gain Vertical position offset
EWTrHSize Ident HLockSpeed 0: Tracking 0: No effect 0: Slow
READ MODE (SLAVE ADDRESS = 8D) XX(57
)
HLock 0: Locked 1: Not locked
Polarity detection XRayAlarm 1: On HVPol VPol 0: Off 1: Negative 1: Negative
Sync detection VExtrDet 0: Not det. HVDet 0: Not det. VDet 0: Not det.
Note 56: With exception of HDUTY and BREF adjustments data that can take effect instantaneously if switches HDutySyncV and B+SyncV are at 0, respectively. Note 57: In Read Mode, the device always outputs data of the status register, regardless of sub address previously selected. Note 58: The TV, TH, TVM and THM bits are for testing purposes and must be kept at 0 by application.
26/56
STV6889
DESCRIPTION OF IC-BUS SWITCHES AND FLAGS Write-to bits Sad00h/D7 - HDutySyncV Synchronization of internal application of Horizontal Duty cycle data, buffered in IC-bus latch, with internal discharge of Vertical oscillator. 0: Asynchronous mode, new data applied with ACK bit of IC-bus transfer on this sub address 1: Synchronous mode Sad02h/D7 - HMoireMode Horizontal Moire characteristics. 0: Adapted to an architecture with EHT generated in deflection section 1: Adapted to an architecture with separated deflection and EHT sections Sad03h/D7 - B+SyncV Same as HDutySyncV, applicable for B+ reference data Sad06h/D7 - BOutPol Polarity of B+ drive signal on BOut pin. 0: adapted to N type of power MOS - high level to make it conductive 1: adapted to P type of power MOS - low level to make it conductive Sad07h/D7 - BOutPh Phase of start of B+ drive signal on BOut pin 0: End of horizontal flyback or horizontal frequency divided by 2, see BOHEdge bit. 1: With one of edges of line drive signal on HOut pin, selected by BOHEdge bit Sad08h/D7 - EWTrHFr Tracking of all corrections contained in waveform on pin EWOut with Horizontal Frequency 0: Not active 1: Active Sad15h/D7 - VDyCorPol Polarity of Vertical Dynamic Correction waveform (parabola) 0: Concave (minimum in the middle of the parabola) 1: Convex (maximum in the middle of the parabola) Sad16h/D0 - HLockEn Enable of output of Horizontal PLL1 Lock/unlock status signal on pin HLckVBk 0: Disabled, vertical blanking only on the pin
HLckVBk
1: Enabled Sad16h/D1 - PLL1InhEn Enable of Inhibition of horizontal PLL1 during extracted vertical synchronization pulse 0: Disabled, PLL1 is never inhibited 1: Enabled Sad16h/D2 and D3- PLL1Pump Horizontal PLL1 charge Pump current
D3 0 1 0 1 D2 0 0 1 1 Time Constant Slowest PLL1, lowest current Moderate Slow PLL1, low current Moderate Fast PLL1, high current Fastest PLL1, highest current
Sad16h/D4 - SDetReset Reset to 0 of Synchronization Detection flags VDet, HVDet and VExtrDet of status register effected with ACK bit of IC-bus data transfer into register containing the SDetReset bit. Also see description of the flags. 0: No effect 1: Reset with automatic return of the bit to 0 Sad16h/D5 - VSyncSel Vertical Synchronization input Selection between the one extracted from composite HV signal on pin H/HVSyn and the one on pin VSyn. No effect if VSyncAuto bit is at 1. 0: V. sync extracted from composite signal on H/HVSyn pin selected 1: V. sync applied on VSyn pin selected Sad16h/D6 - VSyncAuto Vertical Synchronization input selection Automatic mode. If enabled, the device automatically selects between the vertical sync extracted from composite HV signal on pin H/HVSyn and the one on pin VSyn, based on detection mechanism. If both are present, the one coming first is kept. 0: Disabled, selection done according to bit VSyncSel 1: Enabled, the bit VSyncSel has no effect
27/56
STV6889
Sad16h/D7 - XRayReset Reset to 0 of XRay flag of status register effected with ACK bit of IC-bus data transfer into register containing the XRayReset bit. Also see description of the flag. 0: No effect 1: Reset with automatic return of the bit to 0 Sad17h/D0 - BlankMode Blanking operation Mode. 0: Blanking pulse starting with detection of vertical synchronization pulse and ending with end of vertical oscillator discharge (start of vertical sawtooth ramp on the VOut pin) 1: Permanent blanking - high blanking level in composite signal on pin HLckVBk is permanent Sad17h/D1 - VOutEn Vertical Output Enable. 0: Disabled, VoffVOut on VOut pin (see Section
6.5 Vertical section)
If the bit BOutPh is at 0, selection of signal to phase B+ drive output on BOut pin: 1: Horizontal frequency divided by 2 signal, top of horizontal VCO 0: End of horizontal flyback Sad17h/D4,D5,D6,D7 - THM, TVM, TH, TV Test bits. They must be kept at 0 level by application S/W. Sad1Fh/D2 - HLockSpeed Response Speed of lock-to-unlock transition of H-lock component on HLock output and HLock IC-bus flag at signal change. 0: Low 1: High Sad1Fh/D3 - Ident Device Identification bit. If HBOutEn is at 1, the bit has no effect. If HBOutEn is at 0, then 0: The value of Hlock status bit is 1 1: The value of Hlock status bit is 0 Sad1Fh/D4 - EWTrHSize Tracking of all corrections contained in waveform on pin EWOut with Horizontal Size IC-bus register HSIZE. 0: Active 1: Not active Sad1Fh/D5 - BSafeEn B+ Output Safety Enable. 0: Disabled 1: Enabled, BOut goes off as soon as HLock status of Horizontal PLL1 indicates "unlock" state. Retrieval of "lock" state will initiate soft start mechanism of DC/DC controller on BOut output. Sad1Fh/D6 - BMute B+ Output Mute. 0: Disabled 1: Enabled, BOut goes unconditionally off. Programming this bit back to 0 will initiate soft start mechanism of DC/DC controller on BOut output. Sad1Fh/D7 - ThrBlsense Threshold on BISense input corresponding to current limitation. 0: High 1: Low
1: Enabled, vertical ramp with vertical position offset on VOut pin Sad17h/D2 - HBOutEn Horizontal and B+ Output Enable. 0: Disabled, levels corresponding to "power transistor off" on HOut and BOut pins (high for HOut, high or low for BOut, depending on BOutPol bit). 1: Enabled, horizontal deflection drive signal on HOut pin providing that it is not inhibited by another internal event (activated XRay protection). B+ drive signal on BOut pin if not inhibited by another internal event. Programming the bit to 1 after prior value of 0, will initiate soft start mechanism of horizontal drive and, if this is not inhibited by another internal event, also the soft start of B+ DC/DC convertor controller. See also bits BMute and BSafeEn. Sad17h/D3 - BOHEdge If the bit BOutPh is at 1, selection of Edge of Horizontal drive signal to phase B+ drive Output signal on BOut pin. 1: Rising edge 0: Falling edge
28/56
STV6889
Read-out flags SadXX/D0 - VDet(59) Flag indicating Detection of V synchronization pulses on VSyn pin. 0: Not detected 1: Detected SadXX/D1 - HVDet (59) Flag indicating Detection of H or HV synchronization pulses applied on H/HVSyn pin. Once the sync pulses are detected, the flag is set and latched. Disappearance of the sync signal will not lead to reset of the flag. 0: Not detected 1: Detected. SadXX/D2 - VExtrDet (59) Flag indicating Detection of Extracted Vertical synchronization signal from composite H+V signal applied on H/HVSyn pin. 0: Not detected 1: Detected SadXX/D3 - VPol Flag indicating Polarity of V synchronization pulses applied on VSyn pin with respect to mean level of the sync signal. 0: Positive 1: Negative SadXX/D4 - HVPol Flag indicating Polarity of H or HV synchronization pulses applied on H/HVSyn pin with respect to mean level of the sync signal. 0: Positive 1: Negative SadXX/D5 - XRayAlarm Alarm indicating that an event of excessive voltage has passed on XRay pin. Can only be reset to 0 through IC-bus bit XRayReset or by poweron reset. 0: No excess since last reset of the bit 1: At least one event of excess appeared since the last reset of the bit, HOut inhibited SadXX/D6 - VLock Status of "Locking" or stabilizing of Vertical oscillator amplitude to an internal reference by AGC regulation loop. 0: Locked (amplitude stabilized) 1: Not locked (amplitude non-stabilized) SadXX/D7 - HLock Lock status of Horizontal PLL1. 0: Locked 1: Not locked See also bit Ident (Sad1Fh/D3)
Note 59: This flag, by its value of 1, indicates an event of detection of at least one synchronization pulse since its last reset (by means of the SDetReset IC-bus bit). This is to be taken into account by application S/W in a way that enough time (at least the period between 2 synchronization pulses of analyzed signal) must be provided between reset of the flag through SDetReset bit and validation of information provided in the flag after read-out of status register.
29/56
STV6889
9 OPERATING DESCRIPTION 9.1 Supply and control
9.1.1 Power supply and voltage references The device is designed for a typical value of power supply voltage of 12 V. In order to avoid erratic operation of the circuit at power supply ramp-up or ramp-down, the value of VCC is monitored. See Figure 1 and electrical specifications. At switch-on, the device enters a "normal operation" as the supply voltage exceeds VCCEn and stays there until it decreases bellow VCCDis. The two thresholds provide, by their difference, a hysteresis to bridge potential noise. Outside the "normal operation", the signals on HOut, BOut and VOut outputs are inhibited and the ICbus interface is inactive (high impedance on SDA, SCL pins, no ACK), all IC-bus control registers being reset to their default values (see Chapter 8 page 25). The stop of HOut and BOut drive signals when the VCC falls from normal operation below VCCDis is not instantaneous. It is only a trigger point of Soft Stop mechanism (see Subsection 9.3.7- page
35).
Figure 1. Supply voltage monitoring
V(Vcc) VCC VCCEn
hysteresis
VCCDis
Disabled
Normal operation
Disabled t
Internal thresholds in all parts of the circuit are derived from a common internal reference supply VRefO that is lead out to RefOut pin for external filtering against ground as well as for external use with load currents limited to IRefO. The filtering is necessary to minimize interference in output signals, causing adverse effects like e.g. jitter. 9.1.2 IC-bus control The IC-bus is a 2 line bidirectional serial communication bus introduced by Philips. For its general description, refer to corresponding Philips IC-bus specification. This device is an IC-bus slave, compatible with fast (400kHz) IC-bus protocol, with write mode slave address of 8Ch (read mode slave address 8Dh). Integrators are employed at the SCL (Serial Clock) input and at the input buffer of the SDA (Serial Data) input/output to filter off the spikes up to 50ns. The device supports multiple data byte messages (with automatic incrementing of the IC-bus subaddress) as well as repeated Start Condition for ICbus subaddress change inside the IC-bus messages. All IC-bus registers with specified IC-bus subaddress are of WRITE ONLY type, whereas the status register providing a feedback information to the master IC-bus device has no attributed IC-bus subaddress and is of READ ONLY type. The master IC-bus device reads this register sending directly, after the Start Condition, the READ device IC-bus slave address (8Dh) followed by the register read-out, NAK (No Acknowledge) signal and the Stop Condition. For the IC-bus control register map, refer to Chapter 8 - page 25.
9.2 Synchronization processor
9.2.1 Synchronization signals The device has two inputs for TTL-level synchronization signals, both with hysteresis to avoid erratic detection and with a pull-down resistor. On H/ HVSyn input, pure horizontal or composite horizontal/vertical signal is accepted. On VSyn input, only pure vertical sync. signal is accepted. Both positive and negative polarities may be applied on either input, see Figure 2. Polarity detector and programmable inverter are provided on each of the two inputs. The signal applied on H/HVSyn pin, after polarity treatment, is directly lead to horizontal part and to an extractor of vertical sync. pulses, working on principle of integration, see Figure 3. The vertical sync. signal applied to the vertical deflection processor is selected between the signal extracted from the composite signal on H/HVSyn input and the one applied on VSyn input. The selector is controlled by VSyncSel IC-bus bit. Besides polarity detection, the device is capable of detecting presence of sync. signals on each of the inputs and at the output of vertical sync. extractor. The information from all detectors is provided in the IC-bus status register (5 flags: VDet, HVDet,
30/56
STV6889
VExtrDet, VPol, HVPol). The device is equipped with an automatic mode (switched on or off by VSyncAuto IC-bus bit) that also uses the detection information. Figure 2. Horizontal sync signal
Positive TH tPulseHSyn
9.2.2 Sync. presence detection flags The sync. signal presence detection flags in the status register (VDet, HVDet, VExtrDet) do not show in real time the presence or absence of corresponding sync. signal. They are latched to 1 as soon as a single sync. pulse is detected. In order to reset them to 0 (all at once), a 1 must be written into SDetReset IC-bus bit, the reset action taking effect with ACK bit of the IC-bus transfer to the register containing SDetReset bit. The detection circuits are ready to capture another event (pulse). See Note 59.
Negative
Figure 3. Extraction of V-sync signal from H/V-sync signal
H/V-sync TH Internal Integration textrV Extracted V-sync tPulseHSyn
9.2.3 MCU controlled sync. selection mode IC-bus bit VSyncAuto is set to 0. The MCU reads the polarity and signal presence detection flags, after setting the SDetReset bit to 1 and an appropriate delay, to obtain a true information of the signals applied, reads and evaluates this information and controls the vertical signal selector accordingly. The MCU has no access to polarity inverters, they are controlled automatically. See also chapter Chapter 8 - page 25.
9.2.4 Automatic sync. selection mode IC-bus bit VSyncAuto is set to 1. In this mode, the device itself controls the IC-bus bits switching the polarity inverters (HVPol, VPol) and the vertical sync. signal selector (VSyncSel), using the information provided by the detection circuitry. If both extracted and pure vertical sync. signals are present, the one already selected is maintained. No intervention of the MCU is necessary.
31/56
STV6889
9.3 Horizontal section
9.3.1 General The horizontal section consists of two PLLs with various adjustments and corrections, working on horizontal deflection frequency, then phase shifting and output driving circuitry providing H-drive signal on HOut pin. Input signal to the horizontal section is output of the polarity inverter on H/HVSyn input. The device ensures automatically that this polarity be always positive. 9.3.2 PLL1 The PLL1 block diagram is in Figure 5. It consists of a voltage-controlled oscillator (VCO), a shaper with adjustable threshold, a charge pump with inhibition circuit, a frequency and phase comparator and timing circuitry. The goal of the PLL1 is to make the VCO ramp signal match in frequency the sync. signal and to lock this ramp in phase to the sync. signal. On the screen, this offset results in the change of horizontal position of the picture. The loop, by tuning the VCO accordingly, gets and maintains in coincidence the rising edge of input sync. signal with signal REF1, deriving from the VCO ramp by a comparator with threshold adjustable through HPOS IC-bus control. The coincidence is identified and flagged by lock detection circuit on pin HLckVBk as well as by HLock IC-bus flag. The charge pump provides positive and negative currents charging the external loop filter on HPLL1F pin. The loop is independent of the trailing edge of sync. signal and only locks to its leading edge. By design, the PLL1 does not suffer from any dead band even while locked. The speed of the PLL1 depends on current value provided by the charge pump. While not locked, the current is very low, to slow down the changes of VCO frequency and thus protect the external power components at sync. signal change. In locked state, the currents are much higher, four different values being selectable via PLL1Pump IC-bus bits to provide a means to control the PLL1 speed by S/W. Lower value make the PLL1 slower, but more stable. Higher values make it faster and less stable. In general, the PLL1 speed should be higher for high deflection frequencies. The response speed and stability (jitter level) depend on the choice of external components making up the loop filter. A "CRC" filter is generally used (see Figure 4). Figure 4. H-PLL1 filter configuration
HPLL1F
9
R2
C1
C2
The PLL1 is internally inhibited during extracted vertical sync. pulse (if any) to avoid taking into account missing or wrong pulses on the phase comparator. Inhibition is obtained by forcing the charge pump output to high impedance state. The inhibition mechanism can be disabled through PLL1InhEn IC-bus bit. The Figure 7, in its upper part, shows the position of the VCO ramp signal in relation to input sync. pulse for three different positions of adjustment of horizontal position control HPOS.
32/56
STV6889
Figure 5. Horizontal PLL1 block diagram
PLL1InhEn V-sync (extracted) (IC) HLckVBk PLL1 Sync Polarity H/HVSyn 1 INPUT INTERFACE COMP Low Extracted V-sync REF1 PLL1Pump (IC) Blank 3 HLock (IC) HPLL1F RO CO HOscF 9 LOCK DETECTOR PLL INHIBITION CHARGE PUMP HPosF 10 HPOS (IC) VCO HOSC 8 6 4
High
SHAPER
Figure 6. Horizontal oscillator (VCO) schematic diagram
4 HOscF I0 (PLL1 filter) HPLL1F 9 VHO + 4 I0 RO 8 from charge pump 6 CO VHOThrHi VHOThrLo VCO discharge control VHOThrLo I0 2 VHOThrHi + +
RS Flip-Flop
9.3.3 Voltage controlled oscillator The VCO makes part of both PLL1 and PLL2 loops, being an "output" to PLL1 and "input" to PLL2. It delivers a linear sawtooth. Figure 6 explains its principle of operation. The linears are obtained by charging and discharging an external capacitor on pin CO, with currents proportional to the current forced through an external resistor on pin RO, which itself depends on the input tuning voltage VHO (filtered charge pump output). The rising and falling linears are limited by VHOThrLo and VHOThrHi thresholds filtered through HOscF pin.
At no signal condition, the VHO tuning voltage is clamped to its minimum (see section 6.4 - page 10), which corresponds to the free-running VCO frequency fHO(0). Refer to subsection 9.3.1 for formula to calculate this frequency using external components values. The ratio between the frequency corresponding to maximum VHO and the one corresponding to minimum VHO (free-running frequency) is about 4.5. This range can easily be increased in the application. The PLL1 can only lock to input frequencies falling inside these two limits.
33/56
STV6889
9.3.4 PLL2 The goal of the PLL2 is, by means of phasing the signal driving the power deflection transistor, to lock the middle of the horizontal flyback to a certain threshold of the VCO sawtooth. This internal threshold is affected by geometry phase corrections, like e.g., parallelogram. The PLL2 is fast enough to be able to follow the dynamism of phase modulation, this speed is strongly related to the value of the capacitor on HPLL2C. The PLL2 control current (see Figure 7) is significantly increased during discharge of vertical oscillator (during vertical retrace period) to be able to make up for the difference of dynamic phase at the bottom and at the top of the picture. The PLL2 control current is integrated on the external filter on pin HPLL2C to obtain smoothed voltage, used, in comparison with VCO ramp, as a threshold for H-drive rising edge generation. As both leading and trailing edges of the H-drive signal in the Figure 7 must fall inside the rising part of the VCO ramp, an optimum middle position of the threshold has been found to provide enough margin for horizontal output transistor storage time as well as for the trailing edge of H-drive signal with maximum duty cycle. Yet, the constraints thereof must be taken into account while considering the application frequency range and H-flyback duration. The Figure 7 also shows regions for rising and falling edges of the H-drive signal on HOut pin. As it is forced high during the H-flyback pulse and low during the VCO discharge period, no edge during these two events takes effect. The flyback input configuration is in Figure 8. 9.3.5 Dynamic PLL2 phase control The dynamic phase control of PLL2 is used to compensate for picture asymmetry versus vertical axis across the middle of the picture. It is done by modulating the phase of the horizontal deflection with respect to the incoming video (synchronization). Inside the device, the threshold VS(0) is compared with the VCO ramp, the PLL2 locking the middle of H-flyback to the moment of their match. The dynamic phase is obtained by modulation of the threshold by correction waveforms. Refer to Figure 14 and Chapter 7 - page 21. The correction waveforms have no effect in vertical middle of the screen (for middle vertical position). As they are summed, their effect on the phase tends to reach maximum span at top and bottom of the picture. As all the components of the resulting correction waveform (linear for parallelogram correction, parabola of 2nd order for Pin cushion asymmetry correction and half-parabolas of 4th order for corner corrections independently at the top and at the bottom) are generated from the output vertical deflection drive waveform, they all track with real vertical amplitude and position, thus being fixed on the screen. Refer to Chapter 8 - page 25 for details on IC-bus controls. Figure 7. Horizontal timing diagram
tHph
min max
H-sync (polarized) PLL1 lock REF1 (internal)
HPOS (IC)
max. med. min.
VHPosF
H-Osc (VCO)
max. med. min.
VHOThrHi VS(0)
VHOThrLo
7/8TH TH
PLL2 control current H-drive (on HOut) H-drive region H-drive region
ON
tS
+ ON OFF
tHoff
forced high forced low
tph(max)
inhibited
tS: HOT storage time
Figure 8. HFly input configuration
~500W HFly 12 ~20kW
ext.
int. GND
34/56
PLL2
H-fly-back
VThrHFly
PLL1
STV6889
9.3.6 Output Section The H-drive signal is inhibited (high level) during flyback pulse, and also when VCC is too low, when X-ray protection is activated (XRayAlarm IC-bus flag set to 1) and when IC-bus bit HBOutEn is set to 0 (default position). The duty cycle of the H-drive signal is controlled via IC-bus register HDUTY. This is overruled during soft-start and soft-stop procedures (see Section 9.3.7 and Figure 10). The PLL2 is followed by a rapid phase shifting which accepts the signal from H-moire canceller (see Section 9.3.8) The output stage consists of a NPN bipolar transistor, the collector of which is routed to HOut pin (see Figure 9). Figure 9. HOut configuration
26 HOut int. ext.
9.3.8 Horizontal moire cancellation The horizontal moire canceller is intended to blur a potential beat between the horizontal video pixel period and the CRT pixel width, which causes visible moire patterns in the picture. It introduces a microscopic indent on horizontal scan lines by injecting little controlled phase shifts to output circuitry of the horizontal section. Their amplitude is adjustable through HMOIRE IC-bus control. The behaviour of horizontal moire is to be optimized for different deflection design configurations using HMoireMode IC-bus bit. This bit is to be kept at 0 for common architecture (B+ and EHT common regulation) and at 1 for separated architecture (B+ and EHT each regulated separately). The maximum amplitude adjustable though HMOIRE IC-bus control is optimized according to selection by HMoireMode IC-bus bit: larger when B+ and EHT are each regulated separately, smaller when B+ and EHT are common regulation.
9.3.7 Soft-start and soft-stop on H-drive The soft-start and soft-stop procedure is carried out at each switch-on or switch-off of the H-drive signal, either via HBOutEn IC-bus bit or after reset of XRayAlarm IC-bus flag, to protect external power components. By its second function, the external capacitor on pin HPosF is used to time out this procedure, during which the duty cycle of Hdrive signal starts at its maximum (tHoff for soft start/stop in electrical specifications) and slowly decreases to the value determined by the control IC-bus register HDUTY (vice versa at soft-stop). This is controlled by voltage on pin HPosF. In case of supply voltage switch off, the transients on HOut and BOut have different characteristics. See Figure 10, Figure 11 and Section 9.8.1.
35/56
STV6889
Figure 10. Control of HOut and BOut at start/stop at nominal VCC
V(HPosF) VHPosF
minimum value HPOS range (IC) maximum value VHBNorm VBOn
VHOn
Soft start Start H-drv Start B-drv
Normal operation
Soft stop Stop B-drv Stop H-drv t
HOut H-duty cycle BOut (positive) B-duty cycle 0% 100%
Figure 11. Events triggering Soft start and Soft stop
maximum VCC fall down speed for correct operation VCCDis Soft start event Soft stop event VCCStop VCC
V[HPosF]
V[HPosF]
V(HPosF)
VHPosF VHBNorm VBOn
V(HPosF)
VHBNorm VBOn VHOn
VHPosF VHBNorm' VBOn' VHOn'
HBOutEn=1 XRayAlarm=0
t
t
VHOn
t
t HOut duty cycle 100% HOut duty cycle
t 100%
BOut duty cycle
0%
BOut duty cycle
0%
NOMINAL VCC
FALLING VCC
36/56
STV6889
9.4 Vertical section
9.4.1 General The goal of the vertical section is to drive vertical deflection output stage. It delivers a sawtooth waveform with an amplitude independent of deflection frequency, on which vertical linearity corrections of C- and S-type are superimposed (see
Chapter 7 - page 21).
fVO(0) =
150nF C(VCap)
. 100Hz
Block diagram is in Figure 12. The sawtooth is obtained by charging an external capacitor on pin VCap with controlled current and by discharging it via transistor Q1. This is controlled by the CONTROLLER. The charging starts when the voltage across the capacitor drops below VVOB threshold. The discharging starts either when it exceeds VVOT threshold (free run mode) or a short time after arrival of synchronization pulse. This time is necessary for the AGC loop to sample the voltage at the top of the sawtooth. The VVOB reference is routed out onto VOscF pin in order to allow for further filtration. The charging current influences amplitude of the sawtooth. Just before the discharge, the voltage across the capacitor on pin VCap is sampled and compared to VVOTref. The comparison error voltage is stored on a storage capacitor connected on pin VAGCCap. This voltage tunes gain of the transconductance amplifier providing the charging current in the next vertical period. Speed of this AGC loop depends on the storage capacitance on pin VAGCCap. The VLock IC-bus flag is set to 1 when the loop is stabilized, i.e. when the tops of saw tooth on pin VCap match VVOT value. On the screen, this corresponds to stabilized vertical size of picture. After a change of frequency on the sync. input, the stabilization time depends on the frequency difference and on the capacitor value. The lower its value, the shorter the stabilization time, but on the other hand, the lower the loop stability. A practical compromise is a capacitance of 470nF. The leakage current of this capacitor results in difference in amplitude between low and high frequencies. The higher its parallel resistance RL(VAGCCap), the lower this difference. When the synchronization pulse is not present, the charging current is fixed. As a consequence, the free-running frequency fVO(0) only depends on the value of the capacitor on pin VCap. It can be roughly calculated using the following formula
The frequency range in which the AGC loop can regulate the amplitude also depends on this capacitor. The vertical sawtooth with regulated amplitude is lead to amplitude control stage. The discharge exponential is replaced by VVOB level, which, under control of the CONTROLLER, creates a rapid falling edge and a flat part before beginning of new ramp. The AGC output signal passes through gain and position adjustment stages controlled through VSIZE and VPOS IC-bus registers. The resulting signal serves as input to all geometry correction circuitry including EW-drive signal, horizontal phase modulation and dynamic correction outputs. 9.4.2 S and C corrections For the sake of vertical picture linearity, the S- and C-corrections are now superimposed on the linear ramp signal. They both track with VSIZE and VPOS adjustments to ensure unchanged linearity on the screen at changes of vertical size or vertical position. As these corrections are not included in the AGC loop, their adjustment via CCOR and SCOR IC-bus registers, controlling shape of vertical output sawtooth affects by principle its peak-topeak amplitude. However, this stage is conceived in a way that the amplitude be independent of these adjustments if VSIZE and VPOS registers are set to their medium values. 9.4.3 Vertical breathing compensation The signal provided with the linearity corrections is amplitude affected in a gain control stage, ruled by the voltage on VEHTIn input and its IC-bus control VEHTG. 9.4.4 Vertical after-gain and offset control Another gain control is applied via VSAG IC-bus register. Then an offset is added, its amount corresponding to VPOF IC-bus register value. These two controls result in size and position changes with no effect on shape of output vertical sawtooth or any geometry correction signal.
37/56
STV6889
9.4.5 Vertical moire To blur potential moire patterns due to interaction of deflection lines with CRT mask grid, the picture position is to be slightly alternated at frame frequency. For this purpose, a square waveform at half-frame frequency is superimposed on the output waveform. Its amplitude is adjustable through VMOIRE IC-bus control. Figure 12. Vertical section block diagram
Charge current OSC Cap. VVOTref VCap 22 Sampling Discharge VSyn 2 Synchro Polarity Vmidref Vmidref To geometry processing sawtooth R discharge Vmidref VVOB 19 VOscF VEHTIn 18 VVEHTnull VEHTG (IC) SCOR (IC) VMOIRE (IC) S-correction VOut 23 VPOF (IC) VPOS (IC) VSAG (IC) C-correction VSIZE (IC) VPOS (IC) Internal V-ramp Controller Q1 R 20 VAGCCap Sampling Capacitance Trans-conductance amplifier
9.4.6 Biasing of vertical booster The biasing voltage for external DC-coupled vertical power amplifier is to be derived from VRefO voltage provided on pin RefOut, using a resistor divider, this to ensure the same temperature drift of mean (DC) levels on both differential inputs and to compensate for spread of VRefO value (and so mean output value) between particular devices.
CCOR (IC)
38/56
STV6889
9.5 EW drive section
The goal of the EW drive section is to provide, on pin EWOut, a waveform which, used by an external DC-coupled power stage, serves to compensate for those geometry errors of the picture that are symmetric versus vertical axis across the middle of the screen. The waveform consists of an adjustable DC value, corresponding to horizontal size, a parabola of 2nd order for "pin cushion" correction, a linear for "keystone" correction, independent half-parabolas of 4th order for top and bottom corner corrections, Sshape for "S" correction and W shape for "W" correction. All of them are adjustable via IC-bus, see
Chapter 8 - page 25.
Refer to Figure 14, Figure 15 and chapter Chapter 7 page 21. The adjustments of these correction waveforms have no effect in the middle of the vertical scan period (if the VPOS control is adjusted to its medium value). As they are summed, the resulting waveform tends to reach its maximum span at top and bottom of the picture. The voltage at the EWOut is top and bottom limited (see parameter VEW). According to Figure 15, especially the bottom limitation seems to be critical for maximum horizontal size (minimum DC). Actually it is not critical since the parabola component must always be applied to obtain a picture without pin cushion distortion. As all the components of the resulting correction waveform are generated from an internal linear vertical sawtooth waveform bearing VSIZE and VPOS adjustments, they all track with vertical amplitude and position, thus being fixed vertically on the screen. They are not affected by C- and S-cor-
rections, by prescale adjustments (VSAG and VPOF), by vertical breathing compensation and by vertical moire cancellation. The sum of components other than DC is conditionally affected by value in HSIZE IC-bus control in reversed sense. Refer to electrical specifications for value. This tracking with HSIZE can be switched off by EWTrHSize IC-bus bit. The DC value, adjusted via HSIZE control, is also affected by voltage on HEHTIn input, thus providing a horizontal breathing compensation. The effect of this compensation is controlled by HEHTG. The resulting waveform is conditionally multiplied with voltage on HPLL1F, which depends on frequency. Refer to electrical specifications for values. This tracking with frequency provides a rough compensation of variation of picture geometry with frequency and allows to fix the adjustment ranges of IC-bus controls throughout the operating range of horizontal frequencies. It can be switched off by EWTrHFr ICbus bit (off by default). The functionality is explained in Figure 13. The upper part gives the influence on DC component, the lower part on AC component, showing also the tracking with HSIZE. Grey zones give the total span of breathing correction using the whole range of input operating voltage on HEHTIn input and whole range of adjustment of HEHTG register. The EW waveform signal is buffered by an NPN emitter follower, the emitter of which is directly routed to EWOut output. It is internally biased (see electrical specifications for current value).
39/56
STV6889
Figure 13. Tracking of EWOut signal with frequency
HSIZE=max VEW-DC VEW-DC
breathing
H
E S IZ
=m
ax
breathing
breathing
breathing
VEW-base min
HSIZE=min
VEW-base min
HSIZE=min
EWTrHFr=0
min
EWTrHFr=1 VHOThrfr max
min
VHOThrfr max VHO
VHO
HSIZE=min
breathing
breathing
VEW-AC
HSIZE=max
breathing
VEW-AC
=m ZE SI H
in
breathing
H
E SIZ
ax =m
0 min
EWTrHSize=1 EWTrHFr=0 VHOThrfr max VHO
0 min
EWTrHSize=1 EWTrHFr=1 VHOThrfr max VHO
40/56
STV6889
Figure 14. Geometric corrections' schematic diagram
Vmidref
VDC-AMP
VDyCorPol -1
VVD-DC VDyCor 32
X2
EWTrHSize
Int. V-ramp (linear, before corrections)
X4 Keystone KEYST HSIZE
tracking
H-size control
DC 0...2.5V
Breathing
HEHTG VHEHTnull 17
Pin cushion
PCC
Top corner
TCC VEW(max) 0V
HEHTIn
Bot. corner
BCC
EWOut "W" EWWC 0V EWSC VEW-base VEW(min) 24
X3
"S"
Parallelogram
PARAL
Tracking with hor. frequency
1 9 0V HPLL1F
EWTrHFr 0 VHOThrfr To HPLL2
Pin cushion asymmetry Top corner asymmetry Bottom corner asymmetry
PCAC
Controls: 1-quadrant 2-quadrant
TCAC Internal dynamic phase waveform BCAC
41/56
STV6889
Figure 15. EWOut output waveforms
HSIZE (IC)
max.
7Fh
non-linear region non-linear region
max
Tracking with frequency off. (EWTrHFr = 0) HEHTG (IC)
VEW-Key
VEW-PCC
VEW-TCor VEW-BCor
VEW-S
VEW-W
00h
VEW
00h
mid.
7Fh 00h 7Fh
min Top Bottom
min.
Keystone alone
PCC alone
Corners alone
S alone
W alone
Breathing compensation on DC
VHEHT(max)
VHEHT(min)
V(VCap)
Vertical sawtooth
0 TVR 0 TVR 0 TVR 0 TVR 0 TVR
tVR
42/56
VHEHTnull
VRefO
0
VHEHT
VEW-DC
STV6889
9.6 Dynamic correction outputs section
9.6.1 Vertical dynamic correction output
VDyCor
A parabola at vertical deflection frequency is available on pin VDyCor. Its amplitude is adjustable via VDC-AMP IC-bus control and polarity controlled via VDyCorPol IC-bus bit. It tracks with real vertical amplitude and position. It is not affected by C-
and S-corrections or breathing compensation. It does not track with Vertical size after-gain (Sad1Dh) nor with Vertical position offset (Sad1Eh) adjustments. The use of both correction waveforms is up to the application (e.g. dynamic focus, dynamic brightness control).
9.7 DC/DC controller section
The section is designed to control a switch-mode DC/DC converter. A switch-mode DC/DC convertor generates a DC voltage from a DC voltage of different value (higher or lower) with little power losses. The DC/DC controller is synchronized to horizontal deflection frequency to minimize potential interference into the picture. Its operation is similar to that of standard UC3842. The schematic diagram of the DC/DC controller is in Figure 16. The BOut output controls an external switching circuit (a MOS transistor) delivering pulses synchronized on horizontal deflection frequency, the phase of which depends on H/W and IC-bus configuration. See the table at the end of this chapter. Their duration depends on the feedback provided to the circuit, generally a copy of DC/DC converter output voltage and a copy of current passing through the DC/DC converter circuitry (e.g. current through external power component). The polarity of the output can be controlled by BOutPol IC-bus bit. A NPN transistor open-collector is routed out to the BOut pin. During the operation, a sawtooth is to be found on pin BISense, generated externally by the application. According to BOutPh IC-bus bit, the R-S flipflop is set either at H-drive signal edge (rising or falling, depending on BOHEdge IC-bus bit), or a certain delay (tBTrigDel) after middle of H-flyback, or at horizontal frequency divided by two (phase corresponding to VHOThrHi on the VCO ramp). The output is set On at the end of the short pulse generated by the monostable trigger. Timing of reset of the R-S flip-flop affects duty cycle of the output square signal and so the energy transferred from DC/DC converter input to its output. A reset edge is provided by comparator C2 if the voltage on pin BISense exceeds the internal threshold VThrBIsCurr. This represents current limitation if a voltage proportional to the current through the power component or deflection stage is available on pin BISense. This threshold is affected by voltage on pin HPosF, which rises at soft start and descends at soft stop. This ensures self-contained soft control of duty cycle of the output signal on pin
BOut. Refer to Figure 10. Another condition for reset
of the R-S flip-flop, OR-ed with the one described before, is that the voltage on pin BISense exceeds the voltage VC2, which depends on the voltage applied on input BRegIn of the error amplifier O1. The two voltages are compared, and the reset signal generated by the comparator C1. The error amplifier amplifies (with a factor defined by external components) the difference between the input voltage proportional to DC/DC convertor output voltage and internal reference VBReg. The internal reference and so the output voltage is IC-bus adjustable by means of BREF IC-bus control. Both step-up (DC/DC converter output voltage higher than its input voltage) and step-down (output voltage lower than input) can be built. 9.7.1 Synchronization of DC/DC controller For sake of application flexibility, the output drive signal on BOut pin can be synchronized with one of four events in Table 9. For the first line case, the synchronization instant is every second top of horizontal VCO saw tooth. See Figure 7. 9.7.2 Soft-start and soft-stop on B-drive The soft-start and soft-stop procedure is carried out at each switch-on or switch-off of the B-drive signal, either via HBOutEn IC-bus bit or after reset of XRayAlarm IC-bus flag, to protect external power component. See Figure 10 and sub chapter Safety functions on page 45. The drive signal on BOut pin can be switched off alone by means of BMute IC-bus bit, without switching off the drive signal on pin HOut. The switch-off is quasi-immediate, without the soft-stop procedure. At switching back on, the soft-start of the DC/DC controller is performed, timed by an internal timing circuit, see Figure 16. When BSafeEn IC-bus bit is enabled, the drive signal on BOut pin will go off as soon as the horizontal PLL1 indicates unlocked state, without the soft-stop. Resuming of locked state will initiate the soft-start mechanism of the DC/DC controller, timed by an internal timing circuit.
43/56
STV6889
Table 9. IDC/DC controller Off-to-On edge timing
BOutPh (Sad07h/D7) 0 0 1 1 BOHEdge (Sad17h/D3) 1 0 0 1 Timing of Off-to-On transition on BOut output VCO ramp top at Horizontal frequency divided by two Middle of H-flyback plus tBTrigDel Falling edge of H-drive signal Rising edge of H-drive signal
Figure 16. DC/DC converter controller block diagram
0 1 1 0
H-drive edge
BOutPh (IC)
Monostable
H-fly-back (+delay) VCO Feedback VBReg 15 BRegIn + O1 2
BOHEdge (IC)
0 1
~500ns I1 I2 N type VCC
2R
R
VC2
C1 + C2 + + C3 -
-
S R
28 BOut Q P type BOutPol (IC) B-drive inhibition (safety functions) I3
14 BComp VThrBIsCurr Safety block Soft start 16 BISense
10 HPosF
timing
B-drive protection at H-unlock (safety functions)
44/56
STV6889
9.8 Miscellaneous
9.8.1 Safety functions The safety functions comprise supply voltage monitoring with appropriate actions, soft start and soft stop features on H-drive and B-drive signals on HOut and BOut outputs, B-drive cut-off at unlock condition and X-ray protection. For supply voltage supervision, refer to subsection 9.1.1 and Figure 1. A schematic diagram putting together all safety functions and composite PLL1 lock and V-blanking indication is in Figure 17. 9.8.1.1 Soft start and soft stop function For soft start and soft stop features for H-drive and B-drive signal, refer to subsection 9.3.7 and subsection 9.7 , respectively. See also the Figure 10 and Figure 11. Regardless why the H-drive or B-drive signal are switched on or off (IC-bus command, power up or down, X-ray protection), the signals always phase-in and phase-out in the way drawn in the figures, the first to phase-in and last to phase-out being the H-drive signal, which is to better protect the power stages at abrupt changes like switch-on and off. The timing of phase-in and phase-out depends on the capacitance connected to HPosF pin which is virtually unlimited for this function. However, as it has a dual function (see subsection 9.3.2 ), a compromise thereof is to be found. The soft stop at power down condition can be considered as a special case. As at this condition the thresholds VHOn, VBOn and VHBNorm depend on the momentary level of supply voltage (marked VHOn', VBOn', VHBNorm' in Figure 11), the timing of soft stop mechanism depends, apart from the capacitance on HPosF, also on the falling speed of supply voltage. The device is capable of performing a correct soft stop sequence providing that, at the moment the supply voltage reaches VCCStop, the voltage on HPosF has already fallen below VHOn (Section 9.8). 9.8.1.2 B-drive cut-off at unlock condition This function is described in subsection 9.7.2 . 9.8.1.3 X-ray protection The X-ray protection is activated if the voltage level on XRay input exceeds VThrXRay threshold and if the VCC is higher than the voltage level VCCXRayEn. As a consequence, the H-drive and B-drive signals on HOut and BOut outputs are inhibited (switched off) after a 2-horizontal deflection line delay provided to avoid erratic excessive X-ray condition detection at short parasitic spikes. The XRayAlarm IC-bus flag is set to 1 to inform the MCU. This protection is latched; it may be reset either by VCC drop or by IC-bus bit XRayReset (see Chapter 8 - page 25).
45/56
STV6889
Figure 17. Safety functions - block diagram
BSafeEn IC BMute IC H-lock detector HBOutEn IC VCC VCCEn VCCDis + _ H-VCO discharge control VCC supervision 0 = Off 1 = On = start = stop HPosF 10 (timing) SOFT START & STOP INHIBITION CONTROL PLL1 PLL2 DC/DC
B-drive protection at H-unlock
XRayAlarm XRayReset IC XRay 25 VThrXRay VCC VCCXRayEn HFly 12 VThrHFly VOutEn IC BlankMode IC HLockEn IC H-lock detector L1=No blank/blank level L2=H-lock/unlock level HLock V-sawtooth discharge V-sync IC IC bit/flag Int. signal X Pin R S Q IC B-drive inhibition In + _ R Q IC
:2
Out
S B-drive inhibit H-drive inhibit H-drive inhibition (overrule)
Enable
+ _
V-drive inhibition + _
S
HLckVBk 3 L3=L1+L2
46/56
STV6889
9.8.2 Composite output HLckVBk The composite output HLckVBk provides, at the same time, information about lock state of PLL1 and early vertical blanking pulse. As both signals have two logical levels, a four level signal is used to define the combination of the two. Schematic diagram putting together all safety functions and composite PLL1 lock and V-blanking indication is in Figure 17, the combinations, their respective levels and the HLckVBk configuration in Figure 18. The early vertical blanking pulse is obtained by a logic combination of vertical synchronization pulse and pulse corresponding to vertical oscillator discharge. The combination corresponds to the drawing in Figure 18. The blanking pulse is started with Figure 18. Levels on HLckVBk composite output
VCC L1 - No blank/blank level L2 - H-lock/unlock level
the leading edge of any of the two signals, whichever comes first. The blanking pulse is ended with the trailing edge of vertical oscillator discharge pulse. The device has no information about the vertical retrace time. Therefore, it does not cover, by the blanking pulse, the whole vertical retrace period. By means of BlankMode IC-bus bit, when at 1 (default), the blanking level (one of two according to PLL1 status) is made available on the HLckVBk permanently. The permanent blanking, irrespective of the BlankMode IC-bus bit, is also provided if the supply voltage is low (under VCCEn or VCCDis thresholds), if the X-ray protection is active or if the V-drive signal is disabled by VOutEn IC-bus bit.
3
HLckVBk L1(L)+L2(H)
L1(H)+L2(H)
ISinkLckBk
VOLckBk L1(L)+L2(L) V-early blanking HPLL1 locked No Yes
L1(H)+L2(L)
Yes Yes
No No
Yes No
47/56
STV6889
Figure 19. Ground layout recommendations
STV6889
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
General Ground
48/56
STV6889
49/56
STV6889
10 INTERNAL SCHEMATICS
Figure 20. Figure 23.
VCC 5V
VRefO
H/HVSyn 1
200W
5 HPLL2C
Applies also for pin 2 (VSyn)
Figure 21.
VCC
Figure 24.
VCC VRefO VRefO
CO HLckVBk 3 6
Figure 22.
Figure 25.
VCC 12V VRefO VRefO
RO 8 HOscF 4
50/56
3
STV6889
Figure 26. Figure 29.
HPLL1F 9
VCC
BComp 14
Figure 27.
Figure 30.
12V VRefO
VCC
HPosF 10
BRegIn 15
Figure 28.
Figure 31.
VCC VCC BISense 16 HFly 12
51/56
3
STV6889
Figure 32. Figure 35.
VCC
VCC
22 VCap
HEHTIn 17
Applies also for pin 18 (VEHTIn)
Figure 33.
VCC VRefO
Figure 36.
VCC
VOut VOscF 19 23
Figure 34.
Figure 37.
VCC
VCC
VAGCCap 20
EWOut 24
Applies also for pin 32 (VDyCor)
52/56
3
STV6889
Figure 38.
VCC
XRay 25
Figure 39.
VCC
HOut 26
Applies also for pin 28 (BOut)
Figure 40.
VCC
SCL 30
Applies also for pin 31 (SDA)
53/56
3
STV6889
11 PACKAGE MECHANICAL DATA
32 PINS - PLASTIC SHRINK
E E1 A2
A1
A
C L B B1 e Stand-off eA eB D 32 17 1 16 Millimeters Min. 3.556 0.508 3.048 0.356 0.762 .203 27.43 9.906 7.620 3.556 0.457 1.016 0.254 27.94 10.41 8.890 1.778 10.16 12.70 2.540 3.048 3.810 0.100 0.120 4.572 0.584 1.397 0.356 28.45 11.05 9.398 Typ. 3.759 Max. 5.080 Min. 0.140 0.020 0.120 0.014 0.030 0.008 1.080 0.390 0.300 0.140 0.018 0.040 0.010 1.100 0.410 0.350 0.070 0.400 0.500 0.150 0.180 0.023 0.055 0.014 1.120 0.435 0.370
Dimensions A A1 A2 B B1 C D E E1 e eA eB L
Inches Typ. 0.148 Max. 0.200
54/56
4
STV6889
12 GLOSSARY
AC ACK AGC COMP CRT DC EHT EW H/W HOT I2C
IIC Alternate Current ACKnowledge bit of IC-bus transfer Automatic Gain Control COMParator Cathode Ray Tube Direct Current Extra High Voltage East-West HardWare Horizontal Output Transistor Inter-Integrated Circuit Inter-Integrated Circuit Micro-Controller Unit Negated AND (logic operation) Negative-Positive-Negative OSCillator Phase-Locked Loop Positive-Negative-Positive REFerence Reset-Set SoftWare Transistor Transistor Logic Voltage-Controlled Oscillator
MCU NAND NPN OSC PLL PNP REF RS, R-S S/W TTL VCO
55/56
5
STV6889
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
56/56
6

▲Up To Search▲

Price & Availability of STV6889

	To Download STV6889 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .