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UC1823 UC2823 UC3823
High Speed PWM Controller
FEATURES
* * * * * * * * * * * Compatible with Voltage or Current-Mode Topologies Practical Operation @ Switching Frequencies to 1.0MHz 50ns Propagation Delay to Output High Current Totem Pole Output (1.5A peak) Wide Bandwidth Error Amplifier Fully Latched Logic with Double Pulse Suppression Pulse-by-Pulse Current Limiting Soft Start/Max. Duty Cycle Control Under-Voltage Lockout with Hysteresis Low Start Up Current (1.1mA) Trimmed Bandgap Reference (5.1V 1%)
DESCRIPTION
The UC1823 family of PWM control ICs is optimized for high frequency switched mode power supply applications. Particular care was given to minimizing propagation delays through the comparators and logic circuitry while maximizing bandwidth and slew rate of the error amplifier. This controller is designed for use in either current-mode or voltage-mode systems with the capability for input voltage feed-forward. Protection circuitry includes a current limit comparator, a TTL compatible shutdown port, and a soft start pin which will double as a maximum duty cycle clamp. The logic is fully latched to provide jitter free operation and prohibit multiple pulses at the output. An under-voltage lockout section with 800mV of hysteresis assures low start up current. During under-voltage lockout, the output is high impedance. The current limit reference (pin 11) is a DC input voltage to the current limit comparator. Consult specifications for details. These devices feature a totem pole output designed to source and sink high peak currents from capacitive loads, such as the gate of a power MOSFET. The on state is defined as a high level.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Pins 15, 13) . . . . . . . . . . . . . . . . . . . . . . . . 30V Output Current, Source or Sink (Pin14) DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A Pulse (0.5s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0A Analog Inputs (Pins 1, 2, 7, 8, 9, 11) . . . . . . . . . . . -0.3V to +6V Clock Output Current (Pin 4) . . . . . . . . . . . . . . . . . . . . . . . -5mA Error Amplifier Output Current (Pin 3) . . . . . . . . . . . . . . . . 5mA Soft Start Sink Current (Pin 8) . . . . . . . . . . . . . . . . . . . . . 20mA Oscillator Charging Current (Pin 5) . . . . . . . . . . . . . . . . . . -5mA Power Dissipation at TA = 60 C . . . . . . . . . . . . . . . . . . . . . 1W Storage Temperature Range . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 seconds) . . . . . . . . . . 300C Note: All voltages are with respect to ground, Pin 10. Currents are positive into the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages.
BLOCK DIAGRAM
3/97 1
UC1823 UC2823 UC3823 CONNECTION DIAGRAMS
DIL-16, SOIC-16 (TOP VIEW) J or N, DW Package PLCC-20, LCC-20 (TOP VIEW) Q, L Package
PACKAGE PIN FUNCTION FUNCTION PIN
N/C Inv. N.I. E/A Out Clock N/C RT CT Ramp Soft start N/C ILIM/S.D. Ground ILIM REF PWR Gnd N/C VC OUT VCC VREF 5.1V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
ELECTRICAL CHARACTERISTICS: Unless otherwise noted, these specifications apply for RT = 3.65k, CT =
1nF, VCC = 15V, 0C < TA < +70C for the UC3823, -25C < TA < +85C for the UC2823, and -55C < TA < +125C for the UC1823, TA = TJ.
PARAMETER Reference Section Output Voltage Line Regulation Load Regulation Temperature Stability* Total Output Variation* Output Noise Voltage* Long Term Stability* Short Circuit Current Oscillator Section Initial Accuracy* Voltage Stability* Temperature Stability* Total Variation* Clock Out High Clock Out Low Ramp Peak* Ramp Valley* Ramp Valley to Peak* 2.6 0.7 1.6 TJ=25C 10 < VCC < 30V TMIN UC2823 TYP MAX MIN UC3823 TYP MAX UNITS
* These parameters are guaranteed by design but not 100% tested in production.
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UC1823 UC2823 UC3823 ELECTRICAL CHARACTERISTICS: Unless otherwise noted, these specifications apply for RT = 3.65k, CT = 1nF, VCC
= 15V, 0C < TA < +70C for the UC3823, -25C < TA < +85C for the UC2823, and -55C < TA < +125C for the UC1823, TA = TJ.
PARAMETER Error Amplifier Section Input Offset Voltage Input Bias Current Input Offset Current Open Loop Gain CMRR PSRR Output Sink Current Output Source Current Output High Voltage Output Low Voltage Unity Gain Bandwidth* Slew Rate* PWM Comparator Section Pin 7 Bias Current Duty Cycle Range Pin 3 Zero D.C. Threshold Delay to Output* Soft-Start Section Charge Current Discharge Current Current Limit/Shutdown Section Pin 9 Bias Current Current Limit Offset Current Limit Common Mode Range (VPIN 11) Shutdown Threshold Delay to Output* Output Section Output Low Level Output High Level Collector Leakage Rise/Fall Time* Under-Voltage Lockout Section Start Threshold UVLO Hysteresis Supply Current Start Up Current ICC VCC = 8V VPIN 1, VPIN 7, VPIN 9 =0V, VPIN 2 = 1V 1.1 22 2.5 33 1.1 22 2.5 33 mA mA 8.8 0.4 9.2 0.8 9.6 1.2 8.8 0.4 9.2 0.8 9.6 1.2 V V IOUT = 20mA IOUT = 200mA IOUT = -20mA IOUT = -200mA VC = 30V CL = 1nF 13.0 12.0 0.25 1.2 13.5 13.0 100 30 500 60 0.40 2.2 13.0 12.0 0.25 1.2 13.5 13.0 100 30 500 60 0.40 2.2 V V V V A ns 0 < VPIN 9 < 4V VPIN 11 = 1.1V 1.0 1.25 1.40 50 10 15 1.25 1.55 80 1.0 1.25 1.40 50 10 15 1.25 1.55 80 A mV V V ns VPIN 8 = 0.5V VPIN 8 = 1V 3 1 9 20 3 1 9 20 A mA VPIN 7 = 0V VPIN 7 = 0V 0 1.1 1.25 50 80 -1 -5 80 0 1.1 1.25 50 80 -1 -5 85 A % V ns 1 < VO < 4V 1.5 < VCM < 5.5V 10 < VCC < 30V VPIN 3 =1V VPIN 3 = 4V IPIN 3 = -0.5mA IPIN 3 = 1mA 60 75 85 1 -0.5 4.0 0 3 6 0.6 0.1 95 95 110 2.5 -1.3 4.7 0.5 5.5 12 5.0 1.0 10 3 1 60 75 85 1 -0.5 4.0 0 3 6 0.6 0.1 95 95 110 2.5 -1.3 4.7 0.5 5.5 12 5.0 1.0 15 3 1 mV A A dB dB dB mA mA V V MHz V/S TEST CONDITIONS MIN UC1823 UC2823 TYP MAX MIN UC3823 TYP MAX UNITS
* These parameters are guaranteed by design but not 100% tested in production.
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UC1823 UC2823 UC3823 UC1823 PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS
High speed circuits demand careful attention to layout and component placement. To assure proper performance of the UC1823, follow these rules. 1) Use a ground plane. 2) Damp or clamp parasitic inductive kick energy from the gate of driven MOSFET. Don't allow the output pins to ring below ground. A series gate resistor or a shunt 1 Amp Schottky diode at the output pin will serve this purpose. 3) Bypass VCC, VC, and VREF. Use 0.1F monolithic ceramic capacitors with low equivalent series inductance. Allow less than 1 cm of total lead length for each capacitor between the bypassed pin and the ground plane. 4) Treat the timing capacitor, CT, like a bypass capacitor.
ERROR AMPLIFIER CIRCUIT
Simplified Schematic
Open Loop Frequency Response
Unity Gain Slew Rate
PWM APPLICATIONS
Conventional (Voltage Mode) Current-Mode
* A small filter may be required to suppress switch
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UC1823 UC2823 UC3823 OSCILLATOR CIRCUIT
SYNCHRONIZED OPERATION
Two Units in Close Proximity
Generalized Synchronization
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UC1823 UC2823 UC3823 CONSTANT VOLT-SECOND CLAMP CIRCUIT
The circuit shown here will achieve a constant volt-second product clamp over varying input voltages. The ramp generator components, RT and CR are chosen so that the ramp at Pin 9 crosses the 1V threshold at the same time the desired maximum volt-second product is reached. The delay through the inverter must be such that the ramp capacitor can be completely discharged during the minimum deadtime.
OUTPUT SECTION
FEED FORWARD TECHNIQUE FOR OFF-LINE VOLTAGE MODE APPLICATION
UNITRODE CORPORATION 7 CONTINENTAL BLVD. * MERRIMACK, NH 03054 TEL. (603) 424-2410 * FAX (603) 424-3460
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Copyright (c) 1999, Texas Instruments Incorporated

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