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| IRF710 Data Sheet June 1999 File Number 2310.3 2.0A, 400V, 3.600 Ohm, N-Channel Power MOSFET This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. They can be operated directly from integrated circuits. Formerly developmental type TA17444. Features * 2.0A, 400V * rDS(ON) = 3.600 * Single Pulse Avalanche Energy Rated * SOA is Power Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" Ordering Information PART NUMBER IRF710 PACKAGE TO-220AB BRAND IRF710 Symbol D NOTE: When ordering, include the entire part number. G S Packaging JEDEC TO-220AB TOP VIEW SOURCE DRAIN GATE DRAIN (FLANGE) 4-220 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 IRF710 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified IRF710 400 400 2 1.2 5 20 36 0.29 120 -55 to 150 300 260 UNITS V V A A A V W W/oC mJ oC oC oC Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS ID(ON) IGSS rDS(ON) gfs tD(ON) tr tD(OFF) tf Qg(TOT) Qgs Qgd CISS COSS CRSS LD Measured From the Contact Screw on Tab to Center of Die Modified MOSFET Symbol Showing the Internal Device's Measured From the Drain Inductances D Lead, 6mm (0.25in) From Package to Center of Die LD Measured From the Source Lead, 6mm (0.25in) From Header to Source Bonding Pad G LS S TEST CONDITIONS VGS = 0V, ID = -250A (Figure 10) VGS = VDS, ID = 250A VDS = Rated BVDSS, VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 125oC VDS > ID(ON) x rDS(ON)MAX, VGS = 10V VGS = 20V VGS = 10V, ID = 1.1A (Figures 8, 9) VDS 10V, ID = 1.2A (Figure 12) VDD = 50V, ID 5.6A, RG = 24, RL = 8.9, VGS = 10V MOSFET Switching Times are Essentially Independent of Operating Temperature VGS = 10V, ID = 2.0A, VDS = 0.8 x Rated BVDSS Ig(REF) = 1.5mA (Figure 14) Gate charge is Essentially Independent of Operating Temperature VGS = 0V, VDS = 25V, f = 1.0MHz (Figure 11) MIN 400 2.0 2.0 1.0 - TYP 3.3 1.5 8.0 10 21 11 7.0 1.2 4.0 135 35 8.0 3.5 MAX 4.0 250 1000 500 3.6 12 15 32 17 12 - UNITS V V A A A nA S ns ns ns ns nC nC nC pF pF pF nH Drain to Source Breakdown Voltage Gate to Threshold Voltage Zero-Gate Voltage Drain Current On-State Drain Current (Note 2) Gate to Source Leakage Forward Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge Gate to Drain "Miller" Charge Input Capacitance Output Capacitance Reverse-Transfer Capacitance Internal Drain Inductance - 4.5 - nH Internal Source Inductance LS - 7.5 - nH Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient RJC RJA Free Air Operation - - 3.5 62.5 oC/W oC/W 4-221 IRF710 Source to Drain Diode Specifications PARAMETER Continuous Source to Drain Current Pulse Source to Drain Current (Note 3) SYMBOL ISD ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode G D MIN - TYP - MAX 2.0 5.0 UNITS A A S Source to Drain Diode Voltage (Note 2) Reverse Recovery Time Reverse Recovered Charge NOTES: VSD trr QRR TJ = 25oC, ISD = 2.0A, VGS = 0V (Figure 13) TJ = 25oC, ISD = 2.0A, dISD/dt = 100A/s TJ = 25oC, ISD = 2.0A, dISD/dt = 100A/s 110 0.40 - 1.6 520 1.4 V ns C 2. Pulse Test: Pulse width 300s, duty cycle 2%. 3. Repetitive Rating: Pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 50V, starting TJ = 25oC, L = 53H, RG = 25, peak IAS = 2A. Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 Unless Otherwise Specified 2.0 0.8 0.6 0.4 0.2 0 ID, DRAIN CURRENT (A) 0 50 100 150 1.6 1.2 0.8 0.4 0 25 50 75 100 125 TC , CASE TEMPERATURE (oC) 150 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE 10 ZJC, THERMAL IMPEDANCE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 0.5 1 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE 0.1 PDM t1 t2 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC + TC 10-3 10-2 0.1 1 10 t1, RECTANGULAR PULSE DURATION (s) 10-2 10-5 10-4 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 4-222 IRF710 Typical Performance Curves 102 OPERATION IN THIS REGION IS LIMITED BY rDS(ON) ID, DRAIN CURRENT (A) Unless Otherwise Specified (Continued) 3.0 10V 2.4 6.0V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 5.5V ID, DRAIN CURRENT (A) 10 10s 100s 1 1ms 10ms 0.1 TC = 25oC TJ = MAX RATED SINGLE PULSE 1 102 10 VDS, DRAIN TO SOURCE VOLTAGE (V) DC 1.8 VGS = 5.0V 1.2 4.5V 4.0V 0.6 10-2 103 0 0 40 80 120 160 VDS, DRAIN TO SOURCE VOLTAGE (V) 200 FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS IDS(ON), DRAIN TO SOURCE CURRENT (A) 3.0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX ID, DRAIN CURRENT (A) 2.4 5.5V 1.8 VGS = 5.0V 1.2 4.5V 4.0V 0 0 3 6 9 12 VDS, DRAIN TO SOURCE VOLTAGE (V) 15 10V 6.0V 10 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDS 50V 1 0.1 TJ = 150oC TJ = 25oC 0.6 10-2 0 2 4 6 8 VSD, GATE TO SOURCE VOLTAGE (V) 10 FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS RDS(ON), NORMALIZED DRAIN TO SOURCE ON RESISTANCE VOLTAGE 30 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX rDS(ON), DRAIN TO SOURCE 24 ON RESISTANCE () VGS = 10V 3.0 2.4 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX ID = 2.0A, VGS = 10V 18 1.8 12 1.2 6 VGS = 20V 0.6 0 0 1 2 3 ID, DRAIN CURRENT (A) 4 5 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 TJ, JUNCTION TEMPERATURE (oC) FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 4-223 IRF710 Typical Performance Curves 1.25 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A 1.15 C, CAPACITANCE (pF) 400 Unless Otherwise Specified (Continued) 500 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGS 1.05 300 CISS 200 COSS 100 CRSS 0.95 0.85 0.75 -60 -40 -20 0 20 40 60 80 100 120 140 160 0 TJ, JUNCTION TEMPERATURE (oC) 1 2 5 10 2 5 VDS, DRAIN TO SOURCE VOLTAGE (V) 102 FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 2.0 gfs, TRANSCONDUCTANCE (S) TJ = 25oC ISD, SOURCE TO DRAIN CURRENT (A) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 1.6 10 PULSE DURATION = 80s 5 DUTY CYCLE = 0.5% MAX 2 1 5 2 0.1 5 2 10-2 0 0.4 0.8 1.2 ID, DRAIN CURRENT (A) 1.6 2.0 0 1.6 0.4 0.8 1.2 VSD, SOURCE TO DRAIN VOLTAGE (V) 2.0 TJ = 150oC TJ = 25oC 1.2 TJ = 150oC 0.8 0.4 0 FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE 20 VGS, GATE TO SOURCE VOLTAGE (V) ID = 2.0A 16 VDS = 80V 12 VDS = 200V VDS = 320V 8 4 0 0 3 6 9 12 15 Qg, GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 4-224 IRF710 Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD + - 0V IAS 0.01 0 tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON td(ON) tr RL VDS + tOFF td(OFF) tf 90% 90% RG DUT - VDD 0 10% 90% 10% VGS VGS 0 10% 50% PULSE WIDTH 50% FIGURE 17. SWITCHING TIME TEST CIRCUIT VDS (ISOLATED SUPPLY) FIGURE 18. RESISTIVE SWITCHING WAVEFORMS CURRENT REGULATOR VDD SAME TYPE AS DUT Qg(TOT) Qgd Qgs D VDS VGS 12V BATTERY 0.2F 50k 0.3F G DUT 0 IG(REF) 0 IG CURRENT SAMPLING RESISTOR S VDS ID CURRENT SAMPLING RESISTOR IG(REF) 0 FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS 4-225 IRF710 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 4-226 |
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