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| NAND01G-N 1 Gbit (x8/x16) 2112 Byte Page NAND Flash Memory and 512 Mbit (x16) LPSDRAM, 1.8V, Multi-Chip Package PRELIMINARY DATA Features summary Multi-chip Package - NAND Flash Memory - 512 Mbit or 1 Gbit (x8/x16) Large Page Size NAND Flash Memory - 512 Mbit (x16) SDR or DDR LPSDRAM Temperature range - -30 up to 85 C Supply voltage - NAND Flash : VDDF = 1.7V to 1.95V - LPSDRAM: VDDD = VDDQD = 1.7V to 1.9V Electronic Signature ECOPACK packages FBGA TFBGA107 10.5 x 13 x 1.2mm TFBGA149 10 x 13.5 x 1.2mm SDR/DDR LPSDRAM Flash Memory Interface: x16 bus width Programmable Partial Array Self Refresh Auto Temperature Compensated Self Refresh Deep Power Down mode 1.8V LVCMOS interface Quad internal Banks controlled by BA0 and BA1 Wrap sequence: Sequential/Interleaved Automatic and Controlled Precharge Auto Refresh and Self Refresh 8,192 Refresh Cycles/64ms Burst Termination by Burst Stop command and Precharge Command Nand Interface - x8 or x16 bus width - Multiplexed address/data Page size - x8 device: (2048 + 64 spare) Bytes - x16 device: (1024 + 32 spare) Words Block size - x8 device: (128K + 4K spare) Bytes - x16 device: (64K + 2K spare) Words Page Read/Program - Random access: 25s (max) - Sequential access: 50ns (min) - Page program time: 300s (typ) Copy Back Program mode - Fast page copy without external buffering Fast Block Erase - Block Erase time: 2ms (typ) Chip Enable `don't care' - for simple interfacing with microcontrollers Status Register January 2006 Rev1.0 1/23 www.st.com 2 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. NAND01G-N Table 1. Reference NAND01G-N NAND01GR4N5 1Gbit 1.8V (x16) DDR 512Mbit (x16) 1.8V, 133 MHz TFBGA149 1. SDR = Single Data Rate; DDR = Double Data Rate. Product List Part Number NAND01GR3N6 NAND Product 1Gbit 1.8V (x8) LPSDRAM Product(1) SDR 512Mbit (x16) 1.8V, 133MHz Package TFBGA107 2/23 Rev1.0 NAND01G-N Contents Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 NAND Flash component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 LPSDRAM component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 2.17 2.18 2.19 2.20 2.21 2.22 2.23 2.24 2.25 2.26 Flash memory Inputs/Outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . 12 Flash memory Inputs/Outputs (I/O8-I/O15) . . . . . . . . . . . . . . . . . . . . . . . 12 Flash memory Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . 12 Flash memory Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . 12 Flash memory Chip Enable (EF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Flash memory Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Flash memory Write Enable (WF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Flash memory Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Flash memory Ready/Busy (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Flash memory VDDF supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Flash memory VSSF ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 LPSDRAM Address Inputs (A0-A12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 LPSDRAM Bank Select Address Inputs (BA0-BA1) . . . . . . . . . . . . . . . . . 14 LPSDRAM Data Inputs/Outputs (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . 14 LPSDRAM Chip Select (ED) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 LPSDRAM Column Address Strobe (CAS) . . . . . . . . . . . . . . . . . . . . . . . 14 LPSDRAM Row Address Strobe (RAS) . . . . . . . . . . . . . . . . . . . . . . . . . . 14 LPSDRAM Write Enable (WD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 LPSDRAM Clock Input (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 LPSDRAM Clock Input (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 LPSDRAM Clock Enable (KE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 LPSDRAM Lower/Upper Data Input/Output Mask (DQM0, DQM1) . . . . . 15 Lower/Upper Data Read/Write Strobe Input/Output (LDQS, UDQS) . . . . 15 LPSDRAM VDDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 LPSDRAM VDDQD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 LPSDRAM VSSD ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Rev1.0 3/23 Contents NAND01G-N 3 4 5 6 7 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4/23 Rev1.0 NAND01G-N List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Product List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 TFBGA107 10.5x13mm - 10x14 active ball array, 0.80mm pitch, mechanical data . . . . . . 19 TFBGA149 10x13.5mm - 12x16 active ball array, 0.80mm pitch, mechanical data . . . . . . 20 Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Rev1.0 5/23 List of figures NAND01G-N List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 TFBGA107 connections, x16 Bus Width (Top view through package) . . . . . . . . . . . . . . . . 10 TFBGA149 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 TFBGA107 10.5x13mm - 10x14 active ball array, 0.80mm pitch, package outline . . . . . . 19 TFBGA149 10x13.5mm - 12x16 active ball array, 0.80mm pitch, package outline . . . . . . 20 6/23 Rev1.0 NAND01G-N Summary description 1 Summary description The NAND01G-N is a family that combine two memory devices in a Multi-Chip Package: a 1 Gbit NAND Flash memory and 512 Mbit LPSDRAM with 2Kbyte Pages. The NAND Flash memory and LPSDRAM components have separate power supplies and grounds. They also have separate control, address and input/output signals, which allows simultaneous access to both devices at any moment. They are distinguished by two Chip Enable inputs: EF for the NAND Flash memory and ED for the LPSDRAM. The Multi-Chip Packages are available with a 1.8V supply. See Table 1 for a complete list of the products available. All devices are stacked and are offered in: TFBGA107 (10.5 x 13 x 1.2mm) TFBGA149 (10 x 13.5 x 1.2mm) They are supplied with all the NAND Flash memory bits erased (set to `1'). This datasheet should be read in conjunction with the NAND Flash and LPSDRAM datasheets. NAND Flash component NAND01G-N devices contain a 1 Gbit (x8/x16) 2112 Byte/1056 Word Page, NAND Flash Memory. For detailed information on how to use the devices, see the NANDxxx-B datasheet which is available from your local STMicroelectronics distributor. LPSDRAM component NAND01G-N devices contain a 512 Mbit (x16) LPSDRAM. For detailed information on how to use the devices, see: M65KA512AB: SDR 512Mb (x16) M65KG512AB: DDR 512Mb (x16) All above ST datasheets available from ST divisional Marketing. Rev1.0 7/23 Summary description Figure 1. Logic Diagram VDDQD VDDD VDDF NAND01G-N 13 A0-A12 2 BA0-BA1 EF R WF AL CL WP K K(1) KE ED WD RAS CAS DQM0 DQM1 NAND01G-N UDQS-LDQS(1) DQ0-DQ15 I/O8-I/O15, x16(1) I/O0-I/O7, x8/x16 RB VSSQD VSSD VSSF 1. Available on NAND01GR4N5 only. AI10142d 8/23 Rev1.0 NAND01G-N Table 2. Signal Names NAND Flash memory I/O0-I/O7 I/O8-I/O15 AL CL EF R RB WF WP VDDF VSSF Data Input/Outputs for x8 and x16 devices Data Inputs/Outputs for x16 devices Address Latch Enable Command Latch Enable Chip Enable Read Enable Ready/Busy (open-drain output) Write Enable Write Protect Supply Voltage Ground LPSDRAM A0-A12 BA0-BA1 DQ0-DQ15 UDQS-LDQS(1) K K(1) KE ED WD RAS CAS DQM0 DQM1 VDDD VDDQD VSSD VSSQD NC DU Address Inputs A10 determines the Precharge mode. Bank Select Inputs Data Inputs/Outputs Data Strobe Inputs/Outputs Clock Input Clock Input Clock Enable Input Chip Select inputs Write Enable Input Row Address Strobe Input Column Address Strobe Input DQ Mask Enable Input (controls DQ0-DQ7) DQ Mask Enable Input (controls DQ8-DQ15) Supply Voltage Input/Output Supply Voltage Ground Input/Output Ground Not Connected Internally Do Not Use Summary description 1. Available on NAND01GR4N5 only. Rev1.0 9/23 Summary description Figure 2. TFBGA107 connections, x16 Bus Width (Top view through package) 1 2 3 4 5 6 7 8 9 NAND01G-N 10 A DU DU DU B NC NC DQ0 VDDD VSSF VDDF NC A3 NC DU C VSSD DQ2 DQ1 CL EF A0 A1 A2 D VDDQD DQ4 DQ3 AL WF BA0 BA1 A10 E VSSQD DQ6 DQ5 R RB RAS NC ED F VDDQD NC DQ7 WP NC CAS WD VSSD G VSSD DQM0 NC NC NC A12 KE VDDD H VDDD DQM1 K NC NC A8 A9 A11 J VSSQD NC DQ8 I/O0 I/O2 I/O4 I/O6 A7 K VDDQD DQ9 DQ10 NC NC NC NC A6 L VSSQD DQ11 DQ12 I/O1 I/O3 I/O5 I/O7 A5 M VDDD DQ13 DQ14 NC NC NC NC A4 N DU NC DQ15 VSSD VSSF VDDF VDDF VSSF NC DU P DU DU DU DU AI10143c 10/23 Rev1.0 NAND01G-N Figure 3. TFBGA149 Connections (Top view through package) 1 2 3 4 5 6 7 8 9 10 Summary description 11 12 A DU DU DU DU DU DU B DU DU DU DU DU DU C DU NC NC VDDD VSSD K K VDDD VSSD I/O7 NC DU D DU NC NC A0 ED WD KE A7 A8 I/O6 I/O15 E NC RB A1 BA0 CAS A12 A6 NC I/O5 I/O14 F NC R A2 BA1 RAS A11 A5 NC I/O4 I/O13 G VSSF EF A3 A10 NC A9 A4 NC NC I/O12 H VDDF NC NC NC NC NC NC NC VSSF VDDF J NC NC NC NC NC NC NC NC NC NC K NC CL NC NC DQM0 DQM1 NC NC NC I/O11 L NC AL DQ0 DQ3 LDQS UDQS DQ10 DQ13 I/O3 I/O10 M NC WF DQ1 DQ4 DQ6 DQ8 DQ11 DQ14 I/O2 I/O9 N NC WP DQ2 DQ5 DQ7 DQ9 DQ12 DQ15 I/O1 I/O8 P DU NC NC VDDQD VSSQD VDDD VSSD VDDQD VSSD I/O0 NC DU R DU DU DU DU DU DU T DU DU DU DU DU DU AI11007c Rev1.0 11/23 Signals description NAND01G-N 2 Signals description See Figure 1 in conjunction with Table 2, for a brief overview of the signals connected to this device. For extra details on the signals, refer to the NAND Flash and the LPSDRAM datasheets. 2.1 Flash memory Inputs/Outputs (I/O0-I/O7) Input/Outputs 0 to 7 are used by the NAND Flash memory to input the selected address, output the data during a Read operation or input a command or data during a Write operation. The inputs are latched on the rising edge of Write Enable. I/O0-I/O7 are left floating when the NAND Flash memory is deselected or the outputs are disabled. 2.2 Flash memory Inputs/Outputs (I/O8-I/O15) Input/Outputs 8 to 15 are only available in x16 NAND Flash devices. They are used to output the data during a Read operation or input data during a Write operation. Command and Address Inputs only require I/O0 to I/O7. The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when the device is deselected or the outputs are disabled. 2.3 Flash memory Address Latch Enable (AL) The Address Latch Enable activates the latching of the Address inputs in the Command Interface of the NAND Flash memory. When AL is high, the inputs are latched on the rising edge of Write Enable. 2.4 Flash memory Command Latch Enable (CL) The Command Latch Enable activates the latching of the Command inputs in the Command Interface of the NAND Flash memory. When CL is high, the inputs are latched on the rising edge of Write Enable. 2.5 Flash memory Chip Enable (EF) The NAND Flash memory Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is low, VIL, the NAND Flash memory device is selected. If Chip Enable goes high, vIH, while the NAND Flash memory is busy, the device remains selected and does not go into standby mode. 12/23 Rev1.0 NAND01G-N Signals description 2.6 Flash memory Read Enable (R) The NAND Flash memory Read Enable pin, R, controls the sequential data output during Read operations. The falling edge of R also increments the internal column address counter by one. 2.7 Flash memory Write Enable (WF) The NAND Flash memory Write Enable input, W, controls writing to the Command Interface, Input Address and Data latches. Both addresses and data are latched on the rising edge of Write Enable. 2.8 Flash memory Write Protect (WP) The Write Protect pin is a NAND Flash memory input that gives a hardware protection against unwanted program or erase operations. When Write Protect is Low, VIL, the NAND Flash memory device does not accept any program or erase operations. It is recommended to keep the Write Protect pin Low, VIL, during power-up and power-down. 2.9 Flash memory Ready/Busy (RB) The Ready/Busy output, RB, is an open-drain NAND Flash memory output that can be used to identify if the P/E/R Controller is currently active. When Ready/Busy is Low, VOL, a read, program or erase operation is in progress. When the operation completes Ready/Busy goes High, VOH. The use of an open-drain output allows the Ready/Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. 2.10 Flash memory VDDF supply voltage VDDF provides the power supply to the internal core of the NAND Flash memory device. It is the main power supply for all operations (read, program and erase). 2.11 Flash memory VSSF ground Ground, VSSF, is the reference for the power supply for the NAND Flash memory. It must be connected to the system ground. Rev1.0 13/23 Signals description NAND01G-N 2.12 LPSDRAM Address Inputs (A0-A12) The A0-A12 Address Inputs are used by the LPSDRAM to select the row or column to be made active. If a row is selected, all thirteen, A0-A12 Address Inputs are used. If a column is selected, only the nine least significant Address Inputs, A0-A8, are used. In this latter case, A10 determines whether Auto Precharge is used. If A10 is High (set to `1') during Read or Write, the Read or Write operation includes an Auto Precharge cycle. If A10 is Low (set to `0') during Read or Write, the Read or Write cycle does not include an Auto Precharge cycle. 2.13 LPSDRAM Bank Select Address Inputs (BA0-BA1) The BA0 and BA1 Banks Select Address Inputs are used by the LPSDRAM to select the bank to be made active. The LPSDRAM must be enabled, the Row Address Strobe, RAS, must be Low, VIL, the Column Address Strobe, CAS, and W must be High, VIH, when selecting the addresses. 2.14 LPSDRAM Data Inputs/Outputs (DQ0-DQ15) On the LPSDRAM, DQ0-DQ15 output the data stored at the selected address during a Read operation, or are used to input the data during a write operation. 2.15 LPSDRAM Chip Select (ED) The Chip Select input E activates the LPSDRAM state machine, address buffers and decoders when driven Low, VIL. When High, VIH the device is not selected. 2.16 LPSDRAM Column Address Strobe (CAS) The Column Address Strobe, CAS, is used in conjunction with Address Inputs A8-A0 and BA1-BA0, to select the starting column location prior to a Read or Write. 2.17 LPSDRAM Row Address Strobe (RAS) The Row Address Strobe, RAS, is used in conjunction with Address Inputs A11-A0 and BA1-BA0, to select the starting address location prior to a Read or Write. 2.18 LPSDRAM Write Enable (WD) The LPSDRAM Write Enable input, W, controls writing to the LPSDRAM. 14/23 Rev1.0 NAND01G-N Signals description 2.19 LPSDRAM Clock Input (K) The Clock signal, K, is used to clock the Read and Write cycles on the LPSDRAM. During normal operation, the Clock Enable pin, KE, is High, VIH. The clock signal K can be suspended to switch the device to the Self-Refresh, Power-Down or Deep Power-Down mode by driving KE Low, VIL. 2.20 LPSDRAM Clock Input (K) The Clock signal, K, is only available on the DDR LPSDRAM. It is used in conjunction with the Clock signal, K. All LPSDRAM input signals except DQM0/DQM1, UDQS/LDQS and DQ0-DQ15 are referred to the cross point of K rising edge and K falling edge. 2.21 LPSDRAM Clock Enable (KE) The Clock Enable, KE, pin is used by the LPSDRAM to control the synchronizing of the signals with Clock signal K (and K on DDR LPSDRAM). If KE is High, VIH, the next Clock rising edge is valid. When KE is Low, VIL, the signals are no longer clocked and data Read and Write cycles are extended. KE is also involved in switching the device to the SelfRefresh, Power-Down and Deep Power-Down modes. 2.22 LPSDRAM Lower/Upper Data Input/Output Mask (DQM0, DQM1) Data Mask Enable Inputs are used to mask the Read or Write data. 2.23 Lower/Upper Data Read/Write Strobe Input/Output (LDQS, UDQS) LDQS and UDQS are only available on the DDR LPSDRAM. They can be either input or output signals and act as write data strobe and read data strobe respectively. LDQS and UDQS are the strobe signals for DQ0 to DQ7 and DQ8 to DQ15, respectively. 2.24 LPSDRAM VDDD supply voltage VDDD provides the power supply to the internal core of the LPSDRAM. It is the main power supply for all operations (Read and Write). Rev1.0 15/23 Signals description NAND01G-N 2.25 LPSDRAM VDDQD supply voltage VDDQD provides the power supply to the I/O pins of the LPSDRAM and enables all Outputs to be powered independently of VDDD. VDDQD can be tied to VDDD or can use a separate supply. It is recommended to power-up and power-down VDDD and VDDQD together to avoid certain conditions that would result in data corruption. 2.26 LPSDRAM VSSD ground Ground, VSSD, is the reference for the core power supply for the LPSDRAM. It must be connected to the system ground. 16/23 Rev1.0 NAND01G-N Functional description 3 Functional description The NAND Flash memory and LPSDRAM components have separate power supplies and grounds. They also have separate control signals, addresses and data input/outputs, which allows simultaneous access to both devices at any moment. Figure 4. Functional Block Diagram VDDF AL CL EF R WF WP 1 Gbit NAND Flash Memory I/O0-I/O7 I/O8-I/O15 RB VSSF VDDD VDDQD BA0-BA1 A0-A12 K K(1) KE ED WD CAS RAS DQM0 DQM1 LPSDRAM DQ0-DQ15 LDQS-UDQS (1) VSSD VSSQD Ai12401 1. Available on Root Part Number 2 only. Rev1.0 17/23 Maximum rating NAND01G-N 4 Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 3. Absolute Maximum Ratings Value Symbol TA TBIAS TSTG VIO VDDF Parameter Min Ambient Operating Temperature Temperature Under Bias(1) -30 TBD -55 1.8V 1.8V 1.8V 1.8V -0.6 -1.0 -0.6 -1.0 50 1 Max 85 TBD 125 2.7 2.6 2.7 2.6 C C C V V V V mA W Unit Storage Temperature NAND Flash Input or Output Voltage LPSDRAM Input or Output Voltage NAND Flash Supply Voltage LPSDRAM Supply Voltage IOS PD VDDD, VDDQD LPSDRAM Short Circuit Output Current LPSDRAM Power Dissipation 1. TBD stands for `To Be Determined'. 18/23 Rev1.0 NAND01G-N Package mechanical 5 Figure 5. Package mechanical TFBGA107 10.5x13mm - 10x14 active ball array, 0.80mm pitch, package outline D FD D1 b SE E E1 ddd BALL "B1" e FE A SD e A1 A2 BGA-Z24 Table 4. TFBGA107 10.5x13mm - 10x14 active ball array, 0.80mm pitch, mechanical data millimeters inches Max 1.20 0.25 0.80 0.45 10.50 7.20 0.10 13.00 10.40 0.80 1.65 1.30 0.40 0.40 - - 12.90 13.10 0.512 0.409 0.031 0.065 0.051 0.016 0.016 - - 0.508 0.40 10.40 0.50 10.60 0.031 0.018 0.413 0.283 0.004 0.516 0.016 0.409 0.020 0.417 0.010 Typ Min Max 0.047 Symbol Typ A A1 A2 b D D1 ddd E E1 e FD FE SD SE Min Rev1.0 19/23 Package mechanical Figure 6. NAND01G-N TFBGA149 10x13.5mm - 12x16 active ball array, 0.80mm pitch, package outline D D1 b SE E E1 ddd e BALL "A1" FE A FD SD e A1 A2 BGA-Z78 1. Drawing not to scale. Table 5. TFBGA149 10x13.5mm - 12x16 active ball array, 0.80mm pitch, mechanical data millimeters inches Max 1.200 0.250 0.800 0.450 10.000 8.800 0.100 13.500 12.000 0.800 0.600 0.750 0.400 0.400 - - - - - - 13.400 13.600 0.5315 0.4724 0.0315 0.0236 0.0295 0.0157 0.0157 - - - - - - 0.5276 0.400 9.900 0.500 10.100 0.0315 0.0177 0.3937 0.3465 0.0039 0.5354 0.0157 0.3898 0.0197 0.3976 0.0098 Typ Min Max 0.0472 Symbol Typ A A1 A2 b D D1 ddd E E1 e FD FE SD SE Min 20/23 Rev1.0 NAND01G-N Part numbering 6 Table 6. Example: Device Type Part numbering Ordering Information Scheme NAND01G R 3 N 6A ZB 5 E NAND Flash Memory NAND Flash Density 01G = 1Gb NAND Flash Operating Voltage R = 1.7V to 1.95V Bus Width 3 = x8 4 = x16 Family Identifier N = 2112 Byte Page NAND Flash + LPSDRAM Device Options 5 = DDR LPSDRAM 512Mbit (x16), 133 Mhz, BGA149 6 = SDR LPSDRAM 512Mbit (x 16), 133Mhz, BGA107 Product Version A Package ZB = TFBGA ZC = LFBGA Reserved Option E = ECOPACK Package, Standard Packing F = ECOPACK Package, Tape & Reel Packing Devices are shipped from the factory with the Flash memory content bits, in valid blocks, erased to '1'. For further information on any aspect of this device, please contact your nearest ST Sales Office. Rev1.0 21/23 Revision history NAND01G-N 7 Revision history Table 7. Date 18-Oct-2004 19-Oct-2004 Document Revision History Version 0.1 0.2 First Issue Figure 1: Logic Diagram modified. Table 1: Product List modified. NAND512-N device removed from the document.TFBGA137 packages removed from document. SDR 256Mb (x32) and SDR 512Mb (x32) devices removed from document. NAND01GR3N3 removed throughout document. LDQM and UDQM replaced respectively by DQM0 and DQM1throughout document. DRAM changed to LPSDRAM throughout document. LFBGA107 added throughout document. NAND01GR3N1, NAND01GR3N2, NAND01GR3N6, NAND01GR4N5 added throughout document. Note 1 below Table 2: Signal Names and Figure 1: Logic Diagram added to cover both part numbers. Figure 2: TFBGA107 connections, x16 Bus Width (Top view through package) and Figure 3: TFBGA149 Connections (Top view through package) updated. Section 2: Signals description and Section 3: Functional description added. 256Mb LPSDRAM removed. LFBGA107 (12 x 13 x 1.4mm) and LFBGA149 (10 x 13.5 x 1.4mm) replaced by TFBGA107 (10.5x13x1.2mm) and TFBGA149 (10x13.5x1.2mm), respectively. Revision Details 26-Oct-2005 0.3 31-Jan-2006 1.0 22/23 Rev1.0 NAND01G-N Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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