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| S3C4510B PRODUCT OVERVIEW 1 OVERVIEW PRODUCT OVERVIEW Samsung's S3C4510B 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller solution for Ethernet-based systems. An integrated Ethernet controller, the S3C4510B, is designed for use in managed communication hubs and routers. The S3C4510B is built around an outstanding CPU core: the 16/32-bit ARM7TDMI RISC processor designed by Advanced RISC Machines, Ltd. The ARM7TDMI core is a low-power, general purpose microprocessor macro-cell that was developed for use in application-specific and custom-specific integrated circuits. Its simple, elegant, and fully static design is particularly suitable for cost-sensitive and power-sensitive applications. The S3C4510B offers a configurable 8K-byte unified cache/SRAM and Ethernet controller which reduces total system cost. Most of the on-chip function blocks have been designed using an HDL synthesizer and the S3C4510B has been fully verified in Samsung's state-of-the-art ASIC test environment. Important peripheral functions include two HDLC channels with buffer descriptor, two UART channels, 2-channel GDMA, two 32-bit timers, and 18 programmable I/O ports. On-board logic includes an interrupt controller, DRAM/ SDRAM controller, and a controller for ROM/SRAM and flash memory. The System Manager includes an internal 32-bit system bus arbiter and an external memory controller. The following integrated on-chip functions are described in detail in this user's manual: -- 8K-byte unified cache/SRAM -- I2C interface -- Ethernet controller -- HDLC -- GDMA -- UART -- Timers -- Programmable I/O ports -- Interrupt controller 1-1 PRODUCT OVERVIEW S3C4510B FEATURES Architecture * * * Integrated system for embedded ethernet applications Fully 16/32-bit RISC architecture Little/Big-Endian mode supported basically, the internal architecture is big-endian. So, the little-endian mode only support for external memory. Efficient and powerful ARM7TDMI core Cost-effective JTAG-based debug solution Boundary scan * * * * * * * * * * Data alignment logic Endian translation 100/10-Mbit per second operation Full compliance with IEEE standard 802.3 MII and 7-wire 10-Mbps interface Station management signaling On-chip CAM (up to 21 destination addresses) Full-duplex mode with PAUSE feature Long/short packet modes PAD generation * * * System Manager * 8/16/32-bit external bus support for ROM/SRAM, flash memory, DRAM, and external I/O One external bus master with bus request/ acknowledge pins Support for EDO/normal or SDRAM Programmable access cycle (0-7 wait cycles) Four-word depth write buffer Cost-effective memory-to-peripheral DMA interface HDLCs * HDLC protocol features: -- -- -- -- -- * * * * * * * * * * * * * * * * Flag detection and synchronization Zero insertion and deletion Idle detection and transmission FCS generation and detection (16-bit) Abort detection and transmission * * * * * Address search mode (expandable to 4 bytes) Selectable CRC or No CRC mode Automatic CRC generator preset Digital PLL block for clock recovery Baud rate generator NRZ/NRZI/FM/Manchester data formats for Tx/Rx Loop-back and auto-echo modes Tx/Rx FIFOs have 8-word (8 x 32-bit) depth Selectable 1-word or 4-word data transfer mode Data alignment logic Endian translation Programmable interrupts Modem interface Up to 10 Mbps operation HDLC frame length based on octets 2-channel DMA buffer descriptor for Tx/Rx on each HDLC Unified Instruction/Data Cache * * * 2 Two-way, set-associative, unified 8K-byte cache Support for LRU (least recently used) protocol Cache is configurable as an internal SRAM I C Serial Interface * * Master mode operation only Baud rate generator for serial clock generation Ethernet Controller * * * DMA engine with burst mode DMA Tx/Rx buffers (256 bytes Tx, 256 bytes Rx) MAC Tx/Rx FIFO buffers (80 bytes Tx, 16 bytes Rx) 1-2 S3C4510B PRODUCT OVERVIEW DMA Controller * 2-channel General DMA for memory-tomemory, memory-to-UART, UART-to-memory data transfers without CPU intervention Initiated by a software or external DMA request Increments or decrements a source or destination address in 8-bit, 16-bit or 32-bit data transfers 4-data burst mode Programmable I/O * * 18 programmable I/O ports Pins individually configurable to input, output, or I/O mode for dedicated signals * * Interrupt Controller * * * 21 interrupt sources, including 4 external interrupt sources Normal or fast interrupt mode (IRQ, FIQ) Prioritized interrupt handling * UARTs * * * * * * * * * Two UART (serial I/O) blocks with DMA-based or interrupt-based operation Support for 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit and receive Programmable baud rates 1 or 2 stop bits Odd or even parity Break generation and detection Parity, overrun, and framing error detection x16 clock mode Infra-red (IR) Tx/Rx support (IrDA) PLL * * * The external clock can be multiplied by on-chip PLL to provide high frequency system clock The input frequency range is 10-40 MHz The output frequency is 5 times of input clock. To get 50 MHz, input clock frequency should be 10 MHz. Operating Voltage Range * 3.3 V 5 % Operating Temperature Range * 0 C to + 70 C Timers * * Two programmable 32-bit timers Interval mode or toggle mode operation Operating Frequency * Up to 50 MHz Package Type * 208-Pin QFP 1-3 PRODUCT OVERVIEW S3C4510B ARM7TDMI 32-bit RISE CPU ICEBreaker CPU Interface 32-Bit Sytem Bus Memory Controller with Refresh Control 6-bank ROM SRAM FLASH 4-bank DRAM 4-bank External I/O Device Ext Bus REQ/ACK External Bus Master 8-Kbyte Unified Cache 4-Word Write Buffer System Bus Arbiter Bus Rounter SCL SDA 18 I/O Ports including 4: Ext INT req. 2: Timer out (0,1) 2: Ext DMA REQ. 2: Ext DMA ACK Console I2C 18 General I/O ports Interruput Controller UART 0,1 32-bit Timer 0,1 GDMA 0,1 Xtal OSC PLL TAP Controller for JTAG MAC Tx FIFO (80 bytes) Rx FIFO (16 bytes) MII or 7-wire BDMA RAMs Tx Buffer (256 bytes) Rx Buffer (256 bytes) CAM (128 bytes) 2-Channel HDLCs with DMAs Ethernet Controller 2-channel BDMA Remote port A,B Figure 1-1. S3C4510B Block Diagram 1-4 S3C4510B PRODUCT OVERVIEW 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 VSS VDD UARXD1 uUADSR0 UATXD0 uUADTR0 UARXD0 SDA SCL P<17>/TOUT1 VSS VDD P<16>/TOUT0 P<15>/nXDACK<1> P<14>/nXDACK<0> P<13>/nXDREQ<1> P<12>/nXDREQ<0> P<11>/xINREQ<3> P<10>/xINREQ<2> P<9>/xINREQ<1> VSS VDD P<8>/xINREG<0> P<7> P<6> P<5> P<4> P<3> P<2> P<1> VSS VDD P<0> XDATA<31> XDATA<30> XDATA<29> XDATA<28> XDATA<27> XDATA<26> XDATA<25> VSS VDD XDATA<24> XDATA<23> XDATA<22> XDATA<21> XDATA<20> XDATA<19> XDATA<18> XDATA<17> VSS VDD VDDa VSSa FILTER VDD VSS TCK TMS TDI TD0 nTRST TMODE UCLK VDD VSS nECS<0> nECS<1> nECS<2> nECS<3> nEWAIT nOE BOSIZE<0> BOSIZE<1> nRCS<0> CLKOEN SDCLK/MCLKO VDD VSS XCLK VSS nRESET CLKSEL nRCS<1> nRCS<2> nRCS<3> nRCS<4> nRCS<5> nSDCS<0>/nRAS<0> nSDCS<1>/nRAS<1> nSDCS<2>/nRAS<2> VDD VSS nSDCS<3>/nRAS<3> nSDRAS/nCAS<0> nSDCAS/nCAS<2> CKE/nCAS<2> nCAS<3> nDWE DQM0/nWBE<0> DQM1/nWBE<1> DQM2/nWBE<2> VDD VSS 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 VDD VSS nUADTR1 UATXD1 nUADSR1 nDTRA RXDA nRTSA TXDA nCTSA VDD VSS nDCDA RXCA nSYNCA TXCA nDTRB RTDB nRTSB TXDB VDD VSS nCTSB nDCDB RXCB nSYNCB TXCB CRS/CRS_ 10M RX DV/LINK_10M RXD<0>/RXD_10M VDD VSS RXD<1> RXD<2> RXD<3> RX ERR RX_CLK/RXCLK_10M COL/COL_10M TXD<0>/TXD_10M TXD<1>/LOOP_10M VDD VSS TXD<2> TXD<3> TX_ERR/POCMP_10M TX_CLK/TXCLK_10M TX_EN/TXEN_10M MDIO LITTLE MDC VDD VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 S3C4510B 208-QFP VDD VSS XDATA<16> XDATA<15> XDATA<14> XDATA<13> XDATA<12> XDATA<11> XDATA<10> XDATA<9> XDATA<8> XDATA<7> XDATA<6> VSS VDD XDATA<5> XDATA<4> XDATA<3> XDATA<2> XDATA<1> XDATA<0> XDATA<21> XDATA<20> XDATA<19> XDATA<18> VSS VDD ADDR<17> ADDR<16> ADDR<15> ADDR<14> ADDR<13> ADDR<12> ADDR<11> ADDR<10>/AP ADDR<9> ADDR<8> VSS VDD ADDR<7> ADDR<6> ADDR<5> ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> ExtMACK ExtMREQ nWBE<3>/DQM<3> VSS VDD Figure 1-2. S3C4510B Pin Assignment Diagram 1-5 PRODUCT OVERVIEW S3C4510B SIGNAL DESCRIPTIONS Table 1-1. S3C4510B Signal Descriptions Signal XCLK Pin No. 80 Type I Description S3C4510B system clock source. If CLKSEL is Low, PLL output clock is used as the S3C4510B internal system clock. If CLKSEL is High, XCLK is used as the S3C4510B internal system clock. System clock out. MCLKO is monitored with some delay as the same phase of internal system clock, MCLK(SCLK). SDCLK is system clock for SDRAM. Clock select. When CLKSEL is '0'(low level), PLL output clock can be used as the master clock. When CLKSEL is '1'(high level), the XCLK is used as the master clock. Not reset. nRESET is the global reset input for the S3C4510B. To allow a system reset, and for internal digital filtering, nRESET must be held to low level for at least 64 master clock cycles. Refer to "Figure 3. S3C4510B reset timing diagram" for more details about reset timing. Clock out enable/disable. (see the pin description for MCLKO.) Test Mode. The TMODE bit settings are interpreted as follows: '0' = normal operating mode, '1' = chip test mode. This TMODE pin also can be used to change MF of PLL. To get 5 times internal system clock from external clock, '0'(low level) should be assigned to TMODE. If '1'(high level), MF will be changed to 6.6 If the PLL is used, 820pF ceramic capacitor should be connected between the pin and analog ground(pin # 54). JTAG Test Clock. The JTAG test clock shifts state information and test data into, and out of, the S3C4510B during JTAG test operations. This pin is internally connected pull-down. JTAG Test Mode Select. This pin controls JTAG test operations in the S3C4510B. This pin is internally connected pull-up. JTAG Test Data In. The TDI level is used to serially shift test data and instructions into the S3C4510B during JTAG test operations. This pin is internally connected pull-up. JTAG Test Data Out. The TDO level is used to serially shift test data and instructions out of the S3C4510B during JTAG test operations. JTAG Not Reset. Asynchronous reset of the JTAG logic. This pin is internally connected pull-up. MCLKO/SDCLK (note) 77 O CLKSEL 83 I nRESET 82 I CLKOEN TMODE 76 63 I I FILTER TCK 55 58 AI I TMS TDI 59 60 I I TDO 61 O nTRST 62 I 1-6 S3C4510B PRODUCT OVERVIEW Table 1-1. S3C4510B Signal Descriptions (Continued) Signal ADDR[21:0]/ ADDR[10]/AP (note) Pin No. 117-110, 129-120, 135-132 Type O Description Address Bus. The 22-bit address bus, ADDR[21:0], covers the full 4M word address range of each ROM/SRAM, flash memory, DRAM, and the external I/O banks. The 23-bit internal address bus used to generate DRAM address. The number of column address bits in DRAM bank can be programmed 8bits to 11bits use by DRAMCON registers. ADDR[10]/AP is the auto precharge control pin. The auto precharge command is issued at the same time as burst read or burst write by asserting high on ADDR[10]/AP. External (bi-directional, 32-bit) Data Bus. The S3C4510B data bus supports external 8-bit, 16-bit, and 32-bit bus sizes. XDATA[31:0] 141-136, 154-144, 166-159, 175-169 94, 91, 90, 89 98, 97, 96, 95 I/O nRAS[3:0]/ nSDCS[3:0] (note) nCAS[3:0] nCAS[0]/nSDRAS nCAS[1]/nSDCAS nCAS[2]/CKE (note) O Not Row Address Strobe for DRAM. The S3C4510B supports up to four DRAM banks. One nRAS output is provided for each bank. nSDCS[3:0] are chip select pins for SDRAM. Not column address strobe for DRAM. The four nCAS outputs indicate the byte selections whenenver a DRAM bank is accessed. nSDRAS is row address strobe signal for SDRAM. Latches row addresses on the positive going edge of the SDCLK with nSDRAS low. Enable row access and precharge. nSDCAS is column address strobe for SDRAM. Latches column addresses on the positive going edge of the SDCLK with nSDCAS low. Enables column access. CKE is clock enable signal for SDRAM. Masks SDRAM system clock, SDCLK to freeze operation from the next clock cycle. SDCLK should be enabled at least one cycle prior to new command. Disable input buffers of SDRAM for power down in standby. DRAM Not Write Enable. This pin is provided for DRAM bank write operations. (nWBE[3:0] is used for write operations to the ROM/ SRAM/flash memory banks.) . Not External I/O Chip Select. Four external I/O banks are provided for external memory-mapped I/O operations. Each I/O bank stores up to 16 Kbytes. nECS signals indicate which of the four external I/O banks is selected. Not External Wait. This signal is activated when an external I/O device or ROM/SRAM/flash bank 5 needs more access cycles than those defined in the corresponding control register. When de-assert the nEWAIT, you must synchronize the nEWAIT with MCLKO rising edge. If not, memory state machine can get into the Wrong State. O nDWE 99 O nECS[3:0] 70, 69, 68, 67 O nEWAIT 71 I 1-7 PRODUCT OVERVIEW S3C4510B Table 1-1. S3C4510B Signal Descriptions (Continued) Signal nRCS[5:0] Pin No. 88-84, 75 Type O Description Not ROM/SRAM/Flash Chip Select. The S3C4510B can access up to six external ROM/SRAM/Flash banks. By controlling the nRCS signals, you can map CPU addresses into the physical memory banks. Bank 0 Data Bus Access Size. Bank 0 is used for the boot program. You use these pins to set the size of the bank 0 data bus as follows: '01' = one byte, '10' = half-word, '11' = one word, and '00' = reserved. Not Output Enable. Whenever a memory access occurs, the nOE output controls the output enable port of the specific memory device. Not Write Byte Enable. Whenever a memory write access occurs, the nWBE output controls the write enable port of the specific memory device (except for DRAM). For DRAM banks, CAS[3:0] and nDWE are used for the write operation. DQM is data input/output mask signal for SDRAM. External Bus Master Request. An external bus master uses this pin to request the external bus. When it activates the ExtMREQ signal, the S3C4510B drives the state of external bus pins to high impedance. This lets the external bus master take control of the external bus. When it has the control, the external bus master assumes responsibility for DRAM refresh operations. The ExtMREQ signal is deactivated when the external bus master releases the external bus. When this occurs, ExtMACK goes Low level and the S3C4510B assumes the control of the bus. External Bus Acknowledge. (See the ExtMREQ pin description.) Management Data Clock. The signal level at the MDC pin is used as a timing reference for data transfers that are controlled by the MDIO signal. Management Data I/O. When a read command is being executed, data that is clocked out of the PHY is presented on this pin. When a write command is being executed, data that is clocked out of the controller is presented on this pin for the Physical Layer Entity, PHY. Little endian mode select pin. If LITTLE is High, S3C4510B operate in little endian mode. If Low, then in Big endian mode. Default value is low because this pin is pull-downed internally. Collision Detected/Collision Detected for 10M. COL is asserted asynchronously with minimum delay from the start of a collision on the medium in MII mode. COL_10M is asserted when a 10Mbit/s PHY detects a collision. Transmit Clock/Transmit Clock for 10M. The controller drives TXD[3:0] and TX_EN from the rising edge of TX_CLK. In MII mode, the PHY samples TXD[3:0] and TX_EN on the rising edge of TX_CLK. For data transfers, TXCLK_10M is provided by the 10-Mbit/s PHY. B0SIZE[1:0] 74, 73 I nOE 72 O nWBE[3:0]/ DQM[3:0] (note) 107, 102-100 O ExtMREQ 108 I ExtMACK MDC 109 50 O O MDIO 48 I/O LITTLE 49 I COL/COL_10M 38 I TX_CLK/ TXCLK_10M 46 I 1-8 S3C4510B PRODUCT OVERVIEW Table 1-1. S3C4510B Signal Descriptions (Continued) Signal TXD[3:0] LOOP_10M TXD_10M Pin No. 44, 43, 40, 39 Type O Description Transmit Data/Transmit Data for 10 M/Loop-back for 10M. Transmit data is aligned on nibble boundaries. TXD[0] corresponds to the first bit to be transmitted on the physical medium, which is the LSB of the first byte and the fifth bit of that byte during the next clock. TXD_10M is shared with TXD[0] and is a data line for transmitting to the 10-Mbit/s PHY. LOOP_10M is shared with TXD[1] and is driven by the loop-back bit in the control register. Transmit Enable/Transmit Enable for 10M. TX_EN provides precise framing for the data carried on TXD[3:0]. This pin is active during the clock periods in which TXD[3:0] contains valid data to be transmitted from the preamble stage through CRC. When the controller is ready to transfer data, it asserts TXEN_10M. Transmit Error/Packet Compression Enable for 10M. TX_ERR is driven synchronously to TX_CLK and sampled continuously by the Physical Layer Entity, PHY. If asserted for one or more TX_CLK periods, TX_ERR causes the PHY to emit one or more symbols which are not part of the valid data, or delimiter set located somewhere in the frame that is being transmitted. PCOMP_10M is asserted immediately after the packet's DA field is received. PCOMP_10M is used with the Management Bus of the DP83950 Repeater Interface Controller (from National Semiconductor). The MAC can be programmed to assert PCOMP if there is a CAM match, or if there is not a match. The RIC (Repeater Interface Controller) uses this signal to compress (shorten) the packet received for management purposes and to reduce memory usage. (See the DP83950 Data Sheet, published by National Semiconductor, for details on the RIC Management Bus.). This pin is controlled by a special register, with which you can define the polarity and assertion method (CAM match active or not match active) of the PCOMP signal. Carrier Sense/Carrier Sense for 10M. CRS is asserted asynchronously with minimum delay from the detection of a nonidle medium in MII mode. CRS_10M is asserted when a 10Mbit/s PHY has data to transfer. A 10-Mbit/s transmission also uses this signal. Receive Clock/Receive Clock for 10M. RX_CLK is a continuous clock signal. Its frequency is 25 MHz for 100-Mbit/s operation, and 2.5 MHz for 10-Mbit/s. RXD[3:0], RX_DV, and RX_ERR are driven by the PHY off the falling edge of RX_CLK, and sampled on the rising edge of RX_CLK. To receive data, the TXCLK_10 M clock comes from the 10-Mbit/s PHY. Receive Data/Receive Data for 10M. RXD is aligned on nibble boundaries. RXD[0] corresponds to the first bit received on the physical medium, which is the LSB of the byte in one clock period and the fifth bit of that byte in the next clock. RXD_10M is shared with RXD[0] and it is a line for receiving data from the 10Mbit/s PHY. TX_EN/ TXEN_10M 47 O TX_ERR/ PCOMP_10M 45 O CRS/CRS_10M 28 I RX_CLK/ RXCLK_10M 37 I RXD[3:0]/ RXD_10M 35, 34, 33, 30 I 1-9 PRODUCT OVERVIEW S3C4510B Table 1-1. S3C4510B Signal Descriptions (Continued) Signal RX_DV/LINK_10M Pin No. 29 Type I Description Receive Data Valid/Link Status for 10M. PHY asserts RX_DV synchronously, holding it active during the clock periods in which RXD[3:0] contains valid data received. PHY asserts RX_DV no later than the clock period when it places the first nibble of the start frame delimiter (SFD) on RXD[3:0]. If PHY asserts RX_DV prior to the first nibble of the SFD, then RXD[3:0] carries valid preamble symbols. LINK_10M is shared with RX_DV and used to convey the link status of the 10-Mbit/s endec. The value is stored in a status register. Receive Error. PHY asserts RX_ERR synchronously whenever it detects a physical medium error (e.g., a coding violation). PHY asserts RX_ERR only when it asserts RX_DV. HDLC Ch-A Transmit Data. The serial output data from the transmitter is coded in NRZ/NRZI/FM/Manchester data format. HDLC Ch-A Receive Data. The serial input data received by the device should be coded in NRZ/NRZI/FM/Manchester data format. The data rate should not exceed the rate of the S3C4510B internal master clock. HDLC Ch-A Data Terminal Ready. nDTRA output indicates that the data terminal device is ready for transmission and reception. HDLC Ch-A Request To Send. The nRTSA output goes low when there is exist data to be sent in TxFIFO. The data to be sent is transmitted when the nCTS is active(Low) state. HDLC Ch-A Clear To Send. The S3C4510B stores each transition of nCTS to ensure that its occurrence would be acknowledged by the system. HDLC Ch-A Data Carrier Detected. A High level on this pin resets and inhibits the receiver register. Data from a previous frame that may remain in the RxFIFO is retained. The S3C4510B stores each transition of nDCD. HDLC Ch-A Sync is detected. This indicates the reception of a flag. The nSYNC output goes low for one bit time beginning at the last bit of the flag. HDLC Ch-A Receiver Clock. When this clock input is used as the receiver clock, the receiver samples the data on the positive edge of RXCA clock. This clock can be the source clock of the receiver, the baud rate generator, or the DPLL. HDLC Ch-A Transmitter Clock. When this clock input is used as the transmitter clock, the transmitter shifts data on the negative transition of the TXCA clock . If you do not use TXCA as the transmitter clock, you can use it as an output pin for monitoring internal clocks such as the transmitter clock, receiver clock, and baud rate generator output clocks. HDLC Ch-B transmit data. See the TXDA pin description. HDLC Ch-B receive data. See the RXDA pin description. RX_ERR 36 I TXDA RXDA 9 7 O I nDTRA nRTSA 6 8 O O nCTSA 10 I nDCDA 13 I nSYNCA 15 O RXCA 14 I TXCA 16 I/O TXDB RXDB 20 18 O I 1-10 S3C4510B PRODUCT OVERVIEW Table 1-1. S3C4510B Signal Descriptions (Continued) Signal nDTRB nRTSB nCTSB nDCDB nSYNCB RXCB TXCB UCLK Pin No. 17 19 23 24 26 25 27 64 Type O O I I O I I/O I Description HDLC Ch-B data terminal ready. See the nDTRA pin description. HDLC Ch-B request to send. See the nRTSA pin description. HDLC Ch-B clear to send. See the nCTSA pin description. HDLC Ch-B data carrier detected. See the nDCDA pin description. HDLC Ch-B sync is detected. See the nSYNCA pin description. HDLC Ch-B receiver clock. See the RXCA pin description. HDLC Ch-B transmitter clock. See the TXCA pin description. The external UART clock input. MCLK or PLL generated clock can be used as the UART clock. You can use UCLK, with an appropriate divided by factor, if a very precious baud rate clock is required. UART0 receive data. RXD0 is the UART 0 input signal for receiving serial data. UART0 transmit data. TXD0 is the UART 0 output signal for transmitting serial data. Not UART0 data terminal ready. This input signals the S3C4510B that the peripheral (or host) is ready to transmit or receive serial data. Not UART0 data set ready. This output signals the host (or peripheral) that UART 0 is ready to transmit or receive serial data. UART1 receive data. See the RXD0 pin description. UART1 transmit data. See the TXD0 pin description. Not UART1 data terminal ready. See the DTR0 pin description. Not UART1 data set ready. See the DSR0 pin description. General I/O ports. See the I/O ports, chapter 12. External interrupt request lines or general I/O ports. See the I/O ports, chapter 12. I/O I/O I/O I/O I/O I/O Not external DMA requests for GDMA or general I/O ports. See the I/O ports, chapter 12. 195, 194 196 199 200 201 Not external DMA acknowledge from GDMA or general I/O ports. See the I/O ports, chapter 12. Timer 0 out or general I/O port. See the I/O ports, chapter 12. Timer 1 out or general I/O port. See the I/O ports, chapter 12. I2C serial clock. I2C serial data. UARXD0 UATXD0 nUADTR0 202 204 203 I O I nUADSR0 205 O UARXD1 UATXD1 nUADTR1 nUADSR1 P[7:0] XINTREQ[3:0] P[11:8] nXDREQ[1:0]/ P[13:12] nXDACK[1:0] P[15:14] TOUT0/P[16] TOUT1/P[17] SCL SDA 206 4 3 5 185-179, 176 191-189, 186 193, 192 I O I O I/O I/O 1-11 PRODUCT OVERVIEW S3C4510B Table 1-1. S3C4510B Signal Descriptions (Continued) Signal VDDP Pin No. 1, 21, 41, 56, 78, 92, 105, 118, 130, 155, 167, 177, 197 11, 31, 51, 65, 103, 142, 157, 187, 207 2, 22, 42, 57, 79, 81, 93, 106, 119, 131, 156, 168, 178, 198 12, 32, 52, 66, 104, 143, 158, 188, 208 53 54 Type Power I/O pad power Description VDDI Power Internal core power VSSP GND I/O pad ground VSSI GND Internal core ground VDDA VSSA/VBBA Power GND Analog power for PLL Analog/bulk ground for PLL NOTE: SDRAM or EDO/normal DRAM interface signal pins are shared functions. It's functions will be configured by SYSCFG[31]. 1-12 S3C4510B PRODUCT OVERVIEW Table 1-2. S3C4510B Pin List and PAD Type Group System (8) Pin Name XCLK CLKSEL nRESET CLKOEN TMODE LITTLE FILTER TAP Control (5) TCK TMS TDI TDO nTRST Memory Interface (83) ADDR[21:0] XDATA[31:0] nRAS[3:0] nCAS[3:0] nDWE nECS[3:0] nEWAIT nRCS[5:0] B0SIZE[1:0] nOE nWBE[3:0] ExtMREQ ExtMACK Pin Counts 1 1 1 1 1 1 1 1 1 1 1 1 1 22 32 4 4 1 4 1 6 2 1 4 1 1 I/O Type I O I I I I I I I I I O I O I/O O O O O I O I O O I O Pad Type ptic pob4 ptic ptis ptic ptic pticd pia_bb ptic pticu pticu ptot2 pticu ptot6 ptbsut6 ptot4 ptot4 ptot4 ptot4 ptic ptot4 ptic ptot4 ptot4 ptic pob1 Description S3C4510B system source clock. System clock out. Clock select. Not reset Clock out enable/disable. Test mode. Little endian mode select pin PLL filter pin JTAG test clock. JTAG test mode select. JTAG test data in. JTAG test data out. JTAG not reset. Address bus. External, bi-directional, 32-bit data bus. Not row address strobe for DRAM. Not column address strobe for DRAM. Not write enable Not external I/O chip select. Not external wait signal. Not ROM/SRAM/flash chip select. Bank 0 data bus access size. Not output enable. Not write byte enable. External master bus request. External bus acknowledge. Configuration MCLKO 1-13 PRODUCT OVERVIEW S3C4510B Table 1-2. S3C4510B Pin List and PAD Type (Continued) Group Ethernet Controller (18) Pin Name MDC MDIO COL/ COL_10M TX_CLK/ TXCLK_10M TXD[3:0]/ TXD_10M LOOP_10M TX_EN/ TXEN_10M TX_ERR/ PCOMP_10M Pin Counts 1 1 1 1 4 I/O Type O I/O I I O Pad Type pob4 ptbcut4 ptis ptis pob4 Description Management data clock. Management data I/O. Collision detected/collision detected for 10 M. Transmit data/transmit data for 10 M. Transmit data/transmit data for 10 M. I 1 1 1 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 O O I I 1 I I O I O O I I O I I/O O I O O I I O I I/O pob4 pob4 ptis ptis ptis ptis ptis pob4 ptis pob4 pob4 ptis ptis pob4 ptis ptbsut1 pob4 ptis pob4 pob4 ptis ptis pob4 ptis ptbsut1 Transmit enable or transmit enable for 10 M. Transmit error/packet compression enable for 10 M. Carrier sense/carrier sense for 10 M. Receive clock/receive clock for 10 M. Receive data/receive data for 10 M. Receive data valid. Receive error. HDLC channel A transmit data. HDLC channel A receive data. HDLC channel A data terminal ready. HDLC channel A request to send. HDLC channel A clear to send. HDLC channel A data carrier detected. HDLC channel A sync is detected. HDLC channel A receiver clock. HDLC channel A transmitter clock. HDLC channel B transmit data. HDLC channel B receive data. HDLC channel B data terminal ready. HDLC channel B request to send. HDLC channel B clear to send. HDLC channel B data carrier detected. HDLC channel B sync is detected. HDLC channel B receiver clock. HDLC channel B transmitter clock. CRS/ CRS_10M RX_CLK/ RXCLK_10M RXD[3:0]/ RXD_10M RX_DV/ LINK_10M RX_ERR HDLC Channel A (9) TXDA RXDA nDTRA nRTSA nCTSA nDCDA nSYNCA RXCA TXCA HDLC Channel B (9) TXDB RXDB nDTRB nRTSB nCTSB nDCDB nSYNCB RXCB TXCB 1-14 S3C4510B PRODUCT OVERVIEW Table 1-2. S3C4510B Pin List and PAD Type (Continued) Group UART 0 (5) Pin Name UCLK UARXD0 UATXD0 nUADTR0 nUADSR0 UART 1 (4) UARXD1 UATXD1 nUADTR1 NUADSR1 GeneralPurpose I/O (xINTREQ, nXDREQ, nXDACK Timer 0, 1) (18) P[7:0] xINTREQ [3:0]/P[11:8] xXDREQ [1:0]/P[13:12] nXDACK[1:0] / P[15:14] TIMER0/P [16] TIMER1/P [17] I2C (2) SCL SDA Pin Counts 1 1 1 1 1 1 1 1 1 8 4 2 2 1 1 1 1 I/O Type I I O I O I O I O I/O I/O I/O I/O I/O I/O I/O I/O Pad Type ptis ptic pob4 ptic pob4 ptic pob4 ptic pob4 ptbst4sm ptbst4sm ptbst4sm ptbst4sm ptbst4sm ptbst4sm ptbcd4 ptbcd4 Description UART External Clock for UART0/UART1 UART 0 receive data. UART 0 transmit data. Not UART 0 data terminal ready. Not UART 0 data set ready. UART 1 receive data. UART 1 transmit data. Not UART 1 data terminal ready. Not UART 1 data set ready. General I/O ports. External interrupt requests or general I/O ports. External DMA requests for GDMA or general I/O ports. External DMA acknowledge from GDMA or general I/O ports. Timer 0 out or general I/O port. Timer 1 out or general I/O port. I2C serial clock. I2C serial data. 1-15 PRODUCT OVERVIEW S3C4510B Table 1-3. S3C4510B PAD Type Pad Type ptic ptis pticu pticd pia_bb pob1 ptot2 pob4 ptot4 ptot6 ptbsut1 ptbcut4 ptbcd4 ptbst4sm Ptbsut6 I/O Type I I I I I O O O O O I/O I/O I/O I/O I/O Current Drive - - - - - 1 mA 2 mA 4 mA 4 mA 6 mA 1 mA 4 mA 4 mA 4 mA 6 mA Cell Type LVCMOS level LVCMOS schmit trigger level LVCMOS level LVCMOS level Analog input with seperate bulk bias Normal buffer Tri-state buffer Normal buffer Tri-state buffer Tri-state buffer LVCMOS schmit trigger level Tri-state buffer LVCMOS level Tri-state buffer LVCMOS level open drain buffer LVCMOS schmit trigger level LVCMOS schmit trigger level Feature 5 V-tolerant 5 V-tolerant 5 V-tolerant Pull-up register 5 V-tolerant Pull-down register - - 5 V-tolerant - 5 V-tolerant 5 V-tolerant 5 V-tolerant Pull-up register 5 V-tolerant 5 V-tolerant 5 V-tolerant 5 V-tolerant Pull-up register - - - - - - - - Medium - Medium - Slew-Rate Control - - - NOTE: pticu and pticd provides 100K Ohm Pull-up(down) register. For detail information about the pad type, see Chapter 4. Input/Output Cells of the "STD90/MDL90 0.35 um 3.3 V Standard Cell Library Data Book", produced by Samsung Electrionic Co., Ltd, ASIC Team. nRESET 64*fMCLK 512*fMCLK nRSCO NOTE: After the falling edge of nRESET, the S3C4510B count 64 cycles for a system reset and needs further 512 cycles for a TAG RAM clear of cache. After these cycles, the S3C4510B asserts nRCS0 when the nRESET is released. Figure 1-3. Reset Timing Diagram 1-16 S3C4510B PRODUCT OVERVIEW CPU CORE OVERVIEW The S3C4510B CPU core is a general purpose 32-bit ARM7TDMI microprocessor, developed by Advanced RISC Machines, Ltd. (ARM). The core architecture is based on Reduced Instruction Set Computer (RISC) principles. The RISC architecture makes the instruction set and its related decoding mechanism simpler and more efficient than those with microprogrammed Complex Instruction Set Computer (CISC) systems. High instruction throughput and impressive real-time interrupt response are among the major beneifts of the architecture. Pipelining is also employed so that all components of the processing and memory systems can operate continuously. The ARM7TDMI has a 32-bit address bus. An important feature of the ARM7TDMI processor that makes itself distinct from the ARM7 processor is a unique architectural strategy called THUMB. The THUMB strategy is an extension of the basic ARM architecture consisting of 36 instruction formats. These formats are based on the standard 32-bit ARM instruction set, while having been re-coded using 16-bit wide opcodes. As THUMB instructions are one-half the bit width of normal ARM instructions, they produce very high-density codes. When a THUMB instruction is executed, its 16-bit opcode is decoded by the processor into its equivalent instruction in the standard ARM instruction set. The ARM core then processes the 16-bit instruction as it would a normal 32-bit instruction. In other words, the THUMB architecture gives 16-bit systems a way to access the 32-bit performance of the ARM core without requiring the full overhead of 32-bit processing. As the ARM7TDMI core can execute both standard 32-bit ARM instructions and 16-bit THUMB instructions, it allows you to mix the routines of THUMB instructions and ARM code in the same address space. In this way, you can adjust code size and performance, routine by routine, to find the best programming solution for a specific application. Address Register Address Incrementer Register Bank Instruction Decoder and Logic Controll Multiplier Barrel Shifter 32-Bit ALU Write Data Register Instruction Pipeline and Read Data Register Figure 1-4. ARM7TDMI Core Block Diagram 1-17 PRODUCT OVERVIEW S3C4510B INSTRUCTION SET The S3C4510B instruction set is divided into two subsets: a standard 32-bit ARM instruction set and a 16-bit THUMB instruction set. The 32-bit ARM instruction set is comprised of thirteen basic instruction types, which can, in turn, be divided into four broad classes: * * * Four types of branch instructions which control program execution flow, instruction privilege levels, and switching between an ARM code and a THUMB code. Three types of data processing instructions which use the on-chip ALU, barrel shifter, and multiplier to perform high-speed data operations in a bank of 31 registers (all with 32-bit register widths). Three types of load and store instructions which control data transfer between memory locations and the registers. One type is optimized for flexible addressing, another for rapid context switching, and the third for swapping data. Three types of co-processor instructions which are dedicated to controlling external co-processors. These instructions extend the off-chip functionality of the instruction set in an open and uniform way. NOTE All 32-bit ARM instructions can be executed conditionally. The 16-bit THUMB instruction set contains 36 instruction formats drawn from the standard 32-bit ARM instruction set. The THUMB instructions can be divided into four functional groups: * * * * Four branch instructions. Twelve data processing instructions, which are a subset of the standard ARM data processing instructions. Eight load and store register instructions. Four load and store multiple instructions. NOTE Each 16-bit THUMB instruction has a corresponding 32-bit ARM instruction with an identical processing model. The 32-bit ARM instruction set and the 16-bit THUMB instruction set are good targets for compilers of many different high-level languages. When an assembly code is required for critical code segments, the ARM programming technique is straightforward, unlike that of some RISC processors which depend on sophisticated compiler technology to manage complicated instruction interdependencies. Pipelining is employed so that all parts of the processor and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and the third instruction is being fetched from memory. * 1-18 S3C4510B PRODUCT OVERVIEW MEMORY INTERFACE The CPU memory interface has been designed to help the highest performance potential to be realized without incurring high costs in the memory system. Speed-critical control signals are pipelined so that system control functions can be implemented in standard low-power logic. These pipelined control signals allow you to fully exploit the fast local access modes, offered by industry standard dynamic RAMs. OPERATING STATES From a programmers point of view, the ARM7TDMI core is always in one of two operating states. These states, which can be switched by software or by exception processing, are: * ARM state (when executing 32-bit, word-aligned, ARM instructions), and * THUMB state (when executing 16-bit, half-word aligned THUMB instructions). OPERATING MODES The ARM7TDMI core supports seven operating modes: * * * * * * * User mode: a normal program execution state FIQ (Fast Interrupt Request) mode: for supporting a specific data transfer or channel processing IRQ (Interrupt ReQuest) mode: for general purpose interrupt handling Supervisor mode: a protected mode for the operating system Abort mode: entered when a data or instruction pre-fetch is aborted System mode: a privileged user mode for the operating system Undefined mode: entered when an undefined instruction is executed Operating mode changes can be controlled by software. They can also be caused by external interrupts or exception processing. Most application programs execute in user mode. Privileged modes (that is, all modes other than User mode) are entered to service interrupts or exceptions, or to access protected resources. 1-19 PRODUCT OVERVIEW S3C4510B REGISTERS The S3C4510B CPU core has a total of 37 registers: 31 general-purpose 32-bit registers, and 6 status registers. Not all of these registers are always available. Whether a registers is available to the programmer at any given time depends on the current processor operating state and mode. NOTE When the S3C4510B is operating in ARM state, 16 general registers and one or two status registers can be accessed at any time. In privileged mode, mode-specific banked registers are switched in. Two register sets, or banks, can also be accessed, depending on the cores current state, the ARM state register set and the THUMB state register set: * The ARM state register set contains 16 directly accessible registers: R0-R15. All of these registers, except for R15, are for general-purpose use, and can hold either data or address values. An additional (17th) register, the CPSR (Current Program Status Register), is used to store status information. The THUMB state register set is a subset of the ARM state set. You can access 8 general registers, R0-R7, as well as the program counter (PC), a stack pointer register (SP), a link register (LR), and the CPSR. Each privileged mode has a corresponding banked stack pointer, link register, and saved process status register (SPSR). * The THUMB state registers are related to the ARM state registers as follows: * * * THUMB state R0-R7 registers and ARM state R0-R7 registers are identical THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs are identical THUMB state SP, LR, and PC are mapped directly to ARM state registers R13, R14, and R15, respectively In THUMB state, registers R8-R15 are not part of the standard register set. However, you can access them for assembly language programming and use them for fast temporary storage, if necessary. 1-20 S3C4510B PRODUCT OVERVIEW EXCEPTIONS An exception arises when the normal flow of program execution is interrupted, e.g., when processing is diverted to handle an interrupt from a peripheral. The processor state just prior to handling the exception must be preserved so that the program flow can be resumed when the exception routine is completed. Multiple exceptions may arise simultaneously. To process exceptions, the S3C4510B uses the banked core registers to save the current state. The old PC value and the CPSR contents are copied into the appropriate R14 (LR) and SPSR registers. The PC and mode bits in the CPSR are adjusted to the value corresponding to the type of exception being processed. The S3C4510B core supports seven types of exceptions. Each exception has a fixed priority and a corresponding privileged processor mode, as shown in Table 1-4. Table 1-4. S3C4510B CPU Exceptions Exception Reset Data abort FIQ IRQ Prefetch abort Undefined instruction SWI Mode on Entry Supervisor mode Abort mode FIQ mode IRQ mode Abort mode Undefined mode Supervisor mode Priority 1 (highest) 2 3 4 5 6 6 (lowest) 1-21 PRODUCT OVERVIEW S3C4510B SPECIAL REGISTERS Table 1-5. S3C4510B Special Registers Group System Manager Registers SYSCFG CLKCON EXTACON0 EXTACON1 EXTDBWTH ROMCON0 ROMCON1 ROMCON2 ROMCON3 ROMCON4 ROMCON5 DRAMCON0 DRAMCON1 DRAMCON2 DRAMCON3 REFEXTCON Ethernet (BDMA) BDMATXCON BDMARXCO N BDMATXPTR BDMARXPTR BDMARXLSZ BDMASTAT CAM BDMATXBUF BDMARXBUF Offset 0x0000 0x3000 0x3008 0x300C 0x3010 0x3014 0x3018 0x301C 0x3020 0x3024 0x3028 0x302C 0x3030 0x3034 0x3038 0x303C 0x9000 0x9004 0x9008 0x900C 0x9010 0x9014 0x9100- 0x917C 0x9200- 0x92FC 0x9800- 0x99FC R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R/W R/W Description System configuration register Clock control register External I/O timing register 1 External I/O timing register 2 Data bus width for each memory bank ROM/SRAM/Flash bank 0 control register ROM/SRAM/Flash bank 1 control register ROM/SRAM/Flash bank 2 control register ROM/SRAM/Flash bank 3 control register ROM/SRAM/Flash bank 4 control register ROM/SRAM/Flash bank 5 control register DRAM bank 0 control register DRAM bank 1 control register DRAM bank 2 control register DRAM bank 3 control register Refresh and external I/O control register Buffered DMA receive control register Buffered DMA transmit control register Transmit frame descriptor start address Receive frame descriptor start address Receive frame maximum size Buffered DMA status CAM content (32 words) BDMA Tx buffer (64 words) for test mode addressing BDMA Rx buffer (64 words) for test mode addressing Reset/Value 0x37FFFF91 0x00000000 0x00000000 0x00000000 0x00000000 0x20000060 0x00000060 0x00000060 0x00000060 0x00000060 0x00000060 0x00000000 0x00000000 0x00000000 0x00000000 0x000083FD 0x00000000 0x00000000 0x00000000 0x00000000 Undefined 0x00000000 Undefined Undefined Undefined 1-22 S3C4510B PRODUCT OVERVIEW Table 1-5. S3C4510B Special Registers (Continued) Group Ethernet (MAC) Registers MACON CAMCON MACTXCON MACTXSTAT MACRXCON MACRXSTAT STADATA STACON CAMEN EMISSCNT EPZCNT ERMPZCNT ETXSTAT HDLC Channel A HMODE HCON HSTAT HINTEN HTXFIFOC HTXFIFOT HRXFIFO HBRGTC HPRMB HSAR0 HSAR1 HSAR2 HSAR3 HMASK DMATxPTR DMARxPTR HMFLR HRBSR Offset 0xA000 0xA004 0xA008 0xA00C 0xA010 0xA014 0xA018 0xA01C 0xA028 0xA03C 0xA040 0xA044 0x9040 0x7000 0x7004 0x7008 0x700C 0x7010 0x7014 0x7018 0x701C 0x7020 0x7024 0x7028 0x702C 0x7030 0x7034 0x7038 0x703C 0x7040 0x7040 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W W W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Ethernet MAC control register CAM control register MAC transmit control register MAC transmit status register MAC receive control register MAC receive status register Station management data Station management control and address CAM enable register Missed error count register Pause count register Remote pause count register Transmit control frame status HDLC mode register HDLC control register HDLC status register HDLC interrupt enable register TxFIFO frame continue register TxFIFO frame terminate register HDLC RxFIFO entry register HDLC baud rate generate time constant HDLC preamble constant HDLC station address 0 HDLC station address 1 HDLC station address 2 HDLC station address 3 HDLC mask register DMA Tx buffer descriptor pointer DMA Rx buffer descriptor pointer Maximum frame length register DMA receive buffer size register Reset/Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00006000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00010400 0x00000000 - - 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0xFFFFFFFF 0xFFFFFFFF 0xXXXX0000 0xXXXX0000 1-23 PRODUCT OVERVIEW S3C4510B Table 1-5. S3C4510B Special Registers (Continued) Group HDLC Channel B Registers HMODE HCON HSTAT HINTEN HTXFIFOC HTXFIFOT HRXFIFO HBRGTC HPRMB HSAR0 HSAR1 HSAR2 HSAR3 HMASK DMATxPTR DMARxPTR HMFLR HRBSR I/O Ports IOPMOD IOPCON IOPDATA Interrupt Controller INTMOD INTPND INTMSK INTPRI0 INTPRI1 INTPRI2 INTPRI3 INTPRI4 INTPRI5 INTOFFSET INTOSET_FIQ INTOSET_IRQ I C Bus 2 Offset 0x8000 0x8004 0x8008 0x800C 0x8010 0x8014 0x8018 0x801C 0xA020 0x8024 0x8028 0x802C 0x8030 0x8034 0x8038 0x803C 0x8040 0x8044 0x5000 0x5004 0x5008 0x4000 0x4004 0x4008 0x400C 0x4010 0x4014 0x4018 0x401C 0x4020 0x4024 0x4030 0x4034 0XF000 0xF004 0xF008 0xF00C R/W R/W R/W R/W R/W W W R R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R/W R/W R/W R Description HDLC mode register HDLC control register HDLC status register HDLC interrupt enable register TxFIFO frame continue register TxFIFO frame terminate register HDLC RxFIFO entry register HDLC baud rate generate time constant HDLC preamble constant HDLC station address 0 HDLC station address 1 HDLC station address 2 HDLC station address 3 HDLC mask register DMA Tx buffer descriptor pointer DMA Rx buffer descriptor pointer Maximum frame length register DMA receive buffer size register I/O port mode register I/O port control register Input port data register Interrupt mode register Interrupt pending register Interrupt mask register Interrupt priority register 0 Interrupt priority register 1 Interrupt priority register 2 Interrupt priority register 3 Interrupt priority register 4 Interrupt priority register 5 Interrupt offset address register FIQ interrupt offset register IRQ interrupt offset register I C bus control status register I C bus shift buffer register I C bus prescaler register I C bus prescaler counter register 2 2 2 2 Reset/Value 0x00000000 0x00000000 0x00010400 0x00000000 - - 0x00000000 0x00000000 0x00000000 0x00006000 0x00000000 0x00000000 0x00000000 0x00000000 0xFFFFFFFF 0xFFFFFFFF 0xXXXX0000 0xXXXX0000 0x00000000 0x00000000 Undefined 0x00000000 0x00000000 0x003FFFFF 0x03020100 0x07060504 0x0B0A0908 0x0F0E0D0C 0x13121110 0x00000014 0x00000054 0x00000054 0x00000054 0x00000054 Undefined 0x00000000 0x00000000 IICCON IICBUF IICPS IICCOUNT 1-24 S3C4510B PRODUCT OVERVIEW Table 1-5. S3C4510BC Special Registers (Continued) Group GDMA Registers GDMACON0 GDMACON1 GDMASRC0 GDMADST0 GDMASRC1 GDMADST1 GDMACNT0 GDMACNT1 UART ULCON0 ULCON1 UCON0 UCON1 USTAT0 USTAT1 UTXBUF0 UTXBUF1 URXBUF0 URXBUF1 UBRDIV0 UBRDIV1 Timers TMOD TDATA0 TDATA1 TCNT0 TCNT1 Offset 0xB000 0xC000 0xB004 0xB008 0xC004 0xC008 0xB00C 0xC00C 0xD000 0xE000 0xD004 0xE004 0xD008 0xE008 0xD00C 0xE00C 0xD010 0xE010 0xD014 0xE014 0x6000 0x6004 0x6008 0x600C 0x6010 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R W W R R R/W R/W R/W R/W R/W R/W R/W Description GDMA channel 0 control register GDMA channel 1 control register GDMA source address register 0 GDMA destination address register 0 GDMA source address register 1 GDMA destination address register 1 GDMA channel 0 transfer count register GDMA channel 1 transfer count register UART channel 0 line control register UART channel 1 line control register UART channel 0 control register UART channel 1 control register UART channel 0 status register UART channel 1 status register UART channel 0 transmit holding register UART channel 1 transmit holding register UART channel 0 receive buffer register UART channel 1 receive buffer register Baud rate divisor register 0 Baud rate divisor register 1 Timer mode register Timer 0 data register Timer 1 data register Timer 0 count register Timer 1 count register Reset/Value 0x00000000 0x00000000 Undefined Undefined Undefined Undefined Undefined Undefined 0x00 0x00 0x00 0x00 0xC0 0xC0 Undefined Undefined Undefined Undefined 0x00 0x00 0x00000000 0x00000000 0x00000000 0xFFFFFFFF 0xFFFFFFFF 1-25 PRODUCT OVERVIEW S3C4510B NOTES 1-26 S3C4510B PROGRAMMER'S MODEL 2 OVERVIEW PROGRAMMERS MODEL S3C4510B was developed using the advanced ARM7TDMI core designed by advanced RISC machines, Ltd. Processor Operating States From the programmers point of view, the ARM7TDMI can be in one of two states: -- ARM state which executes 32-bit, word-aligned ARM instructions. -- THUMB state which operates with 16-bit, half-word-aligned THUMB instructions. In this state, the PC uses bit 1 to select between alternate half-words. NOTE Transition between these two states does not affect the processor mode or the contents of the registers. SWITCHING STATE Entering THUMB State Entry into THUMB state can be achieved by executing a BX instruction with the state bit (bit 0) set in the operand register. Transition to THUMB state will also occur automatically on return from an exception (IRQ, FIQ, UNDEF, ABORT, SWI etc.), if the exception was entered with the processor in THUMB state. Entering ARM State Entry into ARM state happens: 1. On execution of the BX instruction with the state bit clear in the operand register. 2. On the processor taking an exception (IRQ, FIQ, RESET, UNDEF, ABORT, SWI etc.). In this case, the PC is placed in the exception modes link register, and execution commences at the exceptions vector address. MEMORY FORMATS ARM7TDMI views memory as a linear collection of bytes numbered upwards from zero. Bytes 0 to 3 hold the first stored word, bytes 4 to 7 the second and so on. ARM7TDMI can treat words in memory as being stored either in Big-Endian or Little-Endian format. 2-1 PROGRAMMER'S MODEL S3C4510B BIG-ENDIAN FORMAT In Big-Endian format, the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte. Byte 0 of the memory system is therefore connected to data lines 31 through 24. Higher address 31 24 8 4 0 9 5 9 5 1 15 87 0 Word address 10 6 2 11 7 3 8 4 0 Lower address w w Most significant byte is at lowest address Word is addressed by byte address of most signficant byte Figure 2-1. Big-Endian Addresses of Bytes within Words NOTE The data locations in the external memory are different with Figure 2-1 in the S3C4620. Please refer to the chapter 4, system manager. LITTLE-ENDIAN FORMAT In Little-Endian format, the lowest numbered byte in a word is considered the words least significant byte, and the highest numbered byte the most significant. Byte 0 of the memory system is therefore connected to data lines 7 through 0. Higher address 31 24 11 7 3 23 16 10 6 2 15 87 0 Word address 9 5 1 8 4 0 8 4 0 Lower address w w Most significant byte is at lowest address Word is addressed by byte address of least signficant byte Figure 2-2. Little-Endian Addresses of Bytes Words 2-2 S3C4510B PROGRAMMER'S MODEL INSTRUCTION LENGTH Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB state). Data Types ARM7TDMI supports byte (8-bit), half-word (16-bit) and word (32-bit) data types. Words must be aligned to fourbyte boundaries and half words to two-byte boundaries. OPERATING MODES ARM7TDMI supports seven modes of operation: -- User (usr): -- FIQ (fiq): -- IRQ (irq): -- Supervisor (svc): -- Abort mode (abt): -- System (sys): -- Undefined (und): The normal ARM program execution state Designed to support a data transfer or channel process Used for general-purpose interrupt handling Protected mode for the operating system Entered after a data or instruction prefetch abort A privileged user mode for the operating system Entered when an undefined instruction is executed Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs will execute in User mode. The non-user modes known as privileged modes-are entered in order to service interrupts or exceptions, or to access protected resources. 2-3 PROGRAMMER'S MODEL S3C4510B REGISTERS ARM7TDMI has a total of 37 registers-31 general-purpose 32-bit registers and six status registers - but these cannot all be seen at once. The processor state and operating mode dictate which registers are available to the programmer. The ARM State Register Set In ARM state, 16 general registers and one or two status registers are visible at any one time. In privileged (nonUser) modes, mode-specific banked registers are switched in. Figure 2-3 shows which registers are available in each mode: the banked registers are marked with a shaded triangle. The ARM state register set contains 16 directly accessible registers: R0 to R15. All of these except R15 are general-purpose, and may be used to hold either data or address values. In addition to these, there is a seventeenth register used to store status information. Register 14 is used as the subroutine link register. This receives a copy of R15 when a branch and link (BL) instruction is executed. At all other times it may be treated as a general-purpose register. The corresponding banked registers R14_svc, R14_irq, R14_fiq, R14_abt and R14_und are similarly used to hold the return values of R15 when interrupts and exceptions arise, or when branch and link instructions are executed within interrupt or exception routines. holds the Program Counter (PC). In ARM state, bits [1:0] of R15 are zero and bits [31:2] contain the PC. In THUMB state, bit [0] is zero and bits [31:1] contain the PC. is the CPSR (Current Program Status Register). This contains condition code flags and the current mode bits. Register 15 Register 16 FIQ mode has seven banked registers mapped to R8-14 (R8_fiq-R14_fiq). In ARM state, many FIQ handlers do not need to save any registers. User, IRQ, Supervisor, Abort and Undefined each have two banked registers mapped to R13 and R14, allowing each of these modes to have a private stack pointer and link registers. 2-4 S3C4510B PROGRAMMER'S MODEL ARM State General Registers and Program Counter System & User R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 (PC) R0 R1 R2 R3 R4 R5 R6 R7 R8_fiq R9_fiq R10_fiq R11_fiq R12_fiq R13_fiq R14_fiq R15 (PC) FIQ Supervisor R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_svc R14_svc R15 (PC) About R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_abt R14_abt R15 (PC) IRG R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_irq R14_irq R15 (PC) Undefined R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_und R14_und R15 (PC) ARM State Program Status Register CPSR CPSR SPSR_fiq = banked register CPSR SPSR_svc CPSR SPSR_abt CPSR SPSR_irq CPSR SPSR_und Figure 2-3. Register Organization in ARM State 2-5 PROGRAMMER'S MODEL S3C4510B The THUMB State Register Set The THUMB state register set is a subset of the ARM state set. The programmer has direct access to eight general registers, R0-R7, as well as the Program Counter (PC), a stack pointer register (SP), a link register (LR), and the CPSR. There are banked stack pointers, link registers and Saved Process Status Registers (SPSRs) for each privileged mode. This is shown in Figure 2-4. THUMB State General Registers and Program Counter System & User R0 R1 R2 R3 R4 R5 R6 R7 SP LR PC FIQ R0 R1 R2 R3 R4 R5 R6 R7 SP_fiq LR_fiq PC Supervisor R0 R1 R2 R3 R4 R5 R6 R7 SP_svg LR_svc PC About R0 R1 R2 R3 R4 R5 R6 R7 SP_abt LR_abt PC IRG R0 R1 R2 R3 R4 R5 R6 R7 SP_irq LR_irq PC Undefined R0 R1 R2 R3 R4 R5 R6 R7 SP_und LR_und PC THUMB State Program Status Registers CPSR CPSR SPSR_fiq = banked register CPSR SPSR_svc CPSR SPSR_abt CPSR SPSR_irq CPSR SPSR_und Figure 2-4. Register Organization in THUMB State 2-6 S3C4510B PROGRAMMER'S MODEL The Relationship between ARM and THUMB State Registers The THUMB state registers relate to the ARM state registers in the following way: -- THUMB state R0-R7 and ARM state R0-R7 are identical -- THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs are identical -- THUMB state SP maps onto ARM state R13 -- THUMB state LR maps onto ARM state R14 -- The THUMB state program counter maps onto the ARM state program counter (R15) This relationship is shown in Figure 2-5. THUMB State R0 R1 R2 R3 R4 R5 R6 R7 ARM State R0 R1 R3 R4 R5 R6 R7 R8 R9 R11 R12 Hi-registers R10 Lo-registers R2 Stack Pointer (SP) Link Register (LR) Program Counter (PC) CPSR SPSR Stack Pointer (R13) Link Register (R14) Program Counter (R15) CPSR SPSR Figure 2-5. Mapping of THUMB State Registers onto ARM State Registers 2-7 PROGRAMMER'S MODEL S3C4510B Accessing Hi-Registers in THUMB State In THUMB state, registers R8-R15 (the Hi registers) are not part of the standard register set. However, the assembly language programmer has limited access to them, and can use them for fast temporary storage. A value may be transferred from a register in the range R0-R7 (a Lo register) to a Hi register, and from a Hi register to a Lo register, using special variants of the MOV instruction. Hi register values can also be compared against or added to Lo register values with the CMP and ADD instructions. For more information, refer to Figure 3-34. THE PROGRAM STATUS REGISTERS The ARM7TDMI contains a Current Program Status Register (CPSR), plus five Saved Program Status Registers (SPSRs) for use by exception handlers. These registers functions are: -- Hold information about the most recently performed ALU operation -- Control the enabling and disabling of interrupts -- Set the processor operating mode The arrangement of bits is shown in Figure 2-6. Condition Code Flags 31 N 30 Z 29 C 28 V 27 . 26 . (Reserved) 25 . 24 . . 8 . 7 I 6 F 5 T Control Bits 4 M4 3 M3 2 M2 1 M1 0 M0 Overflow Carry/Borrow/Extend Zero Negative/Less Than Mode bits State bit FIQ disable IRQ disable Figure 2-6. Program Status Register Format 2-8 S3C4510B PROGRAMMER'S MODEL The Condition Code Flags The N, Z, C and V bits are the condition code flags. These may be changed as a result of arithmetic and logical operations, and may be tested to determine whether an instruction should be executed. In ARM state, all instructions may be executed conditionally: see Table 3-2 for details. In THUMB state, only the branch instruction is capable of conditional execution: see Figure 3-46 for details. The Control Bits The bottom 8 bits of a PSR (incorporating I, F, T and M[4:0]) are known collectively as the control bits. These will change when an exception arises. If the processor is operating in a privileged mode, they can also be manipulated by software. The T bit This reflects the operating state. When this bit is set, the processor is executing in THUMB state, otherwise it is executing in ARM state. This is reflected on the TBIT external signal. Note that the software must never change the state of the TBIT in the CPSR. If this happens, the processor will enter an unpredictable state. Interrupt disable bits The mode bits The I and F bits are the interrupt disable bits. When set, these disable the IRQ and FIQ interrupts respectively. The M4, M3, M2, M1 and M0 bits (M[4:0]) are the mode bits. These determine the processors operating mode, as shown in Table 2-1. Not all combinations of the mode bits define a valid processor mode. Only those explicitly described shall be used. The user should be aware that if any illegal value is programmed into the mode bits, M[4:0], then the processor will enter an unrecoverable state. If this occurs, reset should be applied. 2-9 PROGRAMMER'S MODEL S3C4510B Table 2-1. PSR Mode. Bit Values M[4:0] 10000 Mode User Visible THUMB State Registers R7..R0, LR, SP PC, CPSR 10001 FIQ R7..R0, LR_fiq, SP_fiq PC, CPSR, SPSR_fiq 10010 IRQ R7..R0, LR_irq, SP_irq PC, CPSR, SPSR_irq 10011 Supervisor R7..R0, LR_svc, SP_svc, PC, CPSR, SPSR_svc 10111 Abort R7..R0, LR_abt, SP_abt, PC, CPSR, SPSR_abt 11011 Undefined R7..R0 LR_und, SP_und, PC, CPSR, SPSR_und 11111 System R7..R0, LR, SP PC, CPSR R7..R0, R14_fiq..R8_fiq, PC, CPSR, SPSR_fiq R12..R0, R14_irq..R13_irq, PC, CPSR, SPSR_irq R12..R0, R14_svc..R13_svc, PC, CPSR, SPSR_svc R12..R0, R14_abt..R13_abt, PC, CPSR, SPSR_abt R12..R0, R14_und..R13_und, PC, CPSR R14..R0, PC, CPSR Visible ARM State Registers R14..R0, PC, CPSR Reserved bits The remaining bits in the PSRs are reserved. When changing a PSRs flag or control bits, you must ensure that these unused bits are not altered. Also, your program should not rely on them containing specific values, since in future processors they may read as one or zero. 2-10 S3C4510B PROGRAMMER'S MODEL EXCEPTIONS Exceptions arise whenever the normal flow of a program has to be halted temporarily, for example to service an interrupt from a peripheral. Before an exception can be handled, the current processor state must be preserved so that the original program can resume when the handler routine has finished. It is possible for several exceptions to arise at the same time. If this happens, they are dealt with in a fixed order. See Exception Priorities on page 2-14. Action on Entering an Exception When handling an exception, the ARM7TDMI: 1. Preserves the address of the next instruction in the appropriate Link Register. If the exception has been entered from ARM state, then the address of the next instruction is copied into the Link Register (that is, current PC + 4 or PC + 8 depending on the exception. See Table 2-2 on for details). If the exception has been entered from THUMB state, then the value written into the Link Register is the current PC offset by a value such that the program resumes from the correct place on return from the exception. This means that the exception handler need not determine which state the exception was entered from. For example, in the case of SWI, MOVS PC, R14_svc will always return to the next instruction regardless of whether the SWI was executed in ARM or THUMB state. 2. Copies the CPSR into the appropriate SPSR 3. Forces the CPSR mode bits to a value which depends on the exception 4. Forces the PC to fetch the next instruction from the relevant exception vector It may also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions. If the processor is in THUMB state when an exception occurs, it will automatically switch into ARM state when the PC is loaded with the exception vector address. Action on Leaving an Exception On completion, the exception handler: 1. Moves the Link Register, minus an offset where appropriate, to the PC. (The offset will vary depending on the type of exception.) 2. Copies the SPSR back to the CPSR 3. Clears the interrupt disable flags, if they were set on entry NOTE An explicit switch back to THUMB state is never needed, since restoring the CPSR from the SPSR automatically sets the T bit to the value it held immediately prior to the exception. 2-11 PROGRAMMER'S MODEL S3C4510B Exception Entry/Exit Summary Table 2-2 summarizes the PC value preserved in the relevant R14 on exception entry, and the recommended instruction for exiting the exception handler. Table 2-2. Exception Entry/Exit Return Instruction BL SWI UDEF FIQ IRQ PABT DABT RESET MOV PC, R14 MOVS PC, R14_svc MOVS PC, R14_und SUBS PC, R14_fiq, #4 SUBS PC, R14_irq, #4 SUBS PC, R14_abt, #4 SUBS PC, R14_abt, #8 NA PC + 4 PC + 4 PC + 4 PC + 4 PC + 4 PC + 4 PC + 8 - Previous State ARM R14_x THUMB R14_x PC + 2 PC + 2 PC + 2 PC + 4 PC + 4 PC + 4 PC + 8 - 1 1 1 2 2 1 3 4 Notes NOTES: 1. Where PC is the address of the BL/SWI/Undefined Instruction fetch which had the prefetch abort. 2. Where PC is the address of the instruction which did not get executed since the FIQ or IRQ took priority. 3. Where PC is the address of the Load or Store instruction which generated the data abort. 4. The value saved in R14_svc upon reset is unpredictable. FIQ The FIQ (Fast Interrupt Request) exception is designed to support a data transfer or channel process, and in ARM state has sufficient private registers to remove the need for register saving (thus minimizing the overhead of context switching). FIQ is externally generated by taking the nFIQ input LOW. This input can except either synchronous or asynchronous transitions, depending on the state of the ISYNC input signal. When ISYNC is LOW, nFIQ and nIRQ are considered asynchronous, and a cycle delay for synchronization is incurred before the interrupt can affect the processor flow. Irrespective of whether the exception was entered from ARM or Thumb state, a FIQ handler should leave the interrupt by executing SUBS PC,R14_fiq,#4 FIQ may be disabled by setting the CPSR's F flag (but note that this is not possible from User mode). If the F flag is clear, ARM7TDMI checks for a LOW level on the output of the FIQ synchroniser at the end of each instruction. 2-12 S3C4510B PROGRAMMER'S MODEL IRQ The IRQ (Interrupt Request) exception is a normal interrupt caused by a LOW level on the nIRQ input. IRQ has a lower priority than FIQ and is masked out when a FIQ sequence is entered. It may be disabled at any time by setting the I bit in the CPSR, though this can only be done from a privileged (non-User) mode. Irrespective of whether the exception was entered from ARM or Thumb state, an IRQ handler should return from the interrupt by executing SUBS Abort An abort indicates that the current memory access cannot be completed. It can be signalled by the external ABORT input. ARM7TDMI checks for the abort exception during memory access cycles. There are two types of abort: -- PC,R14_irq,#4 Prefetch abort: occurs during an instruction prefetch. -- Data abort: occurs during a data access. If a prefetch abort occurs, the prefetched instruction is marked as invalid, but the exception will not be taken until the instruction reaches the head of the pipeline. If the instruction is not executed - for example because a branch occurs while it is in the pipeline - the abort does not take place. If a data abort occurs, the action taken depends on the instruction type: -- Single data transfer instructions (LDR, STR) write back modified base registers: the Abort handler must be aware of this. The swap instruction (SWP) is aborted as though it had not been executed. Block data transfer instructions (LDM, STM) complete. If write-back is set, the base is updated. If the instruction would have overwritten the base with data (ie it has the base in the transfer list), the overwriting is prevented. All register overwriting is prevented after an abort is indicated, which means in particular that R15 (always the last register to be transferred) is preserved in an aborted LDM instruction. -- -- The abort mechanism allows the implementation of a demand paged virtual memory system. In such a system the processor is allowed to generate arbitrary addresses. When the data at an address is unavailable, the Memory Management Unit (MMU) signals an abort. The abort handler must then work out the cause of the abort, make the requested data available, and retry the aborted instruction. The application program needs no knowledge of the amount of memory available to it, nor is its state in any way affected by the abort. After fixing the reason for the abort, the handler should execute the following irrespective of the state (ARM or Thumb): SUBS SUBS PC,R14_abt,#4 PC,R14_abt,#8 ; for a prefetch abort, or ; for a data abort This restores both the PC and the CPSR, and retries the aborted instruction. 2-13 PROGRAMMER'S MODEL S3C4510B Software Interrupt The software interrupt instruction (SWI) is used for entering Supervisor mode, usually to request a particular supervisor function. A SWI handler should return by executing the following irrespective of the state (ARM or Thumb): MOV PC,R14_svc This restores the PC and CPSR, and returns to the instruction following the SWI. NOTE nFIQ, nIRQ, ISYNC, LOCK, BIGEND, and ABORT pins exist only in the ARM7TDMI CPU core. Undefined Instruction When ARM7TDMI comes across an instruction which it cannot handle, it takes the undefined instruction trap. This mechanism may be used to extend either the THUMB or ARM instruction set by software emulation. After emulating the failed instruction, the trap handler should execute the following irrespective of the state (ARM or Thumb): MOVS PC,R14_und This restores the CPSR and returns to the instruction following the undefined instruction. Exception Vectors The following table shows the exception vector addresses. Table 2-3. Exception Vectors Address 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000014 0x00000018 0x0000001C Reset Undefined instruction Software Interrupt Abort (prefetch) Abort (data) Reserved IRQ FIQ Exception Mode in Entry Supervisor Undefined Supervisor Abort Abort Reserved IRQ FIQ 2-14 S3C4510B PROGRAMMERS MODEL Exception Priorities When multiple exceptions arise at the same time, a fixed priority system determines the order in which they are handled: Highest priority: 1. Reset 2. Data abort 3. FIQ 4. IRQ 5. Prefetch abort Lowest priority: 6. Undefined Instruction, Software interrupt. Not All Exceptions Can Occur at Once: Undefined Instruction and Software Interrupt are mutually exclusive, since they each correspond to particular (non-overlapping) decoding of the current instruction. If a data abort occurs at the same time as a FIQ, and FIQs are enabled (ie the CPSR's F flag is clear), ARM7TDMI enters the data abort handler and then immediately proceeds to the FIQ vector. A normal return from FIQ will cause the data abort handler to resume execution. Placing data abort at a higher priority than FIQ is necessary to ensure that the transfer error does not escape detection. The time for this exception entry should be added to worst-case FIQ latency calculations. 2-15 PROGRAMMERS MODEL S3C4510B Interrupt Latencies The worst case latency for FIQ, assuming that it is enabled, consists of the longest time the request can take to pass through the synchroniser (Tsyncmax if asynchronous), plus the time for the longest instruction to complete (Tldm, the longest instruction is an LDM which loads all the registers including the PC), plus the time for the data abort entry (Texc), plus the time for FIQ entry (Tfiq). At the end of this time ARM7TDMI will be executing the instruction at 0x1C. Tsyncmax is 3 processor cycles, Tldm is 20 cycles, Texc is 3 cycles, and Tfiq is 2 cycles. The total time is therefore 28 processor cycles. This is just over 1.4 microseconds in a system which uses a continuous 20 MHz processor clock. The maximum IRQ latency calculation is similar, but must allow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time. The minimum latency for FIQ or IRQ consists of the shortest time the request can take through the synchroniser (Tsyncmin) plus Tfiq. This is 4 processor cycles. Reset When the nRESET signal goes LOW, ARM7TDMI abandons the executing instruction and then continues to fetch instructions from incrementing word addresses. When nRESET goes HIGH again, ARM7TDMI: 1. Overwrites R14_svc and SPSR_svc by copying the current values of the PC and CPSR into them. The value of the saved PC and SPSR is not defined. 2. Forces M[4:0] to 10011 (Supervisor mode), sets the I and F bits in the CPSR, and clears the CPSR's T bit. 3. Forces the PC to fetch the next instruction from address 0x00. 4. Execution resumes in ARM state. 2-16 S3C4510B INSTRUCTION SET 3 Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond INSTRUCTION SET INSTRUCTION SET SUMMAY This chapter describes the ARM instruction set and the THUMB instruction set in the ARM7TDMI core. FORMAT SUMMARY The ARM instruction set formats are shown below. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 00 00 00 00 00 00 00 01 01 10 10 11 11 11 11 1 Opcode S Rn Rd RdHi Rn 111 Rn Rn Rn Rd Rn RnLo Rd 11 11 Rs Rn 00 11 00 65 4 3 210 Data processing/ PSR Transfer Rm Rm Rm Rn Rm Offset Multiply Multiply Long Single data swap Branch and exchange Halfword data transfer: register offset Halfword data transfer: immediate offset Single data transfer Operand2 1 1 00 00 00 00 1 1 1 1 000 0AS 001UAS 010B0 010 0 1 0 01 001 110 0 P U0 WL 0 P U1 WL 1 P UB WL 1 0 P US WL 1L 0 P UNWL 10 10 11 CP Opc CP Opc L Rd Rd Rd 001SH1 1SH1 Offset 1 Offset Undefined Block data transfer Branch Rn Offset Rn CRn CRn CRd CRd Rd Register List CP# CP# CP# CP# CP# Offset 0 1 CRm CRm Coprocessor data transfer Coprocessor data Operation Coprocessor register Transfer Software Interrupt Ignored by processor 65 4 3 210 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 Figure 3-1. ARM Instruction Set Format NOTE Some instruction codes are not defined but do not cause the Undefined instruction trap to be taken, for instance a Multiply instruction with bit 6 changed to a 1. These instructions should not be used, as their action may change in future ARM implementations. 3-1 INSTRUCTION SET S3C4510B INSTRUCTION SUMMARY Table 3-1. The ARM Instruction Set Mnemonic ADC ADD AND B BIC BL BX CDP CMN CMP EOR LDC LDM LDR MCR MLA MOV MRC MRS MSR MUL MVN Add with carry Add AND Branch Bit clear Branch with link Branch and exchange Coprocessor data processing Compare negative Compare Exclusive OR Load coprocessor from memory Load multiple registers Load register from memory Move CPU register to coprocessor register Multiply accumulate Move register or constant Move from coprocessor register to CPU register Move PSR status/flags to register Move register to PSR status/flags Multiply Move negative register Instruction Rd: = Rn + Op2 Rd: = Rn AND Op2 R15: = address Rd: = Rn AND NOT Op2 R14: = R15, R15: = address R15: = Rn, T bit: = Rn[0] (coprocessor-specific) CPSR flags: = Rn + Op2 CPSR flags: = Rn - Op2 Rd: = (Rn AND NOT Op2) OR (op2 AND NOT Rn) Coprocessor load Stack manipulation (Pop) Rd: = (address) cRn: = rRn { 3-2 S3C4510B INSTRUCTION SET Table 3-1. The ARM Instruction Set (Continued) Mnemonic ORR RSB RSC SBC STC STM STR SUB SWI SWP TEQ TST OR Reverse subtract Reverse subtract with carry Subtract with carry Store coprocessor register to memory Store multiple Store register to memory Subtract Software Interrupt Swap register with memory Test bit-wise equality Test bits Instruction Rd: = Op2 - Rn Rd: = Op2 - Rn-1 + Carry Rd: = Rn - Op2-1 + Carry Address: = CRn Stack manipulation (push) : = Rd Rd: = Rn - Op2 OS call Rd: = [Rn], [Rn] := Rm CPSR flags: = Rn EOR Op2 CPSR flags: = Rn AND Op2 Action Rd: = Rn OR Op2 3-3 INSTRUCTION SET S3C4510B THE CONDITION FIELD In ARM state, all instructions are conditionally executed according to the state of the CPSR condition codes and the instructions condition field. This field (bits 31:28) determines the circumstances under which an instruction is to be executed. If the state of the C, N, Z and V flags fulfils the conditions encoded by the field, the instruction is executed, otherwise it is ignored. There are sixteen possible conditions, each represented by a two-character suffix that can be appended to the instructions mnemonic. For example, a branch (B in assembly language) becomes BEQ for "Branch if "Equal", which means the branch will only be taken if the Z flag is set. In practice, fifteen different conditions may be used: these are listed in Table 3-2. The sixteenth (1111) is reserved, and must not be used. In the absence of a suffix, the condition field of most instructions is set to "Always" (suffix AL). This means the instruction will always be executed regardless of the CPSR condition codes. Table 3-2. Condition Code Summary Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 Suffix EQ NE CS CC MI PL VS VC HI LS GE LT GT LE AL Z set Z clear C set C clear N set N clear V set V clear C set and Z clear C clear or Z set N equals V N not equal to V Z clear AND (N equals V) Z set OR (N not equal to V) (Ignored) Flags Equal Not equal Unsigned higher or same Unsigned lower Negative Positive or zero Overflow No overflow Unsigned higher Unsigned lower or same Greater or equal Less than Greater than Less than or equal Always Meaning 3-4 S3C4510B INSTRUCTION SET BRANCH AND EXCHANGE (BX) This instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. This instruction performs a branch by copying the contents of a general register, Rn, into the program counter, PC. The branch causes a pipeline flush and refill from the address specified by Rn. This instruction also permits the instruction set to be exchanged. When the instruction is executed, the value of Rn[0] determines whether the instruction stream will be decoded as ARM or THUMB instructions. 31 Cond 28 27 24 23 20 19 16 15 12 11 87 43 Rn 0 000100101111111111110001 [3:0] Operand Register If bit0 of Rn = 1, subsequent instructions decoded as THUMB instructions If bit0 of Rn =0, subsequent instructions decoded as ARM instructions [31:28] Condition Field Figure 3-2. Branch and Exchange Instructions INSTRUCTION CYCLE TIMES The BX instruction takes 2S + 1N cycles to execute, where S and N are defined as sequential (S-cycle) and nonsequential (N-cycle), respectively. ASSEMBLER SYNTAX BX - branch and exchange. BX {cond} Rn {cond} Rn Two character condition mnemonic. See Table 3-2. is an expression evaluating to a valid register number. USING R15 AS AN OPERAND If R15 is used as an operand, the behaviour is undefined. 3-5 INSTRUCTION SET S3C4510B Examples ADR R0, Into_THUMB + 1 ; ; ; ; ; ; ; Generate branch target address and set bit 0 high - hence arrive in THUMB state. Branch and change to THUMB state. Assemble subsequent code as THUMB instructions BX CODE16 Into_THUMB * * * R0 ADR R5, Back_to_ARM BX R5 * * * ; Generate branch target to word aligned address ; - hence bit 0 is low and so change back to ARM state. ; Branch and change back to ARM state. ALIGN CODE32 Back_to_ARM ; Word align ; Assemble subsequent code as ARM instructions 3-6 S3C4510B INSTRUCTION SET BRANCH AND BRANCH WITH LINK (B, BL) The instruction is only executed if the condition is true. The various conditions are defined Table 3-2. The instruction encoding is shown in Figure 3-3, below. 31 Cond 28 27 101 25 24 23 L Offset 0 [24] Link Bit 0 = Branch 1 = Branch with link [31:28] Condition Field Figure 3-3. Branch Instructions Branch instructions contain a signed 2's complement 24 bit offset. This is shifted left two bits, sign extended to 32 bits, and added to the PC. The instruction can therefore specify a branch of +/- 32Mbytes. The branch offset must take account of the pre-fetch operation, which causes the PC to be 2 words (8 bytes) ahead of the current instruction. THE LINK BIT Branch with Link (BL) writes the old PC into the link register (R14) of the current bank. The PC value written into R14 is adjusted to allow for the pre-fetch, and contains the address of the instruction following the branch and link instruction. Note that the CPSR is not saved with the PC and R14[1:0] are always cleared. To return from a routine called by branch with link use MOV PC,R14 if the link register is still valid or LDM Rn!,{..PC} if the link register has been saved onto a stack pointed to by Rn. INSTRUCTION CYCLE TIMES Branch and branch with link instructions take 2S + 1N incremental cycles, where S and N are defined as sequential (S-cycle) and internal (I-cycle). 3-7 INSTRUCTION SET S3C4510B ASSEMBLER SYNTAX Items in {} are optional. Items in < > must be present. B{L}{cond} {cond} here there R1,#0 fred sub+ROM R1,#1 sub ; ; ; ; ; ; ; ; ; ; Assembles to 0xEAFFFFFE (note effect of PC offset). Always condition used as default. Compare R1 with zero and branch to fred if R1 was zero, otherwise continue. Continue to next instruction. Call subroutine at computed address. Add 1 to register 1, setting CPSR flags on the result then call subroutine if the C flag is clear, which will be the case unless R1 held 0xFFFFFFFF. 3-8 S3C4510B INSTRUCTION SET DATA PROCESSING The data processing instruction is only executed if the condition is true. The conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-4. 31 Cond 28 27 26 25 24 00 L 21 20 19 S Rn 16 15 Rd 12 11 Operand2 0 Opcode [15:12] Destination Register 0 = Branch 1 = Branch with Link [19:16] 1st operand Register 0 = Branch 1 = Branch with Link [20] Set condition Codes 0 = Do not after condition codes 1 = Set condition codes [24:21] Operation Code 0000 = AND-Rd: = Op1 AND Op2 0001 = EOR-Rd: = Op1 EOR Op2 0010 = SUB-Rd: = Op1-Op2 0011 = RSB-Rd: = Op2-Op1 0100 = ADD-Rd: = Op1+Op2 0101 = ADC-Rd: = Op1+Op2+C 0110 = SBC-Rd: = OP1-Op2+C-1 0111 = RSC-Rd: = Op2-Op1+C-1 1000 = TST-set condition codes on Op1 AND Op2 1001 = TEO-set condition codes on OP1 EOR Op2 1010 = CMP-set condition codes on Op1-Op2 1011 = SMN-set condition codes on Op1+Op2 1100 = ORR-Rd: = Op1 OR Op2 1101 = MOV-Rd: =OP2 1110 = BIC-Rd: = Op1 AND NOT Op2 1111 = MVN-Rd: = NOT Op2 [25] Immediate Operand 0 = Operand 2 is a register 1 = Operand 2 is an immediate Value [11:0] Operand 2 Type Selection 11 Shift [3:0] 2nd Operand Register 11 Rotate 87 Imm [11:8] Shift applied to Imm 34 Rm [11:4] Shift applied to Rm 0 0 [7:0] Unsigned 8 bit immediate value [31:28] Condition Field Figure 3-4. Data Processing Instructions 3-9 INSTRUCTION SET S3C4510B The instruction produces a result by performing a specified arithmetic or logical operation on one or two operands. The first operand is always a register (Rn). The second operand may be a shifted register (Rm) or a rotated 8 bit immediate value (Imm) according to the value of the I bit in the instruction. The condition codes in the CPSR may be preserved or updated as a result of this instruction, according to the value of the S bit in the instruction. Certain operations (TST, TEQ, CMP, CMN) do not write the result to Rd. They are used only to perform tests and to set the condition codes on the result and always have the S bit set. The instructions and their effects are listed in Table 3-3. 3-10 S3C4510B INSTRUCTION SET CPSR FLAGS The data processing operations may be classified as logical or arithmetic. The logical operations (AND, EOR, TST, TEQ, ORR, MOV, BIC, MVN) perform the logical action on all corresponding bits of the operand or operands to produce the result. If the S bit is set (and Rd is not R15, see below) the V flag in the CPSR will be unaffected, the C flag will be set to the carry out from the barrel shifter (or preserved when the shift operation is LSL #0), the Z flag will be set if and only if the result is all zeros, and the N flag will be set to the logical value of bit 31 of the result. Table 3-3. ARM Data Processing Instructions Assembler Mnemonic AND EOR SUB RSB ADD ADC SBC RSC TST TEQ CMP CMN ORR MOV BIC MVN Opcode 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Action Operand1 AND operand2 Operand1 EOR operand2 Operand1 - operand2 Operand2 - operand1 Operand1 + operand2 Operand1 + operand2 + carry Operand1 - operand2 + carry - 1 Operand2 - operand1 + carry - 1 As AND, but result is not written As EOR, but result is not written As SUB, but result is not written As ADD, but result is not written Operand1 OR operand2 Operand2 (operand1 is ignored) Operand1 AND NOT operand2 (Bit clear) NOT operand2 (operand1 is ignored) The arithmetic operations (SUB, RSB, ADD, ADC, SBC, RSC, CMP, CMN) treat each operand as a 32 bit integer (either unsigned or 2's complement signed, the two are equivalent). If the S bit is set (and Rd is not R15) the V flag in the CPSR will be set if an overflow occurs into bit 31 of the result; this may be ignored if the operands were considered unsigned, but warns of a possible error if the operands were 2's complement signed. The C flag will be set to the carry out of bit 31 of the ALU, the Z flag will be set if and only if the result was zero, and the N flag will be set to the value of bit 31 of the result (indicating a negative result if the operands are considered to be 2's complement signed). 3-11 INSTRUCTION SET S3C4510B SHIFTS When the second operand is specified to be a shifted register, the operation of the barrel shifter is controlled by the shift field in the instruction. This field indicates the type of shift to be performed (logical left or right, arithmetic right or rotate right). The amount by which the register should be shifted may be contained in an immediate field in the instruction, or in the bottom byte of another register (other than R15). The encoding for the different shift types is shown in Figure 3-5. 11 7654 0 11 RS 87654 0 1 [6:5] Shift Type 00 = logical left 10 = arithmetic right 01 = logical right 11 = rotate right [6:5] Shift Type 00 = logical left 10 = arithmetic right 01 = logical right 11 = rotate right [11:7] Shift Amount 5 bit unsigned integer [11:8] Shift Register Shift amount specified in bottom-byte of Rs Figure 3-5. ARM Shift Operations Instruction Specified Shift Amount When the shift amount is specified in the instruction, it is contained in a 5 bit field which may take any value from 0 to 31. A logical shift left (LSL) takes the contents of Rm and moves each bit by the specified amount to a more significant position. The least significant bits of the result are filled with zeros, and the high bits of Rm which do not map into the result are discarded, except that the least significant discarded bit becomes the shifter carry output which may be latched into the C bit of the CPSR when the ALU operation is in the logical class (see above). For example, the effect of LSL #5 is shown in Figure 3-6. 31 27 26 Contents of Rm 0 carry out Value of Operand 2 00000 Figure 3-6. Logical Shift Left NOTE LSL #0 is a special case, where the shifter carry out is the old value of the CPSR C flag. The contents of Rm are used directly as the second operand. A logical shift right (LSR) is similar, but the contents of Rm are moved to less significant positions in the result. LSR #5 has the effect shown in Figure 3-7. 3-12 S3C4510B INSTRUCTION SET 31 Contents of Rm 54 0 carry out 00000 Value of Operand 2 Figure 3-7. Logical Shift Right The form of the shift field which might be expected to correspond to LSR #0 is used to encode LSR #32, which has a zero result with bit 31 of Rm as the carry output. Logical shift right zero is redundant as it is the same as logical shift left zero, so the assembler will convert LSR #0 (and ASR #0 and ROR #0) into LSL #0, and allow LSR #32 to be specified. An arithmetic shift right (ASR) is similar to logical shift right, except that the high bits are filled with bit 31 of Rm instead of zeros. This preserves the sign in 2's complement notation. For example, ASR #5 is shown in Figure 38. 31 30 Contents of Rm 54 0 carry out Value of Operand 2 Figure 3-8. Arithmetic Shift Right The form of the shift field which might be expected to give ASR #0 is used to encode ASR #32. Bit 31 of Rm is again used as the carry output, and each bit of operand 2 is also equal to bit 31 of Rm. The result is therefore all ones or all zeros, according to the value of bit 31 of Rm. 3-13 INSTRUCTION SET S3C4510B Rotate right (ROR) operations reuse the bits which overshoot in a logical shift right operation by reintroducing them at the high end of the result, in place of the zeros used to fill the high end in logical right operations. For example, ROR #5 is shown in Figure 3-9. The form of the shift field which might be expected to give ROR #0 is 31 Contents of Rm 54 0 carry out Value of Operand 2 Figure 3-9. Rotate Right used to encode a special function of the barrel shifter, rotate right extended (RRX). This is a rotate right by one bit position of the 33 bit quantity formed by appending the CPSR C flag to the most significant end of the contents of Rm as shown in Figure 3-10. 31 Contents of Rm 10 C in Value of Operand 2 carry out Figure 3-10. Rotate Right Extended 3-14 S3C4510B INSTRUCTION SET Register Specified Shift Amount Only the least significant byte of the contents of Rs is used to determine the shift amount. Rs can be any general register other than R15. If this byte is zero, the unchanged contents of Rm will be used as the second operand, and the old value of the CPSR C flag will be passed on as the shifter carry output. If the byte has a value between 1 and 31, the shifted result will exactly match that of an instruction specified shift with the same value and shift operation. If the value in the byte is 32 or more, the result will be a logical extension of the shift described above: 1. LSL by 32 has result zero, carry out equal to bit 0 of Rm. 2. LSL by more than 32 has result zero, carry out zero. 3. LSR by 32 has result zero, carry out equal to bit 31 of Rm. 4. LSR by more than 32 has result zero, carry out zero. 5. ASR by 32 or more has result filled with and carry out equal to bit 31 of Rm. 6. ROR by 32 has result equal to Rm, carry out equal to bit 31 of Rm. 7. ROR by n where n is greater than 32 will give the same result and carry out as ROR by n-32; therefore repeatedly subtract 32 from n until the amount is in the range 1 to 32 and see above. NOTE The zero in bit 7 of an instruction with a register controlled shift is compulsory; a one in this bit will cause the instruction to be a multiply or undefined instruction. 3-15 INSTRUCTION SET S3C4510B IMMEDIATE OPERAND ROTATES The immediate operand rotate field is a 4 bit unsigned integer which specifies a shift operation on the 8 bit immediate value. This value is zero extended to 32 bits, and then subject to a rotate right by twice the value in the rotate field. This enables many common constants to be generated, for example all powers of 2. WRITING TO R15 When Rd is a register other than R15, the condition code flags in the CPSR may be updated from the ALU flags as described above. When Rd is R15 and the S flag in the instruction is not set the result of the operation is placed in R15 and the CPSR is unaffected. When Rd is R15 and the S flag is set the result of the operation is placed in R15 and the SPSR corresponding to the current mode is moved to the CPSR. This allows state changes which atomically restore both PC and CPSR. This form of instruction should not be used in User mode. USING R15 AS AN OPERAND If R15 (the PC) is used as an operand in a data processing instruction the register is used directly. The PC value will be the address of the instruction, plus 8 or 12 bytes due to instruction prefetching. If the shift amount is specified in the instruction, the PC will be 8 bytes ahead. If a register is used to specify the shift amount the PC will be 12 bytes ahead. TEQ, TST, CMP AND CMN OPCODES NOTE TEQ, TST, CMP and CMN do not write the result of their operation but do set flags in the CPSR. An assembler should always set the S flag for these instructions even if this is not specified in the mnemonic. The TEQP form of the TEQ instruction used in earlier ARM processors must not be used: the PSR transfer operations should be used instead. The action of TEQP in the ARM7TDMI is to move SPSR_ 3-16 S3C4510B INSTRUCTION SET INSTRUCTION CYCLE TIMES Data processing instructions vary in the number of incremental cycles taken as follows: Table 3-4. Incremental Cycle Times Processing Type Normal data processing Data processing with register specified shift Data processing with PC written Data processing with register specified shift and PC written 1S 1S + 1I 2S + 1N 2S + 1N + 1I Cycles NOTE: S, N and I are as defined sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle) respectively. ASSEMBLER SYNTAX -- MOV,MVN (single operand instructions). 3-17 INSTRUCTION SET S3C4510B Examples ADDEQ TEQS R2,R4,R5 R4,#3 ; ; ; ; ; ; ; ; ; ; If the Z flag is set make R2: = R4 + R5 Test R4 for equality with 3. (The S is in fact redundant as the assembler inserts it automatically.) Logical right shift R7 by the number in the bottom byte of R2, subtract result from R5, and put the answer into R4. Return from subroutine. Return from exception and restore CPSR from SPSR_mode. SUB R4,R5,R7,LSR R2 MOV MOVS PC,R14 PC,R14 3-18 S3C4510B INSTRUCTION SET PSR TRANSFER (MRS, MSR) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The MRS and MSR instructions are formed from a subset of the data processing operations and are implemented using the TEQ, TST, CMN and CMP instructions without the S flag set. The encoding is shown in Figure 3-11. These instructions allow access to the CPSR and SPSR registers. The MRS instruction allows the contents of the CPSR or SPSR_ 3-19 INSTRUCTION SET S3C4510B MRS (Transfer PSR Contents to a Register) 31 Cond 28 27 00010 23 22 21 Ps 001111 16 15 Rd 12 11 000000000000 0 [15:21] Destination Register [19:16] Source PSR 0 = CPSR 1 = SPSR_ [31:28] Condition Field MRS (Transfer Register Contents to PSR) 31 Cond 28 27 00010 23 22 21 Pd 101001111 12 11 00000000 43 Rm 0 [3:0] Source Register [22] Destination PSR 0 = CPSR 1 = SPSR_ [31:28] Condition Field MRS (Transfer Register Contents or Immediate Value to PSR Flag Bits Only) 31 Cond 28 27 26 25 24 23 22 21 00 I 10 Pd 101001111 12 11 Soucer Operand 0 [22] Destination PSR 0 = CPSR 1 = SPSR_ [25] Immediate Operand 0 = Source operand is a register 1 = SPSR_ [11:0] Source Operand 11 00000000 43 Rm 0 [3:0] Source Register [11:4] Source operand is an immediate value 11 Rotate 87 Imm 0 [7:0] Unsigned 8 bit immediate value [11:8] Shift applied to Imm [31:28] Condition Field Figure 3-11. PSR Transfer 3-20 S3C4510B INSTRUCTION SET RESERVED BITS Only twelve bits of the PSR are defined in ARM7TDMI (N, Z, C, V, I, F, T & M[4:0]); the remaining bits are reserved for use in future versions of the processor. Refer to Figure 2-6 for a full description of the PSR bits. To ensure the maximum compatibility between ARM7TDMI programs and future processors, the following rules should be observed: -- The reserved bits should be preserved when changing the value in a PSR. -- Programs should not rely on specific values from the reserved bits when checking the PSR status, since they may read as one or zero in future processors. A read-modify-write strategy should therefore be used when altering the control bits of any PSR register; this involves transferring the appropriate PSR register to a general register using the MRS instruction, changing only the relevant bits and then transferring the modified value back to the PSR register using the MSR instruction. Examples The following sequence performs a mode change: MRS BIC ORR MSR R0,CPSR R0,R0,#0x1F R0,R0,#new_mode CPSR,R0 ; ; ; ; Take a copy of the CPSR. Clear the mode bits. Select new mode Write back the modified CPSR. When the aim is simply to change the condition code flags in a PSR, a value can be written directly to the flag bits without disturbing the control bits. The following instruction sets the N, Z, C and V flags: MSR CPSR_flg,#0xF0000000 ; Set all the flags regardless of their previous state ; (does not affect any control bits). No attempt should be made to write an 8 bit immediate value into the whole PSR since such an operation cannot preserve the reserved bits. INSTRUCTION CYCLE TIMES PSR transfers take 1S incremental cycles, where S is defined as sequential (S-cycle). 3-21 INSTRUCTION SET S3C4510B ASSEMBLER SYNTAX -- MRS - transfer PSR contents to a register MRS{cond} Rd, Examples In User mode the instructions behave as follows: MSR MSR MSR MRS CPSR_all,Rm CPSR_flg,Rm CPSR_flg,#0xA0000000 Rd,CPSR ; ; ; ; CPSR[31:28] Rm[31:28] CPSR[31:28] Rm[31:28] CPSR[31:28] 0xA (set N, C; clear Z, V) Rd[31:0] CPSR[31:0] In privileged modes the instructions behave as follows: MSR MSR MSR MSR MSR MSR MRS CPSR_all,Rm CPSR_flg,Rm CPSR_flg,#0x50000000 SPSR_all,Rm SPSR_flg,Rm SPSR_flg,#0xC0000000 Rd,SPSR ; ; ; ; ; ; ; CPSR[31:0] Rm[31:0] CPSR[31:28] Rm[31:28] CPSR[31:28] 0x5 (set Z, V; clear N, C) SPSR_ 3-22 S3C4510B INSTRUCTION SET MULTIPLY AND MULTIPLY-ACCUMULATE (MUL, MLA) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-12. The multiply and multiply-accumulate instructions use an 8 bit Booth's algorithm to perform integer multiplication. 31 Cond 28 27 22 21 20 19 AS Rd 16 15 Rn 12 11 Rs 87 43 Rm 0 000000 1001 [15:12][11:8][3:0] Operand Registers [19:16] Destination Register [20] Set Condition Code 0 = Do not alter condition codes 1 = Set condition codes [21] Accumulate 0 = Multiply only 1 = Multiply and accumulate [31:28] Condition Field Figure 3-12. Multiply Instructions The multiply form of the instruction gives Rd: = Rm * Rs. Rn is ignored, and should be set to zero for compatibility with possible future upgrades to the instruction set. The multiply-accumulate form gives Rd: = Rm * Rs + Rn, which can save an explicit ADD instruction in some circumstances. Both forms of the instruction work on operands which may be considered as signed (2' complement) or unsigned integers. The results of a signed multiply nd of an unsigned multiply of 32 bit operands differ only in the upper 32 bits-the low 32 bits of the signed and unsigned results are identical. As these instructions only produce the low 32 bits of a multiply, they can be used for both signed and unsigned multiplies. For example consider the multiplication of the operands: Operand A Operand B Result 0xFFFFFFF6 0x0000001 0xFFFFFF38 If the Operands are Interpreted as Signed Operand A has the value -10, operand B has the value 20, and the result is -200 which is correctly represented as 0xFFFFFF38. If the Operands are Interpreted as Unsigned Operand A has the value 4294967286, operand B has the value 20 and the result is 85899345720, which is represented as 0x13FFFFFF38, so the least significant 32 bits are 0xFFFFFF38. Operand Restrictions The destination register Rd must not be the same as the operand register Rm. R15 must not be used as an operand or as the destination register. All other register combinations will give correct results, and Rd, Rn and Rs may use the same register when required. 3-23 INSTRUCTION SET S3C4510B CPSR FLAGS Setting the CPSR flags is optional, and is controlled by the S bit in the instruction. The N (Negative) and Z (Zero) flags are set correctly on the result (N is made equal to bit 31 of the result, and Z is set if and only if the result is zero). The C (Carry) flag is set to a meaningless value and the V (overflow) flag is unaffected. INSTRUCTION CYCLE TIMES MUL takes 1S + mI and MLA 1S + (m+1)I cycles to execute, where S and I are defined as sequential (S-cycle) and internal (I-cycle), respectively. m The number of 8 bit multiplier array cycles is required to complete the multiply, which is controlled by the value of the multiplier operand specified by Rs. Its possible values are as follows If bits [32:8] of the multiplier operand are all zero or all one. If bits [32:16] of the multiplier operand are all zero or all one. If bits [32:24] of the multiplier operand are all zero or all one. In all other cases. 1 2 3 4 ASSEMBLER SYNTAX MUL{cond}{S} Rd,Rm,Rs MLA{cond}{S} Rd,Rm,Rs,Rn {cond} {S} Rd, Rm, Rs and Rn Two-character condition mnemonic. See Table 3-2. Set condition codes if S present Expressions evaluating to a register number other than R15. Examples MUL MLAEQS R1,R2,R3 R1,R2,R3,R4 ; R1: = R2 * R3 ; Conditionally R1: = R2 * R3 + R4, setting condition codes. 3-24 S3C4510B INSTRUCTION SET MULTIPLY LONG AND MULTIPLY-ACCUMULATE LONG (MULL,MLAL) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-13. The multiply long instructions perform integer multiplication on two 32 bit operands and produce 64 bit results. Signed and unsigned multiplication each with optional accumulate give rise to four variations. 31 Cond 28 27 23 22 21 20 19 UAS RdHi 16 15 RdLo 12 11 Rs 87 43 Rm 0 00001 1001 [11:8][3:0] Operand Registers [19:16][15:12] Source Destination Registers [20] Set Condition Code 0 = Do not alter condition codes 1 = Set condition codes [21] Accumulate 0 = Multiply only 1 = Multiply and accumulate [22] Unsigned 0 = Unsigned 1 = Signed [31:28] Condition Field Figure 3-13. Multiply Long Instructions The multiply forms (UMULL and SMULL) take two 32 bit numbers and multiply them to produce a 64 bit result of the form RdHi, RdLo: = Rm * Rs. The lower 32 bits of the 64 bit result are written to RdLo, the upper 32 bits of the result are written to RdHi. The multiply-accumulate forms (UMLAL and SMLAL) take two 32 bit numbers, multiply them and add a 64 bit number to produce a 64 bit result of the form RdHi, RdLo: = Rm * Rs + RdHi, RdLo. The lower 32 bits of the 64 bit number to add is read from RdLo. The upper 32 bits of the 64 bit number to add is read from RdHi. The lower 32 bits of the 64 bit result are written to RdLo. The upper 32 bits of the 64 bit result are written to RdHi. The UMULL and UMLAL instructions treat all of their operands as unsigned binary numbers and write an unsigned 64 bit result. The SMULL and SMLAL instructions treat all of their operands as two's-complement signed numbers and write a two's-complement signed 64 bit result. OPERAND RESTRICTIONS -- R15 must not be used as an operand or as a destination register. -- RdHi, RdLo, and Rm must all specify different registers. 3-25 INSTRUCTION SET S3C4510B CPSR FLAGS Setting the CPSR flags is optional, and is controlled by the S bit in the instruction. The N and Z flags are set correctly on the result (N is equal to bit 63 of the result, Z is set if and only if all 64 bits of the result are zero). Both the C and V flags are set to meaningless values. INSTRUCTION CYCLE TIMES MULL takes 1S + (m+1)I and MLAL 1S + (m+2)I cycles to execute, where m is the number of 8 bit multiplier array cycles required to complete the multiply, which is controlled by the value of the multiplier operand specified by Rs. Its possible values are as follows: For Signed Instructions SMULL, SMLAL: -- If bits [31:8] of the multiplier operand are all zero or all one. -- If bits [31:16] of the multiplier operand are all zero or all one. -- If bits [31:24] of the multiplier operand are all zero or all one. -- In all other cases. For Unsigned Instructions UMULL, UMLAL: -- If bits [31:8] of the multiplier operand are all zero. -- If bits [31:16] of the multiplier operand are all zero. -- If bits [31:24] of the multiplier operand are all zero. -- In all other cases. S and I are defined as sequential (S-cycle) and internal (I-cycle), respectively. 3-26 S3C4510B INSTRUCTION SET ASSEMBLER SYNTAX Table 3-5. Assembler Syntax Descriptions Mnemonic UMULL{cond}{S} RdLo, RdHi, Rm, Rs UMLAL{cond}{S} RdLo, RdHi, Rm, Rs SMULL{cond}{S} RdLo, RdHi, Rm, Rs SMLAL{cond}{S} RdLo, RdHi, Rm, Rs where: {cond} {S} RdLo, RdHi, Rm, Rs Examples UMULL UMLALS R1, R4, R2, R3 R1, R5, R2, R3 ; R4, R1: = R2 * R3 ; R5, R1: = R2 * R3 + R5, R1 also setting condition codes Two-character condition mnemonic. See Table 3-2. Set condition codes if S present Expressions evaluating to a register number other than R15. Description Unsigned multiply long Unsigned multiply & Accumulate long Signed multiply long Signed multiply & Accumulate long Purpose 32 x 32 = 64 32 x 32 + 64 = 64 32 x 32 = 64 32 x 32 + 64 = 64 3-27 INSTRUCTION SET S3C4510B SINGLE DATA TRANSFER (LDR, STR) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-14. The single data transfer instructions are used to load or store single bytes or words of data. The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register. The result of this calculation may be written back into the base register if auto-indexing is required. 31 Cond 28 27 26 25 24 23 22 21 20 19 01 I PUBWL Rn 16 15 Rd 12 11 Offset 0 [15:12] Source/Destination Registers [19:16] Base Register [20] Load/Store Bit 0 = Store to memory 1 = Load from memory [21] Write-back Bit 0 = No write-back 1 = Write address into base [22] Byte/Word Bit 0 = Transfer word quantity 1 = Transfer byte quantity [23] Up/Down Bit 0 = Down: subtract offset from base 1 = Up: add offset to base [24] Pre/Post Indexing Bit 0 = Post: add offset after transfer 1 = Pre: add offset bofore transfer [25] Immediate Offset 0 = Offset is an immediate value [11:0] Offset 11 Immediate [11:0] Unsigned 12-bit immediate offset 11 Shift 43 Rm 0 0 [3:0] Offset register [11:4] Shift applied to Rm [31:28] Condition Field Figure 3-14. Single Data Transfer Instructions 3-28 S3C4510B INSTRUCTION SET OFFSETS AND AUTO-INDEXING The offset from the base may be either a 12 bit unsigned binary immediate value in the instruction, or a second register (possibly shifted in some way). The offset may be added to (U = 1) or subtracted from (U = 0) the base register Rn. The offset modification may be performed either before (pre-indexed, P = 1) or after (post-indexed, P = 0) the base is used as the transfer address. The W bit gives optional auto increment and decrement addressing modes. The modified base value may be written back into the base (W = 1), or the old base value may be kept (W = 0). In the case of post-indexed addressing, the write back bit is redundant and is always set to zero, since the old base value can be retained by setting the offset to zero. Therefore post-indexed data transfers always write back the modified base. The only use of the W bit in a post-indexed data transfer is in privileged mode code, where setting the W bit forces nonprivileged mode for the transfer, allowing the operating system to generate a user address in a system where the memory management hardware makes suitable use of this hardware. SHIFTED REGISTER OFFSET The 8 shift control bits are described in the data processing instructions section. However, the register specified shift amounts are not available in this instruction class. See Figure 3-5. BYTES AND WORDS This instruction class may be used to transfer a byte (B = 1) or a word (B = 0) between an ARM7TDMI register and memory. The action of LDR(B) and STR(B) instructions is influenced by the BIGEND control signal of ARM7TDMI core. The two possible configurations are described below. Little-Endian Configuration A byte load (LDRB) expects the data on data bus inputs 7 through 0 if the supplied address is on a word boundary, on data bus inputs 15 through 8 if it is a word address plus one byte, and so on. The selected byte is placed in the bottom 8 bits of the destination register, and the remaining bits of the register are filled with zeros. Please see Figure 2-2. A byte store (STRB) repeats the bottom 8 bits of the source register four times across data bus outputs 31 through 0. The external memory system should activate the appropriate byte subsystem to store the data. A word load (LDR) will normally use a word aligned address. However, an address offset from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 0 to 7. This means that half-words accessed at offsets 0 and 2 from the word boundary will be correctly loaded into bits 0 through 15 of the register. Two shift operations are then required to clear or to sign extend the upper 16 bits. A word store (STR) should generate a word aligned address. The word presented to the data bus is not affected if the address is not word aligned. That is, bit 31 of the register being stored always appears on data bus output 31. 3-29 INSTRUCTION SET S3C4510B Memory A A+3 B A+2 C A+1 D A 0 8 16 24 Register A 24 B 16 C 8 D 0 LDR from word aligned address Memory A A+3 B A+2 C A+1 D A 0 LDR from address offset by 2 8 D 0 16 C 8 24 B 16 Register A 24 Figure 3-15. Little-Endian Offset Addressing Big-Endian Configuration A byte load (LDRB) expects the data on data bus inputs 31 through 24 if the supplied address is on a word boundary, on data bus inputs 23 through 16 if it is a word address plus one byte, and so on. The selected byte is placed in the bottom 8 bits of the destination register and the remaining bits of the register are filled with zeros. Please see Figure 2-1. A byte store (STRB) repeats the bottom 8 bits of the source register four times across data bus outputs 31 through 0. The external memory system should activate the appropriate byte subsystem to store the data. A word load (LDR) should generate a word aligned address. An address offset of 0 or 2 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 31 through 24. This means that half-words accessed at these offsets will be correctly loaded into bits 16 through 31 of the register. A shift operation is then required to move (and optionally sign extend) the data into the bottom 16 bits. An address offset of 1 or 3 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 15 through 8. A word store (STR) should generate a word aligned address. The word presented to the data bus is not affected if the address is not word aligned. That is, bit 31 of the register being stored always appears on data bus output 31. 3-30 S3C4510B INSTRUCTION SET USE OF R15 Write-back must not be specified if R15 is specified as the base register (Rn). When using R15 as the base register you must remember it contains an address 8 bytes on from the address of the current instruction. R15 must not be specified as the register offset (Rm). When R15 is the source register (Rd) of a register store (STR) instruction, the stored value will be address of the instruction plus 12. RESTRICTION ON THE USE OF BASE REGISTER When configured for late aborts, the following example code is difficult to unwind as the base register, Rn, gets updated before the abort handler starts. Sometimes it may be impossible to calculate the initial value. After an abort, the following example code is difficult to unwind as the base register, Rn, gets updated before the abort handler starts. Sometimes it may be impossible to calculate the initial value. Example: LDR R0,[R1],R1 Therefore a post-indexed LDR or STR where Rm is the same register as Rn should not be used. DATA ABORTS A transfer to or from a legal address may cause problems for a memory management system. For instance, in a system which uses virtual memory the required data may be absent from main memory. The memory manager can signal a problem by taking the processor ABORT input HIGH whereupon the data abort trap will be taken. It is up to the system software to resolve the cause of the problem, then the instruction can be restarted and the original program continued. INSTRUCTION CYCLE TIMES Normal LDR instructions take 1S + 1N + 1I and LDR PC take 2S + 2N +1I incremental cycles, where S,N and I are defined as sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle), respectively. STR instructions take 2N incremental cycles to execute. 3-31 INSTRUCTION SET S3C4510B ASSEMBLER SYNTAX Rd Rn and Rm can be: 1 An expression which generates an address: The assembler will attempt to generate an instruction using the PC as a base and a corrected immediate offset to address the location given by evaluating the expression. This will be a PC relative, pre-indexed address. If the address is out of range, an error will be generated. A pre-indexed addressing specification: [Rn] offset of zero [Rn,<#expression>]{!} offset of 2 3 3-32 S3C4510B INSTRUCTION SET Examples STR STR LDR LDR LDREQB STR PLACE R1,[R2,R4]! R1,[R2],R4 R1,[R2,#16] R1,[R2,R3,LSL#2] R1,[R6,#5] R1,PLACE ; ; ; ; ; ; ; ; Store R1 at R2 + R4 (both of which are registers) and write back address to R2. Store R1 at R2 and write back R2 + R4 to R2. Load R1 from contents of R2 + 16, but don't write back. Load R1 from contents of R2 + R3 * 4. Conditionally load byte at R6 + 5 into R1 bits 0 to 7, filling bits 8 to 31 with zeros. Generate PC relative offset to address PLACE. 3-33 INSTRUCTION SET S3C4510B HALFWORD AND SIGNED DATA TRANSFER (LDRH/STRH/LDRSB/LDRSH) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-16. These instructions are used to load or store half-words of data and also load sign-extended bytes or half-words of data. The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register. The result of this calculation may be written back into the base register if auto-indexing is required. 31 Cond 28 27 000 25 24 23 22 21 20 19 PU0WL Rn 16 15 Rd 12 11 0000 876543 1SH1 Rm 0 [3:0] Offset Register [6][5] S H 0 0 1 1 0 = SWP instruction 1 = Unsigned halfwords 1 = Signed byte 1 = Signed half words [15:12] Source/Destination Register [19:16] Base Register [20] Load/Store 0 = Store to memory 1 = Load from memory [21] Write-back 0 = No write-back 1 = Write address into base [23] Up/Down 0 = Down: subtract offset from base 1 = Up: add offset to base [24] Pre/Post Indexing 0 = Post: add/subtract offset after transfer 1 = Pre: add/subtract offset bofore transfer [31:28] Condition Field Figure 3-16. Half-word and Signed Data Transfer with Register Offset 3-34 S3C4510B INSTRUCTION SET 31 Cond 28 27 000 25 24 23 22 21 20 19 PU1WL Rn 16 15 Rd 12 11 Offset 876543 1SH1 Offset 0 [3:0] Immediate Offset (Low Nibble) [6][5] S H 0 0 1 1 0 = SWP instruction 1 = Unsigned halfwords 1 = Signed byte 1 = Signed half words [11:8] Immediate Offset (High Nibble) [15:12] Source/Destination Register [19:16] Base Register [20] Load/Store 0 = Store to memory 1 = Load from memory [21] Write-back 0 = No write-back 1 = Write address into base [23] Up/Down 0 = Down: subtract offset from base 1 = Up: add offset to base [24] Pre/Post Indexing 0 = Post: add/subtract offset after transfer 1 = Pre: add/subtract offset bofore transfer [31:28] Condition Field Figure 3-17. Half-word and Signed Data Transfer with Immediate Offset and Auto-Indexing OFFSETS AND AUTO-INDEXING The offset from the base may be either a 8-bit unsigned binary immediate value in the instruction, or a second register. The 8-bit offset is formed by concatenating bits 11 to 8 and bits 3 to 0 of the instruction word, such that bit 11 becomes the MSB and bit 0 becomes the LSB. The offset may be added to (U = 1) or subtracted from (U = 0) the base register Rn. The offset modification may be performed either before (pre-indexed, P = 1) or after (post-indexed, P = 0) the base register is used as the transfer address. The W bit gives optional auto-increment and decrement addressing modes. The modified base value may be written back into the base (W = 1), or the old base may be kept (W = 0). In the case of post-indexed addressing, the write back bit is redundant and is always set to zero, since the old base value can be retained if necessary by setting the offset to zero. Therefore post-indexed data transfers always write back the modified base. The Write-back bit should not be set high (W = 1) when post-indexed addressing is selected. 3-35 INSTRUCTION SET S3C4510B HALF-WORD LOAD AND STORES Setting S = 0 and H = 1 may be used to transfer unsigned Half-words between an ARM7TDMI register and memory. The action of LDRH and STRH instructions is influenced by the BIGEND control signal. The two possible configurations are described in the section below. SIGNED BYTE AND HALF-WORD LOADS The S bit controls the loading of sign-extended data. When S = 1 the H bit selects between Bytes (H = 0) and Half-words (H = 1). The L bit should not be set low (Store) when Signed (S = 1) operations have been selected. The LDRSB instruction loads the selected Byte into bits 7 to 0 of the destination register and bits 31 to 8 of the destination register are set to the value of bit 7, the sign bit. The LDRSH instruction loads the selected Half-word into bits 15 to 0 of the destination register and bits 31 to 16 of the destination register are set to the value of bit 15, the sign bit. The action of the LDRSB and LDRSH instructions is influenced by the BIGEND control signal. The two possible configurations are described in the following section. ENDIANNESS AND BYTE/HALF-WORD SELECTION Little-Endian Configuration A signed byte load (LDRSB) expects data on data bus inputs 7 through to 0 if the supplied address is on a word boundary, on data bus inputs 15 through to 8 if it is a word address plus one byte, and so on. The selected byte is placed in the bottom 8 bit of the destination register, and the remaining bits of the register are filled with the sign bit, bit 7 of the byte. Please see Figure 2-2. A half-word load (LDRSH or LDRH) expects data on data bus inputs 15 through to 0 if the supplied address is on a word boundary and on data bus inputs 31 through to 16 if it is a half-word boundary, (A[1]=1).The supplied address should always be on a half-word boundary. If bit 0 of the supplied address is high then the ARM7TDMI will load an unpredictable value. The selected half-word is placed in the bottom 16 bits of the destination register. For unsigned half-words (LDRH), the top 16 bits of the register are filled with zeros and for signed half-words (LDRSH) the top 16 bits are filled with the sign bit, bit 15 of the half-word. A half-word store (STRH) repeats the bottom 16 bits of the source register twice across the data bus outputs 31 through to 0. The external memory system should activate the appropriate half-word subsystem to store the data. Note that the address must be half-word aligned, if bit 0 of the address is high this will cause unpredictable behaviour. 3-36 S3C4510B INSTRUCTION SET Big-Endian Configuration A signed byte load (LDRSB) expects data on data bus inputs 31 through to 24 if the supplied address is on a word boundary, on data bus inputs 23 through to 16 if it is a word address plus one byte, and so on. The selected byte is placed in the bottom 8 bit of the destination register, and the remaining bits of the register are filled with the sign bit, bit 7 of the byte. Please see Figure 2-1. A half-word load (LDRSH or LDRH) expects data on data bus inputs 31 through to 16 if the supplied address is on a word boundary and on data bus inputs 15 through to 0 if it is a half-word boundary, (A[1] =1). The supplied address should always be on a half-word boundary. If bit 0 of the supplied address is high then the ARM7TDMI will load an unpredictable value. The selected half-word is placed in the bottom 16 bits of the destination register. For unsigned half-words (LDRH), the top 16 bits of the register are filled with zeros and for signed half-words (LDRSH) the top 16 bits are filled with the sign bit, bit 15 of the half-word. A half-word store (STRH) repeats the bottom 16 bits of the source register twice across the data bus outputs 31 through to 0. The external memory system should activate the appropriate half-word subsystem to store the data. Note that the address must be half-word aligned, if bit 0 of the address is HIGH this will cause unpredictable behaviour. USE OF R15 Write-back should not be specified if R15 is specified as the base register (Rn). When using R15 as the base register you must remember it contains an address 8 bytes on from the address of the current instruction. R15 should not be specified as the register offset (Rm). When R15 is the source register (Rd) of a Half-word store (STRH) instruction, the stored address will be address of the instruction plus 12. DATA ABORTS A transfer to or from a legal address may cause problems for a memory management system. For instance, in a system which uses virtual memory the required data may be absent from the main memory. The memory manager can signal a problem by taking the processor ABORT input high whereupon the data abort trap will be taken. It is up to the system software to resolve the cause of the problem, then the instruction can be restarted and the original program continued. INSTRUCTION CYCLE TIMES Normal LDR(H, SH, SB) instructions take 1S + 1N + 1I. LDR(H, SH, SB) PC take 2S + 2N + 1I incremental cycles. S,N and I are defined as sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle), respectively. STRH instructions take 2N incremental cycles to execute. 3-37 INSTRUCTION SET S3C4510B ASSEMBLER SYNTAX 2 3 4 {!} 3-38 S3C4510B INSTRUCTION SET Examples LDRH ; ; ; R3,[R4,#14] ; R8,[R2],#-223 ; ; R11,[R0] ; ; ; R5, [PC,#(FRED-HERE-8)]; R1,[R2,-R3]! Load R1 from the contents of the half-word address contained in R2-R3 (both of which are registers) and write back address to R2 Store the half-word in R3 at R14+14 but don't write back. Load R8 with the sign extended contents of the byte address contained in R2 and write back R2-223 to R2. Conditionally load R11 with the sign extended contents of the half-word address contained in R0. Generate PC relative offset to address FRED. Store the half-word in R5 at address FRED STRH LDRSB LDRNESH HERE STRH FRED 3-39 INSTRUCTION SET S3C4510B BLOCK DATA TRANSFER (LDM, STM) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-18. Block data transfer instructions are used to load (LDM) or store (STM) any subset of the currently visible registers. They support all possible stacking modes, maintaining full or empty stacks which can grow up or down memory, and are very efficient instructions for saving or restoring context, or for moving large blocks of data around main memory. THE REGISTER LIST The instruction can cause the transfer of any registers in the current bank (and non-user mode programs can also transfer to and from the user bank, see below). The register list is a 16 bit field in the instruction, with each bit corresponding to a register. A 1 in bit 0 of the register field will cause R0 to be transferred, a 0 will cause it not to be transferred; similarly bit 1 controls the transfer of R1, and so on. Any subset of the registers, or all the registers, may be specified. The only restriction is that the register list should not be empty. Whenever R15 is stored to memory the stored value is the address of the STM instruction plus 12. 31 Cond 28 27 100 25 24 23 22 21 20 19 PUSWL Rn 16 15 Register list 0 [19:16] Base Register [20] Load/Store Bit 0 = Store to memory 1 = Load from memory [21] Write-back Bit 0 = No write-back 1 = Write address into base [22] PSR & Force User Bit 0 = Do not load PSR or user mode 1 = Load PSR or force user mode [23] Up/Down Bit 0 = Down: subtract offset from base 1 = Up: add offset to base [24] Pre/Post Indexing Bit 0 = Post: add offset after transfer 1 = Pre: add offset bofore transfer [31:28] Condition Field Figure 3-18. Block Data Transfer Instructions 3-40 S3C4510B INSTRUCTION SET ADDRESSING MODES The transfer addresses are determined by the contents of the base register (Rn), the pre/post bit (P) and the up/ down bit (U). The registers are transferred in the order lowest to highest, so R15 (if in the list) will always be transferred last. The lowest register also gets transferred to/from the lowest memory address. By way of illustration, consider the transfer of R1, R5 and R7 in the case where Rn = 0x1000 and write back of the modified base is required (W = 1). Figure 3.19-22 show the sequence of register transfers, the addresses used, and the value of Rn after the instruction has completed. In all cases, had write back of the modified base not been required (W = 0), Rn would have retained its initial value of 0x1000 unless it was also in the transfer list of a load multiple register instruction, when it would have been overwritten with the loaded value. ADDRESS ALIGNMENT The address should normally be a word aligned quantity and non-word aligned addresses do not affect the instruction. However, the bottom 2 bits of the address will appear on A[1:0] and might be interpreted by the memory system. 0x100C 0x100C Rn 0x1000 R1 0x1000 0x0FF4 1 0x100C R5 R1 Rn R7 R5 R1 2 0x0FF4 0x100C 0x1000 0x1000 0x0FF4 3 4 0x0FF4 Figure 3-19. Post-Increment Addressing 3-41 INSTRUCTION SET S3C4510B 0x100C R1 Rn 0x1000 0x100C 0x1000 0x0FF4 1 0x100C R5 R1 0x1000 Rn 2 R7 R5 R1 0x0FF4 0x100C 0x1000 0x0FF4 3 4 0x0FF4 Figure 3-20. Pre-Increment Addressing 0x100C 0x100C Rn 0x1000 R1 0x0FF4 1 0x100C 2 0x1000 0x0FF4 0x100C 0x1000 R5 R1 0x0FF4 3 Rn R7 R5 R1 4 0x1000 0x0FF4 Figure 3-21. Post-Decrement Addressing 3-42 S3C4510B INSTRUCTION SET 0x100C 0x100C Rn 0x1000 0x1000 0x0FF4 1 0x100C R1 2 0x0FF4 0x100C 0x1000 R5 R1 3 R7 R5 R1 4 0x1000 0x0FF4 Rn 0x0FF4 Figure 3-22. Pre-Decrement Addressing USE OF THE S BIT When the S bit is set in a LDM/STM instruction its meaning depends on whether or not R15 is in the transfer list and on the type of instruction. The S bit should only be set if the instruction is to execute in a privileged mode. LDM with R15 in Transfer List and S Bit Set (Mode Changes) If the instruction is a LDM then SPSR_ 3-43 INSTRUCTION SET S3C4510B INCLUSION OF THE BASE IN THE REGISTER LIST When write-back is specified, the base is written back at the end of the second cycle of the instruction. During a STM, the first register is written out at the start of the second cycle. A STM which includes storing the base, with the base as the first register to be stored, will therefore store the unchanged value, whereas with the base second or later in the transfer order, will store the modified value. A LDM will always overwrite the updated base if the base is in the list. DATA ABORTS Some legal addresses may be unacceptable to a memory management system, and the memory manager can indicate a problem with an address by taking the abort signal high. This can happen on any transfer during a multiple register load or store, and must be recoverable if ARM7TDMI is to be used in a virtual memory system. Aborts during STM Instructions If the abort occurs during a store multiple instruction, ARM7TDMI takes little action until the instruction completes, whereupon it enters the data abort trap. The memory manager is responsible for preventing erroneous writes to the memory. The only change to the internal state of the processor will be the modification of the base register if write-back was specified, and this must be reversed by software (and the cause of the abort resolved) before the instruction may be retried. Aborts during LDM Instructions When ARM7TDMI detects a data abort during a load multiple instruction, it modifies the operation of the instruction to ensure that recovery is possible. -- Overwriting of registers stops when the abort happens. The aborting load will not take place but earlier ones may have overwritten registers. The PC is always the last register to be written and so will always be preserved. -- The base register is restored, to its modified value if write-back was requested. This ensures recoverability in the case where the base register is also in the transfer list, and may have been overwritten before the abort occurred. The data abort trap is taken when the load multiple has completed, and the system software must undo any base modification (and resolve the cause of the abort) before restarting the instruction. INSTRUCTION CYCLE TIMES Normal LDM instructions take nS + 1N + 1I and LDM PC takes (n+1)S + 2N + 1I incremental cycles, where S,N and I are defined as sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle), respectively. STM instructions take (n-1)S + 2N incremental cycles to execute, where n is the number of words transferred. 3-44 S3C4510B INSTRUCTION SET ASSEMBLER SYNTAX Addressing Mode Names There are different assembler mnemonics for each of the addressing modes, depending on whether the instruction is being used to support stacks or for other purposes. The equivalence between the names and the values of the bits in the instruction are shown in the following table 3-6. Table 3-6. Addressing Mode Names Name Pre-Increment load Post-Increment load Pre-Decrement load Post-Decrement load Pre-Increment store Post-Increment store Pre-Decrement store Post-Decrement store Stack LDMED LDMFD LDMEA LDMFA STMFA STMEA STMFD STMED Other LDMIB LDMIA LDMDB LDMDA STMIB STMIA STMDB STMDA L Bit 1 1 1 1 0 0 0 0 P Bit 1 0 1 0 1 0 1 0 U Bit 1 1 0 0 1 1 0 0 FD, ED, FA, EA define pre/post indexing and the up/down bit by reference to the form of stack required. The F and E refer to a "full" or "empty" stack, i.e. whether a pre-index has to be done (full) before storing to the stack. The A and D refer to whether the stack is ascending or descending. If ascending, a STM will go up and LDM down, if descending, vice-versa. IA, IB, DA, DB allow control when LDM/STM are not being used for stacks and simply mean increment after, increment before, decrement after, decrement before. 3-45 INSTRUCTION SET S3C4510B Examples LDMFD STMIA LDMFD LDMFD STMFD SP!,{R0,R1,R2} R0,{R0-R15} SP!,{R15} SP!,{R15}^ R13,{R0-R14}^ ; ; ; ; ; ; ; Unstack 3 registers. Save all registers. R15 <- (SP), CPSR unchanged. R15 <- (SP), CPSR <- SPSR_mode (allowed only in privileged modes). Save user mode regs on stack (allowed only in privileged modes). These instructions may be used to save state on subroutine entry, and restore it efficiently on return to the calling routine: STMED BL LDMED SP!,{R0-R3,R14} somewhere SP!,{R0-R3,R15} ; ; ; ; Save R0 to R3 to use as workspace and R14 for returning. This nested call will overwrite R14 Restore workspace and return. 3-46 S3C4510B INSTRUCTION SET SINGLE DATA SWAP (SWP) 31 Cond 28 27 00010 23 22 21 20 19 B 00 Rn 16 15 Rd 12 11 0000 87 1001 43 Rm 0 [3:0] Source Register [15:12] Destination Register [19:16] Base Register [22] Byte/Word Bit 0 = Swap word quantity 1 = Swap word quantity [31:28] Condition Field Figure 3-23. Swap Instruction The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-23. The data swap instruction is used to swap a byte or word quantity between a register and external memory. This instruction is implemented as a memory read followed by a memory write which are "locked" together (the processor cannot be interrupted until both operations have completed, and the memory manager is warned to treat them as inseparable). This class of instruction is particularly useful for implementing software semaphores. The swap address is determined by the contents of the base register (Rn). The processor first reads the contents of the swap address. Then it writes the contents of the source register (Rm) to the swap address, and stores the old memory contents in the destination register (Rd). The same register may be specified as both the source and destination. The lock output goes HIGH for the duration of the read and write operations to signal to the external memory manager that they are locked together, and should be allowed to complete without interruption. This is important in multi-processor systems where the swap instruction is the only indivisible instruction which may be used to implement semaphores; control of the memory must not be removed from a processor while it is performing a locked operation. BYTES AND WORDS This instruction class may be used to swap a byte (B = 1) or a word (B = 0) between an ARM7TDMI register and memory. The SWP instruction is implemented as a LDR followed by a STR and the action of these is as described in the section on single data transfers. In particular, the description of Big and Little Endian configuration applies to the SWP instruction. USE OF R15 Do not use R15 as an operand (Rd, Rn or Rs) in a SWP instruction. 3-47 INSTRUCTION SET S3C4510B DATA ABORTS If the address used for the swap is unacceptable to a memory management system, the memory manager can flag the problem by driving ABORT HIGH. This can happen on either the read or the write cycle (or both), and in either case, the data abort trap will be taken. It is up to the system software to resolve the cause of the problem, then the instruction can be restarted and the original program continued. INSTRUCTION CYCLE TIMES Swap instructions take 1S + 2N +1I incremental cycles to execute, where S, N and I are defined as squential (Scycle), non-sequential, and internal (I-cycle), respectively. ASSEMBLER SYNTAX 3-48 S3C4510B INSTRUCTION SET SOFTWARE INTERRUPT (SWI) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-24, below 31 Cond 28 27 1111 24 23 Comment Field (Ignored by Processor) 0 [31:28] Condition Field Figure 3-24. Software Interrupt Instruction The software interrupt instruction is used to enter supervisor mode in a controlled manner. The instruction causes the software interrupt trap to be taken, which effects the mode change. The PC is then forced to a fixed value (0x08) and the CPSR is saved in SPSR_svc. If the SWI vector address is suitably protected (by external memory management hardware) from modification by the user, a fully protected operating system may be constructed. RETURN FROM THE SUPERVISOR The PC is saved in R14_svc upon entering the software interrupt trap, with the PC adjusted to point to the word after the SWI instruction. MOVS PC,R14_svc will return to the calling program and restore the CPSR. Note that the link mechanism is not re-entrant, so if the supervisor code wishes to use software interrupts within itself it must first save a copy of the return address and SPSR. COMMENT FIELD The bottom 24 bits of the instruction are ignored by the processor, and may be used to communicate information to the supervisor code. For instance, the supervisor may look at this field and use it to index into an array of entry points for routines which perform the various supervisor functions. INSTRUCTION CYCLE TIMES Software interrupt instructions take 2S + 1N incremental cycles to execute, where S and N are defined as squential (S-cycle) and non-squential (N-cycle). 3-49 INSTRUCTION SET S3C4510B ASSEMBLER SYNTAX SWI{cond} Zero ReadC WriteI ; ; ; ; ; ; ; ; ; SWI has routine required in bits 8-23 and data (if any) in bits 0-7. Assumes R13_svc points to a suitable stack Save work registers and return address. Get SWI instruction. Clear top 8 bits. Get routine offset. Get start address of entry table. Branch to appropriate routine. Enter with character in R0 bits 0-7. R13,{R0-R2,R15}^ ; Restore workspace and return, ; restoring processor mode and flags. 3-50 S3C4510B INSTRUCTION SET COPROCESSOR DATA OPERATIONS (CDP) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-25. This class of instruction is used to tell a coprocessor to perform some internal operation. No result is communicated back to ARM7TDMI, and it will not wait for the operation to complete. The coprocessor could contain a queue of such instructions awaiting execution, and their execution can overlap other activity, allowing the coprocessor and ARM7TDMI to perform independent tasks in parallel. COPROCESSOR INSTRUCTIONS The KS32C6200, unlike some other ARM-based processors, does not have an external coprocessor interface. It does not have a on-chip coprocessor also. So then all coprocessor instructions will cause the undefined instruction trap to be taken on the KS32C6200. These coprocessor instructions can be emulated by the undefined trap handler. Even though external coprocessor can not be connected to the KS32C6200, the coprocessor instructions are still described here in full for completeness. (Remember that any external coprocessor described in this section is a software emulation.) 31 Cond 28 27 1110 24 23 20 19 CRn 16 15 CRd 12 11 Cp# 87 Cp 543 0 CRm 0 CP Opc [3:0] Coprocessor operand register [7:5] Coprocessor information [11:8] Coprocessor number [15:12] Coprocessor destination register [19:16] Coprocessor operand register [23:20] Coprocessor operation code [31:28] Condition Field Figure 3-25. Coprocessor Data Operation Instruction THE COPROCESSOR FIELDS Only bit 4 and bits 24 to 31 are significant to ARM7TDMI. The remaining bits are used by coprocessors. The above field names are used by convention, and particular coprocessors may redefine the use of all fields except CP# as appropriate. The CP# field is used to contain an identifying number (in the range 0 to 15) for each coprocessor, and a coprocessor will ignore any instruction which does not contain its number in the CP# field. The conventional interpretation of the instruction is that the coprocessor should perform an operation specified in the CP Opc field (and possibly in the CP field) on the contents of CRn and CRm, and place the result in CRd. 3-51 INSTRUCTION SET S3C4510B INSTRUCTION CYCLE TIMES Coprocessor data operations take 1S + bI incremental cycles to execute, where b is the number of cycles spent in the coprocessor busy-wait loop. S and I are defined as sequential (S-cycle) and internal (I-cycle). ASSEMBLER SYNTAX CDP{cond} p#, 3-52 S3C4510B INSTRUCTION SET COPROCESSOR DATA TRANSFERS (LDC, STC) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-26. This class of instruction is used to load (LDC) or store (STC) a subset of a coprocessor's registers directly to memory. ARM7TDMI is responsible for supplying the memory address, and the coprocessor supplies or accepts the data and controls the number of words transferred. 31 Cond 28 27 110 25 24 23 22 21 20 19 PUNWL Rn 16 15 CRd 12 11 CP# 87 Offset 0 [7:0] Unsigned 8 Bit Immediate Offset [11:8] Coprocessor Number [15:12] Coprocessor Source/Destination Register [19:16] Base Register [20] Load/Store Bit 0 = Store to memory 1 = Load from memory [21] Write-back Bit 0 = No write-back 1 = Write address into base [22] Transfer Length [23] Up/Down Bit 0 = Down: subtract offset from base 1 = Up: add offset to base [24] Pre/Post Indexing Bit 0 = Post: add offset after transfer 1 = Pre: add offset bofore transfer [31:28] Condition Field Figure 3-26. Coprocessor Data Transfer Instructions THE COPROCESSOR FIELDS The CP# field is used to identify the coprocessor which is required to supply or accept the data, and a coprocessor will only respond if its number matches the contents of this field. The CRd field and the N bit contain information for the coprocessor which may be interpreted in different ways by different coprocessors, but by convention CRd is the register to be transferred (or the first register where more than one is to be transferred), and the N bit is used to choose one of two transfer length options. For instance N = 0 could select the transfer of a single register, and N = 1 could select the transfer of all the registers for context switching. 3-53 INSTRUCTION SET S3C4510B ADDRESSING MODES ARM7TDMI is responsible for providing the address used by the memory system for the transfer, and the addressing modes available are a subset of those used in single data transfer instructions. Note, however, that the immediate offsets are 8 bits wide and specify word offsets for coprocessor data transfers, whereas they are 12 bits wide and specify byte offsets for single data transfers. The 8 bit unsigned immediate offset is shifted left 2 bits and either added to (U = 1) or subtracted from (U = 0) the base register (Rn); this calculation may be performed either before (P = 1) or after (P = 0) the base is used as the transfer address. The modified base value may be overwritten back into the base register (if W = 1), or the old value of the base may be preserved (W = 0). Note that post-indexed addressing modes require explicit setting of the W bit, unlike LDR and STR which always write-back when post-indexed. The value of the base register, modified by the offset in a pre-indexed instruction, is used as the address for the transfer of the first word. The second word (if more than one is transferred) will go to or come from an address one word (4 bytes) higher than the first transfer, and the address will be incremented by one word for each subsequent transfer. ADDRESS ALIGNMENT The base address should normally be a word aligned quantity. The bottom 2 bits of the address will appear on A[1:0] and might be interpreted by the memory system. USE OF R15 If Rn is R15, the value used will be the address of the instruction plus 8 bytes. Base write-back to R15 must not be specified. DATA ABORTS If the address is legal but the memory manager generates an abort, the data trap will be taken. The write-back of the modified base will take place, but all other processor state will be preserved. The coprocessor is partly responsible for ensuring that the data transfer can be restarted after the cause of the abort has been resolved, and must ensure that any subsequent actions it undertakes can be repeated when the instruction is retried. INSTRUCTION CYCLE TIMES Coprocessor data transfer instructions take (n-1)S + 2N + bI incremental cycles to execute, where: n b The number of words transferred. The number of cycles spent in the coprocessor busy-wait loop. S, N and I are defined as sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle), respectively. 3-54 S3C4510B INSTRUCTION SET ASSEMBLER SYNTAX can be: 1 An expression which generates an address: The assembler will attempt to generate an instruction using the PC as a base and a corrected immediate offset to address the location given by evaluating the expression. This will be a PC relative, pre-indexed address. If the address is out of range, an error will be generated A pre-indexed addressing specification: [Rn] offset of zero [Rn,<#expression>]{!} offset of 2 If Rn is R15, the assembler will subtract 8 from the offset value to allow for ARM7TDMI pipelining. Examples LDC STCEQL p1,c2,table p2,c3,[R5,#24]! ; ; ; ; ; ; Load c2 of coproc 1 from address table, using a PC relative address. Conditionally store c3 of coproc 2 into an address 24 bytes up from R5, write this address back to R5, and use long transfer option (probably to store multiple words). NOTE Although the address offset is expressed in bytes, the instruction offset field is in words. The assembler will adjust the offset appropriately. 3-55 INSTRUCTION SET S3C4510B COPROCESSOR REGISTER TRANSFERS (MRC, MCR) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2.. The instruction encoding is shown in Figure 3-27. This class of instruction is used to communicate information directly between ARM7TDMI and a coprocessor. An example of a coprocessor to ARM7TDMI register transfer (MRC) instruction would be a FIX of a floating point value held in a coprocessor, where the floating point number is converted into a 32 bit integer within the coprocessor, and the result is then transferred to ARM7TDMI register. A FLOAT of a 32 bit value in ARM7TDMI register into a floating point value within the coprocessor illustrates the use of ARM7TDMI register to coprocessor transfer (MCR). An important use of this instruction is to communicate control information directly from the coprocessor into the ARM7TDMI CPSR flags. As an example, the result of a comparison of two floating point values within a coprocessor can be moved to the CPSR to control the subsequent flow of execution. 31 Cond 28 27 1110 24 23 21 20 19 CRn 16 15 Rd 12 11 CP# 87 CP 543 1 CRm 0 CP Opc L [3:0] Coprocessor Operand Register [7:5] Coprocessor Information [11:8] Coprocessor Number [15:12] ARM source/Destination Register [19:16] Coprocessor Source/Destination Register [20] Load/Store Bit 0 = Store to coprocessor 1 = Load from coprocessor [21] Coprocessor Operation Mode [31:28] Condition Field Figure 3-27. Coprocessor Register Transfer Instructions THE COPROCESSOR FIELDS The CP# field is used, as for all coprocessor instructions, to specify which coprocessor is being called upon. The CP Opc, CRn, CP and CRm fields are used only by the coprocessor, and the interpretation presented here is derived from convention only. Other interpretations are allowed where the coprocessor functionality is incompatible with this one. The conventional interpretation is that the CP Opc and CP fields specify the operation the coprocessor is required to perform, CRn is the coprocessor register which is the source or destination of the transferred information, and CRm is a second coprocessor register which may be involved in some way which depends on the particular operation specified. 3-56 S3C4510B INSTRUCTION SET TRANSFERS TO R15 When a coprocessor register transfer to ARM7TDMI has R15 as the destination, bits 31, 30, 29 and 28 of the transferred word are copied into the N, Z, C and V flags respectively. The other bits of the transferred word are ignored, and the PC and other CPSR bits are unaffected by the transfer. TRANSFERS FROM R15 A coprocessor register transfer from ARM7TDMI with R15 as the source register will store the PC+ 12. INSTRUCTION CYCLE TIMES MRC instructions take 1S + (b+1)I +1C incremental cycles to execute, where S, I and C are defined as sequential (S-cycle), internal (I-cycle), and coprocessor register transfer (C-cycle), respectively. MCR instructions take 1S + bI +1C incremental cycles to execute, where b is the number of cycles spent in the coprocessor busy-wait loop. ASSEMBLER SYNTAX Examples MRC p2,5,R3,c5,c6 ; ; ; ; ; ; ; ; Request coproc 2 to perform operation 5 on c5 and c6, and transfer the (single 32-bit word) result back to R3. Request coproc 6 to perform operation 0 on R4 and place the result in c6. Conditionally request coproc 3 to perform operation 9 (type 2) on c5 and c6, and transfer the result back to R3. MCR MRCEQ p6,0,R4,c5,c6 p3,9,R3,c5,c6,2 3-57 INSTRUCTION SET S3C4510B UNDEFINED INSTRUCTION The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction format is shown in Figure 3-28. 31 Cond 28 27 011 25 24 xxxxxxxxxxxxxxxxxxxx 543 1 xxxx 0 Figure 3-28. Undefined Instruction If the condition is true, the undefined instruction trap will be taken. Note that the undefined instruction mechanism involves offering this instruction to any coprocessors which may be present, and all coprocessors must refuse to accept it by driving CPA and CPB HIGH. INSTRUCTION CYCLE TIMES This instruction takes 2S + 1I + 1N cycles, where S, N and I are defined as sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle). ASSEMBLER SYNTAX The assembler has no mnemonics for generating this instruction. If it is adopted in the future for some specified use, suitable mnemonics will be added to the assembler. Until such time, this instruction must not be used. 3-58 S3C4510B INSTRUCTION SET INSTRUCTION SET EXAMPLES The following examples show ways in which the basic ARM7TDMI instructions can combine to give efficient code. None of these methods saves a great deal of execution time (although they may save some), mostly they just save code. USING THE CONDITIONAL INSTRUCTIONS Using Conditionals for Logical OR CMP BEQ CMP BEQ This can be replaced by CMP CMPNE BEQ Absolute Value TEQ RSBMI Rn,#0 Rn,Rn,#0 ; Test sign ; and 2's complement if necessary. Rn,#p Rm,#q Label ; If condition not satisfied try other test. Rn,#p Label Rm,#q Label ; If Rn=p OR Rm=q THEN GOTO Label. Multiplication by 4, 5 or 6 (Run Time) MOV CMP ADDCS ADDHI Rc,Ra,LSL#2 Rb,#5 Rc,Rc,Ra Rc,Rc,Ra ; ; ; ; Multiply by 4, Test value, Complete multiply by 5, Complete multiply by 6. Combining Discrete and Range Tests TEQ CMPNE MOVLS Rc,#127 Rc,# " "-1 Rc,# "" ; ; ; ; Discrete test, Range test IF Rc<= "" OR Rc=ASCII(127) THEN Rc:= " " 3-59 INSTRUCTION SET S3C4510B Division and Remainder A number of divide routines for specific applications are provided in source form as part of the ANSI C library provided with the ARM Cross development toolkit, available from your supplier. A short general purpose divide routine follows. MOV CMP CMPCC MOVCC MOVCC BCC MOV CMP SUBCS ADDCS MOVS MOVNE BNE Rcnt,#1 Rb,#0x80000000 Rb,Ra Rb,Rb,ASL#1 Rcnt,Rcnt,ASL#1 Div1 Rc,#0 Ra,Rb Ra,Ra,Rb Rc,Rc,Rcnt Rcnt,Rcnt,LSR#1 Rb,Rb,LSR#1 Div2 ; Enter with numbers in Ra and Rb. ; Bit to control the division. ; Move Rb until greater than Ra. Div1 Div2 ; ; ; ; ; ; Test for possible subtraction. Subtract if ok, Put relevant bit into result Shift control bit Halve unless finished. Divide result in Rc, remainder in Ra. Overflow Detection in the ARM7TDMI 1. Overflow in unsigned multiply with a 32-bit result UMULL TEQ BNE Rd,Rt,Rm,Rn Rt,#0 overflow ; 3 to 6 cycles ; +1 cycle and a register 2. Overflow in signed multiply with a 32-bit result SMULL TEQ BNE Rd,Rt,Rm,Rn Rt,Rd ASR#31 overflow ; 3 to 6 cycles ; +1 cycle and a register 3. Overflow in unsigned multiply accumulate with a 32 bit result UMLAL TEQ BNE Rd,Rt,Rm,Rn Rt,#0 overflow ; 4 to 7 cycles ; +1 cycle and a register 4. Overflow in signed multiply accumulate with a 32 bit result SMLAL TEQ BNE Rd,Rt,Rm,Rn Rt,Rd, ASR#31 overflow ; 4 to 7 cycles ; +1 cycle and a register 3-60 S3C4510B INSTRUCTION SET 5. Overflow in unsigned multiply accumulate with a 64 bit result UMULL ADDS ADC BCS Rl,Rh,Rm,Rn Rl,Rl,Ra1 Rh,Rh,Ra2 overflow ; ; ; ; 3 to 6 cycles Lower accumulate Upper accumulate 1 cycle and 2 registers 6. Overflow in signed multiply accumulate with a 64 bit result SMULL ADDS ADC BVS Rl,Rh,Rm,Rn Rl,Rl,Ra1 Rh,Rh,Ra2 overflow ; ; ; ; 3 to 6 cycles Lower accumulate Upper accumulate 1 cycle and 2 registers NOTE Overflow checking is not applicable to unsigned and signed multiplies with a 64-bit result, since overflow does not occur in such calculations. PSEUDO-RANDOM BINARY SEQUENCE GENERATOR It is often necessary to generate (pseudo-) random numbers and the most efficient algorithms are based on shift generators with exclusive-OR feedback rather like a cyclic redundancy check generator. Unfortunately the sequence of a 32 bit generator needs more than one feedback tap to be maximal length (i.e. 2^32-1 cycles before repetition), so this example uses a 33 bit register with taps at bits 33 and 20. The basic algorithm is newbit: = bit 33 eor bit 20, shift left the 33 bit number and put in newbit at the bottom; this operation is performed for all the newbits needed (i.e. 32 bits). The entire operation can be done in 5 S cycles: ; ; ; ; ; ; ; Enter with seed in Ra (32 bits), Rb (1 bit in Rb lsb), uses Rc. Top bit into carry 33 bit rotate right Carry into lsb of Rb (involved!) (similarly involved!) new seed in Ra, Rb as before TST MOVS ADC EOR EOR Rb,Rb,LSR#1 Rc,Ra,RRX Rb,Rb,Rb Rc,Rc,Ra,LSL#12 Ra,Rc,Rc,LSR#20 MULTIPLICATION BY CONSTANT USING THE BARREL SHIFTER Multiplication by 2^n (1,2,4,8,16,32..) MOV Ra, Rb, LSL #n Multiplication by 2^n+1 (3,5,9,17..) ADD Ra,Ra,Ra,LSL #n Multiplication by 2^n-1 (3,7,15..) RSB Ra,Ra,Ra,LSL #n 3-61 INSTRUCTION SET S3C4510B Multiplication by 6 ADD MOV Ra,Ra,Ra,LSL #1 Ra,Ra,LSL#1 ; Multiply by 3 ; and then by 2 Multiply by 10 and add in extra number ADD ADD Ra,Ra,Ra,LSL#2 Ra,Rc,Ra,LSL#1 ; Multiply by 5 ; Multiply by 2 and add in next digit General recursive method for Rb := Ra*C, C a constant: 1. If C even, say C = 2^n*D, D odd: D=1: D<>1: MOV MOV Rb,Ra,LSL #n {Rb := Ra*D} Rb,Rb,LSL #n 2. If C MOD 4 = 1, say C = 2^n*D+1, D odd, n>1: D=1: D<>1: ADD ADD Rb,Ra,Ra,LSL #n {Rb := Ra*D} Rb,Ra,Rb,LSL #n 3. If C MOD 4 = 3, say C = 2^n*D-1, D odd, n>1: D=1: D<>1: RSB RSB Rb,Ra,Ra,LSL #n {Rb := Ra*D} Rb,Ra,Rb,LSL #n This is not quite optimal, but close. An example of its non-optimality is multiply by 45 which is done by: RSB RSB ADD rather than by: ADD ADD Rb,Ra,Ra,LSL#3 Rb,Rb,Rb,LSL#2 ; Multiply by 9 ; Multiply by 5*9 = 45 Rb,Ra,Ra,LSL#2 Rb,Ra,Rb,LSL#2 Rb,Ra,Rb,LSL# 2 ; Multiply by 3 ; Multiply by 4*3-1 = 11 ; Multiply by 4*11+1 = 45 3-62 S3C4510B INSTRUCTION SET LOADING A WORD FROM AN UNKNOWN ALIGNMENT ; ; ; ; ; ; ; ; ; Enter with address in Ra (32 bits) uses Rb, Rc result in Rd. Note d must be less than c e.g. 0,1 Get word aligned address Get 64 bits containing answer Correction factor in bytes ...now in bits and test if aligned Produce bottom of result word (if not aligned) Get other shift amount Combine two halves to get result BIC LDMIA AND MOVS MOVNE RSBNE ORRNE Rb,Ra,#3 Rb,{Rd,Rc} Rb,Ra,#3 Rb,Rb,LSL#3 Rd,Rd,LSR Rb Rb,Rb,#32 Rd,Rd,Rc,LSL Rb 3-63 INSTRUCTION SET S3C4510B THUMB INSTRUCTION SET FORMAT The thumb instruction sets are 16-bit versions of ARM instruction sets (32-bit format). The ARM instructions are reduced to 16-bit versions, Thumb instructions, at the cost of versatile functions of the ARM instruction sets. The thumb instructions are decompressed to the ARM instructions by the Thumb decompressor inside the ARM7TDMI core. As the Thumb instructions are compressed ARM instructions, the Thumb instructions have the 16-bit format instructions and have some restrictions. The restrictions by 16-bit format is fully notified for using the Thumb instructions. FORMAT SUMMARY The THUMB instruction set formats are shown in the following figure. 15 14 13 12 11 10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0 0 0 1 0 0 1 1 1 0 0 0 1 1 0 0 0 1 1 B 0 1 0 1 1 0 1 1 0 1 1 0 H 1 Op 0 0 1 L H L L L SP 0 L L 0 1 B S 0 1 Op 1 I 9 8 Offset5 7 6 5 4 Rs Rs 3 2 1 Rd Rd 0 Move Shifted register Add/subtract Move/compare/add/ subtract immediate Op Rd Rn/offset3 Offset8 Op Rs Rs/Hs Word8 Ro Ro Rb Rb Rb Rb Word8 Word8 0 R S SWord7 Rlist Rlist Softset8 1 Value8 Offset11 Offset Rd Rd Rd Rd Rd Rd/Hd ALU operations Hi regiter operations /branch exchange PC-relative load Load/store with register offset Load/store sign-extended byte/halfword Load/store with immediate offset Load/store halfword SP-relative load/store Load address Add offset to stack pointer Push/pop register Multiple load/store Conditional branch Software interrupt Unconditional branch Long branch with link Op Rd 0 1 H1 H2 Offset5 Offset5 Rd Rd 0 0 Rb Cond 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 3-29. THUMB Instruction Set Formats 3-64 S3C4510B INSTRUCTION SET OPCODE SUMMARY The following table summarises the THUMB instruction set. For further information about a particular instruction please refer to the sections listed in the right-most column. Table 3-7. THUMB Instruction Set Opcodes Mnemonic ADC ADD AND ASR B Bxx BIC BL BX CMN CMP EOR LDMIA LDR LDRB LDRH LSL LDSB LDSH LSR MOV MUL MVN NEG ORR POP PUSH POR Instruction Add with carry Add AND Arithmetic shift right Unconditional branch Conditional branch Bit clear Branch and link Branch and exchange Compare negative Compare EOR Load multiple Load word Load byte Load half-word Logical shift left Load sign-extended byte Load sign-extended half-word Logical shift right Move register Multiply Move negative register Negate OR Pop registers Push registers Rotate right Lo-Register Operand V V V V V V V V V V V V V V V V V V V V V V V V V V V V Hi-Register Operand - V - - - - - - V - V - - - - - - - - - V - - - - - - - Condition Codes Set V V (1) V V - - V - - V V V - - - - V - - V V (2) V V V V - - V 3-65 INSTRUCTION SET S3C4510B Table 3-7. THUMB Instruction Set Opcodes (Continued) Mnemonic SBC STMIA STR STRB STRH SWI SUB TST Instruction Subtract with carry Store multiple Store word Store byte Store half-word Software interrupt Subtract Test bits Lo-Register Operand V V V V V - V V Hi-Register Operand - - - - - - - - Condition Codes Set V - - - - - V V NOTES: 1. The condition codes are unaffected by the format 5, 12 and 13 versions of this instruction. 2. The condition codes are unaffected by the format 5 version of this instruction. 3-66 S3C4510B INSTRUCTION SET FORMAT 1: MOVE SHIFTED REGISTER 15 0 14 0 13 0 12 Op 11 10 Offset5 6 5 Rs 3 2 Rd 0 [2:0] Destination Register [5:3] Source Register [10:6] Immediate Vale [12:11] Opcode 0 = LSL 1 = LSR 2 = ASR Figure 3-30. Format 1 OPERATION These instructions move a shifted value between Lo registers. The THUMB assembler syntax is shown in Table 3-8. NOTE All instructions in this group set the CPSR condition codes. Table 3-8. Summary of Format 1 Instructions OP 00 01 10 THUMB Assembler LSL Rd, Rs, #Offset5 LSR Rd, Rs, #Offset5 ASR Rd, Rs, #Offset5 ARM Equivalent MOVS Rd, Rs, LSL #Offset5 MOVS Rd, Rs, LSR #Offset5 MOVS Rd, Rs, ASR #Offset5 Action Shift Rs left by a 5-bit immediate value and store the result in Rd. Perform logical shift right on Rs by a 5-bit immediate value and store the result in Rd. Perform arithmetic shift right on Rs by a 5-bit immediate value and store the result in Rd. INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-8. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. Examples LSR R2, R5, #27 ; Logical shift right the contents ; of R5 by 27 and store the result in R2. ; Set condition codes on the result. 3-67 INSTRUCTION SET S3C4510B FORMAT 2: ADD/SUBTRACT 15 0 14 0 13 0 12 1 11 1 10 1 9 Op 8 Rn/Offset3 6 5 Rs 3 2 Rd 0 [2:0] Destination Register [5:3] Source Register [8:6] Register/Immediate Value [9] Opcode 0 = ADD 1 = SUB [10] Immediate Flag 0 = Register operand 1 = Immediate oerand Figure 3-31. Format 2 OPERATION These instructions allow the contents of a Lo register or a 3-bit immediate value to be added to or subtracted from a Lo register. The THUMB assembler syntax is shown in Table 3-9. NOTE All instructions in this group set the CPSR condition codes. Table 3-9. Summary of Format 2 Instructions OP 0 0 1 1 I 0 1 0 1 THUMB Assembler ADD Rd, Rs, Rn ARM Equivalent ADDS Rd, Rs, Rn Action Add contents of Rn to contents of Rs. Place result in Rd. Add 3-bit immediate value to contents of Rs. Place result in Rd. Subtract contents of Rn from contents of Rs. Place result in Rd. Subtract 3-bit immediate value from contents of Rs. Place result in Rd. ADD Rd, Rs, #Offset3 ADDS Rd, Rs, #Offset3 SUB Rd, Rs, Rn SUBS Rd, Rs, Rn SUB Rd, Rs, #Offset3 SUBS Rd, Rs, #Offset3 3-68 S3C4510B INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-9. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. Examples ADD SUB R0, R3, R4 R6, R2, #6 ; R0 : = R3 + R4 and set condition codes on the result. ; R6 : = R2 - 6 and set condition codes. 3-69 INSTRUCTION SET S3C4510B FORMAT 3: MOVE/COMPARE/ADD/SUBTRACT IMMEDIATE 15 0 14 0 13 0 12 Op 11 10 Rd 8 7 Offset8 0 [7:0] Immediate Value [10:8] Source/Destination Register [12:11] Opcode 0 = MOV 1 = CMP 2 = ADD 3 = SUB Figure 3-32. Format 3 OPERATIONS The instructions in this group perform operations between a Lo register and an 8-bit immediate value. The THUMB assembler syntax is shown in Table 3-10. NOTE All instructions in this group set the CPSR condition codes. Table 3-10. Summary of Format 3 Instructions OP 00 01 10 11 THUMB Assembler MOV Rd, #Offset8 CMP Rd, #Offset8 ADD Rd, #Offset8 SUB Rd, #Offset8 ARM Equivalent MOVS Rd, #Offset8 CMP Rd, #Offset8 ADDS Rd, Rd, #Offset8 SUBS Rd, Rd, #Offset8 Action Move 8-bit immediate value into Rd. Compare contents of Rd with 8-bit immediate value. Add 8-bit immediate value to contents of Rd and place the result in Rd. Subtract 8-bit immediate value from contents of Rd and place the result in Rd. INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-10. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. Examples MOV CMP ADD SUB R0, #128 R2, #62 R1, #255 R6, #145 ; ; ; ; R0 : = 128 and set condition codes Set condition codes on R2 - 62 R1 : = R1 + 255 and set condition codes R6 : = R6 - 145 and set condition codes 3-70 S3C4510B INSTRUCTION SET FORMAT 4: ALU OPERATIONS 15 0 14 0 13 0 12 0 11 0 10 0 9 Op 6 5 Rs 3 2 Rd 0 [2:0] Source/Destination Register [5:3] Source Register 2 [9:6] Opcode Figure 3-33. Format 4 OPERATION The following instructions perform ALU operations on a Lo register pair. NOTE All instructions in this group set the CPSR condition codes Table 3-11. Summary of Format 4 Instructions OP THUMB Assembler ARM Equivalent ANDS Rd, Rd, Rs EORS Rd, Rd, Rs MOVS Rd, Rd, LSL Rs MOVS Rd, Rd, LSR Rs MOVS Rd, Rd, ASR Rs ADCS Rd, Rd, Rs SBCS Rd, Rd, Rs MOVS Rd, Rd, ROR Rs TST Rd, Rs RSBS Rd, Rs, #0 CMP Rd, Rs CMN Rd, Rs ORRS Rd, Rd, Rs MULS Rd, Rs, Rd BICS Rd, Rd, Rs MVNS Rd, Rs Rd: = Rd AND Rs Rd: = Rd EOR Rs Rd : = Rd << Rs Rd : = Rd >> Rs Rd : = Rd ASR Rs Rd : = Rd + Rs + C-bit Rd : = Rd - Rs - NOT C-bit Rd : = Rd ROR Rs Set condition codes on Rd AND Rs Rd = - Rs Set condition codes on Rd - Rs Set condition codes on Rd + Rs Rd: = Rd OR Rs Rd: = Rs * Rd Rd: = Rd AND NOT Rs Rd: = NOT Rs Action 0000 AND Rd, Rs 0001 EOR Rd, Rs 0010 LSL Rd, Rs 0011 LSR Rd, Rs 0100 ASR Rd, Rs 0101 ADC Rd, Rs 0110 SBC Rd, Rs 0111 ROR Rd, Rs 1000 TST Rd, Rs 1001 NEG Rd, Rs 1010 CMP Rd, Rs 1011 CMN Rd, Rs 1100 ORR Rd, Rs 1101 MUL Rd, Rs 1110 BIC Rd, Rs 1111 MVN Rd, Rs 3-71 INSTRUCTION SET S3C4510B INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-11. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. Examples EOR ROR NEG CMP MUL R3, R4 R1, R0 R5, R3 R2, R6 R0, R7 ; R3 : = R3 EOR R4 and set condition codes ; Rotate right R1 by the value in R0, store ; the result in R1 and set condition codes ; Subtract the contents of R3 from zero, ; store the result in R5. Set condition codes ie R5 = - R3 ; Set the condition codes on the result of R2 - R6 ; R0 : = R7 * R0 and set condition codes 3-72 S3C4510B INSTRUCTION SET FORMAT 5: HI-REGISTER OPERATIONS/BRANCH EXCHANGE 15 0 14 0 13 0 12 0 11 0 10 0 9 Op 8 7 H1 6 H2 5 Rs/Hs 3 2 Rd/Hd 0 [2:0] Destination Register [5:3] Source Register [6] Hi Operand Flag 2 [7] Hi Operand Flag 1 [9:8] Opcode Figure 3-34. Format 5 OPERATION There are four sets of instructions in this group. The first three allow ADD, CMP and MOV operations to be performed between Lo and Hi registers, or a pair of Hi registers. The fourth, BX, allows a Branch to be performed which may also be used to switch processor state. The THUMB assembler syntax is shown in Table 3-12. NOTE In this group only CMP (Op = 01) sets the CPSR condition codes. The action of H1 = 0, H2 = 0 for Op = 00 (ADD), Op = 01 (CMP) and Op = 10 (MOV) is undefined, and should not be used. 3-73 INSTRUCTION SET S3C4510B Table 3-12. Summary of Format 5 Instructions OP 00 00 00 01 H1 0 1 1 0 H2 1 0 1 1 THUMB Assembler ADD Rd, Hs ADD Hd, Rs ADD Hd, Hs CMP Rd, Hs ARM Equivalent ADD Rd, Rd, Hs ADD Hd, Hd, Rs ADD Hd, Hd, Hs CMP Rd, Hs Action Add a register in the range 8-15 to a register in the range 0-7. Add a register in the range 0-7 to a register in the range 8-15. Add two registers in the range 8-15. Compare a register in the range 0-7 with a register in the range 8-15. Set the condition code flags on the result. Compare a register in the range 8-15 with a register in the range 0-7. Set the condition code flags on the result. Compare two registers in the range 8-15. Set the condition code flags on the result. Move a value from a register in the range 8-15 to a register in the range 0-7. Move a value from a register in the range 0-7 to a register in the range 8-15. Move a value between two registers in the range 8-15. Perform branch (plus optional state change) to address in a register in the range 0-7. Perform branch (plus optional state change) to address in a register in the range 8-15. 01 1 0 CMP Hd, Rs CMP Hd, Rs 01 10 10 00 00 00 1 0 1 0 1 1 1 1 0 1 0 1 CMP Hd, Hs MOV Rd, Hs MOV Hd, Rs MOV Hd, Hs BX Rs BX Hs CMP Hd, Hs MOV Rd, Hs MOV Hd, Rs MOV Hd, Hs BX Rs BX Hs INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-12. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. THE BX INSTRUCTION BX performs a branch to a routine whose start address is specified in a Lo or Hi register. Bit 0 of the address determines the processor state on entry to the routine: Bit 0 = 0 Bit 0 = 1 Causes the processor to enter ARM state. Causes the processor to enter THUMB state. NOTE The action of H1 = 1 for this instruction is undefined, and should not be used. 3-74 S3C4510B INSTRUCTION SET Examples Hi-Register Operations ADD R4, R12 MOV PC, R5 R15, R14 ; ; ; ; ; PC := PC + R5 but don't set the condition codes.CMP Set the condition codes on the result of R4 - R12. Move R14 (LR) into R15 (PC) but don't set the condition codes, eg. return from subroutine. Branch and Exchange ADR MOV BX R1,outofTHUMB R11,R1 R11 ; Switch from THUMB to ARM state. ; Load address of outofTHUMB into R1. ; Transfer the contents of R11 into the PC. ; Bit 0 of R11 determines whether ; ARM or THUMB state is entered, ie. ARM state here. ... ALIGN CODE32 outofTHUMB ; Now processing ARM instructions... USING R15 AS AN OPERAND If R15 is used as an operand, the value will be the address of the instruction + 4 with bit 0 cleared. Executing a BX PC in THUMB state from a non-word aligned address will result in unpredictable execution. 3-75 INSTRUCTION SET S3C4510B FORMAT 6: PC-RELATIVE LOAD 15 0 14 0 13 0 12 0 11 0 10 Rd 8 7 Word 8 0 [7:0] Immediate Value [10:8] Destination Register Figure 3-35. Format 6 OPERATION This instruction loads a word from an address specified as a 10-bit immediate offset from the PC. The THUMB assembler syntax is shown below. Table 3-13. Summary of PC-Relative Load Instruction THUMB Assembler LDR Rd, [PC, #Imm] ARM Equivalent LDR Rd, [R15, #Imm] Action Add unsigned offset (255 words, 1020 bytes) in Imm to the current value of the PC. Load the word from the resulting address into Rd. NOTE: The value specified by #Imm is a full 10-bit address, but must always be word-aligned (ie with bits 1:0 set to 0), since the assembler places #Imm >> 2 in field Word 8. The value of the PC will be 4 bytes greater than the address of this instruction, but bit 1 of the PC is forced to 0 to ensure it is word aligned. INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. Examples LDR R3,[PC,#844] ; ; ; ; ; Load into R3 the word found at the address formed by adding 844 to PC. bit[1] of PC is forced to zero. Note that the THUMB opcode will contain 211 as the Word8 value. 3-76 S3C4510B INSTRUCTION SET FORMAT 7: LOAD/STORE WITH REGISTER OFFSET 15 0 14 1 13 0 12 1 11 L 10 B 9 0 8 Ro 6 5 Rb 3 2 Rd 0 [2:0] Source/Destination Register [5:3] Base Register [8:6] Offset Register [10] Byte/Word Flag 0 = Transfer word quantity 1 = Transfer byte quantity [11] Load/Store Flag 0 = Store to memory 1 = Load from memory Figure 3-36. Format 7 OPERATION These instructions transfer byte or word values between registers and memory. Memory addresses are preindexed using an offset register in the range 0-7. The THUMB assembler syntax is shown in Table 3-14. Table 3-14. Summary of Format 7 Instructions L 0 B 0 THUMB Assembler STR Rd, [Rb, Ro] ARM Equivalent STR Rd, [Rb, Ro] Action Pre-indexed word store: Calculate the target address by adding together the value in Rb and the value in Ro. Store the contents of Rd at the address. Pre-indexed byte store: Calculate the target address by adding together the value in Rb and the value in Ro. Store the byte value in Rd at the resulting address. Pre-indexed word load: Calculate the source address by adding together the value in Rb and the value in Ro. Load the contents of the address into Rd. Pre-indexed byte load: Calculate the source address by adding together the value in Rb and the value in Ro. Load the byte value at the resulting address. 0 1 STRB Rd, [Rb, Ro] STRB Rd, [Rb, Ro] 1 0 LDR Rd, [Rb, Ro] LDR Rd, [Rb, Ro] 1 1 LDRB Rd, [Rb, Ro] LDRB Rd, [Rb, Ro] 3-77 INSTRUCTION SET S3C4510B INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-14. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. Examples STR LDRB R3, [R2,R6] R2, [R0,R7] ; ; ; ; Store word in R3 at the address formed by adding R6 to R2. Load into R2 the byte found at the address formed by adding R7 to R0. 3-78 S3C4510B INSTRUCTION SET FORMAT 8: LOAD/STORE SIGN-EXTENDED BYTE/HALF-WORD 15 0 14 1 13 0 12 1 11 H 10 S 9 1 8 Ro 6 5 Rb 3 2 Rd 0 [2:0] Destination Register [5:3] Base Register [8:6] Offset Register [10] Sign-Extended Flag 0 = Operand not sing-extended 1 = Operand sing-extended [11] H Flag Figure 3-37. Format 8 OPERATION These instructions load optionally sign-extended bytes or half-words, and store half-words. The THUMB assembler syntax is shown below. Table 3-15. Summary of format 8 instructions L 0 B 0 THUMB Assembler STRH Rd, [Rb, Ro] ARM Equivalent STRH Rd, [Rb, Ro] Action Store half-word: Add Ro to base address in Rb. Store bits 0-15 of Rd at the resulting address. Load half-word: Add Ro to base address in Rb. Load bits 0-15 of Rd from the resulting address, and set bits 16-31 of Rd to 0. Load sign-extended byte: Add Ro to base address in Rb. Load bits 0-7 of Rd from the resulting address, and set bits 8-31 of Rd to bit 7. 1 1 LDSH Rd, [Rb, Ro] LDRSH Rd, [Rb, Ro] Load sign-extended half-word: Add Ro to base address in Rb. Load bits 0-15 of Rd from the resulting address, and set bits 16-31 of Rd to bit 15. 0 1 LDRH Rd, [Rb, Ro] LDRH Rd, [Rb, Ro] 1 0 LDSB Rd, [Rb, Ro] LDRSB Rd, [Rb, Ro] 3-79 INSTRUCTION SET S3C4510B INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-15. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. Examples STRH LDSB LDSH R4, [R3, R0] R2, [R7, R1] R3, [R4, R2] ; ; ; ; ; ; Store the lower 16 bits of R4 at the address formed by adding R0 to R3. Load into R2 the sign extended byte found at the address formed by adding R1 to R7. Load into R3 the sign extended half-word found at the address formed by adding R2 to R4. 3-80 S3C4510B INSTRUCTION SET FORMAT 9: LOAD/STORE WITH IMMEDIATE OFFSET 15 0 14 1 13 1 12 B 11 L 10 Offset5 6 5 Rb 3 2 Rd 0 [2:0] Source/Destination Register [5:3] Base Register [10:6] Offset Register [11] Load/Store Flag 0 = Store to memory 1 = Load from memory [12] Byte/Word Flad 0 = Transfer word quantity 1 = Transfer byte quantity Figure 3-38. Format 9 OPERATION These instructions transfer byte or word values between registers and memory using an immediate 5 or 7-bit offset. The THUMB assembler syntax is shown in Table 3-16 Table 3-16. Summary of Format 9 Instructions L 0 B 0 THUMB Assembler STR Rd, [Rb, #Imm] ARM Equivalent STR Rd, [Rb, #Imm] Action Calculate the target address by adding together the value in Rb and Imm. Store the contents of Rd at the address. Calculate the source address by adding together the value in Rb and Imm. Load Rd from the address. 0 1 1 0 LDR Rd, [Rb, #Imm] LDR Rd, [Rb, #Imm] STRB Rd, [Rb, #Imm] STRB Rd, [Rb, #Imm] Calculate the target address by adding together the value in Rb and Imm. Store the byte value in Rd at the address. LDRB Rd, [Rb, #Imm] LDRB Rd, [Rb, #Imm] Calculate source address by adding together the value in Rb and Imm. Load the byte value at the address into Rd. 1 1 NOTE: For word accesses (B = 0), the value specified by #Imm is a full 7-bit address, but must be word-aligned (ie with bits 1:0 set to 0), since the assembler places #Imm >> 2 in the Offset5 field. 3-81 INSTRUCTION SET S3C4510B INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-16. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. Examples LDR R2, [R5,#116] ; ; ; ; ; ; ; ; Load into R2 the word found at the address formed by adding 116 to R5. Note that the THUMB opcode will contain 29 as the Offset5 value. Store the lower 8 bits of R1 at the address formed by adding 13 to R0. Note that the THUMB opcode will contain 13 as the Offset5 value. STRB R1, [R0,#13] 3-82 S3C4510B INSTRUCTION SET FORMAT 10: LOAD/STORE HALF-WORD 15 0 14 1 13 0 12 0 11 L 10 Offset5 6 5 Rb 3 2 Rd 0 [2:0] Source/Destination Register [5:3] Base Register [10:6] Immediate Value [11] Load/Store Flag 0 = Store to memory 1 = Load from memory Figure 3-39. Format 10 OPERATION These instructions transfer half-word values between a Lo register and memory. Addresses are pre-indexed, using a 6-bit immediate value. The THUMB assembler syntax is shown in Table 3-17. Table 3-17. Half-word Data Transfer Instructions L 0 1 THUMB Assembler ARM Equivalent Action STRH Rd, [Rb, #Imm] STRH Rd, [Rb, #Imm] Add #Imm to base address in Rb and store bits 0-15 of Rd at the resulting address. LDRH Rd, [Rb, #Imm] LDRH Rd, [Rb, #Imm] Add #Imm to base address in Rb. Load bits 0-15 from the resulting address into Rd and set bits 16-31 to zero. NOTE: #Imm is a full 6-bit address but must be half-word-aligned (ie with bit 0 set to 0), since the assembler places #Imm >> 1 in the Offset5 field. INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-17. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. Examples STRH R6, [R1, #56] ; ; ; ; Store the lower 16 bits of R4 at the address formed by adding 56 R1. Note that the THUMB opcode will contain 28 as the Offset5 value. Load into R4 the half-word found at the address formed by ; adding 4 to R7. Note that the THUMB opcode will ; contain 2 as the Offset5 value. LDRH R4, [R7, #4] 3-83 INSTRUCTION SET S3C4510B FORMAT 11: SP-RELATIVE LOAD/STORE 15 1 14 0 13 0 12 1 11 L 10 Rd 8 7 Word 8 0 [7:0] Immediate Value [10:8] Destination Register [11] Load/Store Bit 0 = Store to memory 1 = Load from memory Figure 3-40. Format 11 OPERATION The instructions in this group perform an SP-relative load or store. The THUMB assembler syntax is shown in the following table. Table 3-18. SP-Relative Load/Store Instructions L 0 THUMB Assembler STR Rd, [SP, #Imm] ARM Equivalent STR Rd, [R13 #Imm] Action Add unsigned offset (255 words, 1020 bytes) in Imm to the current value of the SP (R7). Store the contents of Rd at the resulting address. Add unsigned offset (255 words, 1020 bytes) in Imm to the current value of the SP (R7). Load the word from the resulting address into Rd. 1 LDR Rd, [SP, #Imm] LDR Rd, [R13 #Imm] NOTE: The offset supplied in #Imm is a full 10-bit address, but must always be word-aligned (ie bits 1:0 set to 0), since the assembler places #Imm >> 2 in the Word8 field. INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-18. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. Examples STR R4, [SP,#492] ; ; ; ; Store the contents of R4 at the address formed by adding 492 to SP (R13). Note that the THUMB opcode will contain 123 as the Word8 value. 3-84 S3C4510B INSTRUCTION SET FORMAT 12: LOAD ADDRES 15 1 14 0 13 1 12 0 11 SP 10 Rd 8 7 Word 8 0 [7:0] 8-bit Unsigned Constant [10:8] Destination Register [11] Source 0 = PC 1 = SP Figure 3-41. Format 12 OPERATION These instructions calculate an address by adding an 10-bit constant to either the PC or the SP, and load the resulting address into a register. The THUMB assembler syntax is shown in the following table. Table 3-19. Load Address SP 0 1 THUMB Assembler ADD Rd, PC, #Imm ADD Rd, SP, #Imm ARM Equivalent ADD Rd, R15, #Imm ADD Rd, R13, #Imm Action Add #Imm to the current value of the program counter (PC) and load the result into Rd. Add #Imm to the current value of the stack pointer (SP) and load the result into Rd. NOTE: The value specified by #Imm is a full 10-bit value, but this must be word-aligned (ie with bits 1:0 set to 0) since the assembler places #Imm >> 2 in field Word 8. Where the PC is used as the source register (SP = 0), bit 1 of the PC is always read as 0. The value of the PC will be 4 bytes greater than the address of the instruction before bit 1 is forced to 0. The CPSR condition codes are unaffected by these instructions. 3-85 INSTRUCTION SET S3C4510B INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-19. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. Examples ADD R2, PC, #572 ; ; ; ; ; ; ; ; R2: = PC + 572, but don't set the condition codes. bit[1] of PC is forced to zero. Note that the THUMB opcode will contain 143 as the Word8 value. R6: = SP (R13) + 212, but don't set the condition codes. Note that the THUMB opcode will contain 53 as the Word 8 value. ADD R6, SP, #212 3-86 S3C4510B INSTRUCTION SET FORMAT 13: ADD OFFSET TO STACK POINTER 15 1 14 0 13 1 12 1 11 0 10 0 9 0 8 0 7 S 6 SWord 7 0 [6:0] 7-bit Immediate Value [7] Sign Flag 0 = Offset is positive 1 = Offset is negative Figure 3-42. Format 13 OPERATION This instruction adds a 9-bit signed constant to the stack pointer. The following table shows the THUMB assembler syntax. Table 3-20. The ADD SP Instruction S 0 1 THUMB Assembler ADD SP, #Imm ADD SP, #-Imm ARM Equivalent ADD R13, R13, #Imm SUB R13, R13, #Imm Action Add #Imm to the stack pointer (SP). Add #-Imm to the stack pointer (SP). NOTE: The offset specified by #Imm can be up to -/+ 508, but must be word-aligned (ie with bits 1:0 set to 0) since the assembler converts #Imm to an 8-bit sign + magnitude number before placing it in field SWord7. The condition codes are not set by this instruction. INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-20. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. Examples ADD SP, #268 ; ; ; ; ; ; SP (R13): = SP + 268, but don't set the condition codes. Note that the THUMB opcode will contain 67 as the Word7 value and S = 0. SP (R13): = SP - 104, but don't set the condition codes. Note that the THUMB opcode will contain 26 as the Word7 value and S = 1. ADD SP, #-104 3-87 INSTRUCTION SET S3C4510B FORMAT 14: PUSH/POP REGISTERS 15 1 14 0 13 1 12 1 11 L 10 1 9 0 8 R 7 Rlist 0 [7:0] Register List [8] PC/LR Bit 0 = Do not store LR/Load PC 1 = Store LR/Load PC [11] Load/Store Bit 0 = Store to memory 1 = Load from memory Figure 3-43. Format 14 OPERATION The instructions in this group allow registers 0-7 and optionally LR to be pushed onto the stack, and registers 0-7 and optionally PC to be popped off the stack. The THUMB assembler syntax is shown in Table 3-21. NOTE The stack is always assumed to be full descending. Table 3-21. PUSH and POP Instructions L 0 0 B 0 1 THUMB Assembler PUSH { Rlist } PUSH { Rlist, LR } ARM Equivalent STMDB R13!, { Rlist } Action Push the registers specified by Rlist onto the stack. Update the stack pointer. STMDB R13!, { Rlist, R14} Push the Link Register and the registers specified by Rlist (if any) onto the stack. Update the stack pointer. LDMIA R13!, { Rlist } LDMIA R13!, {Rlist, R15} Pop values off the stack into the registers specified by Rlist. Update the stack pointer. Pop values off the stack and load into the registers specified by Rlist. Pop the PC off the stack. Update the stack pointer. 1 1 0 1 POP { Rlist } POP { Rlist, PC } 3-88 S3C4510B INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-21. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. Examples PUSH {R0-R4,LR} ; ; ; ; ; ; ; Store R0, R1, R2, R3, R4 and R14 (LR) at the stack pointed to by R13 (SP) and update R13. Useful at start of a sub-routine to save workspace and return address. Load R2, R6 and R15 (PC) from the stack pointed to by R13 (SP) and update R13. Useful to restore workspace and return from sub-routine. POP {R2, R6, PC} 3-89 INSTRUCTION SET S3C4510B FORMAT 15: MULTIPLE LOAD/STORE 15 1 14 1 13 0 12 0 11 L 10 Rb 8 7 Rlist 0 [7:0] Register List [10:8] Base Register [11] Load/Store Bit 0 = Store to memory 1 = Load from memory Figure 3-44. Format 15 OPERATION These instructions allow multiple loading and storing of Lo registers. The THUMB assembler syntax is shown in the following table. Table 3-22. The Multiple Load/Store Instructions L 0 1 THUMB Assembler STMIA Rb!, { Rlist } LDMIA Rb!, { Rlist } ARM Equivalent STMIA Rb!, { Rlist } LDMIA Rb!, { Rlist } Action Store the registers specified by Rlist, starting at the base address in Rb. Write back the new base address. Load the registers specified by Rlist, starting at the base address in Rb. Write back the new base address. INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-22. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. Examples STMIA R0!, {R3-R7} ; ; ; ; Store the contents of registers R3-R7 starting at the address specified in R0, incrementing the addresses for each word. Write back the updated value of R0. 3-90 S3C4510B INSTRUCTION SET FORMAT 16: CONDITIONAL BRANCH 15 1 14 1 13 0 12 1 11 Cond 8 7 SOffset 8 0 [7:0] 8-bit Signed Immediate [11:8] Condition Figure 3-45. Format 16 OPERATION The instructions in this group all perform a conditional Branch depending on the state of the CPSR condition codes. The branch offset must take account of the prefetch operation, which causes the PC to be 1 word (4 bytes) ahead of the current instruction. The THUMB assembler syntax is shown in the following table. Table 3-23. The Conditional Branch Instructions Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 THUMB Assembler BEQ label BNE label BCS label BCC label BMI label BPL label BVS label BVC label BHI label BLS label BGE label ARM Equivalent BEQ label BNE label BCS label BCC label BMI label BPL label BVS label BVC label BHI label BLS label BGE label Branch if Z set (equal) Branch if Z clear (not equal) Branch if C set (unsigned higher or same) Branch if C clear (unsigned lower) Branch if N set (negative) Branch if N clear (positive or zero) Branch if V set (overflow) Branch if V clear (no overflow) Branch if C set and Z clear (unsigned higher) Branch if C clear or Z set (unsigned lower or same) Branch if N set and V set, or N clear and V clear (greater or equal) Action 3-91 INSTRUCTION SET S3C4510B Table 3-23. The Conditional Branch Instructions (Continued) Code 1011 1100 1101 THUMB Assembler BLT label BGT label BLE label ARM Equivalent BLT label BGT label BLE label Action Branch if N set and V clear, or N clear and V set (less than) Branch if Z clear, and either N set and V set or N clear and V clear (greater than) Branch if Z set, or N set and V clear, or N clear and V set (less than or equal) NOTES: 1. While label specifies a full 9-bit two's complement address, this must always be half-word-aligned (ie with bit 0 set to 0) since the assembler actually places label >> 1 in field SOffset8. 2. Cond = 1110 is undefined, and should not be used. Cond = 1111 creates the SWI instruction: see . INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-23. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. Examples CMP R0, #45 BGT over ... ... ... ... ; Branch to over-if R0 > 45. ; Note that the THUMB opcode will contain ; the number of half-words to offset. ; Must be half-word aligned. over 3-92 S3C4510B INSTRUCTION SET FORMAT 17: SOFTWARE INTERRUPT 15 1 14 1 13 0 12 1 11 1 10 1 9 1 8 1 7 Value 8 0 [7:0] Comment Field Figure 3-46. Format 17 OPERATION The SWI instruction performs a software interrupt. On taking the SWI, the processor switches into ARM state and enters Supervisor (SVC) mode. The THUMB assembler syntax for this instruction is shown below. Table 3-24. The SWI Instruction THUMB Assembler SWI Value 8 ARM Equivalent SWI Value 8 Perform Software Interrupt: Move the address of the next instruction into LR, move CPSR to SPSR, load the SWI vector address (0x8) into the PC. Switch to ARM state and enter SVC mode. NOTE: Value 8 is used solely by the SWI handler; it is ignored by the processor. Action INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-24. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. Examples SWI 18 ; Take the software interrupt exception. ; Enter Supervisor mode with 18 as the ; requested SWI number. 3-93 INSTRUCTION SET S3C4510B FORMAT 18: UNCONDITIONAL BRANCH 15 1 14 1 13 1 12 0 11 0 10 Offset11 0 [10:0] Immediate Value Figure 3-47. Format 18 OPERATION This instruction performs a PC-relative Branch. The THUMB assembler syntax is shown below. The branch offset must take account of the prefetch operation, which causes the PC to be 1 word (4 bytes) ahead of the current instruction. Table 3-25. Summary of Branch Instruction THUMB Assembler B label ARM Equivalent Action BAL label (half-word offset) Branch PC relative +/- Offset11 << 1, where label is PC +/- 2048 bytes. NOTE: The address specified by label is a full 12-bit twos complement address, but must always be half-word aligned (ie bit 0 set to 0), since the assembler places label >> 1 in the Offset11 field. Examples here B here B jimmy ... ; ; ; ; Branch onto itself. Assembles to 0xE7FE. (Note effect of PC offset). Branch to 'jimmy'. Note that the THUMB opcode will contain the number of Jimmy ... ; half-words to offset. ; Must be half-word aligned. 3-94 S3C4510B INSTRUCTION SET FORMAT 19: LONG BRANCH WITH LINK 15 1 14 1 13 1 12 1 11 H 10 Offset 0 [10:0] Long Branch and Link Offset High/Low [11] Low/High Offset Bit 0 = Offset high 1 = Offset low Figure 3-48. Format 19 OPERATION This format specifies a long branch with link. The assembler splits the 23-bit two's complement half-word offset specified by the label into two 11-bit halves, ignoring bit 0 (which must be 0), and creates two THUMB instructions. Instruction 1 (H = 0) In the first instruction the Offset field contains the upper 11 bits of the target address. This is shifted left by 12 bits and added to the current PC address. The resulting address is placed in LR. Instruction 2 (H =1) In the second instruction the Offset field contains an 11-bit representation lower half of the target address. This is shifted left by 1 bit and added to LR. LR, which now contains the full 23-bit address, is placed in PC, the address of the instruction following the BL is placed in LR and bit 0 of LR is set. The branch offset must take account of the prefetch operation, which causes the PC to be 1 word (4 bytes) ahead of the current instruction. 3-95 INSTRUCTION SET S3C4510B INSTRUCTION CYCLE TIMES This instruction format does not have an equivalent ARM instruction. Table 3-26. The BL Instruction H 0 1 THUMB Assembler BL label ARM Equivalent none Action LR := PC + OffsetHigh << 12 temp := next instruction address PC := LR + OffsetLow << 1 LR := temp | 1 Examples next BL faraway ... ; ; ; ; ; ; ; Unconditionally Branch to 'faraway' and place following instruction address, ie "next", in R14,the Link register and set bit 0 of LR high. Note that the THUMB opcodes will contain the number of half-words to offset. Must be Half-word aligned. faraway ... 3-96 S3C4510B INSTRUCTION SET INSTRUCTION SET EXAMPLES The following examples show ways in which the THUMB instructions may be used to generate small and efficient code. Each example also shows the ARM equivalent so these may be compared. MULTIPLICATION BY A CONSTANT USING SHIFTS AND ADDS The following shows code to multiply by various constants using 1, 2 or 3 Thumb instructions alongside the ARM equivalents. For other constants it is generally better to use the built-in MUL instruction rather than using a sequence of 4 or more instructions. Thumb 1. Multiplication by 2^n (1,2,4,8,...) LSL Ra, Rb, LSL #n ; MOV Ra, Rb, LSL #n ARM 2. Multiplication by 2^n+1 (3,5,9,17,...) LSL ADD Rt, Rb, #n Ra, Rt, Rb ; ADD Ra, Rb, Rb, LSL #n 3. Multiplication by 2^n-1 (3,7,15,...) LSL SUB Rt, Rb, #n Ra, Rt, Rb ; RSB Ra, Rb, Rb, LSL #n 4. Multiplication by -2^n (-2, -4, -8, ...) LSL MVN Ra, Rb, #n Ra, Ra ; MOV Ra, Rb, LSL #n ; RSB Ra, Ra, #0 5. Multiplication by -2^n-1 (-3, -7, -15, ...) LSL SUB Rt, Rb, #n Ra, Rb, Rt ; SUB Ra, Rb, Rb, LSL #n Multiplication by any C = {2^n+1, 2^n-1, -2^n or -2^n-1} * 2^n Effectively this is any of the multiplications in 2 to 5 followed by a final shift. This allows the following additional constants to be multiplied. 6, 10, 12, 14, 18, 20, 24, 28, 30, 34, 36, 40, 48, 56, 60, 62 ..... (2..5) LSL Ra, Ra, #n ; (2..5) ; MOV Ra, Ra, LSL #n 3-97 INSTRUCTION SET S3C4510B GENERAL PURPOSE SIGNED DIVIDE This example shows a general purpose signed divide and remainder routine in both Thumb and ARM code. Thumb code ;signed_divide ; Signed divide of R1 by R0: returns quotient in R0, ; remainder in R1 ;Get abs value of R0 into R3 ASR R2, R0, #31 EOR R0, R2 SUB R3, R0, R2 ; Get 0 or -1 in R2 depending on sign of R0 ; EOR with -1 (0xFFFFFFFF) if negative ; and ADD 1 (SUB -1) to get abs value ;SUB always sets flag so go & report division by 0 if necessary BEQ divide_by_zero ;Get abs value of R1 by xoring with 0xFFFFFFFF and adding 1 if negative ASR R0, R1, #31 ; Get 0 or -1 in R3 depending on sign of R1 EOR R1, R0 ; EOR with -1 (0xFFFFFFFF) if negative SUB R1, R0 ; and ADD 1 (SUB -1) to get abs value ;Save signs (0 or -1 in R0 & R2) for later use in determining ; sign of quotient & remainder. PUSH {R0, R2} ;Justification, shift 1 bit at a time until divisor (R0 value) ; is just <= than dividend (R1 value). To do this shift dividend ; right by 1 and stop as soon as shifted value becomes >. LSR R0, R1, #1 MOV R2, R3 B %FT0 just_l LSL R2, #1 0 CMP R2, R0 BLS just_l MOV R0, #0 ; Set accumulator to 0 B %FT0 ; Branch into division loop div_l LSR R2, #1 0 CMP R1, R2 ; Test subtract BCC %FT0 SUB R1, R2 ; If successful do a real subtract 0 ADC R0, R0 ; Shift result and add 1 if subtract succeeded CMP R2, R3 ; Terminate when R2 == R3 (ie we have just BNE div_l ; tested subtracting the 'ones' value). ;Now fix up the signs of the quotient (R0) and remainder (R1) POP {R2, R3} ; Get dividend/divisor signs back EOR R3, R2 ; Result sign EOR R0, R3 ; Negate if result sign = -1 SUB R0, R3 EOR R1, R2 ; Negate remainder if dividend sign = -1 SUB R1, R2 MOV pc, lr 3-98 S3C4510B INSTRUCTION SET ARM Code signed_divide ANDS RSBMI EORS ;ip bit 31 = sign of result ;ip bit 30 = sign of a2 RSBCS ; Effectively zero a4 as top bit will be shifted out later a4, a1, #&80000000 a1, a1, #0 ip, a4, a2, ASR #32 a2, a2, #0 ;Central part is identical code to udiv (without MOV a4, #0 which comes for free as part of signed entry sequence) MOVS a3, a1 BEQ divide_by_zero just_l ; Justification stage shifts 1 bit at a time CMP a3, a2, LSR #1 MOVLS a3, a3, LSL #1 ; NB: LSL #1 is always OK if LS succeeds BLO s_loop div_l CMP a2, a3 ADC a4, a4, a4 SUBCS a2, a2, a3 TEQ a3, a1 MOVNE a3, a3, LSR #1 BNE s_loop2 MOV a1, a4 MOVS ip, ip, ASL #1 RSBCS a1, a1, #0 RSBMI a2, a2, #0 MOV pc, lr 3-99 INSTRUCTION SET S3C4510B DIVISION BY A CONSTANT Division by a constant can often be performed by a short fixed sequence of shifts, adds and subtracts. Here is an example of a divide by 10 routine based on the algorithm in the ARM Cookbook in both Thumb and ARM code. Thumb Code udiv10 MOV LSR SUB LSR ADD LSR ADD LSR ADD LSR ASL ADD ASL SUB CMP BLT ADD SUB 0 MOV ARM Code udiv10 SUB SUB ADD ADD ADD MOV ADD SUBS ADDPL ADDMI MOV a2, a1, #10 a1, a1, a1, lsr #2 a1, a1, a1, lsr #4 a1, a1, a1, lsr #8 a1, a1, a1, lsr #16 a1, a1, lsr #3 a3, a1, a1, asl #2 a2, a2, a3, asl #1 a1, a1, #1 a2, a2, #10 pc, lr ; Take argument in a1 returns quotient in a1, ; remainder in a2 pc, lr a2, a1 a3, a1, #2 a1, a3 a3, a1, #4 a1, a3 a3, a1, #8 a1, a3 a3, a1, #16 a1, a3 a1, #3 a3, a1, #2 a3, a1 a3, #1 a2, a3 a2, #10 %FT0 a1, #1 a2, #10 ; Take argument in a1 returns quotient in a1, ; remainder in a2 3-100 S3C4510B SYSTEM MANAGER 4 OVERVIEW * * * * * SYSTEM MANAGER The S3C4510B microcontroller's System Manager has the following functions. To arbitrate system bus access requests from several master blocks, based on fixed priorities. To provide the required memory control signals for external memory accesses. For example, if a master block such as the DMA controller or the CPU generates an address which corresponds to a DRAM bank, the System Manager's DRAM controller generates the required normal/EDO or SDRAM access signals. The interface signals for normal/EDO or SDRAM can be switched by SYSCFG[31]. To provide the required signals for bus traffic between the S3C4510B and ROM/SRAM and the external I/O banks. To compensate for differences in bus width for data flowing between the external memory bus and the internal data bus. S3C4510B supports both little and big endian for external memory or I/O devices. NOTE By generating an external bus request, an external device can access the S3C4510B's external memory interface pins. In addition, the S3C4510B can access slow external devices using a Wait signal. The Wait signal, which is generated by the external device, extends the duration of the CPU's memory access cycle beyond its programmable value. 4-1 SYSTEM MANAGER S3C4510B SYSTEM MANAGER REGISTERS To control external memory operations, the System Manager uses a dedicated set of special registers (see Table 4-1). By programming the values in the System Manager special registers, you can specify such things as * * * * * Memory type External bus width access cycle Control signal timing (RAS and CAS, for example) Memory bank locations The sizes of memory banks to be used for arbitrary address spacing The System Manager uses special register settings to control the generation and processing of the control signals, addresses, and data that are required by external devices in a standard system configuration. Special registers are also used to control access to ROM/SRAM/Flash banks, up to four DRAM banks and four external I/O banks, and a special register mapping area. The address resolution for each memory bank base pointer is 64K-bytes (16 bits). The base address pointer is 10 bits. This gives a total addressable memory bank space of 16 M words. NOTE When writing a value to a memory bank control register from ROMCON0 to REFEXTCON (locations 0x3014 to 0x303C), as shown in Table 4-1, you must always set the register using a single STM (Store Multiple) instruction. Additionally, the address spaces for successive memory banks must not overlap in the system memory map. 4-2 S3C4510B SYSTEM MANAGER 0x3FFFFFF Reserved Special Register Bank Internal SRAM External I/O Bank 3 External I/O Bank 2 External I/O Bank 1 External I/O Bank 0 DRAM/SDRAM Bank 3 16M words (16 M X 32 bits) SA [25:0] DRAM/SDRAM Bank 2 DRAM/SDRAM Bank 1 DRAM/SDRAM Bank 0 ROM/SRAM/Flash Bank 5 ROM/SRAM/Flash Bank 4 ROM/SRAM/Flash Bank 3 ROM/SRAM/Flash Bank 2 ROM/SRAM/Flash Bank 1 ROM/SRAM/Flash Bank 0 0x0000000 NOTE: 16K words-4M words (32 bits) ADDR [21:0] Continuous 16K word space for 4 external I/O banks 16K words (fixed) 0, 4 or 8K bytes (fixed) 4K words (Fixed for all I/O banks) You can define banks anywhere within the 64-Mbyte address space. Figure 4-1. S3C4510B System Memory Map 4-3 SYSTEM MANAGER S3C4510B SYSTEM MEMORY MAP Following are several important features to note about the S3C4510B system memory map: * The size and location of each memory bank is determined by the register settings for "current bank base pointer" and "current bank end pointer". You can use this base/next bank pointer concept to set up a consecutive memory map. To do this, you set the base pointer of the "next bank" to the same address as the next pointer of the "current bank". Please note that when setting the bank control registers, the address boundaries of consecutive banks must not overlap. This can be applied even if one or more banks are disabled. Four external I/O banks are defined in a continuous address space. A programmer can only set the base pointer for external I/O bank 0. The start address of external I/O bank 1 is then calculated as the external I/O bank 0 start address +16 K. Similarly, the start address for external I/O bank 2 is the external I/O bank 0 start address + 32 K, and the start address for external I/O bank 3 is the external I/O bank 0 start address + 48 K. Therefore, the total consecutive addressable space of the four external banks is defined as the start address of external I/O bank 0 + 64 K bytes. Within the addressable space, the start address of each I/O bank is not fixed. You can use bank control registers to assign a specific bank start address by setting the bank's base pointer. The address resolution is 64 K bytes. The bank's start address is defined as "base pointer << 16" and the bank's end address (except for external I/O banks) is "next pointer << 16 - 1". * * After a power-on or system reset, all bank address pointer registers are initialized to their default values. In this case, all bank pointers except for the next pointer of ROM bank 0 are set to zero. This means that, except for ROM bank 0, all banks are undefined following a system start-up. The reset values for the next pointer and base pointer of ROM bank 0 are 0x200 and 0x000, respectively. This means that a system reset automatically defines ROM bank 0 as a 32-Mbyte space with a start address of zero. This initial definition of ROM bank 0 lets the system power-on or reset operation pass control to the user-supplied boot code that is stored in external ROM. (This code is located at address 0 in the system memory map.) When the boot code (i.e. ROM program) executes, it performs various system initialization tasks and reconfigures the system memory map according to the application's actual external memory and device configuration. The initial system memory map following system start-up is shown in Figure 4-2. 4-4 S3C4510B SYSTEM MANAGER 0X3FFFFFF Special Function Registers 0X3FF8000 Undefined Area 64 M Bytes SA[25:0] 0X2000000 ROM/SRAM/FLASH Bank 0 Area (Non-Accessible) 32 M ROM/SRAM/FLASH Bank 0 Area (Accessible) 0X0000000 4 M Address[21:0] Figure 4-2. Initial System Memory Map (After Reset) Table 4-1. System Manager Registers Registers SYSCFG CLKCON EXTACON0 EXTACON1 EXTDBWTH ROMCON0 ROMCON1 ROMCON2 ROMCON3 ROMCON4 ROMCON5 DRAMCON0 DRAMCON1 DRAMCON2 DRAMCON3 REFEXTCON Offset 0x0000 0x3000 0x3008 0x300C 0x3010 0x3014 0x3018 0x301C 0x3020 0x3024 0x3028 0x302C 0x3030 0x3034 0x3038 0x303C R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description System configuration register Clock control register External I/O timing register 1 External I/O timing register 2 Data bus width of each bank ROM/SRAM/Flash bank 0 control register ROM/SRAM/Flash bank 1 control register ROM/SRAM/Flash bank 2 control register ROM/SRAM/Flash bank 3 control register ROM/SRAM/Flash bank 4 control register ROM/SRAM/Flash bank 5 control register DRAM bank 0 control register DRAM bank 1 control register DRAM bank 2 control register DRAM bank 3 control register Refresh and external I/O control register Reset Value 0x37FFFF91 0x00000000 0x00000000 0x00000000 0x00000000 0x20000060 0x00000060 0x00000060 0x00000060 0x00000060 0x00000060 0x00000000 0x00000000 0x00000000 0x00000000 0x000083FD 4-5 SYSTEM MANAGER S3C4510B EXTERNAL ADDRESS TRANSLATION METHOD DEPENDS ON THE WIDTH OF EXTERNAL MEMORY The S3C4510B address bus is, in some respects, different than the bus used in other standard CPUs. Based on the required data bus width of each memory bank, the internal system address bus is shifted out to an external address bus, ADDR[21:0]. This means that memory control signals such as nRAS[3:0], nCAS[3:0], nECS[3:0], nRCS[5:0], and nWBE[3:0] are generated by the system manager according to a pre-configured external memory scheme (see Table 4-2). This is applied to SDRAM signals as same method. Table 4-2. Address Bus Generation Guidelines Data Bus Width 8-bit 16-bit 32-bit External Address Pins, ADDR[21:0] A21-A0 (internal) A22-A1 (internal) A23-A2 (internal) Accessible Memory Size 4M bytes 4M half-words 4M words Data Bus Width Configuration (8-bit/16-bit/32-bit) 8-bit External Address Pins ADDR [21:0] 22-bit 16-bit 32-bit 22-bit 22-bit 22-bit SA [21:0] SA [22:1] SA [23:2] System Address Bus: SA [25:0] Figure 4-3. External Address Bus Diagram 4-6 S3C4510B SYSTEM MANAGER CONNECTION OF EXTERNAL MEMORY WITH VARIOUS DATA WIDTH As another example, let us see how the S3C4510B maps CPU address spaces to physical addresses in external memory: When the CPU issues an arbitrary address to access an external memory device, the S3C4510B compares the upper 10 bits of the issued address with the address pointers of all memory banks. It does this by consecutively subtracting each address pointer value from the CPU address. There are two reasons why this subtraction method is used: * * To check the polarities of the subtraction result so as to identify which bank corresponds to the address issued by the CPU. To derive the offset address for the corresponding bank. When the bank is identified and the offset has been derived, the corresponding bank selection signal (nRCS[5:0], or nECS[3:0]) is generated, and the derived offset is driven to address external memory through the S3C4510B physical address bus. The S3C4510B can be configured as big-endian or little-endian mode by external little/big selection pin(LITTLE, 49). In Big Endian mode, the most significant byte of the external memory data is stored at the lowest numbered byte and the least significant byte at the highest numbered byte. Eg.) In case of the external word memory system, Byte 0 of the memory is connected to data lines 31 through 24, D[31:24]. In Little Endian mode, vice versa.(See Figure 4-4 External Memory Interface) 4-7 SYSTEM MANAGER S3C4510B ENDIAN MODES S3C4510B supports both little-endian and big-endian for external memory or I/O devices by setting the pin LITTLE (pin 49).The system diagram for S3C4510B is shown in Figure 4-4. S3C4510B External Memory CPU (ARM7TMDI) Memory Controller SA (Addr.) SD (Data) ADDR XDATA 31 0 Bit Number CPU Addr. CPU Data Bus ...X0 ...X4 ...X8 Word Address 31 0 31 0 ...XC CPU Register Special Register Figure 4-4. Data Bus Connection with External Memory Below tables (4-4 through 4-14) are show the program/data path between the CPU register and the external memory using little-/big-endian and word/half-word/byte access. 4-8 S3C4510B SYSTEM MANAGER Table 4-3 and Table 4-4 Using big-endian and word access, Program/Data path between register and external memory WA=Address whose LSB is 0, 4, 8, C X=Don't care CAS3-0/nWBE3-0=0 means active and 1 means inactive Table 4-3. Word Access Store Operation with Big-Endian STORE (CPU Reg External Memory) Ext. Memory Type Bit Num. CPU Register Data CPU Address Bit Num. CPU Data Bus Bit Num. Internal SD Bus External Address CAS3-0/nWBE3-0 Bit Num. XDATA Bit Num. Ext. Memory Data Timing Sequence Word 31 0 Half Word 31 0 Byte 31 0 abcd WA 31 0 31 0 abcd WA 31 0 31 0 31 0 abcd WA 31 0 31 0 abcd 31 0 abcd 31 0 abcd 31 0 abcd 31 0 abcd 31 0 abcd 31 0 abcd 31 0 abcd WA 0000 31 0 abcd WA XX00 15 0 abcd WA + 2 XX00 15 0 abcd WA XXX0 70 abcd WA + 1 XXX0 70 abcd WA + 2 XXX0 70 abcd WA + 3 XXX0 70 abcd 31 0 ab 15 0 cd 15 0 a 70 b 70 c 70 d 70 abcd ab 1st write cd 2nd write a 1st write b 2nd write c 3rd write d 4th write Table 4-4 Word Access Load Operation with Big-Endian LOAD (CPU Reg External Memory) Ext. Memory Type Bit Num. CPU Register Data CPU Address Bit Num. CPU Data Bus Bit Num. Internal SD Bus External Address CAS3-0/nWBE3-0 Bit Num. XDATA Bit Num. Ext. Memory Data Timing Sequence Word 31 0 Half Word 31 0 Byte 31 0 abcd WA 31 0 31 0 abcd WA 31 0 31 0 31 0 abcd WA 31 0 31 0 abcd 31 0 abXX 31 0 abcd 31 0 aXXX 31 0 abXX 31 0 abcX 31 0 abcd 31 0 abcd WA 0000 31 0 abXX WA XX00 15 0 abcd WA + 2 XX00 15 0 aXXX WA XXX0 70 abXX WA + 1 XXX0 70 abcX WA + 2 XXX0 70 abcd WA + 3 XXX0 70 abcd 31 0 ab 15 0 cd 15 0 a 70 b 70 c 70 d 70 abcd ab 1st read cd 2nd read a 1st read b 2nd read c 3rd read d 4th read 4-9 SYSTEM MANAGER S3C4510B Table 4-5 and 4-6 Using big-endian and half-word access, Program/Data path between register and external memory. HA=Address whose LSB is 0, 2, 4, 6, 8, A, C, E HAL=Address whose LSB is 0, 4, 8, C HAU=Address whose LBS is 2, 6, A, E X=Don't care CAS3-0/nWBE3-0=0 means active and 1 means inactive Table 4-5. Half-Word Access Store Operation with Big-Endian STORE (CPU Reg External Memory) Ext. Memory Type Bit Num. CPU Register Data CPU Address Bit Num. CPU Data Bus Bit Num. Internal SD Bus External Address CAS3-0/nWBE3-0 Bit Num. XDATA Bit Num. Ext. Memory Data Timing Sequence HAL 31 0 Word 31 0 Half word 31 0 Byte 31 0 abcd HAU 31 0 abcd HA 31 0 31 0 abcd HA 31 0 cdcd 31 0 cdcd 31 0 cdcd 31 0 cdcd 31 0 cdcd 31 0 cdcd HAL 0011 31 0 cdcd HAL 1100 31 0 cdcd HA XX00 15 0 cdcd HA XXX0 70 cdcd HA + 1 XXX0 70 cdXX 31 16 XXcd 15 0 cd 15 0 c 70 d 70 cd cd cd c 1st write d 2nd write Table 4-6. Half-Word Access Load Operation with Big-Endian LOAD (CPU Reg External Memory) Ext. Memory Type Bit Num. CPU Register Data CPU Address Bit Num. CPU Data Bus Bit Num. Internal SD Bus External Address CAS3-0/nWBE3-0 Bit Num. XDATA Bit Num. Ext. Memory Data Timing Sequence HAL 31 0 Word 15 0 Half word 15 0 Byte 15 0 ab HAU 31 0 ab HA 31 0 31 0 ab HA 31 0 abab 31 0 cdcd 31 0 abab 31 0 aXaX 31 0 abab 31 0 abab HAL XXXX 31 0 cdcd HAL XXXX 31 0 abab HA XXXX 15 0 aXaX HA XXXX 70 abab HA + 1 XXXX 70 abcd 31 0 abcd abcd ab 15 0 a 70 b 70 ab a 1st read b 2nd read 4-10 S3C4510B SYSTEM MANAGER Table 4-7 and 4-8 Using big-endian and byte access, Program/Data path between register and external memory BA=Address whose LSB is 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F BAL=Address whose LSB is 0,2,4,6,8,A,C,E BAU=Address whose LBS is 1,3,5,7,9,B,D,F BA0=Address whose LSB is 0,4,8,C BA1=Address whose LBS is 1,5,9,D BA2=Address whose LSB is 2,6,A,E BA3=Address whose LBS is 3,7,B,F X=Don't care CAS3-0/nWBE3-0=0 means active and 1 means inactive Table 4-7. Byte Access Store Operation with Big-Endian STORE (CPU Reg External Memory) Ext. Memory Type Bit Num. CPU Register Data CPU Address Bit Num. CPU Data Bus Bit Num. Internal SD Bus External Address CAS3-0/nWBE3-0 Bit Num. XDATA Bit Num. Ext. Memory Data Timing Sequence BA0 31 0 Word 31 0 Half Word 31 0 Byte 31 0 abcd BA1 31 0 abcd BA2 31 0 abcd BAU 31 0 BA3 31 0 BAL 31 0 BA 31 0 dddd 31 0 dddd 31 0 dddd 31 0 dddd 31 0 dddd 31 0 dddd 31 0 dddd 31 0 dddd BA0 0111 31 0 dddd BA0 1011 31 0 dddd BA0 1101 31 0 dddd BA0 1110 31 0 dddd BAL XX10 15 0 dddd BAL XX01 15 0 dddd BA XXX0 70 dXXX 31 24 XdXX 23 16 XXdX 15 8 XXXd 70 dX 15 0 Xd 15 0 d 70 d d d d d d d 4-11 SYSTEM MANAGER S3C4510B Table 4-8. Byte Access Load Operation with Big-Endian LOAD (CPU Reg External Memory) Ext. Memory Type Bit Num. CPU Register Data CPU Address Bit Num. CPU Data Bus Bit Num. Internal SD Bus External Address CAS3-0/nWBE3-0 Bit Num. XDATA Bit Num. Ext. Memory Data Timing Sequence BA0 31 0 Word 70 Half Word 70 Byte 70 a BA1 31 0 a BA2 31 0 a BAU 31 0 BA3 31 0 BAL 31 0 BA 31 0 aaaa 31 0 bbbb 31 0 cccc 31 0 dddd 31 0 aaaa 31 0 bbbb 31 0 aaaa 31 0 aaaa BA0 XXXX 31 0 bbbb BA0 XXXX 31 0 cccc BA0 XXXX 31 0 dddd BA0 XXXX 31 0 aaaa BAL XXXX 15 0 bbbb BAL XXXX 15 0 aaaa BA XXXX 70 abcd 31 0 abcd abcd abcd ab 15 0 ab a 70 abcd ab a 4-12 S3C4510B SYSTEM MANAGER Table 4-9 and 4-10 Using little-endian and word access, Program/Data path between register and external memory WA=Address whose LSB is 0,4,8,C X=Don't care CAS3-0/nWBE3-0=0 means active and 1 means inactive Table 4-9. Word Access Store Operation with Little-Endian STORE (CPU Reg External Memory) Ext. Memory Type Bit Num. CPU Register Data CPU Address Bit Num. CPU Data Bus Bit Num. Internal SD Bus External Address Bit Num. XDATA Bit Num. Ext. Memory Data Timing Sequence 31 0 Word 31 0 Half Word 31 0 Byte 31 0 abcd WA 31 0 31 0 abcd WA 31 0 31 0 31 0 abcd WA 31 0 31 0 abcd 31 0 abcd 31 0 abcd 31 0 abcd 31 0 abcd 31 0 abcd 31 0 abcd 31 0 abcd abcd WA 15 0 abcd WA 15 0 abcd WA + 2 70 abcd WA 70 abcd WA + 1 70 abcd WA + 2 70 abcd 31 0 cd 15 0 ab 15 0 d 70 c 70 b 70 a 70 abcd cd 1st write ab 2nd write d 1st write c 2nd write b 3rd write a 4th write Table 4-10. Word Access Load Operation with Little-Endian LOAD (CPU Reg External Memory) Ext. Memory Type Bit Num. CPU Register Data CPU Address Bit Num. CPU Data Bus Bit Num. Internal SD Bus External Address Bit Num. XDATA Bit Num. Ext. Memory Data Timing Sequence Word 31 0 Half Word 31 0 Byte 31 0 abcd WA 31 0 31 0 abcd WA 31 0 31 0 31 0 abcd WA 31 0 31 0 abcd 31 0 XXcd 31 0 abcd 31 0 XXXd 31 0 XXcd 31 0 Xbcd 31 0 abcd 31 0 abcd WA 31 0 XXcd WA 15 0 abcd WA + 2 15 0 XXXd WA 70 XXcd WA + 1 70 Xbcd WA + 2 70 abcd WA + 3 70 abcd 31 0 cd 15 0 ab 15 0 d 70 c 70 b 70 a 70 abcd cd 1st read ab 2nd read d 1st read c 2nd read b 3rd read a 4th read 4-13 SYSTEM MANAGER S3C4510B Table 4-11 and 4-12 Using little-endian and half-word access, Program/Data path between register and external memory HA=Address whose LSB is 0, 2, 4, 6, 8, A, C, E HAL=Address whose LSB is 0, 4, 8, C HAU=Address whose LBS is 2, 6, A, E X=Don't care CAS3-0/nWBE3-0=0 means active and 1 means inactive Table 4-11. Half-Word Access Store Operation with Little-Endian STORE (CPU Reg External Memory) Ext. Memory Type Bit Num. CPU Register Data CPU Address Bit Num. CPU Data Bus Bit Num. Internal SD Bus External Address CAS3-0/nWBE3-0 Bit Num. XDATA Bit Num. Ext. Memory Data Timing Sequence HAL 31 0 Word 31 0 Half word 31 0 Byte 31 abcd HAU 31 0 abcd HA 31 0 31 0 d0 abc HA 31 0 cdcd 31 0 cdcd 31 0 cdcd 31 0 cdcd 31 0 cdcd 31 0 cdcd HAL 1100 31 0 cdcd HAL 0011 31 0 cdcd HA XX00 15 0 cdcd HA XXX0 70 cdcd HA+1 XXX0 70 cdcd 15 0 cdcd 31 16 cd 15 0 d 70 c 70 cd cd cd d 1st write c 2nd write Table 4-12. Half-Word Access Load Operation with Little-Endian LOAD (CPU Reg External Memory) Ext. Memory Type Bit Num. CPU Register Data CPU Address Bit Num. CPU Data Bus Bit Num. Internal SD Bus External Address CAS3-0/nWBE3-0 Bit Num. XDATA Bit Num. Ext. Memory Data Timing Sequence HAL 31 0 Word 15 0 Half word 15 0 Byte 15 0 cd HAU 31 0 ab HA 31 0 31 0 ba HA 31 0 cdcd 31 0 abab 31 0 abab 31 0 XaXa 31 0 baba 31 0 cdcd HAL XXXX 31 0 abab HAL XXXX 31 0 abab HA XXXX 15 0 XaXa HA XXXX 70 baba HA+1 XXXX 70 abcd 31 0 abcd ab 15 0 a 70 b 70 abcd ab a 1st read b 2nd read 4-14 S3C4510B SYSTEM MANAGER Table 4-13 and 4-14 Using little-endian and byte access, Program/Data path between register and external memory BA=Address whose LSB is 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F BAL=Address whose LSB is 0,2,4,6,8,A,C,E BAU=Address whose LBS is 1,3,5,7,9,B,D,F BA0=Address whose LSB is 0,4,8,C BA1=Address whose LBS is 1,5,9,D BA2=Address whose LSB is 2,6,A,E BA3=Address whose LBS is 3,7,B,F X=Don't care CAS3-0/nWBE3-0=0 means active and 1 means inactive Table 4-13. Byte Access Store Operation with Little-Endian STORE (CPU Reg External Memory) Ext. Memory Type Bit Num. CPU Register Data CPU Address Bit Num. CPU Data Bus Bit Num. Internal SD Bus External Address CAS3-0/nWBE3-0 Bit Num. XDATA Bit Num. Ext. Memory Data Timing Sequence BA0 31 0 Word 31 0 Half Word 31 0 Byte 31 0 abcd BA1 31 0 abcd BA2 31 0 abcd BAU 31 0 BA3 31 0 BAL 31 0 BA 31 0 dddd 31 0 dddd 31 0 dddd 31 0 dddd 31 0 dddd 31 0 dddd 31 0 dddd 31 0 dddd BA0 1110 31 0 dddd BA0 1101 31 0 dddd BA0 1011 31 0 dddd BA0 0111 31 0 dddd BAL XX10 15 0 dddd BAL XX01 15 0 dddd BA XXX0 70 XXXd 70 XXdX 15 8 XdXX 23 16 dXXX 31 24 Xd 70 dX 15 8 d 70 d d d d d d d 4-15 SYSTEM MANAGER S3C4510B Table 4-14. Byte Access Load Operation with Little-Endian LOAD (CPU Reg External Memory) Ext. Memory Type Bit Num. CPU Register Data CPU Address Bit Num. CPU Data Bus Bit Num. Internal SD Bus External Address CAS3-0/nWBE3-0 Bit Num. XDATA Bit Num. Ext. Memory Data Timing Sequence Word 70 70 70 d BA0 31 0 31 0 c BA1 31 0 31 0 31 0 a BA3 31 0 31 0 dddd 31 0 cccc 31 0 bbbb 31 0 aaaa 31 0 bbbb 31 0 aaaa 31 0 aaaa 31 0 dddd BA0 XXXX 31 0 cccc BA0 XXXX 31 0 bbbb BA0 XXXX 31 0 aaaa BA0 XXXX 31 0 bbbb BAL XXXX 15 0 aaaa BAL XXXX 15 0 aaaa BA XXXX 70 abcd abcd 31 0 abcd abcd abcd ab 15 0 ab ab a 70 a 4-16 S3C4510B SYSTEM MANAGER BUS ARBITRATION In the S3C4510B microcontroller, the term "system bus" refers to the separate system address and data buses inside the chip. The S3C4510B's internal function blocks, or external devices, can request mastership of the system bus and then hold the system bus in order to perform data transfers. Because the design of S3C4510B bus allows only one bus master at a time, a bus controller is required to arbitrate when two or more internal units or external devices simultaneously request bus mastership. When bus mastership is granted to an internal function block or an external device, other pending requests are not acknowledged until the previous bus master has released the bus. To facilitate bus arbitration, priorities are assigned to each internal S3C4510B function block. The bus controller arbitrattion requests for the bus mastership according to these fixed priorities. In the event of contention, mastership is granted to the function block with the highest assigned priority. These priorities are listed in Table 4-15. NOTE An external bus master can also be granted bus mastership and hold the S3C4510B system bus. In Table 4-3, you will note that all external devices are assigned the identical priority. Therefore, in systems made up of several external devices which can become the bus master, external circuitry must be implemented to assign additional bus arbitration priorities to all potential external bus masters. Table 4-15. Bus Priorities for Arbitration Function Block External bus master DRAM memory refresh controller General DMA 1 (GDMA 1) General DMA 0 (GDMA 0) High level data link controller B (HDLC B) High level data link controller A (HDLC A) MAC buffered DMA (BDMA) Writer buffer Bus router A-2 A-3 A-4 A-5 A-6 A-7 (Lowest priority in Group A) B-1 (Highest priority in Group B) B-2 (Lowest priority in Group B) Bus Priority (Group) A-1 (Highest priority in Group A) NOTE: Internal function blocks are divided into two groups, Group A and Group B. Within each group, the bus arbitration priorities are fixed according to the assigned level. The relative priority of Group A and Group B is determined more or less in an alternating manner. 4-17 SYSTEM MANAGER S3C4510B EXTERNAL BUS MASTERSHIP The S3C4510B can receive and acknowledge bus request signals (ExtMREQs) that are generated by an external bus master. When the CPU asserts an external bus acknowledge signal (ExtMACK), mastership is granted to the external bus master, assuming the external bus request is still active. When the external bus acknowledge signal is active, the S3C4510B's memory interface signals go to highimpedance state so that the external bus master can drive the required external memory interface signals. The S3C4510B does not perform DRAM refreshes when it is not the bus master. When an external bus master is in control of the external bus, and if it retains control for a long period of time, it must assume the responsibility of performing the necessary DRAM refresh operations. SCLK MCLKO tEMZ Address, Data, nOE, nWBE, nDWE, nRCS , nCAS, nRAS tEMRs Data Data tEMRh ExtMREQ tEMAr tEMAf ExtMACK Figure 4-5. External Bus Request Timing NOTE: When External Bus Master requests the ExtMREQ during the Sync DRAM writing cycles, the ExtMACK can be generated with the wrong writing control signals of Sync DRAM. Just floating the Sync DRAM control signals at the time ExtMACK , it can cause the feasible active writing on the Sync DRAM. As the result, the wrong data can be written into unexpected address on Sync DRAM. If this address is in the range of stack or code area, the crash will be happen sooner or later. The other memory interfaces doesn't have this problem, which is asynchronous with MCLKO, that is why Sync DRAM write cycle only. You can avoid this by disabling the SDCS (Sync DRAM Chip Select HIGH) as soon as receiving the ExtMACK and driving the Address and Data after one or two MCLKO cycles. 4-18 S3C4510B SYSTEM MANAGER CONTROL REGISTERS SYSTEM CONFIGURATION REGISTER (SYSCFG) The System Manager has one system configuration register, SYSCFG. The SYSCFG register determines the start address of the System Manager's special registers and the start address of internal SRAM. (The total special register space in the system memory map is fixed at 64 K bytes.) You also use SYSCFG settings to control write buffer enable, cache enable, and stall enable operations. All DRAM banks can be configured to SDRAM banks by set the Synchronous DRAM mode (SYSCFG[31]). NOTE If you write a "10" into the cache mode field, SYSCFG[5:4], the cache enable bit is cleared automatically (see Figure 4-6). Table 4-16. SYSCFG Register Registers SYSCFG Offset Address 0x0000 R/W R/W Description System configuration register Reset Value 0x37FFFF91 4-19 SYSTEM MANAGER S3C4510B 31 30 S PD_ID D M 26 25 Special Register Bank Base Pointer 16 15 Internal SRAM Base Pointer 6543210 CM 0WCS EEE [0] Stall enable (SE) Must be set to zero. [1] Cache enable (CE) When set to '1', cache operations are enabled. [2] Write buffer enable (WE) When set to "1", write buffer operations are enabled. [5:4] Cache mode (CM) This 2-bit value determines how internal memory is to be devided into cache and SRAM. 00 = 4-Kbyte SRAM, 4Kbyte cache 01 = 0-Kbyte SRAM, 8Kbyte cache 10 = 8-Kbyte SRAM, 0Kbyte cache NOTE: When you write 10 to this field, the cache enable bit is cleared automatically. [15:6] Internal SRAM base pointer This 10-bit address becomes the upper address of SRAM. A25 through A16, the remaining SRAM address, and A15 through A0, are filled with zeros. [25:16] Special register bank base pointer The resolution of this value is 64K. Therefore, to place the start address at 1800000H (24M), use this formula: Setting value = (1800000H/64K) << 16. [30:26] Product Identifier (PD_ID) 00001 = S3C4510X (KS32C50100) 11001 = S3C4510B [31] Sync. DRAM Mode 0 = Normal/EDO DRAM interface for 4 DRAM banks 1 = Sync. DRAM interface for 4 DRAM banks. Figure 4-6. System Configuration Register (SYSCFG) 4-20 S3C4510B SYSTEM MANAGER Start Address Setting The start address of the System Manager special register area is initialized to 3FFFF91H. (You can also set the start address to an arbitrary value by writing the address, 3FF0000H.) When you have set the start address of the special register area, the register addresses are automatically defined as the start address plus the register's offset. Assume for example, that a reset initialize the start address to 3FF0000H. The offset address of the ROMCON register is 3014H. Therefore, the physical address for ROMCON is 3FF0000H + 3014h = 3FF3014H. If you then modified the start address of the special register area to 3000000H, the new address for the ROMCON register would be 3003014H. Cache Disable/Enable To enable or disable the cache, you set the cache enable (CE) bit of the SYSCFG register to "1" or "0", respectively Because cache memory does not have an auto-flush feature, you must be careful to verify the coherency of data whenever you re-enable the cache. You must also carefully check any changes that the DMA controller may make to data stored in memory. (Usually, the memory area that is allocated to DMA access operations must be non-cachable.) The internal 8-Kbyte SRAM can be used as a cache area. To configure this area, you use the cache mode bits, SYSCFG[5:4]. If you do not need to use the entire 8-Kbyte area as cache, you can use the remaining area as internal SRAM. This area is accessed using the address of the base pointer in the internal SRAM field. Write Buffer Disable/Enable The S3C4510B has four programmable write buffer registers that are used to improve the speed of memory write operations. When you enable a write buffer, the CPU writes data into the write buffer, instead of an external memory location. This saves the cycle that would normally be required to complete the external memory write operation. The four write buffers also enhance the performance of the ARM7TDMI core's store operations. To maintain data coherency between the cache and external memory, the S3C4510B uses a write-through policy. An internal 4-level write buffer compensates for performance degradation caused by write-throughs. (For more information, read Chapter 5.) 4-21 SYSTEM MANAGER S3C4510B SYSTEM CLOCK AND MUX BUS CONTROL REGISTER CLOCK CONTROL REGISTER (CLKCON) There is a clock control register in the System Manager. This control register is used to divide the internal system clock, so the slower clock than the system clock can be made by clock dividing value. In this register, ROM bank 5 address/data MUX. enable control function is included. Table 4-17. CLKCON Register Registers CLKCON Offset Address 0x3000 R/W R/W Description Clock control register Reset Value 0x00000000 Table 4-18. CLKCON Register Description Bit Number [15:0] Bit Name Clock dividing value Description S3C4510B System Clock source. If CLKSEL is Low, PLL output clock is used as the S3C4510B internal system clock. If CLKSEL is High, XCLK is used as the S3C4510B internal system clock. The internal system clock is divided by this value. The clock divided is used to drive the CPU and system peripherals. Only one bit can be set in CLKCON[15:0], that is, the clock deviding value is defined as 1, 2, 4, 8, 16,... If all bits are zero, a nondivided clock is used. [16] [17] ROM bank 5 wait enable Wait cycle will check the next cycle after a chip selection signal is activated. ROM bank 5 address/data MUX. enable MUX Bus address cycle Using multiplex bus at ROM bank 5, this bit must be set to 1. [19:18] When address phase of multiplexed bus is not enough long for external device to receive, address phase can be extended by setting this bit.(You can see tAC in timing diagram.) 00 = 1 MCLK 01 = 2 MCLK 10 = 3 MCLK [31] Test bit This bit is for factory use only. During the normal operation, it must always be 0. 4-22 S3C4510B SYSTEM MANAGER 31 CLKCON 20 19 18 17 16 15 Clock Divided Value 0 [15:0] Clock diving value If all bits are 0, non-divided clock is used. Only one bit can be set in CLKCON[15:0]. That is, the clock diving value is defined as 1,2,4,8,16,... Internal system clock, fMCLK = fICLK/(CLKCON+1) [16] ROM bank 5 wait enable 0 = Disable ROM bank 5 wait. 1 = Enable ROM bank 5 wait. [17] ROM bank 5 address/data bus MUX enable 0 = Normal operation 1 = Enable bus multiplexing [19:18] MUX bus Address (tAC) 00 = 1 MCLK 01 = 2 MCLK 10 = 3 MCLK [31] Test bit This bit should be always 0. Figure 4-7. Clock Control Register (CLKCON) 4-23 SYSTEM MANAGER S3C4510B SYSTEM CLOCK The external clock input, XCLK, can be used to the internal system clock by assign VDD to CLKSEL pin. Using PLL for the internal system clock, VSS has to be assigned to CLKSEL pin. In this case, the internal system clock is XCLK x MF. To get 50MHz of system clock, a 10 MHz external clock must be used. CLKSEL pdown (1) MF (2) TMOD XCLK PLL 0: MF = 5.0 1: MF = 6.6 0 ICLK MUX 1 MCLKO CLKOEN NOTES: 1. If CLKSEL is 1, the PLL block became to the state of power down. 2. MF means Multiplication Factor. Clock Divider for Low Power Control (CLKCON) Internal System Clock SCLK (MCLK) Figure 4-8. System Clock Circuit For the purpose of power save, Clock Control Register (CLKCON) can be programed at low frequency. When the internal system clock is divided by CLKCON, it's duty-cycle is changed. If CLKCON is programed to zero, the internal system clock remains the same as the internal clock, ICLK. In other cases, the duty cycle of internal system clock is no longer 50%. Figure 4-9 shows the internal system clock, SCLK(MCLK) waveform according to the clock dividing value. ICLK SCLK(MCLK) CLKCON = 0 SCLK(MCLK) CLKCON = 1 SCLK(MCLK) CLKCON = 2 Figure 4-9. Divided System Clocks Timing Diagram 4-24 S3C4510B SYSTEM MANAGER EXTERNAL I/O ACCESS CONTROL REGISTERS (EXTACON0/1) The System Manager has four external I/O access control registers. These registers correspond to the up to four external I/O banks that are supported by S3C4510B. Table 4-19 describes the two registers that are used to control the timing of external I/O bank accesses. You can control external I/O access cycles using either a specified value or an external wait signal, nEWAIT. To obtain access cycles that are longer than those possible with a specified value, you can delay the active time of nOE or nWBE by tCOS value setting. After nOE or nWBE active, nEWAIT should be active previously at the first MCLK(SCLK) falling edge. In case of ROM bank 5, nRCS and nOE/nWBE signals are activated simultaneously, that is, there is no control parameter as like tCOS. As a result, nEWAIT should be valid previously at the second MCLK(SCLK) falling edge after nRCS active for the ROM bank 5. EXTACON0 is used to set the access timings for external I/O banks 0 and 1. EXTACON1 is used to set the external access timings for I/O banks 2 and 3. NOTE The base pointer for external I/O bank 0 is set in the REFEXTCON register(REFEXTCON register is in DRAM control registers part). Table 4-19. External I/O Access Control Register Description Registers EXTACON0 EXTACON1 Offset Address 0x3008 0x300C R/W R/W R/W Description External I/O access timing register 0 External I/O access timing register 1 Reset Value 0x00000000 0x00000000 4-25 SYSTEM MANAGER S3C4510B 31 30 29 28 27 EXTACON0 EXTACON1 0000 0000 25 24 22 21 19 18 16 15 14 13 12 11 0000 0000 tACC0 tACC2 98 65 tACS0 tACS2 32 0 tACC1 tACC3 tCOH1 tCOH3 tACS1 tACS3 tCOS1 tCOS3 tCOH0 tCOH2 tCOS0 tCOS2 [2:0] Chip selection set-up time on nOE (tCOS0, tCOS2) [18:16] tCOS1, tCOS3 000 = 0 cycle 001 = 1 cycle 010 = 2 cycles 011 = 3 cycles 100 = 4 cycles 101 = 5 cycles 110 = 6 cycles 111 = 7 cycles [5:3] Address set-up time before nECS (tACS0, tACS2) [21:19] tACS1, tACS3 000 = 0 cycle 001 = 1 cycle 010 = 2 cycles 011 = 3 cycles 100 = 4 cycles 101 = 5 cycle 110 = 6 cycle 111 = 7 cycles [8:6] Chip selection hold time on nOE (tCOH0, tCOH2) [24:22] tCOH1, tCOH3 000 = 0 cycle 001 = 1 cycle 010 = 2 cycles 011 = 3 cycles 100 = 4 cycles 101 = 5 cycles 110 = 6 cycles 111 = 7 cycles [11:9] Access cycles (nOE low time) (tACC0, tACC2) [27:25] tACC1, tACC3 000 = 0 cycle 001 = 1 cycle 010 = 2 cycles 011 = 3 cycles 100 = 4 cycles 101 = 5 cycles 110 = 6 cycles 111 = 7 cycles Figure 4-10. External I/O Access Control Registers (EXTACON0, EXTACON1) 4-26 S3C4510B SYSTEM MANAGER SCLK MCLKO tNECS nECS tNROE nOE tADDRh Address Addr tACC tNECS tNROE Data Data nEWAIT Data Fetch tACS = 0 (0 cycle) tCOS = 0 (0 cycle) tACC = 4 (5 cycles) tCOH = 0 (0 cycle) Figure 4-11. External I/O Read Timing 1 When nEWAIT is asserted for external I/O banks, the tCOS and tCOH should not be zero. When ROM banks, except ROM bank 5, are selected, the nEWAIT can not be asserted. Even if you does not use nEWAIT, nEWAIT pin should be connected pull-up for safe operation. 4-27 SYSTEM MANAGER S3C4510B SCLK MCLKO tNECS nECS tACS tNROE nOE tADDRh Address Addr tACC tNECS tCOH tNROE Data Data nEWAIT Data Fetch tACS = 1 (1 cycle) tCOS = 0 (0 cycle) tACC = 3 (4 cycles) tCOH = 1 (1 cycle) Figure 4-12. External I/O Read Timing 2 4-28 S3C4510B SYSTEM MANAGER SCLK MCLKO tNECS tACC tCOH tNECS nECS tACS tNROE nOE tADDRd Address Addr tCOS tNROE Data tWs nEWAIT tWh Data Data Read Point (tCOH = 1) tACS = 1 (1 cycle) tCOS = 1 (1 cycle) tACC = 1 (2 cycles) tCOH = 1 (1 cycle) Figure 4-13. External I/O Read Timing with nEWAIT The nEWAIT should be valid at the first SCLK falling edge after nOE active. In this case, tCOS and tCOH need to have a minimum of one cycle, and by the setting of tCOS value slower device can be supported. Naimly, nEWAIT valid time depends on tCOS value. Deassertion timing depends on the applied Ext. I/O devices. When the nEWAIT de-assert, it must be synchronized with MCLKO rising edge.(Because we can not detect SCLK falling edge.) If not, memory state machine can go into the wrong state. 4-29 SYSTEM MANAGER S3C4510B SCLK MCLKO tNECS tACC tNECS nECS tNWBE tNWBE nWBE tADDRd tADDRh Address tWDd Addr tWDh Data Data nEWAIT tACS = 0 (0 cycle) tCOS = 0 (0 cycle) tACC = 4 (5 cycles) tCOH = 0 (0 cycle) Figure 4-14. External I/O Write Timing 1 4-30 S3C4510B SYSTEM MANAGER SCLK MCLKO tNECS tACC tCOH tNECS nECS tACS tNWBE tNWBE nWBE tADDRd Address tWDd Addr tWDh Data Data nEWAIT tACS = 1 (1 cycle) tCOS = 0 (0 cycle) tACC = 3 (4 cycles) tCOH = 1 (1 cycle) Figure 4-15. External I/O Write Timing 2 4-31 SYSTEM MANAGER S3C4510B SCLK MCLKO tNECS tACC tCOH tNECS nECS tACS tNWBE tNWBE nWBE tADDRd tCOS Address tWDd Addr tWDh Data tWs nEWAIT tWh Data tACS = 1 (1 cycle) tCOS = 1 (1 cycle) tACC = 1 (2 cycles) tCOH = 1 (1 cycle) Figure 4-16. External I/O Write Timing with nEWAIT 4-32 S3C4510B SYSTEM MANAGER DATA BUS WIDTH REGISTER (EXTDBWTH) The S3C4510B has interfaces for 8/16/32-bit external ROMs, SRAMs, flash memories, DRAMs, SDRAMs, and external I/O ports. Using data bus width register, you can set the data bus width that is required for specific external memory and external I/O banks. NOTE In Figure 4-20, the term "Disable" means that the S3C4510B does not generate the access signal for the corresponding external I/O bank. Table 4-20. EXTDBWTH Register Description Registers EXTDBWTH Offset 0x3010 R/W R/W Description Data bus width of each bank Reset Value 0x00000000 4-33 SYSTEM MANAGER S3C4510B 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTDBWTH 0 0 0 0 DSX3 DSX2 DSX1 DSX0 DSD3 DSD2 DSD1 DSD0 DSR5 DSR4 DSR3 DSR2 DSR1 DSR0 [1:0] Data bus width for ROM/SRAM/FLASH bank 0 (DSR0) DSR0 is read-only data at the B0SIZE [1:0] pins. DSR0 is used as read-only because ROM/SRAM/FLASH bank 0 is used to boot the ROM while the data bus width for ROM/SRAM/FLASH bank 0 is set using B0SIZE [1:0]. 00 = Not permitted 01 = Byte (8 bits) 10 = Half-word (16 bits) 11 = Word (32 bits) [3:2] Data bus width for ROM/SRAM/FLASH bank 1 (DSR1) [5:4] DSR2, [7:6] DSR3, [9:8] DSR4, [11:10] DSR5 00 = Disable 01 = Byte (8 bits) 10 = Half- word (16 bits) 11 = Word (32 bits) [13:12] Data bus width for DRAM bank 0 (DSD0) [15:14] DSD1, [17:16] DSD2, [19:18] DSD3 00 = Disable 01 = Byte (8 bits) 10 = Half-word (16 bits) 11 = Word (32 bits) [21:20] Data bus width for external I/O bank 0 (DSX0) [23:22] DSX1, [25:24] DSX2, [27:26] DSX3 00 = Dissable 01 = Byte (8 bits) 10 = Half-word (16 bits) 11 = Word (32 bits) NOTE: When you select "Disable", the assigned external I/O bank access signal is not generated. Figure 4-17. Data Bus Width Register (EXTDBWTH) 4-34 S3C4510B SYSTEM MANAGER ROM/SRAM/FLASH CONTROL REGISTERS (ROMCON) The System Manager has six control registers for ROM, SRAM, and flash memory (see Table 4-21). These registers correspond to the up to six ROM/SRAM/Flash banks that are supported by S3C4510B. For ROM/SRAM/Flash bank 0, the external data bus width is determined by the signal at the B0SIZE[1:0] pins: When B0SIZE[1:0] = "01", the external bus width for ROM/SRAM/Flash bank 0 is 8 bits. When B0SIZE[1:0] = "10", the external bus width for ROM/SRAM/Flash bank 0 is 16 bits. When B0SIZE[1:0] = "11", the external bus width for ROM/SRAM/Flash bank 0 is 32 bits. You can determine the start address of a special register's bank by the value of the corresponding "special register bank base pointer". The control register's physical address is always the sum of the register's bank base pointer plus the register's offset address.(For example, base pointer is 0x3ff0000 and ROMCON0's offset is 0x3014. Then ROMCON0's physical address becomes 0x3ff3014.) NOTE If you attach SRAM to a ROM/SRAM/Flash bank, you must set the page mode configuration bits, ROMCONn[1:0], in the corresponding control register to "00" (normal ROM). Table 4-21. ROM/SRAM/Flash Control Register Description Registers ROMCON0 ROMCON1 ROMCON2 ROMCON3 ROMCON4 ROMCON5 Offset 0x3014 0x3018 0x301C 0x3020 0x3024 0x3028 R/W R/W R/W R/W R/W R/W R/W Description ROM/SRAM/Flash bank 0 control register ROM/SRAM/Flash bank 1 control register ROM/SRAM/Flash bank 2 control register ROM/SRAM/Flash bank 3 control register ROM/SRAM/Flash bank 4 control register ROM/SRAM/Flash bank 5 control register Reset Value 0x20000060 0x00000060 0x00000060 0x00000060 0x00000060 0x00000060 4-35 SYSTEM MANAGER S3C4510B 31 30 29 00 ROM/SRAM/Flash Bank # Next Pointer 20 19 ROM/SRAM/Flash Bank # Base Pointer 10 9 8 7 6 000 tACC 43210 tPA PMC [1:0] Page mode configuration (PMC) 00 = Normal ROM 10 = 8-word page 01 = 4-word page 11 = 16-word page [3:2] Page address access time (tPA) 00 = 5 cycles 10 = 3 cycles 01 = 2 cycles 11 = 4 cycles [6:4] Programmable access cycle (tACC) 000 = Disable bank 010 = 3 cycle 110 = 7 cycle 001 = 2 cycles 011 = 4 cycles 111 = Reserved [19:10] ROM/SRAM/Flash bank # base pointer This value is the start address of the ROM/SRAM/Flash bank #. The start address is calculated as ROM/SRAM/FLASH bank # base pointer << 16. [29:20] ROM/SRAM/FLASH bank # next pointer This value is the current bank end address << 16 + 1. Figure 4-18. ROM/SRAM/FLASH Control Registers (ROMCON0-ROMCON5) 4-36 S3C4510B SYSTEM MANAGER SCLK MCLKO tNRCS tNRCS nRCS tNROE tACC nOE tADDRd tADDRh Addr Address tRDs tRDh Data Data Data Fetch Point tACC = 4 (5 cycles) Figure 4-19. ROM/SRAM/Flash Read Access Timing 4-37 SYSTEM MANAGER S3C4510B SCLK MCLKO tNRCS tNRCS tACC tNROE tPA tPA tPA tNROE nRCS nOE tADDRd Address Addr tRDh Addr + 1 tRDh Data Addr + 2 tRDh Data Addr + 3 tRDh Data Data Data Data Fetch Data Fetch Data Fetch Data Fetch tACC = 2 (3 cycles) tPA = 1 (2 cycles) PMC = 1 (4 word page) Figure 4-20. ROM/SRAM/Flash Page Read Access Timing 4-38 S3C4510B SYSTEM MANAGER SCLK MCLKO tNRCS tNRCS tACC tNWBE tNWBE nRCS nWBE tADDRd Address tWDd Addr Data Data tACC = 4 (5 cycles) Figure 4-21. ROM/SRAM/Flash Write Access Timing 4-39 SYSTEM MANAGER S3C4510B SCLK MCLKO tNRCS tNRCS tACC tNWBE tNWBE tPA nRCS nWBE tADDRd tADDRd Addr tADDRh Addr + 1 Address Data Data Data tACC = 2 (3 cycles) tPA = 1 (2 cycles) PMC = 1 (4 word page) Figure 4-22. ROM/SRAM/Flash Page Write Access Timing 4-40 S3C4510B SYSTEM MANAGER SCLK MCLKO tNRCS NOTE 1 tNRCS tACC tPA (or tACC) tNWBE tNWBE nRCS nWBE tNROE tNROE nOE tADDRd tADDRd Addr Addr + 1 tADDRh Address Data Data Data Data Fetch tACC = 2 (3 cycles) tPA = 1 (2 cycles) PMC = 1(4 word page) NOTE: Page hit case: tPA Page miss case: tACC Figure 4-23. ROM/SRAM/Flash Read and Write Access Timing 4-41 SYSTEM MANAGER S3C4510B SCLK MCLKO tNRCS tACC tPA tNRCS nRCS tNWBE tNWBE nWBE tNROE tNROE nOE tADDRd tADDRd tADDRh Address Addr Addr + 1 Data Data Data Figure 4-24. ROM/SRAM/Flash Write and Read Access Timing 4-42 S3C4510B SYSTEM MANAGER ROM BANK 5 ADDRESS/DATA MULTIPLEXED BUS Overview The S3C4510B has separate address and data bus. S3C4510B supports multiplexed address/data bus for low cost chips which require multiplexed bus. To support this feature, the S3C4510B has one special bank (ROM bank 5) which can support address/data multiplexed bus and 4-data burst access by GDMA. For this feature, you should set the MUX enable bit and wait enable bit of CLKCON register. You can also use ROM bank 5 as normal ROM bank by clearing MUX enable bit of CLKCON register. When you set the wait enable bit in the CLKCON register, wait cycle can be added by nEWAIT pin for ROM bank 5. Other ROM banks except ROM bank 5 has no effects. nEWAIT pin also can be used to add wait cycle for EXT I/O bank regardless of the wait enable bit. Random Access by CPU At the first cycle of ROM bank 5, address comes out from data bus. Therefore, any device which is connected to the ROM bank 5 can get address. The rest cycle is for data. As the S3C4510B has not a dedicated address strobe signal for address phase in the data burst, you should generate address strobe signal in the application device. Four-data Burst Access by GDMA When you set FB (4-data burst enable) bit in the GDMACON register, the GDMA requests 4-data burst access. When you access ROM bank 5 by 4-data burst mode, the multiplexed ROM bank 5 bus has only one address phase. Therefore, you should internally calculate the address at the data phase. To notify the 4-data burst mode to ROM bank 5 device, the ADDR[21] remains "1" during address phase. 4-43 SYSTEM MANAGER S3C4510B SCLK MCLKO tNRCS tNRCS tACC tNROE tNROE nRCS[5] nOE nWBE tADDRd Address tAC Addr Data Addr Address Cycle Data Cycle Data nEWAIT 1 wait Data Read Point tAC = 0 (1 cycle) tACC = 1 (2 cycles) MUX BUS Enable Figure 4-25. ROM/SRAM/FLASH Bank 5 random Read with nEWAIT Access Timing 4-44 S3C4510B SYSTEM MANAGER SCLK MCLKO tNRCS tNRCS nRCS[5] tNROE tACC tACC tACC tACC tNROE nOE nWBE tADDRd Address tAC Addr 0 Addr 1 Addr 2 Addr 3 Data Addr Address Cycle Data 0 Data Cycle Data 1 Data 2 Data 3 nEWAIT tAC = 0 (1 cycle) tACC = 1 (2 cycles) MUX BUS Enable Figure 4-26. ROM/SRAM/FLASH Bank 5 four word burst Read Access Timing When GDMA Request 4-45 SYSTEM MANAGER S3C4510B SCLK MCLKO tNRCS tNRCS tACC nRCS[5] nOE tNWBE tNWBE nWBE tADDRd Address tAC Addr Data Addr Data Address Cycle Data Cycle nEWAIT 1 Wait tAC = 0 (1 cycle) tACC = 1 (2 cycles) MUX BUS Enable Figure 4-27. ROM/SRAM/FLASH Bank 5 Write Timing with nEWAIT Access Timing 4-46 S3C4510B SYSTEM MANAGER SCLK MCLKO tNRCS tNRCS tACC tACC tACC tACC nRCS[5] nOE tNWBE tNWBE nWBE tADDRd Address tAC Addr 0 Addr 1 Addr 2 Addr 3 Data Addr Address Cycle Data 0 Data 1 Data 2 Data 3 Data Cycle nEWAIT tAC = 0 (1 cycle) tACC = 1 (2 cycles) MUX BUS Enable Figure 4-28. ROM/SRAM/FLASH Bank5 Four-data Burst Mode Write Timing When GDMA Requests 4-47 SYSTEM MANAGER S3C4510B DRAM CONTROL REGISTERS The System Manager has four DRAM control registers, DRAMCON0-DRAMCON3. These registers correspond to the up to four DRAM banks that are supported by S3C4510B. A fifth register, REFEXTCON, is used to set the base pointer for external I/O bank 0. S3C4510B supports EDO, normal, Synchronous DRAM(SDRAM). SDRAM mode can be selected by setting SYSCFG[31]. If this bit is set to '1', all DRAM banks are selected SDRAM. Otherwise, EDO/FP DRAM banks are selected. Table 4-22. DRAM and External I/O Control Register Description Registers DRAMCON0 DRAMCON1 DRAMCON2 DRAMCON3 REFEXTCON Offset 0x302C 0x3030 0x3034 0x3038 0x303C R/W R/W R/W R/W R/W R/W Description DRAM bank 0 control register DRAM bank 1 control register DRAM bank 2 control register DRAM bank 3 control register Refresh and external I/O control register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 4-48 S3C4510B SYSTEM MANAGER 31 30 29 DRAMCON# CAN 20 19 10 9 8 7 6 43210 E tCS D O DRAM Bank # Next Pointer DRAM Bank # Base Pointer t t tRP R Reserve C P C [0] EDO mode (EDO) 0 = Normal DRAM (Fast page mode DRAM) 1 = EDO DRAM [2:1] CAS strobe time (tCS) (note) 00 = 1 cycle 10 = 3 cycles 01 = 2 cycles 11 = 4 cycles [3:3] CAS pre-charge time (tCP) 0 = 1 cycle 1 = 2 cycles [6:4] Reserved These bits default value is 000. But, you must set to 001. [7] RAS to CAS delay (tRC or tRCD) 0 = 1 cycle 1 = 2 cycles [9:8] RAS pre-charge time (tRP) 00 = 1 cycle 10 = 3 cycles 01 = 2 cycles 11 = 4 cycles [19:10] DRAM bank # base pointer This value indicates the start address of DRAM bank #. The start address is calculated as RAM bank # base pointer << 16 [29:20] DRAM bank # next pointer This value is the current bank end address << 16 + 1 [31:30] Number of column address bits in DRAM bank # (CAN) 00 = 8 bits 10 = 10 bits NOTE: 01 = 9 bits 11 = 11 bits In SDRAM mode, this bit affect SDRAM cycle. tCS value[1]: 0 = 1 cycle 1 = 2 cycle Figure 4-29. DRAM Control Registers (DRAMCON-DRAMCON3) 4-49 SYSTEM MANAGER S3C4510B SCLK MCLKO tNRASf nRAS tRP tNCASf tRC tNROE tNROE tCS tCP tCS tNRASr tNCASr nCAS nOE nDWE tADDRd Address Row Addr Column Addr Column Addr (Same page) Data Data Data Fetch (Normal DRAM) Data Data Data Fetch (Normal DRAM) Data Data Fetch (EDO DRAM) Data Fetch (EDO DRAM) tRP = 0 (1 cycle) tCS = 1 (2 cycles) tCP = 0 (1 cycle) tRC = 0 (1 cycle) Figure 4-30. EDO/FP DRAM Bank Read Timing (Page Mode) 4-50 S3C4510B SYSTEM MANAGER SCLK MCLKO tNRASr tCS tRP tNCASwf nCAS tNDWE nDWE tNCASwr tCP tCS tNRASf nRAS tRC tNDWE nOE tADDRd Address Row Addr Column Addr Column Addr (Same page) Data Data Data tRP = 0 (1 cycle) tCS = 1 (2 cycles) tCP = 0 (1 cycle) tRC = 0 (1 cycle) Figure 4-31. EDO/FP DRAM Bank Write Timing (Page Mode) 4-51 SYSTEM MANAGER S3C4510B SCLK MCLKO tNRASr tCS tRP tNCASf nCAS tNROE nOE tNDWE nDWE tADDRd Address Row Addr Column Addr tWDDd Data Data Data Column Addr (Same page) tWDDh tNDWE tNCASr tNCASwf tNCASwr tCP tCS tNRASf nRAS tRC tNROE Data Fetch (Normal DRAM) Data tRP = 0 (1 cycle) tCS = 1 (2 cycles) tCP = 0 (1 cycle) tRC = 0 (1 cycle) Data Fetch (EDO DRAM) Figure 4-32. EDO/FP DRAM Bank Read and Write Timing (Page Mode) 4-52 S3C4510B SYSTEM MANAGER SCLK MCLKO tNRASr tCS tRP tNCASwf nCAS tNCASwr tNCASf tNCASr tCP tCS tNRASf nRAS tRC tNROE tNROE nOE tNDWE nDWE tADDRd Address Row Addr tWDDd Data Data Column Addr tWDDh Data Column Addr (Same page) tNDWE Data Read Point tRP = 0 (1 cycle) tCS = 1 (2 cycles) tCP = 0 (1 cycle) tRC = 0 (1 cycle) Normal DRAM Figure 4-33. EDO/FP DRAM Bank Write and Read Timing (Page Mode) 4-53 SYSTEM MANAGER S3C4510B 200 us Precharge (All banks) Auto Refresh Auto Refresh Mode Register Set (MRS) SCLK MCLKO CKE High level is necessary. nSDCS nSDRAS nSDCAS ADDR Key BA A10/AP nDWE DQM RFU KEY A9 0 TM A8 A7 00 CAS Latency A6 A5 A4 010 BT A3 0 Burst Length A2 A1 A0 000 Figure 4-34. SDRAM Power-up Sequence 4-54 S3C4510B SYSTEM MANAGER 1 SCLK 2 3 4 5 6 7 8 9 10 11 12 13 MCLKO CKE nSDCS tRP nSDRAS tRCD nSDCAS ADDR Row Col0 Col1 (1) Col2 nDWE Rd (2) DATA Wd Rd DQM Precharge (All banks) 0xF Row Active 0x0 0xF (3) 0x0 0xF Read Fetch Write Read Fetch NOTES: 1. There is minimum 1 cycle gap between data-in and data-out of SDRAM to prevent bus confliction. 2. All DQM signals go to zero during read operation. 3. Only valid signals go to zero during write operation. Figure 4-35. Non-burst, Read-Write-Read Cycles @CAS Latency = 2, Burst Length = 1 4-55 SYSTEM MANAGER S3C4510B DRAM INTERFACE FEATURES The S3C4510B provides a fully programmable external DRAM interface. You can easily modify the characteristics of this interface by manipulating the corresponding DRAM control registers. Programmable features include * * * * External data bus width Control fast page or EDO mode by DRAMCON[0] Select fast page/EDO mode or SDRAM mode by SYSCFG Number of access cycles for each DRAM bank, and CAS strobe time, CAS precharge time, RAS to CAS delay, RAS pre-charge time * The refresh and external I/O control register, REFEXTCON, controls DRAM refresh operations and external I/O bank accesses. The S3C4510B eliminates the need for an external refresh signal by automatically issuing an internal CAS-before-RAS refresh or auto-refresh control signal. The S3C4510B generates row and column addresses for DRAM accesses with 23-bit internal address bus. It also supports symmetric or asymmetric DRAM addressing by changing the number of column address lines from 8 to 11. EDO Mode DRAM Accesses The timing for accessing a DRAM in EDO mode is comparable to DRAM accesses in normal fast page mode. However, in EDO mode, the S3C4510B CPU fetches data (when read) one-half clock later than in normal fast page mode. This is possible because EDO mode can validate the data even if CAS goes High when RAS is Low. In this way, gives the CPU sufficient time to access and latch the data so that the overall memory access cycle time can be reduced. Synchronous DRAM Accesses Synchronous DRAM interface features are as follows: * MRS cycle with address key program -- CAS latency (2 cycles) -- Burst length (1) -- Burst type (Sequential) Auto refresh SDRAM interface signal: CKE, SDCLK, nSDCS[3:0], nSDCAS, nSDRAS, DQM[3:0], ADDR[10]/AP * * The address bits except row and column address among the 23-bit internal address bus can be assigned to Bank select address(BA) for SDRAM. See the SDRAM interface example, Figure 4-36. 4-56 S3C4510B SYSTEM MANAGER Available Samsung SDRAM Components for S3C4510B Components S3C4510B can support below SDRAM configuration for 1 bank. * * * * * 2MBytes to 1 bank 1 x (2Mx32 with 4banks) 4MBytes to 1 bank 2 x (1Mx16 with 2banks) 8MBytes to 1 bank 4 x (2Mx8 with 2banks) 16MBytes to 1bank 2 x (4Mx16 with 2/4banks) 32MBytes to 1bank 4 x (8Mx8 with 2/4banks) You can select any combination among them. SDRAM components that are available are as follow. x4 SDRAM whose capacity is larger than 16M SDRAM is not supported at S3C4510B. 16M bit SDRAM -- 4Mx4 with 2banks (Supported) -- 2Mx8 with 2banks (Supported) -- 1Mx16 with 2banks (Supported) 64M bit 2Banks SDRAM -- 16Mx4 with 2banks (not supported) -- 8Mx8 with 2banks (supported) -- 4Mx16 with 2banks (supported) 64M bit 4Banks SDRAM -- 16Mx4 with 4banks (not supported) -- 8Mx8 with 4banks (supported) -- 4Mx16 with 4banks (supported) 2Mx32 (64M bit) SDRAM -- 2Mx32 with 4banks (supported) 100 Pin DIMM Module SDRAM KMM330S104CT -- 1Mx32 based on 2 1Mx16 2banks components KMM330S204CT -- 4Mx32 based on 4 1Mx16 2banks components KMM330S2424CT -- 4Mx32 based on 2 4Mx16 4banks componets KMM330S824CT -- 8Mx32 based on 4 4Mx16 4banks componets RA0-RA10, CA0-CA9 RA0-RA10, CA0-CA8 RA0-RA10, CA0-CA7 RA0-RA12, CA0-CA9 RA0-RA12, CA0-CA8 RA0-RA12, CA0-CA7 RA0-RA11, CA0-CA9 RA0-RA11, CA0-CA8 RA0-RA11, CA0-CA7 RA0-RA10, CA0-CA7 RA0-RA10, CA0-CA7 RA0-RA10, CA0-CA7 RA0-RA11, CA0-CA7 RA0-RA11, CA0-CA7 4-57 SYSTEM MANAGER S3C4510B Relationship Between CAN (Column Address Number) and Address MUX Output for SDRAM Table 4-23. CAN and Address MUX Output CAN 00 Output Timing Column address Row address 01 Column address Row address 10 Column address Row address [21:15] x x x x x x 14 A22 A22 0 0 0 0 13 A21 A21 A22 A22 0 0 External Address Pins (ADDR) 12 A20 A20 A21 A21 A22 A22 11 A19 A19 A20 A20 A21 A21 10 A10/AP A18 A10/AP A19 A10/AP A20 9 A9 A17 A9 A18 A9 A19 8 A8 A16 A8 A17 A8 A18 7-0 A7-A0 A15-A8 A7-A0 A16-A9 A7-A0 A17-A10 NOTES: 1. A22 to A0 depends on external bus width. In case of x32 memory, A[22:0] is word address. 2. A[22:0] consists of: Bank Address + Valid Row Address + Valid Column Address DRAM BANK SPACE The S3C4510B DRAM interface supports four DRAM banks. Each bank can have a different configuration. You use the DRAM control registers, DRAMCON0-DRAMCON3, to program the DRAM access cycles and memory bank locations. Each DRAM control register has two 10-bit address pointers, one base pointer and one next pointer, to denote the start and end address of each DRAM bank. The 10-bit pointer values are mapped to the address [25:16]. This gives each bank address an offset value of 64 K bytes (16 bits). The next pointer value will be the DRAM bank's end address + 1. System Initialization Values When the system is initialized, the four DRAM control registers are initialized to 00000000H, disabling all external DRAMs. 4-58 S3C4510B SYSTEM MANAGER CLK CS CKE RAS CAS WE <3> Address DQM DQ0-7 MCLKO/SDCLK nRAS/nSDCS 0, 1, 2, 3 nCAS2/CKE nCAS0/nSDRAS nCAS1/nSDCAS S3C451B nDWE ADDR[10:0] nWBE[3:0]/DQM[3:0] XDATA[31:0] ADDR[11] BA0 All SDRAM's BA pin <2> CLK CS CKE RAS CAS WE Address DQM DQ0-7 CLK CS CKE RAS CAS WE <1> Address DQM DQ0-7 CLK CS CKE RAS CAS WE <0> Address DQM DQ0-7 NOTE: 4 components have the following features: 1 M x 8 bit x 2 Banks 9 bit column, 11 bit row- address D3 D2 D1 D0 Figure 4-36. SDRAM Application Example 4-59 SYSTEM MANAGER S3C4510B DRAM REFRESH AND EXTERNAL I/O CONTROL REGISTER The S3C4510B DRAM interface supports the CAS-before-RAS (CBR) refresh mode for EDO/FP DRAM and auto-refresh for SDRAM. Settings in the DRAM refresh and external I/O control register, REFEXTCON, control DRAM refresh mode, refresh timings, and refresh intervals. REFEXTCON also contains the 10-bit base pointer value for the external I/O bank 0. NOTE Whenever the S3C4510B CPU writes one of system manager registers, the validity of special register field (that is, the VSF bit) is automatically cleared and the external bus is disabled. To reactivate external bus, you must set the VSF bit to "1" using a STMIA instruction. It is recommended that programmers always use STMIA instructions to write the 10 system manager special registers. The instruction used to set the VSF bit should always be the last instruction in the register write sequence. 4-60 S3C4510B SYSTEM MANAGER 31 REFEXTCON Refresh Count Value 21 20 19 t C S R 17 16 15 14 13 12 11 10 9 RV ES00000 NF External I/O Bank 0 Base Pointer 0 tCHR [9:0] External I/O bank 0 base pointer (base address) This value is the start address of I/O external I/O bank 0. Start address is defined as external I/O bank 0 base pointer << 16. The end address of external I/O bank 0 is defined as external I/O bank 0 base pointer >> 16 + 16 Kbytes - 1. NOTE: All external I/O banks are located in the continuous address space which begins at the start address of external I/O bank 0. The size of each external I/O bank is fixed at 16Kbytes. The start and end addresses of the other three external I/O banks can be derived from the external I/O bank 0 base pointer value. [15] Validity of spedial register field (VSF) 0 = Not accessible to memory bank 1 = Accessible to memory bank [16] Refresh enable (REN) 0 = Disable DRAM refresh 1 = Enable DRAM refresh [19:17] CAS hold time (tCHR) ROW cycle time (tRC) (Note 1) 000 = 1 cycle 001 = 2 cycles 010 = 3 cycles 011 = 4 cycles 100 = 5 cycles 101 = Not used (6 cycles) 110 = Not used 111 = Not used [20] CAS setup time (tCSR)(Note 2) 0 = 1 cycle 1 = 2 cycles [31:21] Refresh count value (duration) The refresh period is calculate as (211 - value + 1)/fMCK NOTES: 1. In EDO/normal DRAM mode, CAS hold time can be programmed upto 5 cycles. But in SDRAM mode, this bit fields function are defined as ROW cycle time (tRC) and can be programmed upto 6 cycles. 2. In SDRAM mode, this bit field is reserved. Figure 4-37. DRAM Refresh and External I/O Control Register (REFEXTCON) 4-61 SYSTEM MANAGER S3C4510B External I/O Bank 3 External I/O Bank 2 External I/O Bank 1 End Address of External I/O Bank 0 External I/O Bank 0 Start Address of External I/O Bank 0 4 Kwords (fixed for all I/O banks) Continuous 16 Kword address space for 4 external I/O banks Start address of external I/O bank n = (External I/O bank 0 base pointer << 16) + 16 Kbytes x n End address of external I/O bank n = (External I/O bank 0 base pointer << 16) + 16 Kbytes x (n + 1) - 1 Where, n is an external I/O bank number (= 0, 1, 2, 3) Figure 4-38. External I/O Bank Address Map 4-62 S3C4510B SYSTEM MANAGER SCLK MCLKO nRAS tCSR nCAS tCHR nDWE/ nOE Address Data Figure 4-39. EDO/FP DRAM Refresh Timing 4-63 SYSTEM MANAGER S3C4510B SCLK MCLKO CKE High level is necessary nSDCS tRP nSDRAS tRC nSDCAS nDWE Precharge (All banks) Auto Refresh New Command Figure 4-40. Auto Refresh Cycle of SDRAM NOTE At auto-refresh cycle, DRAM bank0's tRP bit field is used as RAS pre-charge time parameter. 4-64 S3C4510B UNIFIED INSTRUCTION/DATA CACHE 5 OVERVIEW UNIFIED INSTRUCTION/DATA CACHE The S3C4510B CPU has a unified internal 8K byte instruction/data cache. Using cache control register settings, you can use part or all of this cache as internal SRAM. To raise the cache hit ratio, the cache is configured using two-way, set-associative addressing. The replacement algorithm is pseudo-LRU (Least Recently Used). The cache line size is four words (16 bytes). When a miss occurs, four words must be fetched consecutively from external memory. Typically, RISC processors take advantage of unified instruction/data caches to improve performance. Without an instruction cache, bottlenecks that occur during instruction fetches from external memory may seriously degrade performance. CACHE CONFIGURATION The S3C4510B's 4K byte, two-way set-associative instruction/data cache uses a 15-bit tag address for each set. The CS bits (a 2-bit value) in tag memory stores information for cache replacement. When a reset occurs, the CS value is "00", indicating that the contents of cache set 0 and cache set 1 are invalid. When the first cache fill operation occurs while exiting from the reset operation, the CS value becomes "01" at the specified line to indicate that only set 0 is valid. When the subsequent cache fill occurs, the CS value becomes "11" at the specified line, indicating that the contents of both set 0 and set 1 are valid. 5-1 UNIFIED INSTRUCTION/DATA CACHE S3C4510B 31 30 29 28 27 26 25 Tag Address (15-bit) Enable non-cacheable control 100: Set 0 direct access 101: Set 1 direct access 110: TAG direct access 15 (14) 10 9 43210 7 (8) bits 2-bit switch 2 CS 15 (14) Set 1 Tag 15 (14) Height = 128 (256) Set 0 Tag 7 (8)-bit Decoder Tag RAM (32-bit) Set I Cache 1 = 4 instruction/data (128-bit) Instr3 Instr2 Instr1 Instr0 Set I Cache 0 = 4 instruction/data (128-bit) Instr3 Instr2 Instr1 Instr0 7 (8)-bit Height = 128 (256) 32-bit 32-bit 2 32 2 (Set 0 Hit) (Set 1 Hit) 32 32 Figure 5-1. Memory Configuration for 4-Kbyte (or 8-Kbyte) Cache 5-2 S3C4510B UNIFIED INSTRUCTION/DATA CACHE CACHE REPLACE OPERATIONS When the contents of two sets are valid and when the content of the cache must be replaced due to a cache miss, the CS value becomes "10" at specified line. This indicates that the content of set 0 (S0) was replaced. When CS is "10" and when another replacement is required due to a cache miss, the content of set 1 (S1) is replaced by changing the CS value to "01". To summarise, at its normal steady state, the CS value is changed from "01" or "10" to "10" or "01". This modification provides the information necessary to implement a 2-bit pseudo-LRU (Least Recently Used) cache replacement policy. Reset(/) NVALID: 00 ; Set 0, set 1 all invalid miss S0 only: 01 miss Hit Miss or hit 1 AV-S1D: 11 Hit 1 Miss or hit 0 AV-S0D: 10 Hit 0 ; Chahe miss occurs ; Set 0 = valid, set 1 = invalid Status does not change on hit ; Read miss ; AV_S1D = All valid and set 1 is dirty. Dirty means to access just before; status does not change on hit. ; AV_S0D = All valid and set 0 is dirty. Figure 5-2. Cache Replace Algorithm State Diagram 5-3 UNIFIED INSTRUCTION/DATA CACHE S3C4510B CACHE DISABLE/ENABLE To disable the cache disable entirely following a system reset, you must set SYSCFG[1] to "0". By setting the cache mode bits, SYSCFG[5:4], you can specify a cache size of 0, 4, or 8K bytes. If you do not need the entire 8Kbyte area for cache, you can use the remaining area as normal internal SRAM. The start address of the internal SRAM area is defined by writing an appropriate value to SYSCFG[15:6]. CACHE FLUSH OPERATION To flush cache lines, you must write a zero to Tag memory bits 31 and 30, respectively. The 4-Kbyte set 0 RAM area, 4-Kbyte set 1 RAM area, and the 1-Kbyte Tag RAM area (total 256 words) can be accessed from locations 0x10000000H, 0x10800000H, and 0x11000000H, respectively. You can do this independently of the current cache mode bit and cache enable bit settings. Tag RAM is normally cleared by hardware following a power-on reset. However, if you change the cache or memory bank configuration when the cache is being enabled, you will have to clear the Tag RAM area using application software. NON-CACHEABLE AREA CONTROL BIT Although the cache affects the entire system memory, it is sometimes necessary to define non-cacheable areas when the consistency of data stored in memory and the cache must be ensured. To support this, the S3C4510B provides a non-cacheable area control bit in the address field, ADDR[26]. If ADDR[26] in the ROM/SRAM, flash memory, DRAM, or external I/O bank's access address is "0", then the accessed data is cacheable. If the ADDR[26] value is "1", the accessed data is non-cacheable. Cacheable Area 000_0000 000_0000 000_FFFF Non-cacheable Area 400_0000 Cacheable Area Non-cacheable Area 401_0000 401_FFFF 16 M word 002_0000 Cacheable Area 3FF_FFFF 3FF_FFFF 7FF_FFFF NOTE: The non-cacheable area has the same space in memory as the cacheable area. To access the non-cacheable area, you can change the address of the space in memory using non-cacheable control bit. Figure 5-3. Non-Cacheable Area Control NOTE A SWAP command must be used within a non-cacheable area. 5-4 S3C4510B I2C BUS CONTROLLER 6 OVERVIEW -- I2C BUS CONTROLLER The S3C4510B's internal IC bus (I2C-bus) controller has the following important features: It requires only two bus lines, a serial data line (SDA) and a serial clock line (SCL). When the I2C-bus is free, both lines are High level. -- Each device that is connected to the bus is software-addressable by a single master using a unique address. slave relationships on the bus are constant. The bus master can be either a master-transmitter or a masterreceiver. The I2C bus controller supports only single master mode. -- It supports 8-bit, bi-directional, serial data transfers. -- The number of ICs that you can connect to the same I2C-bus is limited only by the maximum bus capacitance of 400 pF. Figure 6-1 shows a block diagram of the S3C4510B I2C-bus controller SDA Data Control Serial Clock Prescaler 16 Shift Buffer Register (IICBUF) SCL SCL Control 0 System Clock (fMCK) Prescaler Register (IICPS) 0 BUSY COND1 COND0 ACK LRB IEN BF Control Status Register (IICCON) Figure 6-1. I2C BUS Block Diagram 6-1 I2C BUS CONTROLLER S3C4510B FUNCTIONAL DESCRIPTION The S3C4510B I2C bus controller is the master of the serial I2C-bus. Using a prescaler register, you can program the serial clock frequency that is supplied to the I2C bus controller. The serial clock frequency is calculated as follows: MCLK / (16 x (prescaler register value + 1) + 3) To initialize the serial I2C-bus, the programmer sends a start code by writing "01" to bits [5:4]of the control status register, IICCON. The bus controller then sends the 7-bit slave address and a read/write control bit through shift buffer register. The receiver sends an acknowledge by pulling the SDA line from high to low during a master SCL pulse. To continue the data write operation, you must set the BF bit in the control status register and then write the data to the shift buffer register. Whenever the shift buffer register is read or written, the BF bit is cleared automatically. For the consecutive read/write operations, you must set the ACK bit in the control status register. For read operations, you can read the data after you have set the BF bit in the control status register. To signal the end of the read operation, you can reset the ACK bit to inform the receiver/transmitter when the last byte is to be written/read. Following a read/write operation, you set IICCON[5:4] to "10" to generate a stop code. If you want to complete another data transfer before issuing the Stop code, you can send the start code using the repeat start command (with IICCON[5:4] = "11"). When the slave address and read/write control bit have been sent, and when the receive acknowledge has been issued to control SCL timing, the data transfer is initiated. 6-2 S3C4510B I2C BUS CONTROLLER I2C-BUS CONCEPTS Basic Operation The I2C-bus has two wires, a serial data line (SDL) and a serial clock line (SCL), to carry information between the ICs connected to the bus. Each IC is recognized by a unique address and can operate as either a transmitter or receiver, depending on the function of the specific ICs. The I2C-bus is a multi-master bus. This means that more than one IC which is capable of controlling the bus can be connected to it. data transfers proceed as follows: Case 1: A master IC wants to send data to another IC (slave): 1. Master addresses slave 2. Master sends data to the slave (master is transmitter, slave is receiver) 3. Master terminates the data transfer Case 2: A master IC wants to receive information from another IC (slave): 1. Master addresses slave 2. Master receives data from the slave (master is receiver, slave is transmitter) 3. Master terminates the data transfer Even in case 2, the master IC must generate the timing signals and terminate the data transfer. If two or more masters try to put information simultaneously onto the bus, the first master to issue a "1" when the other issues a "0" will lose the bus arbitration. The clock signals used for arbitration are a synchronized combination of the clocks generated by the bus masters using the wired-AND connection to the SCL line. The master IC is always responsible for generating the clock signals on the I2C-bus. Bus clock signals from a master can only be altered by 1) a slow slave IC which "stretches" the signal by temporarily holding the clock line Low, or 2) by another master IC during arbitration. General Characteristics Both SDA and SCL are bi-directional lines which are connected to a positive supply voltage through a pull-up resistor. When the I2C-bus is free, the SDA and SCL lines are both high level. The output stages of I2C interfaces connected to the bus have an open-drain or open-collector to perform the wired-AND function. Data on the I2Cbus can be transferred at a rate up to 100 Kbits/s. The number of interfaces that can be connected to the bus is solely dependent on the limiting bus capacitance of 400 pF. Bit Transfers Due to the variety of different ICs (CMOS, NMOS, and I2L, for example) which can be connected to the I C-bus, the levels of logic zero (low) and logic one (high) are not fixed and depend on the associated level of VDD. One clock pulse is generated for each data bit that is transferred. 2 6-3 I2C BUS CONTROLLER S3C4510B Data Validity The data on the SDA line must be stable during the high period of the clock. The high or low state of the data line can only change when clock signal on the SCL line is low. Start and Stop Conditions Start and stop conditions are always generated by the master. The bus is considered to be busy after the start condition is generated. The bus is considered to be free again when a brief time interval has elapsed following the Stop condition. -- Start condition: a High-to-Low transition of the SDA line while SCL is high. -- Stop condition: a Low-to-High transition of the SDA line while SCL is high. SDA SCL 1-7 S Start Address Condition 8 R/W 9 ACK 1-7 DATA 8 9 ACK 1-7 DATA 8 9 P Stop ACK Condition Figure 6-2. Start and Stop Conditions 6-4 S3C4510B I2C BUS CONTROLLER DATA TRSANSFER OPERATIONS Data Byte Format Every data byte that is put on the SDA line must be 8 bits long. The number of bytes that can be transmitted per transfer is unlimited. Each byte must be followed by an acknowledge bit. Data is transferred MSB-first. If the receiver cannot receive another complete byte of data until it has performed some other function (such as servicing an internal interrupt), it can hold the clock line SCL Low to force the transmitter into a wait state. The data transfer then continues when the receiver is ready for another byte of data and releases the SCL line. Acknowledge Procedure Data transfer with acknowledge is obligatory. The acknowledge-related clock pulses must be generated by the bus master. The transmitter releases the SDA line (High) during the acknowledge clock pulse. The receiver must pull down the SDA line during the acknowledge pulse so that it remains stable low during the High period of this clock pulse. Usually, a receiver which has been addressed is obliged to generate an acknowledge after each byte is received. When a slave receiver does not acknowledge from the slave address, the slave must leave the data line high. The master can then generate a stop condition to abort the transfer. If a slave receiver acknowledges the slave address, but later in the transfer cannot receive any more data bytes, the master must again abort the transfer. This is indicated by the slave not generating the acknowledge on the first byte to follow. The slave leaves the data line high and the master generates the stop condition. If a master receiver is involved in a transfer, it must signal the end of data to the slave transmitter by not generating an acknowledge on the last byte that was clocked out of the slave. The slave transmitter must then release the data line to let the master generate the stop condition. 6-5 I2C BUS CONTROLLER S3C4510B Data Transfer Format Data transfers uses the format shown in Figure 6-3. After the start condition has been generated, a 7-bit slave address is sent. The eighth bit is a data direction bit (R/W). A "0" direction bit indicates a transmission (Write) and a "1" indicates a request for data (Read). A data transfer is always terminated by a stop condition which is generated by the master. However, if a master still wishes to communicate on the bus, it can generate another start condition and address another slave without first generating a stop condition. This feature supports the use of various combinations of read/write formats for data transfers. Multiple Byte Slave Receiver Format: S Slave address WA Data 1 (8 bits) A Data 2 A Data M AP Multiple Byte Slave Transmitter Format: S Slave address RA Data 1 (8 bits) A Data 2 A Data M AP NOTE: S (Start) W (Write; bit value is 0) R (Read; bit value is 1) P (Stop), A (Acknowledge; The ACK is first sent to the slave. Afterwards, the direction depends on the data transfer direction. In other words, if the mater reads the data, it sends the ACK.) Figure 6-3. Data Transfer Format 6-6 S3C4510B I2C BUS CONTROLLER I2C-Bus Addressing The addressing procedure for the I2C-bus is such that the first byte after the start condition determines which slave the master will select. Usually, this first byte immediately follows the start procedure. An exception is the "general call" address which can address all ICs simultaneously. When this address is used, all ICs should, in theory, respond with an acknowledge. However, ICs can also be made to ignore this address. The second byte of the general call address then defines the action to be taken. Definition of Bits in the First Data Byte The first seven bits of the first data byte make up the slave address. The eighth bit is the LSB, or direction bit, which determines the direction (R/W) of the message. When an address is sent, each IC on the bus compares the first 7 bits received following start condition with its own address. If the addresses match, the IC considers itself addressed by the master as a slave receiver or a slave transmitter. General Call Address The general call address can be used to address every IC that connected to the I2C-bus. However, if an IC does not need any of the data supplied within the general call structure, it can ignore this address by not acknowledging it. If an IC does require data from a general call address, it can then acknowledge this address and behave as a slave receiver. The second and following bytes will be acknowledged by every slave receiver capable of handling this data. A slave which cannot process one of these bytes must ignore it by not acknowledging. The meaning of the general call address is always specified in the second byte. Start Byte Every data transfer is preceded by a start procedure: -- A start condition, S -- A start byte, "00000001" -- An acknowledge (ACK) clock pulse, and -- A repeated start condition, Sr After the start condition (S) has been transmitted by a master which requires bus access, the start byte ("00000001") is transmitted. Another IC can therefore sample the SDA line at a low sampling rate until one of the seven zeros in the start byte is detected. After it detects this low level on the SDA line, the IC can switch to a higher sampling rate to find the repeated start condition (Sr) which is then used for synchronization. (A) hardware receiver will reset upon receipt of the repeated start condition (Sr) and will therefore ignore the start byte.) An acknowledge-related clock pulse is generated after the start byte. This is done only to conform with the byte handling format used on the bus. No IC is allowed to acknowledge the start byte. 6-7 I2C BUS CONTROLLER S3C4510B I2C BUS SPECIAL REGISTERS The I2C-bus controller has three special registers: a control status register (IICCON), a prescaler register (IICPS), and a shift buffer register (IICBUF). Control Status Register (IICCON) The control status register for the I2C-bus, IICCON, is described in Table 6-2. Table 6-1. Control Status Register (IICCON) Register IICCON Offset Address 0xf000 R/W R/W Description Control status register Rest Value 0x00000000 Table 6-2. IICCON Register Description Bit Number [0] Bit Name Buffer flag (BF) Description The BF bit is set when the buffer is empty in transmit mode or when the buffer is full in receive mode. To clear the buffer, you write a "0" to this bit. The BF bit is cleared automatically whenever the IICBUF register is written or read. If you set BF bit to one, the I2C -bus is stopped. To activate I2C-bus, you should clear the BF bit to zero. Setting the interrupt enable bit to "1" enables the I2C-bus interrupt. The LRB bit is read only. It holds the value of the last received bit over the I2C-bus. Normally, this bit will be the value of the slave acknowledgement. To check for slave acknowledgement, you test the LRB. The ACK bit is normally set to "1". This causes the I2C-bus controller to send an acknowledge automatically after each byte. This bit must be "0" when the I2C-bus controller is operating in receiver mode and requires no further data to be received from the slave transmitter. This causes a negative acknowledge on the I2C-bus, which halts further reception from the slave device. These bits control the generation of the start, Stop, and repeat Start conditions: "00" = no effect, "01" = start, "10" = stop, and "11" = repeat start. This bit is a read-only flag that indicates when the I2C-bus is in use. A "1" indicates that the bus is busy. This bit is set or cleared by a start or stop condition, respectively. If "1" is written to the reset bit, the I C-bus controller is reset to its initial state. Not applicable. 2 [1] [2] Interrupt enable (IEN) Last received bit (LRB) [3] Acknowledge enable (ACK) [5:4] COND1, COND0 [6] Bus busy (BUSY) [7] [31:8] Reset Reserved 6-8 S3C4510B I2C BUS CONTROLLER 31 Reserved 987 R E S E T 65 C BO U SN YD 1 4 C O N D 0 3210 AL IB CRE KBNF [0] Buffer Flag (BF) 0 = Automatically cleared when the IICBUF register is written or read. To manually clear the BF, write 0. 1 = Automatically set when the buffer is empty in transmit mode or when the buffer is full in receive mode. [1] Interrupt enable (IEN) 0 = Disable 1 = Enable; an interrupt is generated if the BF bit is 1. [2] Last received bit (LRB) Use this read-only status bit to theck for ACK signals from the receiver (slave), or to monitor SDA operation of SDA when writing 11 to IICCON [5:4] for repeated starts. 0 = The most recent SDA is low. (ACK is received) 1 = The most recent SDA is high. (ACK not received) [3] Acknowledge enable (ACK) Controls generation of an ACK signal in receive mode. 0 = Do not generate an ACK at 9th SCL (No more received data is required from the slave) 1 = Generate an ACK signal at 9th SCL. [5:4] COND 1 and COND 0 Generate a bus control such as start or stop. 00 = No effect. 01 = Generate start condition. 10 = Generate stop condition. 11 = SCL will be released to high level to generate repeated start condition. [6] Bus busy (BUSY) Data transmission is in progress on the IIC-bus. 0 = Bus is currently not in use. (not busy) 1 = Bus is in use. (busy) [7] Reset 0 = Normal 1 = Reset the IIC-bus controller. [31:8] Reserved Figure 6-4. I2C Control Status Register 6-9 I2C BUS CONTROLLER S3C4510B Shift Buffer Register (IICBUF) The shift buffer register for the I2C-bus described in Table 6-4. Table 6-3. IICBUF Register Register IICBUF Offset Address 0xf004 R/W R/W Description Shift buffer register Rest Value Undefined Table 6-4. IICBUF Register Description Bit Number [7:0] Data Bit Name Description This data field acts as serial shift register and read buffer for interfacing to the I2C-bus. All read and write operations to/from the I2C-bus are done via this register. The IICBUF register is a combination of a shift register and a data buffer. 8-bit parallel data is always written to the shift register, and read form the data buffer. I2Cbus data is always shifted in or out of the shift register. Not applicable. [31:8] Reserved Prescaler Register (IICPS) The prescaler register for the I2C-bus is described in Table 6-6. Table 6-5. IICPS Register Register IICPS Offset Address 0xf008 R/W R/W Description Prescaler register Rest Value 0x00000000 Table 6-6. IICPS Register Description Bit Number [15:0] Bit Name Prescaler value Description This prescaler value is used to generate the serial I2C-bus clock. The system clock is divided by (16 x (prescaler value + 1) + 3) to make the serial I2C clock. If the prescaler value is zero, the system clock is when divided by 19 to make the serial I2C clock. Not applicable. [31:16] Reserved 6-10 S3C4510B I2C BUS CONTROLLER Prescaler Counter Register (IICCNT) The prescaler counter register for the I2C-bus is described in Table 6-8. Table 6-7. IICCNT Register Register IICCNT Offset Address 0xf00c R/W R/W Description Prescaler counter register Rest Value 0x00000000 Table 6-8. IICCNT Register Description Bit Number [15:0] [31:16] Bit Name Counter value Reserved Description This 16-bit value is the value of the prescaler counter. It is read (in test mode only) to check the counter's current value. Not applicable. 6-11 I2C BUS CONTROLLER S3C4510B NOTES 6-12 S3C4510B ETHERNET CONTROLLER 7 OVERVIEW ETHERNET CONTROLLER The S3C4510B has an ethernet controller which operates at either 100-Mbits or 10-Mbits per second in halfduplex or full-duplex mode. In half-duplex mode, the controller supports the IEEE 802.3 carrier sense multiple access with collision detection (CSMA/CD) protocol. In full-duplex mode, it supports the IEEE 802.3 MAC control layer, including the pause operation for flow control. The ethernet controllers MAC layer supports both the media independent interface (MII) and the buffered DMA interface (BDI). The MAC layer itself consists of the receive and the transmit blocks, a flow control block, a content addressable memory (CAM) for storing network addresses, and a number of command, status, and error counter registers. The MII supplies the transmit and receive clocks of 25 MHz for 100-Mbit/s operation or 2.5 MHz at the 10-Mbit/s speed. The MII conforms to the ISO/IEC 802-3 standards for a media-independent layer which separates physical layer issues from the MAC layer. 7-1 ETHERNET CONTROLLER S3C4510B BDMA+SBUS I/F MAC MAC Tx Buffer Controller Physical Layer BDMA Tx Buffer Controller BDMA Tx Buffer (64 Words) 32 8 MAC Tx Buffer (80 bytes) 32 S y s t e m B u s Bus Arbiter/ Controller BDMA Rx Buffer (64 Words) B D I 8 MAC Rx Buffer (16 bytes) Preamble/ Jam/Pad/CRC Generator 32 BDMA Rx Buffer Controller 32 32 MAC Rx Buffer Controller Address CAM Interface and Comparator M I I / 10 M b p s 7 W i r e M D I CAM Contents Memory (32-Words) Flow Controller CRC Checker 32 BDMA Control and Status Register MAC Control and Status Register Station Manager Figure 7-1. Ethernet System Flow Control 7-2 S3C4510B ETHERNET CONTROLLER FEATURES AND BENEFITS The most important features and benefits of the S3C4510B ethernet controller are as follows: -- Cost-effective connection to an external RIC/Ethernet backbone -- Buffered DMA (BDMA) engine using burst mode -- BDMA Tx/Rx buffers (256 bytes/256 bytes) -- MAC Tx/Rx FIFOs (80 bytes/16 bytes) to support re-transmit after collision without DMA request and to handle DMA latency -- Data alignment logic -- Endian translation -- Support for old and new media (compatible with existing 10-Mbit/s networks) -- 100-Mbit/s or 10-Mbits/s operation to increase price/performance options and to support phased conversions -- Full IEEE 802.3 compatibility for existing applications -- Media Independent interface (MII) or 7-wire interface -- Station management (STA) signaling for external physical layer configuration and link negotiation -- On-chip CAM (21 addresses) -- Full-duplex mode for doubled bandwidth -- Pause operation hardware support for full-duplex flow control -- Long packet mode for specialized environments -- Short packet mode for fast testing -- PAD generation for ease of processing and reduced processing time 7-3 ETHERNET CONTROLLER S3C4510B MAC FUNCTION BLOCKS The major function blocks of the ethernet controllers MAC layer are described in Table 7-1 and Figure 7-1. Table 7-1. MAC Function Block Descriptions Function Block Media Independent Interface (MII) Transmit block Description The interface between the physical layer and the transmit and receive blocks. Moves the outgoing data from the transmit buffer to the MII. The transmit block includes circuits for generating the CRC, checking parity, and generating preamble or jam. The transmit block also has timers for back-off after collision and for the interframe gap the follows a transmission. Accepts incoming data from the MII and stores it in the receive FIFO. The receive block has logic for computing and checking the CRC value, generating parity for data from the MII, and checking minimum and maximum packet lengths. The receive block also has a content addressable memory (CAM) block which provides for address lookup, and for acceptance or rejection for packets based on their destination address. Recognizes MAC control packets and supports the pause operation for full-duplex links. The flow control block also supports generation of pause packets, and provides timers and counters for pause control. Controls programmable options, including the enabling or disabling of signals which notify the system when conditions occur. The status registers hold information for error handling software, and the error counters accumulate statistical information for network management software. Provides for MAC-layer testing in isolation from the MII and physical layer. Receive block Flow control block MAC control (command) and status registers Loop-back circuit 7-4 S3C4510B ETHERNET CONTROLLER Transmit Block Tx_DB[7:9] MAC Transmit FIFO (80 bytes) Preamble and Jam Generator Pad and CRC Generator Parity Check MAC Loop-back TxD[3:0] B D I Rx_DB[7:0] Flow Control MAC Receive FIFO (16 bytes) CRC and CAM Filter Receive Block MAC Control and Status Register MII Station Manager MDC MDIO 10 M b / s I/F TxD_10 Backoff and Intergap Timer RxD_10 Parity Generator RxD[3:0] M I I Figure 7-2. MAC Layer Flow Control Function Blocks 7-5 ETHERNET CONTROLLER S3C4510B MEDIA INDEPENDENT INTERFACE (MII) Transmit and receive blocks both operate using the MII, which was developed by the IEEE802.3 task force on 100-Mbit/s ethernet. This interface has the following characteristics: -- Media independence -- Multi-vendor points of interoperability -- Supports connection of MAC layer and physical layer entity (PHY) devices -- Capable of supporting both 100-Mbit/s and 10-Mbit/s data rates -- Data and delimiters are synchronous to clock references -- Provides independent 4-bit wide transmit and receive data paths -- Uses TTL signal levels that are compatible with common digital CMOS ASIC processes -- Supports connection of PHY layer and station management (STA) devices -- Provides a simple management interface -- Capable of driving a limited length of shielded cable PHYSICAL LAYER ENTITY (PHY) The physical layer entity, or PHY, performs all of the decoding/encoding on incoming and outgoing data. The manner of decoding and encoding (Manchester for 10BASE-T, 4B/5B for 100BASE-X, or 8B/6T for 100BASE-T4) does not affect the MII. The MII provides the raw data it receives, starting with the preamble and ending with the CRC. The MII expects raw data for transmission, also starting with the preamble and ending with the CRC. The MAC layer also generates jam data and transmits it to the PHY. BUFFERED DMA INTERFACE (BDI) The buffered DMA interface (BDI) supports read and write operations across the system bus. Two eight-bit buses transfer data with optional parity checking. The system interface initiates data transfers. The MAC-layer controller responds with a ready signal to accept data for transmission, or to deliver data which has been received. An endof-frame signal indicates the boundary between packets. 7-6 S3C4510B ETHERNET CONTROLLER THE MAC TRANSMIT BLOCK The MAC transmit block is responsible for transmitting data. It complies with the IEEE802.3 standard for carrier sense multiple access with collision detection (CSMA/CD) protocol. The MAC transmit block consists of the following sections: -- Transmit FIFO and controllers -- Preamble and jam generators -- Pad generator -- Parallel CRC generator -- Threshold logic and counters -- Back-off and retransmit timers -- Transmit state machine Figure 7-3 shows the MAC transmit function blocks in detail. Parity Check Tx_DB [7:0] and PARITY 9 Preamble and JAM generator TxD [3:0] 9 PAD Generator B D I Tx_EOF Tx_wr# Tx_rdy Write FIFO Controller and Counter Read FIFO Controller and Counter 8 Tx_CLK CRC Generator CrS Tx_er Transmit State Matchine Tx_en Col Back off and Retransmit Timers M I I a n d 10 M b y t e I/F MAC Transmit FIFO (80 x 9) Threshold Logic and Counters SYS_CLK Domain Tx_CLK Domain Figure 7-3. MAC Transmit Function Blocks 7-7 ETHERNET CONTROLLER S3C4510B Transmit FIFO and Read/Write Controllers The transmit FIFO has an 80-byte depth. An extra bit is associated with each data byte for parity checking. This 80-byte by 9-bit size allows the first 64 bytes of a data packet to be stored and retransmitted, without further system involvement, in case of a collision. If no collision occurs and transmission is underway, the additional 16 bytes handle system latency and avoid FIFO under-run. When the system interface has set the transmit enable bit in the appropriate control register, the transmit state machine requests data from the BDI. The system controller then fetches data from the system memory. The FIFO controller stores data in the transmit FIFO until the threshold for transmit data is satisfied. The FIFO controller passes a handshaking signal to the transmit state machine, indicating that sufficient data is in the FIFO to start the transmit operation. If the FIFO is not full, the FIFO controller issues a request to the BDI for more data. The transmit state machine continues transmitting data until it detects the end-of-frame signal, which signals the last byte. It then appends the calculated CRC to the end of the data (unless the CRC truncate bit in the transmit control register is set). The packet transmit bit in the status register is set, generating an interrupt if it is enabled. The FIFO counters in this block (the Write counter) and the transmit FIFO counter of the transmit state machine (the Read counter) co-ordinate their functions based on each other's count value, although they do have different clock sources. The FIFO controller stores parity bits with the data in the FIFO. It checks for parity and can halt transmission after reading the data out of the FIFO and sending it for the CRC calculation. If a parity error occurs, the FIFO controller sets an error status bit, generating an interrupt if it is enabled. Preamble and Jam Generator As soon as the transmit enable bit in the control register is set and there are eight bytes of data in the FIFO, the transmit state machine starts the transmission by asserting the Tx_en signal and transmitting the preamble and the start frame delimiter (SFD). In case there is a collision, it transmits a 32-bit string of "1s" after the preamble as a jam pattern. PAD Generator If a short data packet is transmitted, the MAC will normally generate pad bytes to extend the packet to a minimum of 64 bytes. The pad bytes consist entirely of "0" bits. A control bit is also used to suppress the generation of pad bytes. Parallel CRC Generator The CRC generation of the outgoing data starts from the destination address and continues through the data field. You can suppress CRC generation by setting the appropriate bit in the transmit control register. This is useful in testing, for example, to force the transmission of a bad CRC in order to test error detection in the receiver. It can also be useful in certain bridge or switch applications, where end-to-end CRC checking is desired. 7-8 S3C4510B ETHERNET CONTROLLER Threshold Logic and Counters The transmit state machine uses a counter and logic to control the threshold of when transmission can begin. before it attempts to initiate transmission, the MAC waits until eight bytes or a complete packet has been placed in the transmit FIFO. This gives the DMA engine some latency without causing an underflow during transmission. Back-Off and Retransmit Timers When a collision is detected on the network, the transmitter block stops the transmission and starts a jamming pattern to ensure that all the nodes detect the collision. After this, the transmitter waits for a minimum of 96 bit times and then retransmits the data. After 16 attempts, the transmit state machine sets an error bit and generates an interrupt, if enabled, to signify the failure to transmit a packet due to excessive collisions. It flushes the FIFO, and the MAC is ready for the next packet. Transmit Data Parity Checker Data in the FIFO is odd-parity protected. When data is read for transmission, the transmit state machine checks the parity. If a parity error is detected, the transmit data parity checker does the following: -- It stops transmission. -- It sets the parity error bit in the transmit status register. -- It generates an interrupt, if enabled. Transmit State Machine The transmit state machine is the central control logic for the transmit block. It controls the passing of signals, the timers, and the posting of errors in the status registers. 7-9 ETHERNET CONTROLLER S3C4510B THE MAC RECEIVE BLOCK The MAC receive block is responsible for receiving data. It complies with the IEEE802.3 standard for carrier sense multiple access with collision detection (CSMA/CD) protocol. After it receives a packet, the receive block checks for a number of error conditions: CRC errors, alignment errors, and length errors. Several of these checks can be disabled by setting bits in the appropriate control registers. depending on the CAM status, the destination address and the receive block may reject an otherwise acceptable packet. The MAC receive block consists of the following units: -- Receive FIFO, FIFO controller, and counters -- Receive BDI state machine -- Threshold logic and counters -- CAM block for address recognition -- Parallel CRC checker -- Receive state machine The main components of the receive block are shown in Figure 7-4. Rx_DB [7:0] and parity 9 CAM Checker CRC Checker BDI Rx_rd Rx_rdy Rx_EOF Rx_keep Rx_toss Rx_load CAM_hit# Receive BDI state Machine MAC Receive FIFO (16X10) Write address /WE Write FIFO controller and counter RxD[3:0] Parity Check SFD Detect Rx_clk MII and 7-Wire I/F Read address Write FIFO controller and counter Receive State Machine Rx_DV Rx_er Thershold logic and counter SYS_CLK Domain Rx_CLK Domain Figure 7-4. MAC Receive Function Blocks 7-10 S3C4510B ETHERNET CONTROLLER Receive FIFO Controller The receive FIFO controller accepts data one byte at a time. Parity starts with the destination address. The receive controller updates the counter with the number of bytes received. As the FIFO stores the data, the CAM block checks the destination address against its stored address. If the CAM recognizes the address, the FIFO continues receiving the packet. If the CAM block does not recognize the address and rejects the packet, the receive block discards the packet and flushes the FIFO. Address CAM and Address Recognition The CAM block provides direct comparison address recognition. The CAM compares the destination address of the received packet to stored addresses. If it finds a match, the receive state machine continues to receive the packet. The CAM is organized to hold six-byte address entries. With its 32-word size, the CAM can store 21 address entries. CAM address entries 0, 1, and 18 are used to send the pause control packet. To send a pause control packet, you must write the destination address to CAM0, the source address to CAM1, and length/type, op-code, and operand to the CAM18 entry. You must them write the MAC transmit control register to set the send pause control bit. In addition, CAM19 and CAM20 can be used to construct a user-define control frame. Parallel CRC Checker The receive block computes a CRC across the data and the transmitted CRC, and then checks that the resulting syndrome is valid. A parallel CRC checking scheme handles data arriving in 4-bit nibbles at 100 Mbps. To support full-duplex operation, the receive and transmit blocks have independent CRC circuits. Receive State Machine In MII mode, the receive block receives data from the MII on the RxD[3:0] lines. This data is synchronized to Rx_clk at 25 MHz or 2.5 MHz. In 7-wire mode, and at 10 MHz, data is received on the RxD_10 line only. After it detects the preamble and SFD, the receive state machine arranges data in byte configurations, generates parity, and stores the result in the receive FIFO one byte at a time. If the CAM block accepts the destination address, the receive FIFO stores the rest of the packet. At the end of the reception, the receive block marks the packet received by setting the appropriate bits in the receive status register. Any error in reception will reset the FIFO and the state machine will wait for the end of the current packet. It will then idle while it is waiting for the next preamble and SFD. BDMA Interface Receive State Machine The BDMA I/F receive state machine issues the Rx_rdy signal to request that the receive FIFO have data whenever data is present in the receive FIFO. The last byte of the packet is signaled by asserting the Rx_EOF. In case there are any errors during the reception, or if there is a CRC error at the end, the BDMA I/F receive state machine asserts the Rx_toss signal to indicate that the received packet should be discarded. 7-11 ETHERNET CONTROLLER S3C4510B FLOW CONTROL BLOCK The flow control block provides for the following functions: -- Recognition of MAC control frames received by the receive block -- Transmission of MAC control frames, even if transmitter is paused -- Timers and counters for pause operation -- Command and status register (CSR) interface -- Options for passing MAC control frames through to software drivers The receive logic in the flow control block recognizes a MAC control frame as follows: -- The length/type field must have the special value specified for MAC control frames. The destination address must be recognized by the CAM. The frame length must be 64 bytes, including CRC. The CRC must be valid, and the frame must contain a valid pause op-code and operation. -- If the length/type field does not have the special value specified for MAC control frames, the MAC takes no action, and the packet is treated as a normal packet. If the CAM does not recognize the destination address, the MAC rejects the packet. If the packet length is not 64 bytes, including CRC, the MAC does not perform the operation. The packet is then marked as a MAC control packet, and is passed forward to the software drivers, if pass-through is enabled. You can set control bits in the transmit status register to generate a Full-Duplex pause operation or other MAC control functions, even if the transmitter itself is paused. Two timers and two corresponding CSR registers are used during a pause operation. One timer/register pair is used when a received packet causes the transmitter to pause. The other pair is used to approximate the pause status of the other end of the link, after the transmitter sends a Pause command. The command and status register (CSR) interface provides control and status bits within the transmit and receive control registers and status registers. These lets you initiate the sending of a MAC control frame, enable and disable MAC control functions, and read the values of the flow control counters. Control bits are provided for processing MAC control frames entirely within the controller, or for passing MAC control frames on to the software drivers. This lets you enable flow control by default even on software drivers which are not otherwise "flow control aware". 7-12 S3C4510B ETHERNET CONTROLLER BUFFERED DMA INTERFACE BUFFERED DMA (BDMA) CONTROL BLOCKS The BDMA engine controls a transmit buffer and a receive buffer. The BDMA transmit buffer holds data and status information for packets being transmitted. The BDMA receive buffer holds data and status information for packets being received. Each FIFO has a control block which controls data being placed in, and removed from, the buffers. Half_full Half_empty SD [31:0] nREQ_Tx SD[31:0] nACK S Y S T E M B U S I/F nREQ BUS Arbiter Rx Bus Request Tx_Underflow nREQ_Rx SA[25:0] Address Generator Rx Bus Request Target Address for Rx RX_over flow Source Address for Tx Rx_Widget Byte-to-Word Converter TAIL Ptr Tx widget Big/little Word-to-Byte Converter Data Swapper HEAD Ptr BDMA Rx Buffer (33 x 64) HEAD Ptr TAIL Ptr BDMA Tx Buffer (32 x 64) Tx_clk Tx Control Machine Tx_wr Tx_rdy Half_full Tx_DB[7:0] B D I ( Big/Little Rx_clk Rx_rd Rx_rdy Half_empty Rx_DB[7:0] B D M A I/F ( Rx Control Machine Figure 7-5. BDMA Control Blocks 7-13 ETHERNET CONTROLLER S3C4510B The Bus Arbiter The bus arbiter decides which of the BDMA buffer controllers, transmit (Tx) or receive (Rx), has the highest priority for accessing the system bus. The prioritization is dynamic. The BDMA arbiter outputs a bus request signal (nREQ) to the system manager when -- A buffer contains more words than the Rx burst size, -- An EOF (End of Frame) was saved to the buffer, or -- A buffer contains more free space than the Tx burst size. After it receives a bus acknowledge signal (nACK) from the system manager, the BDMA bus arbiter determines the correct bus access priority. If nREQ_Tx and nREQ_Rx were requested simultaneously, the bus arbiter decodes the nACK signal using the following method: switch (Half_empty, Half_full) { case 2'b01: nACK_Rx nACK case 2'b10: nACK_Tx nACK default: //case 2'b00 or 2'b11: if (Rx buffsize (Head - Tail) < Tx buffsize) // Rx more urgent nACK_Rx nACK else nACK_Tx nACK} 7-14 S3C4510B ETHERNET CONTROLLER BDMA Bus Control Logic The function blocks of the BDMA controller provide logic for controlling bus master read and write operations across the system bus. This control logic supports the following operations: -- Burst size control, to optimize system bus utilization. -- Transmit threshold control (based on 1/8 of transmit buffer size) to match transmission latency to system bus latency. -- Little-Endian byte swapping, to support the data transfer of Little-Endian memory usage for frame data. -- A transmit/receive alignment widget to circumvent word alignment restrictions. In systems with an ATM LAN emulation or an MPOA interface, and in certain other systems as well, the beginning of a packet should be placed on a byte or half-word boundary. You may not, however misalign the BDMA transfer, as this would complicate the design of the DMA, and would degrade performance. To avoid this, you can use an alignment widget between the BDMA buffer (word) and the MAC FIFO (byte). In the receiver, the BDMA bus control logic inserts a programmable number of bytes (up to three) into the received data stream while the preamble is being received. This adds some padding to the beginning of the frame. This padding can then be used to solve alignment problems downstream, without having to use a copy of the buffer. Because there is never more than three bytes, this feature does not degrade performance. Also, because the data is inserted prior to the concatenation of bytes into words, it does not misalign the subsequent DMA transfer. The length of the alignment data is read from a control register. This length value should be set by software immediately after the MAC module is reset, and it should not be modified. You can use a corresponding transmit alignment widget to remove data from the buffer. In the simplest implementation, the widget discards the first "n" bytes (up to three), where "n" is the value read from the transmit frame descriptor which configures the transmit alignment widget. MEMORY DATA STRUCTURES The flow control 100-/10-Mbit/s ethernet controller uses three data structures to exchange control information and data: -- Transmit frame descriptor -- Receive frame descriptor -- Frame data buffer Each frame descriptor has the following elements: -- Frame start address -- Ownership bit -- Control field for transmitter -- Status field -- Frame length -- Next frame descriptor pointer Figure 7-6 shows data structures of the transmit and receive frame descriptors. 7-15 ETHERNET CONTROLLER S3C4510B DATA FRAMES The ownership bit in the MSB of the frame start address controls the owner of the descriptor. When the ownership bit is "1", the BDMA controller owns the descriptor. When this bit is "0", the CPU owns the descriptor. The owner of the descriptor always owns the associated data frame. (The descriptor's frame start address field always points to this frame.) As it receives the data frame, software sets the maximum frame size register in the BDMA block to the system frame buffer size (typically, to 1536 or 2048). Software also sets the Rx frame descriptor start address register to point to a chain of frame descriptors, all of which have their ownership bit set. The BDMA engine can then be started to set the BDMA receive enable bit in the BDMARXCON register. When a frame is received, it is copied into memory at the address specified by the Rx frame start address. Please note that no configurable offset or page boundary calculation is required. The received frame is written into the frame data buffer until the end of frame is reached, or until the length exceeds the configured maximum frame size. If the entire frame is received successfully, the status bits in the frame descriptor are set to indicate this. Otherwise, the status bits are set to indicate that an error occurred. The ownership bit in the frame start address field is cleared and an interrupt may now be generated. The BDMA controller copies the next frame descriptor register value into the Rx frame descriptor start address register. If the next frame descriptor address is null (0), the BDMA simply halts, and all subsequent frames are dropped. Otherwise, the descriptor is read in, and the BDMA controller starts again with the next frame, as described in the previous paragraph. If the received frame size exceeds the maximum frame size, the data frame will be overwritten by the last word of maximum frame. The overflow data is written to the Rx status bit [19] in the receive frame descriptor. When the BDMA reads a descriptor, if the ownership bit is not set, it has two options: -- Skip to the next frame descriptor, or -- Generate an interrupt and halt the BDMA operation. Transmit frame descriptors contain the following components: -- A four-byte pointer to the frame data -- Widget alignment control bits [6:5] -- Frame data pointer increment/decrement bit [4] -- Little-Endian control bit [3] -- Interrupt enable after transmit [2] -- No-CRC [1], and -- No-padding [0] During transmission, the two-byte frame length at the Tx frame descriptor is moved into the BDMA internal Tx register. After transmission, Tx status is saved in the Tx frame descriptor. The BDMA controller then updates the next frame descriptor address register for the linked list structure. When the Tx frame descriptor start address register points to the first frame buffer, transmitter starts transmitting the frame data into the frame buffer memory. 7-16 S3C4510B ETHERNET CONTROLLER 31 30 O 16 15 Frame Data Pointer Reserved Rx Status Next Frame Descriptor Pointer Frame Length 0 [31] Ownership bit (O) 0 = CPU 1 = BDMA [30:0] Frame Data Pointer Address of the frame data to be saved. [15:0] Frame Length The size of the received frame. [31:16] Rx Status The Rx status field of the receive frame is updated by the MAC after reception is complete. [31:0] Next frame descriptor pointer Address of next frame descriptor. Figure 7-6. Data Structure of Rx Frame Descriptor 7-17 ETHERNET CONTROLLER S3C4510B 31 30 O Tx Status Reserved 16 15 Frame Data Pointer 76 WA 54 3 21 0 ALTCP Frame Length Next Frame Descriptor Pointer [0] No-padding mode (P) 0 = Padding mode 1 = No-padding mode [1] No-CRC mode (C) 0 = CRC mode 1 = No-CRC mode [2] MAC transmit interrupt enable after transmission of this frame (T) 0 = Disable 1 = Enable [3] Little-Endian mode (L) 0 = Big-endian 1 = Little-endian [4] Frame data pointer increment/decrement (A) 0 = Decrement 1 = Increment [6:5] Widget alignment control (WA) (Non-aligned data must be transmitted without alignment control.) 00 = No invalid bytes 01 = One invalid byte 10 = Two invalid bytes 11 = Three invalid bytes [31] Ownership bit (0) 0 = CPU 1 = BDMA [30:0] Frame data pointer The address of the frame data to be transmitted. [15:0] Frame length The size of the transmit frame. [31:16] Tx status This Tx frame status field is updated by the MAC after transmission. [31:0] Next frame descriptor pointer The address of the next frame descriptor. Figure 7-7. Data Structure of Tx Frame Descriptor 7-18 S3C4510B ETHERNET CONTROLLER Rx Status 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R x H a l t e d O AR L vClx C o R I O eRi1 t G n x n v rCg0 i o p0g t 0M000 fEnS R o E a R a lrEt c d r r x x orra v r w rt [19] Over maximum size (OvMax) Set if the received frame data size exceeds the maximum frame size. [21] Control received (CtlRcv) Set if the received packet is a MAC control frame. [22] Interrupt on receive (IntRx) Set if reception of packet caused an interrupt condition. This includes Good received, if the Engood bit, MACRXCON [14], is set. [23] Receive 10 Mb/s status (Rx10stat) Set if packet was received over the 7-wire interface. Reset if packet was received over the MII. [24] Alignment error (AlignErr) Frame length in bits was not a multiple of eight and the CRC was invalid. [25] CRC Error (CRCErr) CRC at end of packet did not match the computed value, or else the PHY asserted Rx_er during packet reception. [26] Overflow error (Overflow) The MAC receive FIFO was full when it needed to store a received byte. [27] Long error (LongErr) Received a frame longer than 1518 bytes. Not set if the long enable bit set to one in the receive control register. [29] Receive parity error (RxPar) MAC receive FIFO has detected a parity error. [30] Good received (Good) Successfully received a packet with no errors. If EnGood = 1, an interrupt is generated on each packet that is received successfully. [31] Reception halted (RxHalted) Reception interrupted by user clearing RxEN or setting Haltlmm in the MAC control register. Figure 7-8. Rx Descriptor Status Bits 7-19 ETHERNET CONTROLLER S3C4510B Tx Status 31 30 29 28 27 26 25 24 23 22 21 20 19 R x H a l t e d L a t e C o l l P a u s e d T x D e f e r E x C o l l 16 C o m p T x p a r S Q E r r N C a r r D e f e r U n d e r I n t T x TxCollCnt [19:16] Transmit collision count (TxCollCnt) Count of collisions during transmission of a single packet. After 16 collisions, TxColl is zero, and ExColl is set. [20] Excessive collision (ExColl) 16 collisions occured in the same packet. [21] Transmit deferred (TxDefer) [22] Paused [23] Interrupt on transmit (IntTx) Set if transmission of packet caused an interrupt condition. This includes the enable completion (EnComp), MACTXCON [14], if enabled. [24] Underrun (Under) MAC transmit FIFO becomes empty during transmission. [25] Deferral (Defer) MAC defers for max_deferral 0.32768ms for 100Mbit/s or 3.27680ms for 10Mbit/s. [26] No carrier (NCarr) Carrier sense is not detected during the entire transmission of a packet (from the SFD to the CRC). [27] SQE error (SQErr) After transmit frame, set if the fake collision (COL) signal did not come from the PHY for 1.6 s. [28] Late collision (LateColl) A collision occurred after 512 bit times (64 byte times) [29] Transmit parity error (TxPar) MAC transmit FIFO detected a parity error. [30] Completion (Comp) MAC complete a transmit or discard of one packet. [31] Transmission halted (TxHalted) Transmission halted by clearing RxEn or setting the Haltlmm in the MAC control register. Or, an interrupt was generated by an error condition (not completion). Figure 7-9. Tx Descriptor Status Bits 7-20 S3C4510B ETHERNET CONTROLLER Frame Descriptor Start Address Register Frame Data Pointer #1 Status Frame Length Frame Data #1 Unused Frame Data #2 BDMARXLSZ Unused Receive Frame Maximum Size Register (BDMARXLSZ) Next Frame Descriptor Frame Data Pointer #2 (For Ring Type Linked List) Status Frame Length Next Frame Descriptor Frame Data #N BDMARXLSZ Frame Data Pointer #N Status Frame Length Memory for Frame Buffer In single linked lists, the last next frame descriptor is filled with a Null address Next Frame Descriptor Figure 7-10. Data Structure of the Receive Frame Data Buffer 7-21 ETHERNET CONTROLLER S3C4510B ETHERNET CONTROLLER SPECIAL REGISTERS The special registers used by the S3C4510B ethernet controller are divided into two main groups: -- BDMA control and status registers -- MAC control and status registers BDMA CONTROL AND STATUS REGISTERS All registers that contain a memory address must store the address in a word-aligned format. Table 7-2. BDMA Control and Status Registers Registers BDMATXCON BDMARXCON BDMATXPTR BDMARXPTR BDMARXLSZ BDMASTAT CAM BDMATXBUF (1) Offset 0x9000 0x9004 0x9008 0x900C 0x9010 0x9014 0x9100-0x917C 0x9200-0x92FC 0x9800-0x98FC 0x9900-0x99FC R/W R/W R/W R/W R/W R/W R/W W R/W R/W Description Buffered DMA transmit control register Buffered DMA receive control register Transmit frame descriptor start address Receive frame descriptor start address Receive frame maximum size Buffered DMA status CAM content (32 words) BDMA transmit (Tx) buffer (64 words) for test mode addressing only BDMA receive (Rx) buffer (64 words) for test mode addressing only Reset Value 0x00000000 0x00000000 0xFFFFFFFF 0xFFFFFFFF Undefined 0x00000000 Undefined Undefined Undefined BDMARXBUF (1) NOTES: 1. For testing, you can read the BDMA Tx/Rx buffer directly. The BDMA receive buffer has a 64 word by 33 bit size. The highest bit, [32], indicates the data frame boundary, as shown in the following illustration: 32 0x9800 31 0 0x9900 0x98FC 0x99FC EOF (End of Frame); Boundary of frame data. Figure 7-11. End of Frame Bit 2. You can access the EOF bit by reading the address range, 0x9800-0x98FC (read into LSB bit 0). 7-22 S3C4510B ETHERNET CONTROLLER Buffered DMA Transmit Control Register The buffered DMA transmit control register, BDMATXCON, is described in Tables 7-3 and 7-4 below. Table 7-3. BDMATXCON Register Registers BDMATXCON Offset 0x9000 R/W R/W Description Buffered DMA transmit control register Reset Value 0x00000000 Table 7-4. BDMA Transmit Control Register Description Bit Number [4:0] Bit Name BDMA Tx burst size (BTxBRST) BDMA Tx stop/skip frame by owner bit (BTxSTSKO) Reserved Description (Word size + 1) of data bursts requested in BDMA mode. If the BTxBRST is zero, the burst size is one word. If the BTxBRST is 31, the burst size is 32 words. This bit determines whether the BDMA Tx controller issues an interrupt, if enabled, or skips the current frame and goes to the next frame descriptor (assuming BDMA is not the owner). Not applicable. [5] [6] [7] BDMA Tx complete to send Setting this bit enables the BDMA Tx complete to send contol control packet interrupt enable packet interrupt when the MAC has finished sending the (BTxCCPIE) control packet. BDMA Tx Null list interrupt enable (BTxNLIE) This bit enables the BDMA Tx Null list interrupt which indicates that the transmit frame descriptor start address pointer, BDMATXPTR, in the BDMA Tx block has a null (0x00000000) address. This bit enables the BDMA Tx not owner interrupt when the ownership bit of the current frame does not belong to the BDMA controller, and if the BTxSTSKO bit is set. Set this bit is "1" to enable the Tx buffer empty interrupt. These bits determine when the new frame data in BDMA Tx buffer can be moved to the MAC Tx FIFO when a new frame arrives. 000 means no wait, 001 means wait to fill 1/8 of the BDMA Tx buffer, 010 means wait to fill 2/8 of the buffer, 011 for 3/8 and 1xx for 4/8. NOTE: If the last data of the frame arrives in BDMA Tx buffer, the data transfer from the BDMA Tx buffer to the MAC Tx FIFO starts immediately, regardless of the level of these bits. [8] [9] BDMA Tx not owner interrupt enable (BTxNOIE) BDMA Tx buffer empty interrupt enable (BTxEmpty) BDMA transmit to MAC Tx start level (BTxMSL) [10] [13:11] 7-23 ETHERNET CONTROLLER S3C4510B Table 7-4. BDMA Transmit Control Register Description (Continued) Bit Number [14] Bit Name BDMA Tx enable (BTxEn) Description When the Tx enable bit is set to "1", the BDMA Tx block is enabled. Even if this bit is disabled, buffer data will be moved to the MAC Tx FIFO until the BDMA Tx buffer underflows (as long as the FIFO is not empty and the MAC Tx is enabled). This bit is automatically disabled in the following cases: 1) if the next frame pointer is null, or 2) if the owner bit is zero, and the BTxSTSKO bit is set. NOTE: The frame descriptor start address pointer must be assigned before the BDMA Tx enable bit is set. [15] BDMA Tx reset (BTxRS) Set this bit to "1" to reset the BDMA Tx block. 7-24 S3C4510B ETHERNET CONTROLLER BDMATxCON Register 31 16 15 14 13 12 11 10 9 8 7 6 5 4 B T x R s B T x E n B T x M S L B T x E m p t y B T x N O I E B T x N L I E B T x C C P I E B T x M A I N C B T x S T S K O 0 Reserved BTxBRST [4:0] BDMA Tx burst size (BTxBRST) (Word size + 1) of data bursts reqested in BDMA mode. If BTxBRST is zero, the burst size is one word. If BTxBRST is 31, the burst size is 32 words. [5] BDMA Tx stop/skip frame by owner bit (BTxSTSKO) 0 = Skips the current frame and goes to the next frame descriptor (if BDMA is not the owner of the frame) 1 = BDMA transmitter generates an interrupt (if enabled). [6] Reserved [7] BDMA Tx complete to send control packet interrupt enable (BTxCCPIE) 0 = Disable complete to send control packet interrupt. 1 = Enable complete to send control packet interrupt. (The interrupt is generated when the MAC completes sending the control packet). [8] BDMA Tx Null list interrupt enable (BTxNLIE) 0 = Disable transmit Null list interrupt. 1 = Enable Null list interrupt to indicate that BDMATxPTR in the BDMA Tx unit has a Null address (0x00000000). [9] BDMA Tx not owner interrupt enable (BTxNOIE) 0 = Disable BDMA Tx not owner interrupt for the current frame. 1 = Enable BDMA Tx not owner interrupt for the current frame (and if the BTxSTSKO bit is set). [10] BDMA Tx buffer empty interrupt (BTxEmpty) 0 = Disable Tx buffer empty interrupt. 1 = Enable Tx buffer empty interrupt. [13:11] BDMA transmit to MAC Tx start level (BTxMSL) 000 = No waiting 010 = Wait to fill 2/8 of the Tx buffer 100 = Wait to fill 4/8 of the Tx buffer 001 = Wait to fill 1/8 of the Tx buffer 011 = Wait to fill 3/8 of the Tx buffer 1xx = Wait to fill 4/8 of the Tx buffer NOTE: Use this formula to calculate transmit time to the MAC Tx FIFO tBtOM: tBtOM = (BTxMSL/8) * size of the BDMA Tx buffer [14] BDMA Tx enable (BTxEn) 0 = Disable the BDMA transmitter. 1 = Enable the BDMA transmitter. [15] BDMA Tx reset (BTxRS) 0 = No effect. 1 = Reset the BDMA Tx block. Figure 7-12. Buffered DMA Transmit Control Register 7-25 ETHERNET CONTROLLER S3C4510B Buffered DMA Receive Control Register The buffered DMA receive control register, BDMARXCON, is described in Tables 7-5 and 7-6 below. Table 7-5. BDMA RXCON Register Register BDMARXCON Offset Address 0x9004 R/W R/W Description Buffered DMA receive control register Rest Value 0x00000000 Table 7-6. BDMA Receive Control Register Description Bit Number [4:0] Bit Name BDMA Rx burst size (BRxBRST) BDMA Rx stop/skip frame by owner bit (BRxSTSKO) BDMA Rx memory address inc/dec (BRxMAINC) BDMA Rx every received frame interrupt enable (BRxDIE) BDMA Rx Null list interrupt enable (BRxNLIE) Description (Word size + 1) of data bursts requested in BDMA mode. If the BRxBRST is zero, the burst size is one word. If the BRxBRST is 31, the burst size is 32 words. This bit determines whether the BDMA Rx controller issues an interrupt, if enabled, or skips the current frame and goes to the next frame descriptor (assuming BDMA is not the owner). This bit determines whether the address is incremented or decremented. If this bit is set to "1", the address will be incremented. This bit enables the BDMA Rx every received frame interrupt which is generated by the BDMA controller each time is moves a complete data frame into memory. This bit enables the BDMA Rx null list interrupt which indicates that the receive frame descriptor start address pointer, BDMARXPTR, in the BDMA Rx block has a null (0x00000000) address. This bit enables the BDMA Rx not owner interrupt when the ownership bit of the current frame does not belong to the BDMA controller, and if the BRxSTSKO bit is set. [5] [6] [7] [8] [9] BDMA Rx not owner interrupt enable (BRxNOIE) [10] BDMA Rx maximum size over This bit enables the BDMA Rx maximum size over interrupt interrupt enable (BRxMSOIE) when the received frame size is larger than the value in receive frame maximum size register. BDMA Rx Big/Little Endian (BRxLittle) BDMA Rx word alignment (BRxWA) This bit determines whether the data is stored in Little- or BigEndian format. If it is set to "1", word swapping will take place between the receive buffer and the system data bus. The Rx word alignment bits determine how many bytes are invalid in the first word of each data frame. These invalid bytes are inserted when the word is assembled by the BDMA controller. "00" = No invalid bytes, "01" = 1 invalid byte, "10" = 2 invalid bytes, and "11" = 3 invalid bytes. [11] [13:12] 7-26 S3C4510B ETHERNET CONTROLLER Table 7-6. BDMA Receive Control Register Description (Continued) Bit Number [14] Bit Name BDMA Rx enable (BRxEn) Description When the Rx enable bit is set to "1", the BDMA Rx block is enabled. Even if this bit is disabled, the MAC will receive Rx data until the MAC Rx FIFO overflows (as long as the FIFO is not empty and the MAC Rx is enabled). This bit is automatically disabled in the following cases: 1) if the next frame pointer is Null, or 2) if the owner bit is zero, and the BRxSTSKO bit is set. NOTE: The frame descriptor start address pointer must be assigned before the BDMA Rx enable bit is set. [15] [16] [17] BDMA Rx reset (BRxRS) BDMA Rx buffer empty interrupt enable (BRxEmpty) BDMA Rx early notify interrupt enable (BRxEarly) Set this bit to "1" to reset the BDMA Rx block. Set this bit is "1" to enable the Rx buffer empty interrupt. Set this bit to "1" to enable the Rx early notify interrupt. The function of this interrupt is to note the length of a data frame that is being received from its frame length field. 7-27 ETHERNET CONTROLLER S3C4510B BDMARxCON Register 31 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 B R x E a r l y B R x E m p t y B R x L i t t l e B R x M S O I E B R x N O I E B R x N L I E B R x M A I N C B R x S T S K O 0 Reserved B R x R S B R x E n B R x W A B R x D I E BRxBRST [4:0] BDMA Rx burst size (BRxBRST) Burst data size = ( BRxBRST + 1 ) word. [5] BDMA Rx stop/skip frame (or interrupt if not owner of the current frame (BRxSTSKO) 0 = Skips the current frame and goes to the next frame descriptor. 1 = BDMA receiver generates an interrupt (if enabled). [6] BDMA Rx memory address increment/decrement (DRxMAINC) 0 = Decrement the frame memory address. 1 = Increment the frame memory address. [7] BDMA Rx every receuve frane interrupt enable (BRxDIE) 0 = Disable frame receive done interrupt. 1 = Enable frame receive done interrupt. [8] BDMA Rx Null list interrupt enable (BRxNLIE) 0 = Disable Null address (0x00000000) receive interrupt. 1 = Enable Null address (0x00000000) receive interrupt. [9] BDMA Rx not owner interrupt enable (BRxNOIE) 0 = Disable interrupt for BDMA Rx not owner of the current frame. 1 = Enable interrupt for BDMA Rx not onwer of the current frame. [10] BDMA Rx maximum size over interrupt enable (BRxMSOIE) 0 = Disable interrupt for received frame if larger than the maximum frame size. 1 = Enable interrupt for received frame if larger than the maximum frmae size. [11] BDMA Rx Big/Little Endian (BRxLittle) 0 = Big-Endian frame data format. 1 = Little-Endian. (Frame data in BDMA Rx buffer is word-swapped on the system bus). [13:12] BDMA Rx word alignment (BRxWA) 00 = Do not insert an invalid byte in the first received frame data. 01 = Insert one invalid byte in the first received frame data. 10 = Insert two invalid bytes in the firat received frame data. 11 = Insert three invalid bytes in the first received frame data. [14] BDMA Rx enable (BRxEn) 0 = Disable the BDMA receiver. (If the MAC Rx FIFO is not empty, move data to the BDMA Rx buffer). 1 = Enable the BDMA receiver. [15] BDMA Rx reset (BRxRs) 0 = No effect. 1 = Reset the BDMA receiver. [16] BDMA Rx buffer empty interrupt (RxEmpty) 0 = Disable the Rx buffer empty interrupt. 1 = Enable the Rx buffer empty interrupt. [17] BDMA Rx early notify interrupt (BRxEarly) 0 = Disable the Rx early notify interrupt. 1 = Enable the interrupt when BDMA captures the length of the received frame type. Figure 7-13. Buffered DMA Receiver Control Register 7-28 S3C4510B ETHERNET CONTROLLER BDMA Transmit Frame Descriptor Start Address Register Table 7-7. BDMATXPTR Register Registers BDMATXPTR Offset 0x9008 R/W R/W Description Buffered DMA transmit control register Reset Value 0xFFFFFFFF Table 7-8. BDMA Transmit Frame Descriptor Start Address Register Description Bit Number [25:0] Bit Name BDMA transmit frame descriptor start address Description The BDMA transmit frame descriptor start address register contains the address of the frame descriptor on the frame to be sent. During a BDMA operation, this start address pointer is updated to the next frame address. BDMA Receive Frame Descriptor Start Address Register Table 7-9. BDMARXPTR Register Registers BDMARXPTR Offset 0x900C R/W R/W Description Buffered DMA transmit control register Reset Value 0xFFFFFFFF Table 7-10. BDMA Receive Frame Descriptor Start Address Register Description Bit Number [25:0] Bit Name BDMA receive frame descriptor start address Description The BDMA receive frame descriptor start address register contains the address of the frame descriptor on the frame to be saved. During a BDMA operation, this start address pointer is updated to the next frame address. 7-29 ETHERNET CONTROLLER S3C4510B BDMA Receive Frame Maximum Size Register Table 7-11. BDMARXLSZ Register Registers BDMARXLSZ Offset 0x9010 R/W R/W Description Receive frame maximum size Reset Value Undefined Table 7-12. BDMA Receive Frame Maximum Size Register Description Bit Number [15:0] Bit Name BDMA receive frame maximum size (BRxLSZ) BDMA receive frame length (BRxFSZ), read-only Description This register value controls how many bytes per frame can be saved to memory. If the received frame size exceeds the value stored in this location, an error condition is reported. When an early notification (early notify) interrupt occurs, the frame Length/Ethernet type field contains the Frame size of the frame that is currently being received. To save space in the frame memory buffer, you can determine the current frame length by 1) enabling the early notification interrupt, and 2) reading the BRxFSZ field when the interrupt occurs. To calculate the value of the next frame start address pointer, you add the current frame size value (BRxFSZ) to the BDMA receive start address register. (For a control packet, additional space may be needed.) NOTE: To obtain the next Rx frame address that is to be saved in the Rx frame start address register, we recommend that you first halt the BDMA operation. BDMA Status Register Table 7-13. BDMASTAT Register Registers BDMASTAT Offset 0x9014 R/W R/W Description Buffered DMA status Reset Value 0x00000000 [31:16] 7-30 S3C4510B ETHERNET CONTROLLER Table 7-14. BDMA Status Register Description Bit Number [0] Bit Name BDMA Rx done every received frame (BRxRDF) BDMA Rx null list (BRxNL) Description This bit is set each time the BDMA receiver moves one received data frame to memory. This bit must be cleared for the receiving next frame interrupt generation. If this bit is set, the BDMARXPTR has a null address. Even if BDMA Rx is disabled, data is transferred from the MAC Rx FIFO to the BDMA Rx buffer until the BDMA Rx buffer overflows. [1] [2] [3] [4] [5] [6] [7] BDMA Rx not owner (BRxNO) If this bit is set, BDMA is not the owner of the current data frame. The BRxSTSKO bit is set and BDMA Rx is stopped. BDMA Rx maximum size over If this bit is set, the received frame size is larger than the value (BRxMSO) in the Rx frame maximum size register, BDMARXLSZ. BDMA Rx buffer empty (BRxEmpty) Early notification (BRxSEarly) Reserved One more frame data in BDMA receive buffer (BRxFRF) Number of frames in BDMA receive buffer (BRxNFR) BDMA Tx complete to send control packet (BTxCCP) BDMA Tx null list (BTxNL) If this bit is set, the BDMA Rx buffer is empty. This bit is set when the BDMA receiver has received the length/Ether-type field of the current frame. Not applicable. This bit is set whenever an additional data frame is received in the BDMA receive buffer. This value indicates the total number of data frames currently in the BDMA receive buffer. Bit [16] is set each time the MAC sends a complete control packet. If this bit is set, the BDMATXPTR value is a null address. In this case, BDMA Tx is disabled but data continues to be transferred from the BDMA Tx buffer to the MAC Tx FIFO until the BDMA Tx buffer underflows. This bit is read only. If you set BDMA Tx reset bit by software, this bit is cleared automatically. To resume data transfer, you must then set the new frame descriptor pointer and enable BDMA Tx. If [18] is set, BDMA is not owner of the current frame. In this case, the BSTSKO bit is set and BDMA Tx is stopped. Not applicable. If this bit is set, the BDMA Tx buffer is empty. Not applicable. [15:8] [16] [17] [18] [19] [20] [31:21] BDMA Tx not owner (BTxNO) Reserved BDMA Tx buffer empty (BTxEmpty) Reserved 7-31 ETHERNET CONTROLLER S3C4510B 31 21 20 19 18 17 16 15 B T x E X m p t y B T x C C P 8 7 6 5 B R x S E a r l y 4 B R x E m p t y 3 2 1 0 Reserved B T x N O B T x N L BRxNFR B R x F R F X B R x M S O B R x N O B R x N L B R x R D F [0] BDMA Rx done evert received frame (BRxRDF) 0 = Reset frame data receive state. 1 = Receipt of the data frame is complete. [1] BDMA Rx Null list (BRxNL) 0 = Reset state of new frame descriptor (BDMARXPTR) is set. 1 = Current frame descriptor address is Null (0x00000000). [2] BDMA Rx not owner (BRxNO) 0 = BDMA is owner of the current frame. 1 = The owner of the current frame is not BDMA (CPU). In this case, BDMA Rx is stopped and the BSTSKO bit is set. [3] BDMA Rx maximum size over (BRxMSO) 0 = Reset state or next frame arrived at BDMA Rx buffer. 1 = Received frame exceeds the maximum frame size. [4] BDMA Rx buffer empty (BRxEmpty) 0 = Not empty. 1 = BDMA Rx buffer empty. [5] Early notify (BRxSEarly) 0 = Normal operation. 1 = Lengthe of current frame can be accessed by reading the BDMA receive maximum frame size register, BDMARXLSZ [31:16]. [7] One more frame data in BDMA receive buffer (BRxFRF) 0 = Only one frame data in BDMA receive buffer. 1 = One more frame data was in the BDMA receive buffer. [15:8] Number of frame data in BDMA receive buffer (BRxNFR) [16] BDMA Tx complete to send control packet (BTxCCP) 0 = Clear but by writing a 1 to this bit or by resetting BDMA Tx. 1 = MAC complete to send the control packet. [17] BDMA Tx Null list (BTxNL) 0 = Reset stste of new frame descriptor (BDMATXPTR) is set. 1 = Current frame descriptor address is Null (0x00000000). [18] BDMA Tx not owner (BTxNO) 0 = BDMA is owner of the current frame. 1 = The owner of the current frame is not BDMA (CPU). In this case, BDMA Tx is stopped if the BTxSTSKO bit is set to one. [19] Reserved [20] BDMA Tx buffer empty (BTxEmpty) 0 = Not empty 1 = BDMA Tx buffer empty. [31:21] Reserved NOTE: Bit 0, 1, 2, 3, 4, 16, 17, 18 and 20 should be cleared for interrupt generation for the next frame. The method is write 1 to the corresponding bit location. Figure 7-14. BDMA Status Register 7-32 S3C4510B ETHERNET CONTROLLER Content Address Memory (CAM) Register There are 21 CAM entries for the destination address and the pause control packet. For the destination address CAM value, one destination address consists of 6 bytes. Using the 32-word space (32 x 4 bytes), you can therefore maintain up to 21 separate destination addresses. You use CAM entries 0, 1, and 18 to send pause control packets. To send a pause control packet, you write the CAM0 entry with the destination address, the CAM1 entry with the source address, and the CAM 18 entry with length/type, opcode, and operand. You then set the send pause bit in the MAC transmit control register. Table 7-15. CAM Register Registers CAM Offset 0x9100-0x917C R/W W Description CAM content (32 words) Reset Value Undefined Table 7-16. Content Address Memory (CAM) Register Description Bit Number [31:0] Bit Name CAM content (CAM) Description The CPU uses the CAM content register as a data base for destination address. To activate the CAM function, you must set the appropriate enable bits in CAM enable register. 7-33 ETHERNET CONTROLLER S3C4510B MEDIA ACCESS CONTROL (MAC) REGISTERS This section describes the control and status registers for the flow control 100-/10-Mbit/s ethernet MAC. These include a master MAC control register, control registers for transmit and receive, control registers for the CAM, a counter for network management, and various flow control registers (see Table 7-17). Table 7-17. MAC Control and Status Registers Registers MACON CAMCON MACTXCON MACTXSTAT MACRXCON MACRXSTAT STADATA STACON CAMEN EMISSCNT EPZCNT ERMPZCNT ETXSTAT Offset 0XA000 0xA004 0xA008 0xA00C 0xA010 0xA014 0xA018 0xA01C 0xA028 0xA03C 0xA040 0xA044 0x9040 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RClr/W R R R MAC control CAM control Transmit control Transmit status Receive control Receive status Station management data Station management control and address CAM enable Missed error count Pause count Remote pause count Transmit control frame status Description Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00006000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 NOTE: MAC transmit/receive interrupt is generated whenever the Tx/Rx status field of Tx/Rx frame descriptor is written. 7-34 S3C4510B ETHERNET CONTROLLER MAC Control Register The MAC control register provides global control and status information for the MAC. The missed roll/link10 bit is a status bit. All other bits are MAC control bits. MAC control register settings affect both transmission and reception. You can also control transmit and receive operations separately. To select customized operating features, you should write this register during power-up. This way, you will not need to write or read it again during normal operation. After a reset is complete, the MAC controller clears the reset bit. Not all PHYs support full-duplex operation. (setting the MAC loopback bit overrides the full-duplex bit.) Also, some 10-Mb/s PHYs may interpret the loop10 bit to control different functions, and manipulate the link10 bit to indicate a different status condition. Table 7-18. MACON Register Registers MACON Offset 0XA000 R/W R/W MAC control Description Reset Value 0x00000000 Table 7-19. MAC Control Register Description Bit Number [0] [1] [2] [3] [4] [5] [6] Bit Name Halt request (HaltReq) Halt immediate (HaltImm) Software reset (Reset) Full-duplex (FullDup) MAC loopback (MACLoop) Reserved MII-OFF Description Set this bit to stop data packet transmission and reception as soon as Tx/Rx of any current packets has been completed. Set this bit to immediately stop all transmission and reception. Set this bit to reset all MAC control and status register and MAC state machines. Set this bit to start transmission while reception is in progress. Set this bit to cause transmission signals to be presented as input to the receive circuit without leaving the controller. Not applicable Use this bit to select the connection mode. If this bit is set to one, 10 M bits/s interface will select the 10 M bits/s endec. Otherwise, the MII will be selected. If this bit is set, the Loop_10 external signal is asserted to the 10-Mb/s endec. Not applicable. This bit is automatically set when the missed error counter rolls over. Not applicable. Clear this bit to enable the MDC clock generation for power management. If it is set to one, the MDC clock generation is disabled. Set this bit to generate an interrupt whenever the missed error counter rolls over. Not applicable This bit value is read as a buffered signal on the link 10 pin. Not applicable. [7] [9:8] [10] [11] [12] Loop 10 Mb/s (Loop10) Reserved Missed roll (MissRoll) Reserved MDC-OFF [13] [14] [15] [31:16] Enable missed roll (EnMissRoll) Reserved Link status 10 Mb/s (Link10) Reserved 7-35 ETHERNET CONTROLLER S3C4510B CAM Control Register The three accept bits in the CAM control register are used to override CAM rejections. To place the MAC in promiscuous mode, use CAM control register settings to accept packets with all three types of destination addresses. The three types of destination address packets are as follows: -- Station packets, which has an even first byte. For example, 00-00-00-00-00-00. -- A multicast-group, which has an odd first byte, but which is not FF-FF-FF-FF-FF-FF. For example, 01-00-0000-00-00. -- A broadcast, defined as FF-FF-FF-FF-FF-FF. When you enable CAM compare mode, the CAM memory reads the destination addresses to filter incoming messages. (You will recall that the CAM memory consists of 6-byte entries.) An alternative way to place the MAC in promiscuous mode is to set, in turn, to accept the them. To reject all packets, simply clear all of the bits in the CAMCON register. Table 7-20. CAMCON Register Registers CAMCON Offset 0XA004 R/W R/W CAM control Description Reset Value 0x00000000 Table 7-21. CAM Control Register Description Bit Number [0] [1] [2] [3] Bit Name Station accept (StationAcc) Group accept (GroupAcc) Broadcast accept (BroadAcc) Negative CAM (NegCAM) Description Set this bit to accept any packet with a "unicast" station address. Accept any packet with a multicast-group address. Accept any packet with a broadcast address. When this bit is "0", packets the CAM recognizes are accepted and others are rejected. When "1", packets the CAM recognizes are rejected and others are accepted. Set this bit to enable compare mode. Not applicable. [4] [31:5] Compare enable (CompEn) Reserved 7-36 S3C4510B ETHERNET CONTROLLER MAC Transmit Control Register To generate an interrupt after each packet, set the enable completion bit and all of the MAC error enable bits. Using MAC transmit control register settings, you can also selectively enable interrupts for specific conditions. Table 7-22. MACTXCON Register Registers MACTXCON Offset 0XA008 R/W R/W Description Transmit control Reset Value 0x00000000 Table 7-23. MAC Transmit Control Register Description Bit Number [0] [1] [2] [3] [4] [5] [6] Bit Name Transmit enable (TxEn) Transmit halt request (TxHalt) Suppress padding (NoPad) Suppress CRC (NoCRC) Fast back-off (FBack) No defer (NoDef) Send Pause (SdPause) Description Set this bit to enable transmission. To stop transmission immediately, clear the transmit enable bit to "0". Set this bit to halt transmission after completing any current packet. Set to not generate pad bytes for packets of less than 64 bytes. Set to suppress addition of a CRC at the end of a packet. Set this bit to use faster back-off times for testing. Set to disable the defer counter. (The defer counter keeps counting until the carrier sense (CrS) bit is turned off.) Set this bit to send a pause command or other MAC control packet. The send pause bit is automatically cleared when a complete MAC control packet has been transmitted. Writing a "0" to this register bit has no effect. Set this bit to enable MII 10-Mb/s SQE test mode. Set this bit to generate an interrupt if the MAC transmit FIFO is empty during a transmission. Set this bit to generate an interrupt if the MAC defers for MAX_DEFERRAL time: "0" = 0.32768 ms at 100 Mb/s; "1" = 3.2768 ms at 10-Mb/s. Set this bit to generate an interrupt if a carrier sense is not detected while an entire packet is transmitted. Set this bit to enable an interrupt if 16 collisions occur in the same packet. Set this bit to generate an interrupt if a collision occurs after 512 bit times (or 64 byte times). Set this bit to generate an interrupt if a parity error is detected in the MAC transmit FIFO. Set this bit to generate an interrupt whenever the MAC transmits or discards one packet. Not applicable. [7] [8] [9] MII 10-Mb/s SQE test mode enable (SQEn) Enable underrun (EnUnder) Enable deferral (EnDefer) [10] [11] [12] [13] [14] [31:15] Enable no carrier (EnNCarr) Enable excessive collision (EnExColl) Enable late collision (EnLateColl) Enable transmit parity (EnTxPar) Enable completion (EnComp) Reserved 7-37 ETHERNET CONTROLLER S3C4510B MAC Transmit Status Register A transmission status flag is set in the transmit status register, MACTXSTAT, whenever the corresponding event occurs. In addition, an interrupt is generated if the corresponding enable bit in the transmit control register is set. A MAC transmit FIFO parity error sets TxPar, and also clears TxEn, if the interrupt is enabled. You can read and mask the five low-order bits as a single collision count. That is, when ExColl is "1", TxColl is "0". If TxColl is not "0", then ExColl is "0". Table 7-24. MACTXSTAT Register Registers MACTXSTAT Offset 0XA00C R/W R/W Description Transmit status Reset Value 0x00000000 Table 7-25. MAC Transmit Status Register Description Bit Number [3:0] [4] [5] [6] [7] [8] [9] Bit Name Transmit collision count (TxColl) Excessive collision (ExColl) Description [10] [11] [12] [13] [14] [15] [31:16] This 4-bit value is the count of collisions that occurred while successfully transmitting the packet. This bit is set if 16 collisions occur while transmitting the same packet. In this case, packet transmission is aborted. Transmit deferred (TxDeferred) This bit is set if transmission of a packet was deferred because of a delay during transmission. Paused (Paused) This bit is set if transmission of a packet was delayed due to a Pause being received. Interrupt on transmit (IntTx) This bit is set if transmission of a packet causes an interrupt condition. Underrun (Under) This bit is set if the MAC transmit FIFO becomes empty during a packet transmission. Deferral (Defer) This bit is set if the MAC defers a transfer because of MAX_DEFERRAL at 0.32768 ms for 100 Mb/s or 3.2768 ms for 10Mb/s. No carrier (NCarr) This bit is set if no carrier sense is detected during the transmission a packet. Signal quality error (SQE) According to the IEEE802.3 rule, the SQE signal reports the status of the PMA (MAU or transceiver) operation to the MAC layer. After transmission is complete and 1.6 s has elapsed, a collision detection signal is issued for 1.5 s to the MAC layer. This signal is called the SQE test signal. The MAC sets the SQE bit in the MACTXSTAT register if this signal is not reported within the IFG time of 6.4s. Late collision (LateColl) This bit is set if a collision occurs after 512 bit times (or 64 byte times). Transmit parity error (TxPar) This bit is set if a collision occurs after 512 bit times (or 64 byte times). Completion (Comp) This bit is set when the MAC transmits, or discards, one packet. Transmission halted (TxHalted) Transmission was halted by clearing the TxEn bit or the halt immediate (HaltImm) bit. Reserved Not applicable. 7-38 S3C4510B ETHERNET CONTROLLER MAC Receive Control Register To issue an interrupt after each packet is received, set the enable good bit and all of the error enable bits in the MACRXCON register. You can also enable interrupts for specific conditions. Standard packet length values do not include a preamble or a start frame delimiter (SFD). Table 7-26. MACRXCON Register Registers MACRXCON Offset 0XA010 R/W R/W Description Receive control Reset Value 0x00000000 Table 7-27. MAC Receive Control Register Description Bit Number [0] [1] [2] [3] [4] [5] [6] [7] [8] Bit Name Receive enable (RxEn) Receive halt request (RxHalt) Long enable (LongEn) Short enable (ShortEn) Strip CRC value (StripCRC) Pass control packet (PassCtl) Ignore CRC value (IgnoreCRC) Reserved Enable alignment (EnAlign) Description Set this bit to "1" to enable MAC receive operation. If "0", stop reception immediately. Set this bit to halt reception after completing the reception of any current packet. Set this bit to receive frames with lengths greater than 1518 bytes. Set this bit to receive frames with lengths less than 64 bytes. Set this bit to check the CRC, and then strip it from the message. Set this bit to enable the passing of control packets to a MAC client. Set this bit to disable CRC value checking. Not applicable. Set this bit to enable the alignment interrupt. An alignment interrupt occurs when a packet is received whose length (in bits) is not a multiple of eight, and whose CRC is invalid. Set this bit to enable the CRC interrupt. A CRC interrupt occurs when a packet is received whose CRC is invalid or if, during its reception, the PHY asserts Rx_er. Set this bit to enable the overflow interrupt. An overflow interrupt is generated when a packet is received and the MAC receive FIFO is full. [9] Enable CRC error (EnCRCErr) Enable overflow (EnOver) [10] [11] [12] [13] [14] [31:15] Enable long error (EnLongErr) Set this bit to enable the long error interrupt. A long error interrupt is generated when a frame longer than 1518 bytes is received (unless the long enable bit is set). Reserved Not applicable. Enable receive parity (EnRxPar) Enable Good (EnGood) Reserved Set this bit to enable a receive parity interrupt if the MAC receive FIFO detects a parity error. Set this bit to enable the good (packet) interrupt upon error-free reception of a complete data packet. Not applicable. NOTE: The frame lengths given above do not include preamble and start frame delimiter (SFD). 7-39 ETHERNET CONTROLLER S3C4510B MAC Receive Status Register A receive status flag is set in the MAC receive status register, MACRXSTAT, whenever the corresponding event occurs. When a status flag is set, it remains set until another packet arrives, or until software writes a "1" to the flag to clear the status bit. If the corresponding interrupt enable bit in the receive control register is set, an interrupt is generated whenever a status flag is set. A MAC receive parity error sets RxPar, and also clears the RxEn bit (if an interrupt is enabled). Table 7-28. MACRXSTAT Register Registers MACRXSTAT Offset 0XA014 R/W R/W Receive status Description Reset Value 0x00000000 Table 7-29. MAC Receive Status Register Description Bit Number [4:0] [5] Reserved Bit Name Not applicable. Description Control frame received (CtlRecd) This bit is set if the packet received is a MAC control frame (type = 8808H), if the CAM recognizes the packet address, and if the frame length is 64 bytes. Interrupt on receive (IntRx) This bit is set if the reception of a packet caused an interrupt to be generated. This includes a good received interrupt, if the EnGood bit is set. This bit is set to "1" if a packet was received over the 7-wire interface or to "0" if a packet was received over the MII. This bit is set if the frame length in bits was not a multiple of eight and the CRC was invalid. This bit is set if the CRC at the end of a packet did not match the computed value, or else the PHY asserted Rx_er during packet reception. This bit is set if the MAC receive FIFO was full when it needed to store a received byte. This bit is set if the MAC received a frame longer than 1518 bytes. (It is not set if the long enable bit in the receive control register, MACRXCON, is set.) Not applicable. This bit is set if a parity error is detected in the MAC receive FIFO. This bit is set if a packet was successfully received with no errors. If EnGood = "1", an interrupt is also generated. This bit is set if reception was halted by clearing RxEn or by setting the HaltImm bit in the MAC control register, MACON. Not applicable. [6] [7] [8] [9] Receive 10-Mb/s status (Rx10Stat) Alignment error (AlignErr) CRC error (CRCErr) [10] [11] Overflow error (overflow) Long error (LongErr) [12] [13] [14] [15] Reserved Receive parity error (RxPar) Good received (Good) Reception halted (RxHalted) [31:16] Reserved 7-40 S3C4510B ETHERNET CONTROLLER MAC Station Management Data Register Table 7-30. STADATA Register Registers STADATA Offset 0XA018 R/W R/W Description Station management data Reset Value 0x00000000 Table 7-31. Station Management Register Description Bit Number [15:0] Bit Name Station management data. Description This register contains a 16-bit data value for the station management function. 7-41 ETHERNET CONTROLLER S3C4510B MAC Station Management Data Control and Address Register The MAC controller provides support for reading and writing station management data to the PHY. Setting options in station management registers does not affect the controller. Some PHYs may not support the option to suppress preambles after the first operation. Table 7-32. STACON Register Registers STACON Offset 0XA01C R/W R/W Description Station management control and address Reset Value 0x00008000 Table 7-33. STACON Register Description Bit Number [4:0] [9:5] [10] [11] Bit Name PHY register address (Addr) PHY address (PHY) Write (Wr) Busy bit (Busy) Description A 5-bit address, contained in the PHY, of the register to be read or written. The 5-bit address of the PHY device to be read or written. To initiate a write operation, set this bit to "1". For a read operation, clear it to "0". To start a read or write operation, set this bit to "1". The MAC controller clears the Busy bit automatically when the operation is completed. If you set this bit, the preamble is not sent to the PHY. If it is clear, the preamble is sent. Control the MDC period. MD_CA[15:13] MDC period 000 001 010 . . [12] [15:13] Preamble suppress (PreSup) MDC clock rating 16 x (1/fMCLK) 18 x (1/fMCLK) 20 x (1/fMCLK) . . 111 30 x (1/fMCLK) MDC period = MD_CA[15:13] x 2 + 16 Default MDC_CA[15:13] = 100 [31:16] Reserved Not applicable. 7-42 S3C4510B ETHERNET CONTROLLER CAM Enable Register The CAM enable register, CAMEN, indicates which CAM entries are valid, using a direct comparison mode. Up to 21 entries, numbered 0 through 20, may be active, depending on the CAM size. If the CAM is smaller than 21 entries, the higher bits are ignored. Table 7-34. CAMEN Register Registers CAMEN Offset 0XA028 R/W R/W CAM enable Description Reset Value 0x00000000 Table 7-35. CAM Enable Register Description Bit Number [20:0] Bit Name CAM enable (CAMEn) Description Set the bits in this 21-bit value to selectively enable CAM locations 20 through 0. To disable a CAM location, clear the appropriate bit. Not applicable. [31:21] Reserved 7-43 ETHERNET CONTROLLER S3C4510B MAC Missed Error Count Register The value in the missed error count register, EMISSCNT, indicates the number of packets that were discarded due to various type of errors. Together with status information on packets transmitted and received, the missed error count register and the two pause count registers provide the information required for station management. Reading the missed error counter register clears the register. It is then the responsibility of software to maintain a global count with more bits of precision. The counter rolls over from 0x7FFF to 0x8000 and sets the corresponding bit in the MAC control register. It also generates an interrupt if the corresponding interrupt enable bit is set. If station management software wants more frequent interrupts, you can set the missed error count register to a value closer to the rollover value of 0x7FFF. For example, setting a register to 0x7F00 would generate an interrupt when the count value reaches 256 occurrences. Table 7-36. EMISSCNT Register Registers EMISSCNT Offset 0XA03C R/W R(Clr)/W Description Missed error count Reset Value 0x00000000 Table 7-37. Missed Error Count Register Description Bit Number [15:0] Bit Name Alignment error count (AlignErrCnt) CRC error count (CRCErrCnt) Description The number of packets received with alignment errors. This software counter increments at the end of a packet reception if the Rx_Stat value indicates an alignment error. The number of packets received with a CRC error. This software counter increments if the Rx_Stat value indicates a CRC error. If the Rx_Stat value indicates another type of error, such as an alignment error, this counter is not incremented. The number of valid packets rejected by the MAC unit because of MAC receive FIFO overflows, parity errors, or because the Rx_En bit was cleared. This count does not include the number of packets rejected by the CAM. Not applicable. Missed error count (MissErrCnt) [31:16] Reserved 7-44 S3C4510B ETHERNET CONTROLLER MAC Received Pause Count Register The received pause count register, EPZCNT, stores the current value of the 16-bit received pause counter. Table 7-38. EPZCNT Register Registers EPZCNT Offset 0XA040 R/W R Pause count Description Reset Value 0x00000000 Table 7-39. Received Pause Count Register Description Bit Number [15:0] Bit Name Received pause count (EPZCNT) Description The count value indicates the number of time slots the transmitter was paused due to the receipt of control pause operation packets from the MAC. MAC Remote Pause Count Register The remote Pause count register, ERMPZCNT, stores the current value of the 16-bit remote Puase counter. Table 7-40. ERMPZCNT Register Registers ERMPZCNT Offset 0XA044 R/W R Description Remote pause count Reset Value 0x00000000 Table 7-41. Remote Pause Count Register Description Bit Number [15:0] Bit Name Received pause count (EPZCNT) Description The count value indicates the number of time slots that a remote MAC was paused as a result of its sending control pause operation packets. 7-45 ETHERNET CONTROLLER S3C4510B MAC Transmit Control Frame Status The transmit control frame status register, ETXSTAT, is a RAM-based register which provides the status of a MAC control packet as it is sent to a remote station. This operation is controlled by the SdPause bit in the transmit control register, MACTXCON. It is the responsibility of the DMA engine to read this register, and to generate an interrupt to notify the system that the transmission of a MAC control packet has been completed. Table 7-42. ETXSTAT Register Registers ETXSTAT Offset 0X9040 R/W R Description Transmit control frame status Reset Value 0x00000000 Table 7-43. Transmit Control Frame Register Description Bit Number [15:0] Bit Name Tx_Stat value Description A 16-bit value indicating the status of a MAC control packet as it is sent to a remote station. Read by the DMA engine. 7-46 S3C4510B ETHERNET CONTROLLER ETHERNET CONTROLLER OPERATIONS This section contains additional details about the following operations of the S3C4510B ethernet controller: -- MAC frame and packet formats -- Transmitting a frame -- Receiving a frame -- Full-duplex pause operation -- Error signalling and network management MAC Frame and Packet Formats The MAC transmits each byte of all fields, except the FCS, least-significant bit first. In this document, the term "packet" is used to denote all of the bytes that are transmitted and received, while "frame" refers only to the bytes delivered by the station for transmission, and to the station who is receiving. Table 7-44 lists the eight fields in a standard data packet (IEEE 802.3/Ethernet frame). See also Figure 7-13. Table 7-44. MAC Frame and Package Format Description Field Name Preamble Start frame delimiter (SFD) Destination address Source address Field Size 7 bytes 1 byte 6 bytes 6 bytes Description The bits in each preamble byte are 10101010, transmitted from left to right. The SFD bits are 10101011, transmitted from left to right. The destination address can be an individual address or a multicast (or broadcast) address. The MAC does not interpret the source address bytes. However, to qualify as a valid station address, the first bit transmitted (the LSB of the first byte) must be a "0". The MAC treats length fields greater than 1500 bytes as type fields. Byte values less than or equal to 1500 indicate the number of logical link control (LLC) data bytes in the data field. The MAC transmits the high-order byte first. Length or type 2 bytes Logical link control (LLC) data PAD Frame check sequence (FCS) 46 to 1500 bytes Data bytes used for logical link control. 0 to 46 bytes 4 bytes If the LLC data is less than 46 bytes long, the MAC transmits pad bytes of all zeros. The FCS field contains a 16-bit error detection code that is computed as a function of all fields except the preamble, the SFD, and the FCS itself. The FCS - 32 polynomial function is as follows: " X32 + X26 + X23 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X1 + 1". 7-47 ETHERNET CONTROLLER S3C4510B Packet (Encoded on the Medium) Added by Transmitter, Stripped by Receiver S F D 1 Data Frame (sent by user) Data frame (delivered to user) Added by transmitter Optionaly stripped by receiver LLC data 46-1500 bytes PAD FCS Preamble Destination Address 6 bytes Source Address 6 bytes Length or type 2 bytes 7 bit 0-46 4 bytes LLC header DSAP OR DSAP 1 byte SSAP 1 byte CTRL SSAP CTRL LLC information field IP/X.25/...... SNAP OUI PID IP/X.25/...... 1 byte 3 bytes 2 bytes SSAP = Source service access point SNAP = Subnetwork access protocol PID = Protocol identifier LLC = Logical lick control FCS = Frame check sequence DSAP = Destination service access point CTRL = Control field OUI = Origanizationally unique identifier SFD = Starting frame delimiter Figure 7-15. Fields of an IEEE802.3/Ethernet Packet (Frame) Options That Affect the Standard MAC Frame There are a number of factors and options which can affect the standard MAC frame, as described in Table 7-44: -- Some PHYs may deliver a longer or shorter preamble. -- Short packet mode permits LLC data fields with less than 46 bytes. Options are available to suppress padding and to support the reception of short packets. -- Long packet mode supports LLC data fields with more than 1500 bytes. An option is also available to support to reception of long packets. -- "No CRC" mode suppresses the appending of a CRC field. -- "Ignore CRC" mode allows the reception of packets without valid CRC fields. 7-48 S3C4510B ETHERNET CONTROLLER Destination Address Format Bit 0 of the destination address is an address type designation bit. It identifies the address as either an individual or a group address. Group addresses are sometimes called "multicast" addresses and individual addresses are called "unicast" addresses. The broadcast address is a special group address in the special hex format: FF-FFFF-FF-FF-FF. Bit 1 of the destination address distinguishes between locally or globally administered addresses. For globally administered or universal (U) addresses, the bit value is "0". If an address is to be assigned locally, you must set this bit to "1". For the broadcast address, this bit must also be set to "1". Destination Address Block ID or OUI (3 bytes) MAC Address (3 bytes) U/L I/G [0] Individual or group flag (I/G) 0 = Individual (= unicast) address. 1 = Group (= multicast) address. [1] Universal or local address flag (U/L) 0 = Universal address. 1 = Local address. Figure 7-16. Destination Address Format Special Flow Control Destination Address The current specification for full-duplex flow control specifies a special destination address for the Pause operation packet. In order for the MAC to receive packets which contain this special destination address, the address must be programmed in one of the CAM entries. This CAM entry must then be enabled, and the CAM activated. Some CAM entries are also used when generating a flow control packet using the SdPause bit in the MAC transmit control register. 7-49 ETHERNET CONTROLLER S3C4510B TRANSMITTING A FRAME To transmit a frame, the transmit enable bit in the transmit control register must be set and the transmit halt request bit must be zero. In addition, the halt immediate and halt request bits in the MAC control register must be "0". These conditions are normally set after any BDMA controller initialization has occurred. The system then uses the Tx_wr# and Tx_EOF signals to transfer bytes to the transmit data buffer. The transmit state machine starts transmitting the data in the FIFO, and will retain the first 64 bytes until after this station has acquired the net. At that time, the transmit block requests more data and transmits it until the system asserts the Tx_EOF input, signaling the end of data to be transmitted. The transmit block appends the calculated CRC to the end of the packet, and transmission ends. It then sets the transmit status register bit 0, signaling a successful transmission. This action may causes an interrupt, if enabled. A frame transmit operation can be subdivided into two operations, 1) a MII interface operation, and 2) a BDMA/ MAC interface operation. BDI TRANSMIT OPERATION The BDI transmit operation is a simple FIFO mechanism. The BDMA engine stores data to be transmitted, and the transmit state machine empties it when the MAC successfully acquires the net. Note that the two time domains intersect at the FIFO controller. The writing and reading of data is asynchronous and on different clocks. Reading is driven by either a 25-MHz or a 2.5-MHz transmit clock. Writing is driven by the synchronous Sys_clk, which is asynchronous to Tx_clk. After a reset, the transmit FIFO is empty. The transmit block asserts the Tx_rdy signal, and transmission is disabled. To enable transmission, the system must set the transmit enable bit in the transmit control register. In addition, eight bytes of data must be present in the transmit FIFO. The BDMA engine can start stuffing data into the FIFO, and then enable the transmit bit. (Or it can enable the transmit bit first and then start stuffing data into the FIFO.) The transmit operation can only start if both of these conditions are met. 7-50 S3C4510B ETHERNET CONTROLLER BDI Transmit Timing When the transmit block asserts the Tx_rdy signal, the BDMA engine can write data into the transmit FIFO by asserting the Tx_wr# signal. Figure 7-15 shows timing sequences for back-to-back transfers and transfers with wait states. This is a synchronous interface, which means that data is latched in at the rising edge of the Sys_clk when Tx_wr# is asserted. For slower interfaces, the rising edge of Tx_wr# can be delayed. This is the equivalent of asserting a wait state in a synchronous operation. The transmit FIFO machine checks the Tx_par and the Tx_EOF bits. If there is a parity error, the transmit block aborts the transmission, resets the FIFO, and generates an interrupt by setting the TxPar bit in the transmit status register. The Tx_EOF bit signals the end of one frame to be transmitted. When it detects this bit, the transmit block deasserts Tx_rdy until it has transmitted the packet. It then re-asserts Tx_rdy when the BDMA can transfer the next packet into the MAC FIFO. SYS_CLK ~ ~ Rx_rdy Rx_wr# ~ ~ ~ ~ ~~ ~~ Rx_DB B1 B2 B3 ~~ ~~ Rx_BE# B1 B2 B3 ~~ ~~ Rx_par B1 B2 B3 ~~ ~~ Rx_EOF Figure 7-17. BDI Transmit Data Timing 7-51 ETHERNET CONTROLLER S3C4510B MII TRANSMIT OPERATION The transmit block consists of three state machines: the gap_ok state machine, the back_off state machine, and the main transmit state machine. The gap_ok State Machine The gap_ok state machine tracks and counts the inter-gap timing between the frames. When not operating in full-duplex mode, it counts 96 bit times from the deassertion of the carrier sense (CrS) signal. If there is any traffic within the first 64 bit times, the gap_ok state machine reset itself and starts counting from zero. If there is any traffic in the last 1/3 of the inter-frame gap, the gap_ok state machine continues counting. Following a successful transmission, a gap_ok is sent at the end of the next 96 bit times, regardless of the network traffic. In full-duplex mode, the gap_ok state machine starts counting at the end of the transmission and the gap_ok signal is sent at the end of the 96 bit times, regardless of the network traffic. Assemble MAC frame Yes Carrier sense==ON? Wait for interframe gap (96-bit time), start Tx with preamble + SFD Continue transmission Collision detected? Yes Preamble and SFD transmitted? Yes Stop transmission, send 32-bit jam, ++ Attemp_count Done. Complete Tx Wait for back-off time: (=slot time x r), k = minimum (n, back-off limit (=10)) 0<=n Figure 7-18. CSMA/CD Transmit Operation 7-52 S3C4510B ETHERNET CONTROLLER The back_off State Machine The back_off state machine implements the back-off and retry algorithm of the 802.3 CSMA/CD. When a collision is detected, the main transmit state machine starts the back_off state machines counters and waits for the back-off time (including zero) to elapse. This time is a multiple of 512 bit times that elapse before the packet that caused the collision is re-transmitted. Each time there is a collision (for one single packet), the back_off state machine increments an internal retry attempt countner. A 11-bit pseudo random number generator outputs a random number by selecting a subset of the value of the generator at any time. The subset is incremented by one bit for each subsequent attempt. This implementation is represented by the following equation: 0 =< random integer(r) < 2K K = min (n, backoff limit (= 10)) where "r" is the number of slot times the MAC must wait in case of a collision, and "n" is the number of retry attempts. For example, after the first collision, "n" is 1 and "r" is a random number between 0 and 1. The pseudo random generator in this case is one-bit wide and gives a random number of either 0 or 1. After the second attempt, "r" is a random number between 0 and 3. Therefore, the state machine looks at the two least-significant bits of the random generator (n = 2), which gives a value between 0 and 3. The Main Transmit State Machine The main transmit state machine implements the remaining MAC layer protocols. If there is data to be transferred, if the inter-frame gap is valid, and if the MII is ready (that is, if there are no collisions and no CRS in full-duplex mode), the transmit block then transmits the preamble followed by the SFD. After the SFD and preamble are transmitted, the block transmits 64 bytes of the data, regardless of the packet length, unless short transmission is enabled. This means that if the packet is less than 64 bytes, it will pad the LLC data field with zeros. It will also appends the CRC to the end of the packet, if CRC generation is enabled. If there is any collision during this first 72 bytes (8 bytes of preamble and SFD, and 64 bytes of the frame), the main transmit state machine stops the transmission and transmits a jam pattern (32 bits of 1s). It then increments the collision attempt counter, returns control to the back_off state machine, and re-transmits the packet when the back-off time has elapsed and the gap time is valid. If there are no collisions, the transmit block transmits the rest of the packet. At this time (that is, after the first 60 bytes have been transmitted without collisions), the main transmit state machine lets the BDMA engine overwrite the packet. After it transmits the first 64 bytes, the transmit block transmits the rest of the packet, appending the CRC to the end. parity errors, FIFO errors, or more than 16 collisions will cause the transmit state machine to abort the packet (no retry) and queue up the next packet. In case of any transmission errors, the transmit block sets the appropriate error bit in the transmit status register. It may also generate an interrupt, depending on the enable bit settings in the transmit control register. 7-53 ETHERNET CONTROLLER S3C4510B Tx_clk ~~ ~~ Tx_en ~~ ~~ TxD [3:0] P R E A M B L E ~ ~ Crs Col Figure 7-19. Timing for Transmit without Collision ~ ~ Tx_clk Tx_en TxD [3:0] P1 P2 P3 P4 P5 P6 P7 P8 J1 J2 J3 J4 Crs Col Figure 7-20. Timing for Transmit with Collision in Preamble 7-54 S3C4510B ETHERNET CONTROLLER RECEIVING A FRAME The receive block, when enabled, constantly monitors a data stream coming either from the MII or, if in loopback mode, from the transmit block. The MII supplies from zero to seven bytes of preamble, followed by the start frame delimiter (SFD). The receive block checks that the first nibbles received are preamble, and then looks for the SFD (10101011) in the first eight bytes. If it does not detect the SFD by then, it treats the packet as a fragment and discards it. The first nibble of destination address follows the SFD, least-significant bits first. When it has received a byte, the receive block generates parity, stores the byte with its parity in the receive FIFO, and asserts Rx_rdy. It combines subsequent nibbles into bytes and stores them in the FIFO. BDI RECEIVE DATA TIMING When the system asserts Rx_rd#, the receive block reads the first byte from the FIFO, checks parity, and drives the byte on Rx_DB, and the byte's parity on Rx_par. If the FIFO is now empty, it drops Rx_rdy. When it drives out the last byte of a packet, it asserts Rx_EOF. Figure 7-19 shows the timing sequence for transmitting bytes back-to-back, transmitting with wait states, and transmitting the last byte. Sys_clk ~ ~ Rx_rdy ~ ~ ~ ~ Rx_rd# ~~ ~~ Rx_DB B1 B2 B3 BN ~~ ~~ Rx_par PAR PAR PAR PAR Rx_EOF ~ ~ Figure 7-21. BDI Receive Data Timing 7-55 ETHERNET CONTROLLER S3C4510B RECEIVE FRAME TIMING WITH/WITHOUT ERROR If, during frame reception, both Rx_DV and Rx_er are asserted, a CRC error is reported for the current packet. As each nibble of the destination address is received, the CAM block attempts to recognize it. After receiving the last destination address nibble, if the CAM block rejects the packet, the receive block asserts the Rx_toss signal, and discards any bytes not yet removed from the receive FIFO that came from the current packet. If this operation leaves the FIFO empty, it drops Rx_rdy. Figure 7-20 shows the MII receive data timing without error. The RX_DV signal, which entered the MII from the PCS layer, will be ON when the PCS layer recovers the Rx_clk from the receive bit stream and delivers the nibble data on RxD[3:0] data line. The RX_DV signal must be ON before the starting frame delimiter(SFD) is received. When the Rx_DV signal is ON, the preamble and SFD parts of the frame header are delivered to MII, synchronized with the 25-MHz Rx_clk. (The carrier sense (CrS) signal was turned on during receive frame.) As its response to the Rx_er signal, the MII immediately inserts an alternative data bit stream into the receive data stream. As a result, the MAC discards this received error frame using the FCS. Rx_clk ~ ~ Rx_DV ~ ~ ~~ ~~ Preamble SFD DA SFD RxD [3:0] Crs Rx_er ~ ~ ~ ~ Figure 7-22. Receiving Frame without Error Rx_clk ~ ~ Rx_DV ~ ~ ~~ ~~ Preamble SFD DA SFD RxD [3:0] Crs Rx_er ~ ~ ~ ~ Figure 7-23. Receiving Frame with Error 7-56 S3C4510B ETHERNET CONTROLLER Carrier Sense== On yse Carrier sense = On, after detection SFD, store byte-stream in in FISO no Discard the Frame Report Error Status Recognize Address? Move the byte stream in the FIFO to the receive buffer memory Frame too short ? Frame too long? Valid FCS ? Interrput CPU for Handing the Frame Check ethertype or length field MAC Drive Software (Software jobs for typical LAN cards) Disassemble Frame Signal to Upper Layer Figure 7-24. CSMA/CD Receive Operation 7-57 ETHERNET CONTROLLER S3C4510B THE MII STATION MANAGER The MDIO (management data input/output) signal line is the transmit and receive path for control/status information for the station management entity, STA. The STA controls and reads the current operating status of the PHY layer. The speed of transmit and receive operations is determined by the management data clock, MDC. The frame structure of the STA which writes command to control registers, or which reads the status register of a PHY device, is shown Table 7-45. The PHY address is defined as the identification (ID) value of the various PHY devices that may be concected to a single MAC. Register addresses can contain the ID value for up to 32 types of PHY registers. Turn-around bits are used to regulate the turn-around time of the transmit/receive direction between the STA and a PHY device. So that the STA can read the set value of a PHY device register, it must transmit the frame data, up to a specific register address, to the PHY device. During the write time (which is an undirected transmission), the STA transmits a stream of turn-around bits. As a result, by transmitting a write or read message to a PHY device through the MDIO, the STA can issue a request to set the operation or to read the operation status. As its response this message, the PHY device resets itself, sets loop-back mode, selects active/non-active autonegotiation process, separates the PHY and MII electrically, and determines whether or not to activate the collision detection process. When it receives a read command, the PHY reports the kind of PHY device it is, such as 100Base-T4, FDX 100base-X, HDX 100Base-X, 10-Mb/s FDX, or 10-Mb/s HDX. Table 7-45. STA Frame Structure Description Preamble Write (Command) Read (Status) 11111111 (32 bits) 11111111 (32 bits) Start of Frame 01 Operation Code 01 (write) PHY Address 5 bits Register Address 5 bits Turnaround 10 (2 bits) Data 16 bits (register value) 16 bits (register value) Idle Z 01 10 (read) 5 bits 5 bits Z0 Z Direction: STA to PHY Direction: PHY to STA 7-58 S3C4510B ETHERNET CONTROLLER FULL-DUPLEX PAUSE OPERATIONS Transmit Pause Operation To enable a full-duplex Pause operation, the special broadcast address for MAC control packets must be programmed into the CAM, and the corresponding CAM enable bit set. The special broadcast address can be a CAM location. To optimize the utilization CAM entries, you can specify a preference for specific CAM locations. This feature is described below. The MAC receive circuit recognizes a full-duplex Pause operation when the following conditions are met: -- The type/length field has the special value for MAC Control packets, 0x8808. -- The packet is recognized by the CAM. -- The length of the packet is 64 bytes. -- The operation field specifies a Pause operation. When a full-duplex pause operation is recognized, the MAC receive circuit loads the operand value into the pause count register. It then signals both the MAC and the BDMA engine that the pause should begin at the end of the current packet, if any. The pause circuit maintains the pause counter, and decrements it to zero. It does this before it signals the end of the pause operation, and before allowing the transmit circuit to resume its operation. If a second full-duplex pause operation is recognized while the first operation is in effect, the pause counter is reset with the current operand value. Note that a count value of zero may cause pre-mature termination of a pause operation that is already in progress. Remote Pause Operation To send a remote pause operation, following these steps: 1. Program CAM location 0 with the destination address. 2. Program CAM location 1 with the source address. 3. Program CAM location 18 with length/type field, opcode, and operand. 4. Program the 2 bytes that follow the operand with 0000H. 5. Program the three double words that follow CAM location 18 with zeros. 6. Write the transmit control register to set the SdPause bit. The destination address and source address are commonly used as the special broadcast address for MAC control frames and the local station address, respectively. To support future uses of MAC control frames, these values are fully programmable in the flow control 100-/10-Mbit/s Ethernet MAC. When the remote Pause operation is completion, the transmit status is written to the transmit control frame status register. The BDMA engine is responsible for providing an interrupt enable control. 7-59 ETHERNET CONTROLLER S3C4510B Error Signalling The error/abnormal operation flags asserted by the MAC are arranged into transmit and receive groups. These flag groups are located either in the transmit status register (Tx_stat) or the receive status register (Rx_stat). A missed packet error counter is included for system network management purposes. Normally, software does not have enough direct control to examine the status registers directly. Therefore, the BDMA engine must store the values in system memory so that they can be examined there by software. Reporting of Transmission Errors A transmit operation terminates when the entire packet (preamble, SFD, data, and CRC) has been successfully transmitted through the MII without a collision. In addition, the transmit block detects and reports both internal and network errors. Under the following conditions, the transmit operation will be aborted (in most cases). Parity error The 8 bits of data coming in through the BDII has an optional parity bit. A parity bit also protects each byte in the MAC transmit FIFO. If a parity error occurs, it is reported to the transmit state machine, and the transmission is aborted. A detected parity error sets the TxPar bit in the transmit status register. The 80-byte transmit FIFO can handle a system latency of 6.4bi (640 bit times). An underrun of the transmit FIFO during transmission indicates a system problem (namely, that the system cannot keep up with the demands of the MAC), and the transmission is aborted. The carrier sense signal (CrS) is monitored from the beginning of the start of frame delimiter (SFD) to the last byte transmitted. A "No CrS" indicates that CrS was never present during transmission (a possible network problem), but the ransmission will NOT be aborted. Note that during loop-back mode, the MAC is disconnected from the network, and a "No CRC" will not be detected. Whenever the MAC encounters a collision during transmit, it will back off, update the "attempt counter," and retry the transmission later on. When the attempt counter reaches 16 (16 attempts that all resulted in a collision), the transmission is aborted. This indicates a network problem. (Transmit out of window collision) Normally, the MAC would detect a collision (if one occurs) within the first 64 bytes of data that are transmitted, including the preamble and SFD. If a collision occurs after this time frame, a possible network problem is indicated. The error is reported to the transmit state machine, but the transmission is NOT aborted. Instead, it performs a back-off, as usual. During its first attempt to send a packet, the MAC may have to defer the transmission because the network is busy. If this deferral time is longer than 32K bit times, the transmission is aborted. Excessive deferral errors indicate a possible network problem. Transmit FIFO underrun No CRS Excessive collision error Late collision error Excessive deferral error 7-60 S3C4510B ETHERNET CONTROLLER Reporting of Receive Errors When it detects a start of frame delimiter (SFD), the receive state machine starts putting data it has received from the MII into the receive FIFO. It also checks for internal errors (FIFO overruns) while reception is in progress. When the receive operation is completed, the receive state machine checks for external errors, such as frame alignment, length, CRC, and frame too long. The following is a description of the types of errors that may occur during a receive operation: Priority error A parity bit protects each byte in the MAC receive FIFO. If a parity error occurs, it is reported to the receive state machine. A detected parity error sets the RxPar bit in the receive status register. (Dribble) After receiving a packet, the receive block checks that the incoming packet (including CRC) was correctly framed on an 8-bit boundary. If it is not and if the CRC is invalid, data has been disrupted through the network, and the receive block reports a frame alignment error. A CRC error is also reported. After receiving a packet, the receive block checks the CRC for validity, and reports a CRC error if it is invalid. The receive unit can detect network-related errors such as CRC, frame alignment, and length errors. It can also detect these types of errors in the following combinations: -- -- -- -- Frame too long CRC errors only Frame alignment and CRC errors only Length and CRC errors only Frame alignment, length, and CRC errors Frame Alignment Error CRC Error The receive block checks the length of the incoming packet at the end of reception (including CRC, but excluding preamble and SFD). If the length is longer than the maximum frame size of 1518 bytes, the receive block reports receiving a "long packet", unless long frame mode is enabled. During reception, the incoming data are put into the receive FIFO temporarily before they are transferred to the system memory. If the FIFO is filled up because of excessive system latency or for other reasons, the receive block sets the overrun bit in the receive status register. The PHY informs the MAC if it detects a medium error (such as a coding violation) by asserting the input pin Rx_er. When the MAC sees Rx_er asserted, it sets CRCErr bit of the receive status register. Receive FIFO overrun MII error 7-61 ETHERNET CONTROLLER S3C4510B Timing Parameters for MII Transactions The timing diagrams in this section conform to the guidelines described in the "Draft Supplement to ANSI/IEEE Std. 802.3, Section 22.3, Signal Characteristics." Tx_clk 0ns MIN, 25ns MAX TxD[3:0] Tx_en Figure 7-25. Transmit Signal Timing Relationship at MII Rx_clk 10ns MIN RxD[3:0], Rx_DV, Rx_er 10ns MIN INPUT VALID Figure 7-26. Receive Signal Timing Relationship at MII 7 Cycles 7 Cycles MDC 0ns MIN, 300ns MAX MDIO Figure 7-27. MDIO Sourced by PHY MDC 10ns MIN MDIO 10ns MIN INPUT VALID Figure 7-28. MDIO Sourced by STA 7-62 S3C4510B ETHERNET CONTROLLER MAC CONTROLLER 7-WIRE INTERFACE TIMING Table 7-46. 7-Wire Interface Receive Timing Symbol Ts_crs Th_crs Ts_dv Th_dv Ts_d Th_d Ts_er Th_er Tcyc Condition CRS low to high setup time CRS low to high hold time RX_DV set-up time RX_DV hold time RxD set-up time RxD hold time Rx_er set-up time Rx_er hold time Rx_clk clock period Min 0.92 0.38 0.9 0.4 0.79 0.51 0.9 0.4 100 Typ Max Unit ns ns ns ns ns ns ns ns ns Th_crs Rx_clk Ts_crs Rx_DV Th_dv Ts_dv Tcyc RxD Preamble SFD DA CRC Crs Th_d Ts_d Rx_er Th_er Ts_er Figure 7-28. Rx Timing in 7 Wire Interface 7-63 ETHERNET CONTROLLER S3C4510B Table 7-47. 7-Wire Interface Transmit Timing Symbol Ts_en Th_en Ts_crs Th_crs Ts_d Th_d Ts_col Th_col Tcol Condition Tx_en set-up time Tx_en hold time CRS set-up time CRS hold time TxD set-up time TxD hold time COL set-up time COL hold time COL minimum active time Min 0.8 0.71 0.72 0.75 1.2 0.5 0.82 0.79 200 Typ Max Unit ns ns ns ns ns ns ns ns ns Ts_col Th_cn Tx_clk Ts_en Th_col Tx_en Ts_d TxD Th_d Crs Th_crs Ts_crs Col Tcol Figure 7-29. Tx Timing in 7 Wire Interface 7-64 S3C4510B HDLC CONTROLLERS 8 OVERVIEW HDLC CONTROLLERS The S3C45310B has two high-level data link controllers (HDLCs) to support two-channel serial communications. The HDLC module supports a CPU/data link interface that conforms to the synchronous data link control (SDLC) and high-level data link control (HDLC) standards. In addition, the following function blocks are integrated into the HDLC module: -- Two-channel DMA engine for Tx/Rx -- Support buffer descriptors per frame -- Digital phase-locked loop (DPLL) block -- Baud rate generator (BRG) 8-1 HDLC CONTROLLERS S3C4510B FEATURES Important features of the S3C4510B HDLC block are as follows: -- Protocol features: Flag detection and synchronization Zero insertion and deletion Idle detection and transmission FCS encoding and detection (16-bit) Abort detection and transmission -- Four address station registers and one mask register for address search mode -- Selectable CRC/No-CRC mode -- Automatic CRC generator preset -- Digital PLL block for clock recovery -- Baud rate generator -- NRZ/NRZI/FM/Manchester data formats for Tx/Rx -- Loop-back and auto-echo mode -- Tx and Rx clock inversion -- Tx and Rx FIFOs with 8-word (8 x 32-bit) depth -- Selectable 1-word or 4-word data transfer mode for Tx/Rx -- Data alignment logic -- Endian translation -- Programmable interrupts -- Modem interface -- Hardware flow control -- Buffer descriptor for Tx / Rx -- Two-channel DMA Controller Two channels for HTxFIFO and HRXFIFO Single or 4-word (4 x 32-bit) burst transfer mode Maximum frame size allows for up to 64K bytes -- Up to 10 Mbps full-duplex operation using an external/internal clock -- HDLC frame length based on octets 8-2 S3C4510B HDLC CONTROLLERS FUNCTION DESCRIPTIONS Figure 8-1 shows the HDLC module's function blocks. These function blocks are described in detail in the following sections. Tx FIFO (8 Words) Address DMA Controlller FCS Generator autoecho Flag/Abort/Idle Generateor and Transmitter Zero Insertion Encoder TxD Word HDLC Control and Status Registers Flag/Abort/Idle Detection Remote Serial Port System BUS Control Data Address Bus Arbiter/ Controller FCS Checker Receive shift Register Zero Deletion loop Decoder dplloutR dplloutT brgout2 RxD TxC brgout1 BRG RxC Rx FIFO (8 words) DPLL MCLK2 (= 25 MHz) Figure 8-1. HDLC Module Block Diagram 8-3 HDLC CONTROLLERS S3C4510B HDLC FRAME FORMAT The HDLC transmits and receives data (address, control, information and CRC field) in a standard format called a frame. All frames start with an opening flag (beginning of flag, BOF, 7EH) and end with a closing flag (end of flag, EOF, 7EH). Between the opening and the closing flags, a frame contains an address (A) field, a control (C) field, an information (I) field (optional), and a frame check sequence (FCS) field (see Table 8-1). Table 8-1. HDLC Data Frame Format Opening Flag 01111110 Address Field 8 bits per byte Control Field 8 bits per byte Information Field 8 bits per byte; variable length Frame Check Sequence Field 16 bits Closing Flag 01111110 NOTE: The address field can be extended up to four bytes using a optional software control setting. Flag (F) A flag is a unique binary pattern (01111110) that is used to delimit HDLC frames. This pattern is generated internally by the transmitter. An opening flag starts a frame and a closing flag ends the frame. Opening flags and closing flags are automatically appended to frames. A single flag pattern can optionally serve as both the closing flag of one frame and the opening flag of the next one. This feature is controlled by the double-flag (FF), single-flag (F), or frame separator selection bit (the TxSDFL bit in the HCON register). Order of Bit Transmission Address field, control field, and information field bytes are transferred between the CPU and the HDLC module in parallel over the data bus. These bytes are transmitted and received LSB first. The 16-bit frame check sequence (FCS) field is, however, transmitted and received MSB first. 8-4 S3C4510B HDLC CONTROLLERS Address (A) Field The eight bits that follow the opening flag are called address (A) field. The address field are expendable. To extend this address byte, simply user-defined address write to the station address register. To check address byte against the incoming data, have to be used the MASK register. If match occurred, the frame's data including address and CRC(16-bit) into the HRXFIFO and then moved to system memory. If it is not matched, simply discarded. S3C4510B allows up to 32-bits address. For instance, SDLC and LAPB use an 8-bit address. LAPD further divides its 16-bit address into different fields to specify various access points one piece of equipment. Some HDLC-type protocol allows for extended addressing beyond 16-bit. Control (C) Field The eight bits that follow the address field are called the control (link control, C) field. The S3C4510B HDLC module treats the control field in the same way as the information field. That is, it passes the eight bits to the CPU or memory during reception. The CPU is responsible for how the control field is handled and what happens to it. Information (I) Field The information (I) field follows the control (C) field and precedes the frame check sequence (FCS) field. The information field contains the data to be transferred. Not every frame, however, must actually contain information data. The word length of the I-field is eight bits in the S3C4510B HDLC module. And Its total length can be extended by 8 bits until terminated by the FCS field and the closing flag. Frame Check Sequence (FCS) Field The 16 bits that precede the closing flag comprise the frame check sequence (FCS) field. The FCS field contains the cyclic redundancy check character, CRCC. The polynomial x16 + x12 + x5 + 1 is used both for the transmitter and the receiver. Both the transmitter and the receiver polynomial registers are all initialized to 1 prior to calculating of the FCS. The transmitter calculates the frame check sequence of all address bits, control bits, and information fields. It then transmits the complement of the resulting remainder as the FCS value. The receiver performs a similar calculation for all address, control, and information bits, as well as for all the FCS fields received. It then compares the result to F0B8H. When a match occurs, the frame valid (RxFV) status bit is set to '1'. When the result does not match, the receiver sets the CRC error bit (RxCRCE) to '1'. The transmitter and the receiver automatically perform these FCS generation, transmission and checking functions. The S3C4510B HDLC module also supports NO CRC operation mode. In NO CRC mode, transmitter does not append FCS to the end of data and the receiver also does not check FCS. In this mode, the data preceding the closing flag is transferred to the HRXFIFO. In CRC mode, the FCS field is transferred to the HRXFIFO. 8-5 HDLC CONTROLLERS S3C4510B PROTOCOL FEATURES INVALID FRAME A valid frame must have at least the A, C, and FCS fields between its opening and closing flags. Even if no-CRC mode is set, the frame size should not be less than 32 bits. There are three invalid frame conditions: -- Short frame: a frame that contains less than 25 bits between flags. Short frames are ignored. -- Invalid frame: a frame with 25 bits or more, having a CRC compare error or non- byte-aligned. Invalid frames are transferred to the HRXFIFO, then the invalid frame error flag (RxCRCE, RxNO in the status register) is set to indicate that an invalid frame has been received. -- Aborted frame: a frame aborted by the reception of an abort sequence is handled as an invalid frame. ZERO INSERTION AND ZERO DELETION The zero insertion and zero deletion feature, which allows the content of a frame to be transparent, is handled automatically by the HDLC module. While the transmitter inserts a binary '0' following any sequence of five 1s within a frame, the receiver deletes a binary '0' that follows a sequence of five 1s within a frame. ABORT The function of early termination of a data link is called an abort The transmitter aborts a frame by sending at least eight consecutive 1s immediately after the abort transmitter control bit (TxABT in HCON) is set to '1'. (Setting this control bit automatically clears the HTxFIFO.) The abort sequence can be extended up to (at least) 16 consecutive 1s by setting the abort extend control bit (TxABTEXT in HCON) to '1'. This feature is useful for forcing the mark idle state. The receiver interprets the reception of seven or more consecutive 1s as an abort. The receiver responds the abort received as follows: -- An abort in an 'out of frame' condition: an abort has no meaning during the idle or the time fill -- An abort 'in frame' after less than 25 bits are received after an opening flag: under this condition, no field of the aborted frame is transferred to the HRXFIFO. The HDLC module clears the aborted frame data in the receiver and flag synchronization. The aborted reception is indicated in the status register. -- An abort 'in frame' after 25 bits or more are received after an opening flag: in this condition, some fields of the aborted frame may be transferred to the HRXFIFO. The abort status is set in the status register and the data of the aborted frame in the HRXFIFO is cleared. Flag synchronization is also cleared and the DMA operation for receiving is aborted too. IDLE AND TIME FILL When the transmitter is not transmitting a frame, it is in an idle state. The transmitter signals that it has entered an idle state in one of the following two ways: 1) by transmitting a continuous series of flag patterns (time fill), or 2) by transmitting a stream of consecutive 1s (mark idle). The flags and mark idle are not transferred to the HRXFIFO. The flag or mark idle selection bit (TxFLAG in HCON) controls this function: when TxFLAG is '0', mark idle is selected; when TxFLAGIDLE is '1', the time fill method is selected. 8-6 S3C4510B HDLC CONTROLLERS FIFO STRUCTURE In both transmit and receive directions, 32-byte (8 word) deep FIFOs are provided for the intermediate storage of data between the serial interface and the CPU Interface. TWO-CHANNEL DMA ENGINE The HDLC module has a two-channel DMA engine for Tx/Rx FIFOs. The DMA Tx channel programming and the RX channel programming are described in the transmitter and receiver operation sections, respectively. BAUD RATE GENERATOR The HDLC module contains a programmable baud rate generator(BRG). The BRG register contains a 16-bit time constant register, a 12-bit down counter for time constant value, two control bit to divide 16, and another two control bits to divide 16 or 32. A clock diagram of the BRG is shown in Figure 8-2. At a start-up, the flip-flop on the output is set in a High state, the value in the time constant register is loaded into the counter, and the counter starts counting down. The output of the baud rate generator may toggle upon reaching zero, the value in the time constant register is loaded into the counter, and the process is repeated. The time constant may be changed any time, but the new value does not take effect until the next load of the counter. The output of the baud rate generator may be used as either the transmit clock, the receive clock, or both. It can also drive the digital phase-locked loop. If the receive or transmit clock is not programmed to come from the TXC pin, the output of the baud rate generator may be echoed out via the TXC pin. The following formula relates the time constant to the baud rate where MCLK2 or RXC is the baud rate generator input frequency in Hz. BRG generates 2 output signals, BRGOUT1, BRGOUT2, for transmit/receive clocks and the DPLL input clock. BRGOUT1 = (MCLK2 or RXC) / (CNT0 + 1) / (16CNT1) BRGOUT2 = BRGOUT1 / (1 or 16 or 32 according to CNT2 value of the HBRGTC) CNT0 RxC MCLK2 12-bit counter CNT1 CNT2 Divide by 1 or 16 BRGOUT2 Divide by 1 or 16 or 32 BRGOUT1 BRGCLK CNT0: HBRGTC [15:4] CNT1: HBRGTC [3:2] CNT2: HBRGTC [1:0] BRGCLK: HMODE [19] Figure 8-2. Baud Rate Generator Block Diagram 8-7 HDLC CONTROLLERS S3C4510B The example in the following Table assumes a 25 MHz clock from MCLK2, a 24.576 MHz clock from RxC, showing a time constant for a number of commonly used baud rates. Table 8-2. Baud Rate Example of HDLC Baud Rate (BRGOUT2) 1200 2400 4800 9600 19200 38400 57600 115200 CNT0 1301 650 324 162 80 40 26 13 0 0 0 0 0 0 0 0 MCLK = 25 MHz CNT1 CNT2 1 1 1 1 1 1 1 1 Freq. 1200.1 2400.2 4807.7 9585.9 19290.1 38109.8 57870.4 111607.1 Dev.(%) 0.0 0.0 0.2 - 0.1 0.5 - 0.8 0.5 - 3.1 CNT0 1279 639 319 159 79 39 26 12 RxC = 24.576 MHz x CNT1 0 0 0 0 0 0 0 0 CNT2 1 1 1 1 1 1 1 1 Freq. 1200.0 2400.0 4800.0 9600.0 19200.0 38400.0 56888.9 118153.8 Dev.(%) 0.0 0.0 0.0 0.0 0.0 0.0 -1.2 2.6 8-8 S3C4510B HDLC CONTROLLERS DIGITAL PHASE-LOCKED LOOP (DPLL) The HDLC module contains a digital phase-locked loop (DPLL) function to recover clock information from a data stream with NRZI or FM encoding. The DPLL is driven by a clock that is normally 32 (NRZI) or 16 (FM) times the data rate. The DPLL uses this clock, along with the data stream, to construct the clock. This clock may then be used as the receive clock, the transmit clock, or both. Figure 8-3 shows a block diagram of the digital phase-locked loop. It consists of a 5-bit counter, an edge detector and a pair of output decoders. RxD Edge Detector Count Modifier Decoder Receive Clock dplloutR TxC RxC MCLK BRGOUT1 BRGOUT2 HMODE[18:16] 5-bit Counter Decoder Transmit clock dplloutT Figure 8-3. DPLL Block Diagram CLOCK USAGE METHOD BRGCLK BRGOUT1 Baud Rate Generator BRGOUT2 TxC RxC MCLK BRGOUT1 BRGOUT2 DPLLCLK DPLLOUTT DPLL DPLLORTR RxC MCLK2 TxCLK TxC RxC DPLLOUTT BRGOUT1 BRGOUT2 NOTE: TxC RxC DPLLOUTT BRGOUT1 BRGOUT2 RxCLK Transmit Clock Transmitter Transmit Data Receive Clock Receiver Receive Data BRGCLK = HMODE [19] DPLLCLK = HMODE [18:16] TxCLK = HMODE [22:20] RxCLK = HMODE [26:24] Figure 8-4. Clock Usage Method Diagram 8-9 HDLC CONTROLLERS S3C4510B In the NRZ/NRZI mode, the DPLL source clock must be 32 times the data rates. In this mode, the transmit and receive clock outputs of the DPLL are identical, and the clocks are phased so that the receiver samples the data in the middle of the bit cell. The DPLL counts the 32x clock using an internal 5-bit counter. As the 32x clock is counted, the DPLL searches the incoming data stream for edges (either positive or negative transition). The output of DPLL is High while the DPLL is waiting for an edge in the incoming data stream. When it detects a transition, the DPLL starts the clock recovery operation. The first sampling edge of the DPLL occurs at the counter value of 16 after the first edge is detected in the incoming data stream. The second sampling edge occurs following the next 16. When the transition of incoming data occurs at a count value other than 16, the DPLL adjusts its clock outputs during the next 0 to 31 counting cycle by extending or shortening its count by one, which effectively moves the edge of the clock sampling the receive data closer to the center of the bit cell. The adding or subtracting of a count of 1 will produce a phase jitter of 5.63 degrees on the output. Because the DPLL uses both edges of the incoming signal for its clock source comparison, the mark-space ratio (50%) of the incoming signal must not deviate more than 1.5% of its baud rate if proper locking is to occur. In the FM mode, the DPLL clock must be 16 times the data rate. The 5-bit counter in the DPLL counts from 0 to 31, so the DPLL makes two sampling clocks during the 0 to 31 counting cycle. The DPLL output is Low while the DPLL is waiting for an edge in the incoming data stream. The first edge the DPLL detects is assumed to be a valid clock edge. From this point, the DPLL begins to generate output clocks. In this mode, the transmit clock output of the DPLL lags the receive clock outputs by 90 degrees to make the transmit and receive bit cell boundaries the same, because the receiver must sample the FM data at a onequarter and three-quarters bit time. You can program the 32X clock for the DPLL to originate from one of the RxC input pins, from the TxC pin, or from the baud rate generator output. You can also program the DPLL output to be "echoed out" of the HDLC module over the TXC pin(if the TXC pin is not being used as an input). During idle time, you can set the TxPRMB in HCON to send the special pattern required for a remote DPLL to lock the phase. In this case, the content of the HPRMB register is sent repeatedly. The length of preamble is determined by TxPL bit in HMODE[10:8]. It is noticed that the frequency of the receive clock (RxC) should be slower than half of the internal system clock i.e., MCLK/2. Otherwise, the data transfer from receive FIFO to memory could be lost. 8-10 S3C4510B HDLC CONTROLLERS HDLC OPERATIONAL DESCRIPTION The following sections describe the operation of the HDLC module. HDLC INITIALIZATION A power-on or reset operation initializes the HDLC module and forces it into the reset state. After a reset, the CPU must write a minimum set of registers, as well as any options set, based on the features and operating modes required. First, the configuration of the serial port and the clock mode must be defined. These settings include the following: -- Data format select -- BRG clock select -- DPLL clock select -- Transmit clock select -- Receive clock select -- BRG/DPLL enable to use internal clock You must also set the clock for various components before each component is enabled. Additional registers may also have to be programmed, depending on the features you select. All settings for the HDLC mode register, HMODE, and the HDLC control register, HCON, must be programmed before the HDLC is enabled. To enable the HDLC module, you must write a '1' to the receiver enable bit and/or the transmitter enable bit. During normal operation, you can disable the receiver or the transmitter by writing a '0' to the RxEN or TxEN bit, respectively. You can disable the receiver and HRXFIFO or the transmitter and HTxFIFO by writing a '1' to the RxRS or TxRS bit, respectively. 8-11 HDLC CONTROLLERS S3C4510B HDLC DATA ENCODING/DECODING Data encoding is utilized to allow the transmission of clock and data information over the same medium. This saves the need to transmit clocks and data over a separate medium as would normally be required for synchronous data. The HDLC provides four different data encoding methods, selected by bits in HCON1[18:16]. An example of these four encoding methods is shown in figure 8-5. Data NRZ 1 1 0 0 1 0 Bit Cell Level: High = 1 Low = 0 No Change = 1 Change = 0 Bit Center Transition: Transition = 1 No Transition = 0 No Transition = 1 Transition = 0 High Low Low = 1 High = 0 NRZI FM1 (Biphase Mark) FM0 (Biphase Space) Manchester NRZ, NRZI Type TxClock Data RxClock FM0/FM1/Manchester type TxClock Data RxClock Figure 8-5. Data Encoding Methods and Timing Diagrams 8-12 S3C4510B HDLC CONTROLLERS HDLC DATA SETUP AND HOLD TIMING WITH CLOCK You can see the timing of TxD and RxD in terms of TxC and RxC HDLC clock in Figure 8-6. Table 8-3. HMODEA and HMODEB Register Symbol Ttxdf Trxdf Condition TxD falling edge delay time TxD falling edge delay time Min 9.82 1.0 Typ Max 10.66 Unit ns ns 40 ns TxC TxD 9.82 ns 10.66 ns RxC RxD 0.2 ns 1.0 ns Figure 8-6. Data Encoding Methods and Timing Diagrams Tx data will be sent with delayed 9.82 nsec to 10.66 nsec from the falling edge of Tx Clock. In case of RxD, the black period should not be changed. That is, the RxD should be stable from 0.2nsec to 1.0nsec after RxC rising edge. (It does not allow data transition during this period) The RxC will be Rx(receiver) clock through Rx clock selection part with some delay. And this RxC delay is larger then RxD delay. In Figure 8-6, the dotted-clock is real internal Rx clock used by the receiver. Therefore, there should not be transit in Rx data to avoid setup or hold violation. 8-13 HDLC CONTROLLERS S3C4510B HDLC TRANSMITTER OPERATION The HTxFIFO register cannot be pre-loaded when the transmitter is disabled. After the HDLC Tx is enabled, the flag or mark idle control bit (TxFLAG in HCON) is used to select either the mark idle state (inactive idle) or the flag 'time fill' (active idle) state. This active or inactive idle state will continue until data is loaded into the HTxFIFO. The content of the HPRMB register can be sent out by setting the TxPRMB in HCON for the remote DPLL before the data is loaded into the HTxFIFO. The length of preamble to be transmitted is determined by TxPL bits in HMODE. The availability of data in the HTxFIFO is indicated by the HTxFIFO available bit (TxFA in HSTAT) under the control of the 4-word transfer mode bit (Tx4WD in HCON). When you select 1-word transfer mode (not 4-word select mode), one word can be loaded into the HTxFIFO (assuming the TxFA bit is set to '1'). When you select 4-word transfer mode, four successive words can be transferred to the FIFO if the TxFA bit is set to '1'. The nCTS (clear-to-send) input, nRTS (request-to-send), and nDCD (data-carrier-detect) are provided for a modem or other hardware peripheral interface. In auto enable mode, nDCD becomes the receiver enable. However, the receiver enable bit must be set before the nDCD pin is used in this manner. The TxFC status bit(in HSTAT) can cause an interrupt to be generated upon frame completion (This bit is set when there is no data in HTxFIFO and when the closing flag or an abort is transmitted). 8-14 S3C4510B HDLC CONTROLLERS Transmitter Interrupt Mode The first byte of a frame (the address field) should be written into the Tx FIFO at the 'frame continue' address. Then, the transmission of the frame data starts automatically. The bytes of the frame continue to be written into the Tx FIFO as long as data is written to the 'frame continue' address. The HDLC logic keeps track of the field sequence within the frame. The frame is terminated when the last frame data is written to the Tx FIFO's 'frame terminate' address. The FCS field is automatically appended by hardware, along with a closing flag. Data for a new frame can be loaded into the Tx FIFO immediately after the previous frame data, if TxFA is '1'. The closing flag can serve as the opening flag of the next frame or separate opening and closing flags can be transmitted. If a new frame is not ready to be transmitted, a flag time fill or mark idle pattern is transmitted automatically. If the Tx FIFO becomes empty at any time during the frame transmission, an underrun occurs and the transmitter automatically terminates the frame by transmitting an abort. The underrun state is indicated when the transmitter underrun status bit (TxU) is '1'. Whenever you set the transmission abort control bit (TxABT in HCON), the transmitter immediately aborts the frame (transmits at least eight consecutive 1s), clearing the Tx FIFO. If the transmission abort extension control bit (TxABTEXT) is set at the time, an idle pattern (at least 16 consecutive 1s) is transmitted. An abort or idle in an out- of-frame condition can be useful to gain 8 or 16 bits of delay time between read and write operations. Transmitter DMA Mode To use DMA operation without CPU intervention, you have to make Tx buffer descriptor chain in advance. And set the DMA Tx buffer descriptor pointer (DMATxPTR) register to the address of the first buffer descriptor of the chain, and then DMA Tx channel should be enabled. When Tx underrun or CTS lost condition occurs during DMA operation, DMA Tx enable bit(HCON[6]) is cleared and DMA Tx operation is stopped. This situation is reported to system with DTxABT bit set (HSTAT[22]). In case of Tx underrun, abort signal sent and then idle pattern is sent if TxEN bit is set. In case of CTS lost, TxD output goes high state as long as CTS remains high level. 8-15 HDLC CONTROLLERS S3C4510B HDLC RECEIVER OPERATION The HDLC receiver is provided with data and a pre-synchronized clock by means of the RxD and the internal DPLL clock, the TxC pin, or the RxC pin. The data is a continuous stream of binary bits. One of the characteristics of this bit stream is that a maximum of five consecutive 1s can occur unless an abort, flag, or idle condition occurs. The receiver continuously searches (bit-by-bit) for flags and aborts. When a flag is detected, the receiver synchronizes the frame to the flag timing. If a series of flags is received, the receiver re-synchronizes the frame to each successive flag. If the frame is terminated because of a short frame condition (frame data is less than 32 bits after an opening flag), the frame is simply ignored. Noise on the data input line (RxD) during time fill can cause this kind of invalid frame. The received data which is clocked by the external TxC or RxC, or by an internal DPLL or BRG source enters a 56-bit or 32-bit shift register before it is transferred into the HRXFIFO. Synchronization is established when a flag is detected in the first eight locations of the shift register. When synchronization has been achieved, data is clocked through to the last byte location of the shift register where it is transferred into the HRxFIFO. In 1-word transfer mode, when the HRxFIFO available bit (RxFA) is '1', data is available at least in one-word. In 4-word transfer mode, the RxFA is '1' when data is available in the last four FIFO register locations (registers 4, 5, 6, and 7). The nDCD input is provided for a modem or other hardware interface. If AutoEN bit in HCON[28] is set to '1', the receiver operation is dependent on the nDCD input level. Otherwise, receiver operation is free of the nDCD input level. Receiver Interrupt Mode Whenever data is available in the HRXFIFO, an interrupt is generated by RxFA (if the interrupt is enabled). The CPU reads the HDLC status register either in response to the interrupt request or in turn during a polling sequence. When the received data available bit(RxFA) is '1', the CPU can read the data from the HRXFIFO. If the CPU reads normal data or address data from the HRXFIFO, the RxFA bit is automatically cleared. In CRC mode, the 16 bits preceding the closing flag are regarded as the FCS and checked by hardware, and they are transferred to the HRXFIFO. Also, in no CRC mode, without the hardware checking, all data bits preceding the closing flag are transferred to the HRXFIFO. When the closing flag is sent to the receiver, the frame is terminated. Whatever data is present in the most significant byte of the receiver, the shift register is right justified and transferred to the HRXFIFO. The frame boundary pointer, which is explained in the HRXFIFO register section, is set simultaneously in the HRXFIFO. When the last byte of the frame appears at the 1-word or 4-word boundary location of the HRXFIFO, depending on the settings of the Rx4WD control bit, the frame boundary pointer sets the frame valid status bit (if the frame is completed with no error) or the RxCRCE status bit(if the frame was completed, but with a CRC error). If the frame reception is completed, an RxCRCE interrupt (for a frame error) or an RxFV interrupt (for normal state) is generated. At this point, the CPU can read the Rx remaining bytes (RxRB) status bits to know how many bytes of this frame still remain in the HRXFIFO. When you set the frame discontinue control bit (the incoming frame discard control bit) to '1', the receiver discards the current frame data without dropping the flag synchronization. You can use this feature to ignore a frame with a non-matched address. 8-16 S3C4510B HDLC CONTROLLERS Receiver DMA Mode To use DMA operation without CPU intervention, you have to make Rx buffer descriptor chain in advance. And set the DMA Rx buffer descriptor pointer (DMARxPTR) register to the address of the first buffer descriptor of the chain, and then DMA Rx channel should be enabled. HARDWARE FLOW CONTROL TxClock TxD last RTS CTS Figure 8-7. nCTS Already Asserted When nCTS is active and there exists data to be transmitted in Tx FIFO, nRTS enters Low, allowing data transmission. At the beginning of the data is an open flag while at the end a closing flag. If the frame being transferred discontinues, nRTS goes back to the High after the data transmission is completed. TxClock TxD Data 5-13 cycles RTS 14 - 22 cycles CTS Figure 8-8. CTS Lost during Transmission When the condition of nCTS is shifted from Low to High, it is detected at the falling edge of Tx clock, where nRTS also goes High. For about 5 to 13 cycles after nRTS enters High, the data transmission continues. nRTS remains High for a maximum of 22 cycles and goes back to the Low condition if there remains any data to be transmitted in HTxFIFO. If nCTS is still High even when nRTS went back to Low, not the data in HTxFIFO but a mark idle pattern is transmitted when AutoEn bit set to one. 8-17 HDLC CONTROLLERS S3C4510B TxClock TxD 5 - 12 cycles RTS Data CTS Figure 8-9. CTS Delayed on If nCTS remains still High for a while after nRTS enters Low to allow data transmission from HTxFIFO, the data transmission starts 5-12 cycles after nCTS is shifted to Low 8-18 S3C4510B HDLC CONTROLLERS MEMORY DATA STRUCTURE The flow control to the HDLC controller uses two data structures to exchange control information and data. -- Transmit buffer descriptor -- Receive buffer descriptor Each Tx DMA buffer descriptor has the following elements. -- Buffer data pointer -- Ownership bit -- Control field for transmitter -- Status field for Tx -- Transmit buffer length -- Next buffer descriptor pointer Each Rx DMA buffer descriptor has the following elements. -- Buffer data pointer -- Ownership bit -- Status field for Rx -- Accumulated received buffer length for a frame -- Next buffer descriptor pointer 8-19 HDLC CONTROLLERS S3C4510B DATA BUFFER DESCRIPTOR The ownership bit in the MSB of the buffer data pointer controls the ownership of the descriptor. When the ownership bit is '1', the DMA controller owns the descriptor. When this bit is '0', the CPU has the descriptor. The owner of the descriptor always owns the associated data frame. (The descriptor's buffer data pointer field always points to this buffer for about a frame.) As it receives the data, the software sets the maximum frame length register. If the received data is longer than the value of the maximum frame length register, this frame is ignored and the FLV bit is set. The software also sets the DMA Rx buffer descriptor pointer to point to a chain of buffer descriptors, all of which have their ownership bit. The DMA controller can be started to set the DMA Rx enable bit in the control register. When a frame is received, it is moved into memory at the address specified by the DMA Rx data buffer pointer. If a frame is longer than the value of the RxBuf Size register, then the next buffer descriptors are fetched to receive the frame. That is, to handle a frame, one or more buffer descriptors could be used. Please note that no configurable offset or page boundary calculation is required. The received frame is moved to the buffer memory whose address is pointed to by the buffer data pointer until the end of frame, or until the length exceeds the maximum frame length configured.If the length exceeds the maximum frame length configured, the frame length violated bit is set. If the entire frame is received successfully, the status bits in the receive buffer descriptor are set to indicate the received frame status. The ownership bit in the buffer descriptor pointer is cleared by the CPU which has the ownership and an interrupt may now be generated. The DMA controller copies the next buffer descriptor pointer into the DMA Rx buffer descriptor pointer register. If the next buffer descriptor pointer is null(0), the DRxEN bit is cleared, and DMA Rx operation is stopped. Otherwise, the descriptor is read, and the DMA controller starts again with the next data, as described in the previous paragraph. When the DMA reads a descriptor, if the ownership bit is not set, it has two options: -- Skip to the next buffer descriptor when DRxSTSK bit is '0' -- Generate an interrupt and halt the DMA operation when DRxSTSK bit is '1' During transmission, the two-byte frame length at the Tx buffer descriptor is moved to the DMA internal Tx register. After transmission, the Tx status is saved in the Tx buffer descriptor. The DMA controller then updates the next buffer descriptor pointer for the linked list structure. When the DMA Tx buffer descriptor register points to the first buffer descriptor, the transmitter starts transmitting the frame data from the buffer memory to Tx FIFO. 8-20 S3C4510B HDLC CONTROLLERS BUFFER DESCRIPTOR TRANSMIT BUFFER DESCRIPTOR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 O Buffer Data Pointer Reserved Reserved T Buffer Length Next Buffer Descriptor Pointer WA DLENP [30:0] Buffer Data Pointer [31] Ownership (O) 0 = CPU 1 = DMA Tx Control Bits [0] Preamable (P) 0 = No preamble [1] TxNoCRC Mode (N) 0 = CRC mode [2] Little-Endian Mode (E) 0 = Big-endian 1 = Preamble 1 = No CRC mode 1 = Little-endian [3] Last (L) 0 = This is not the last buffer in the frame. 1 = This is the last buffer in the frame. [4] Buffer Data Pointer Decrement (D) 0 = Increment 1 = Decrement [6:5] Widget Aligment Control (WA) 00 = No invalid bytes 01 = 1 invalid bytes 10 = 2 invalid bytes 11 = 3 invalid bytes [23:0] Buffer Length Tx Status Bit These bit may be regarded as valid when the L bit (in Tx control bit) is set. [26] Transmission Completion (T) 0 = Normal 1 = One frame completed [31:0] Next Buffer Descriptor Pointer The address of the next buffer descriptor Figure 8-10. Transmit Buffer Descriptor 8-21 HDLC CONTROLLERS S3C4510B RECEIVE BUFFER DESCRIPTOR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 O Buffer Data Pointer Reserved Reserved F AD LLFBTONC VOD V TM Next Buffer Descriptor Pointer Buffer Length [30:0] Buffer Data Pointer [31] Ownership (O) 0 = CPU 1 = DMA [15:0] Buffer Length Received buffer lengths are wrote to this buffer descriptor Rx Status Bits This bits may be regarded as valid when L bit (in Rx status bit) is set. [16] CD Lost (CD) 0 = Normal 1 = CD lost occurs [17] CRC Error (CE) 0 = Normal 1 = CRC error occurs to the frame received. [18] Non-octet Aligned Frame (NO) 0 = Normal 1 = Non-octet aligned frame is reveived. [19] Over-run (OV) 0 = Normal 1 = The reveived frame overruns. [20] DPLL Two Miss (DTM) 0 = Normal 1 = DPLL two miss clock occurs. [21] Rx Abort (ABT) 0 = Normal 1 = The received frame aborted. [22] First In Frame (F) 0 = This buffer descriptor status is not the first to the frame. 1 = This buffer descriptor status is the first to the frame. [23] Last In Frame (L) 0 = This buffer descriptor status is not the last to the frame. 1 = This buffer descriptor status is the first to the frame. [24] Frame Length Violation (FLV) 0 = Normal 1 = This received frame length exceeds the value of the maximum frame length register. [31:0] Next Buffer Descriptor Pointer The address of the next buffer descriptor Figure 8-11. Receive Buffer Descriptor 8-22 S3C4510B HDLC CONTROLLERS Rx Buffer Descriptor Start Address Pointer Buffer Data Pointer #1 Reserved Status Buffer Length Next Buffer Descriptor Buffer Data Pointer #2 Reserved Status Buffer Length Next Buffer Descriptor Buffer Data #1 Unused Rx Bufsize Register Value Rx Bufsize Register Value Buffer Data #2 Unused Buffer Data #N Unused Buffer Data Pointer #N Reserved Status Buffer Length In single linked lists, the next buffer descriptor is filled with a null address. Next Buffer Descriptor NOTE: Buffer length is accumulated until the last bit is set in STATUS. Buffer data pointer indicates the buffer memory start address. Figure 8-12. Data Structure of the Receive Data Buffer 8-23 HDLC CONTROLLERS S3C4510B HDLC SPECIAL REGISTERS The HDLC special registers are defined as read-only or write-only registers according to the direction of information flow. The addresses of these registers are shown in Table 8-4 and 8-5. The transmitter FIFO register can be accessed using two different addresses, the frame terminate address and the frame continue address. The functions of these addresses are discussed in detail in the FIFO section below. Table 8-4. HDLC Channel A Special Registers Registers HMODE HCON HSTAT HINTEN HTxFIFOC (Frame Continue) HTxFIFOT (Frame Terminate) HRxFIFO HBRGTC HPRMB HSAR0 HSAR1 HSAR2 HSAR3 HMASK HDMATxPTR HDMARxPTR HMFLR HRBSR Offset 0x7000 0x7004 0x7008 0x700c 0x7010 0x7014 R/W R/W R/W R/W R/W W W Description HDLC mode register HDLC control register HDLC status register HDLC interrupt enable register HTxFIFO frame continue register HTxFIFO frame terminate register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 - - 0x7018 0x701c 0x7020 0x7024 0x7028 0x702c 0x7030 0x7034 0x7038 0x703c 0x7040 0x7044 R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W HRxFIFO entry register HDLC BRG time constant register HDLC preamble register HDLC station address 0 HDLC station address 1 HDLC station address 2 HDLC station address 3 HDLC mask register DMA Tx buffer descriptor pointer DMA Rx buffer descriptor pointer Maximum frame length register Receive buffer size register 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0xFFFFFFFF 0xFFFFFFFF 0xXXXX0000 0xXXXX0000 8-24 S3C4510B HDLC CONTROLLERS Table 8-5. HDLC Channel B Special Registers Registers HMODE HCON HSTAT HINTEN HTxFIFOC (Frame Continue) HTxFIFOT (Frame Terminate) HRxFIFO HBRGTC HPRMB HSAR0 HSAR1 HSAR2 HSAR3 HMASK HDMATxPTR HDMARxPTR HMFLR HRBSR Offset 0x8000 0x8004 0x8008 0x800c 0x8010 0x8014 R/W R/W R/W R/W R/W W W Description HDLC mode register HDLC control register HDLC status register HDLC interrupt enable register HTxFIFO frame continue register HTxFIFO frame terminate register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 - - 0x8018 0x801c 0x8020 0x8024 0x8028 0x802c 0x8030 0x8034 0x8038 0x803c 0x8040 0x8044 R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W HRxFIFO entry register HDLC BRG time constant register HDLC preamble register HDLC station address 0 HDLC station address 1 HDLC station address 2 HDLC station address 3 HDLC mask register DMA Tx buffer descriptor pointer DMA Rx buffer descriptor pointer Maximum frame length register Receive buffer size register 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0xFFFFFFFF 0xFFFFFFFF 0xXXXX0000 0xXXXX0000 8-25 HDLC CONTROLLERS S3C4510B HDLC GLOBAL MODE REGISTER Table 8-6. HMODEA and HMODEB Register Registers HMODEA HMODEB Offset 0x7000 0x8000 R/W R/W R/W Description HDLC Mode register HDLC Mode register Reset Value 0x00000000 0x00000000 Table 8-7. HMODE Register Description Bit Number [0] [1] [2] [3] [4] Bit Name Description Multi-Frame in HTxFIFO If this bit is set, more than one frame can be loaded into HTxFIFO. In this in DMA operation (MFF) case, the frame size may be less than the FIFO size. Reserved Rx clock inversion(RXCINV) Tx clock inversion(TXCINV) Rx Little-Endian mode (RxLittle) Not applicable. If this bit set to '0', the receive clock samples the data at the rising edge. If this bit set to '1', the receive clock samples the data at the falling edge. If this bit set to '0', the transmit clock shifts the data at the falling edge. If this bit set to '1', the transmit clock shifts the data at the rising edge. This bit determines whether the data is in Little- or Big-endian format. HRXFIFO is in Little-endian. If this bit is set to '0', then the data on the system bus should be in Big-endian. Therefore the bytes will be swapped in Big- endian. This bit determines whether Tx data is in Little or Big endian (TxLittle) format. HTxFIFO is in Little-endian. If this bit is set to '1', the data on the system bus is Little endian. If this bit is set to '0', the data on the system bus is in Big-endian. (that is, the data bytes are swapped to be Little endian format.) Not applicable These bits determine the length of preamble to be sent before the opening flag when the TxPRMB bit is set in the control register. 000 1byte, 001 2bytes,and 111 8bytes will be sent. Not applicable When the DF bits are '000', data is transmitted and received in the NRZ data format. When DF is '001', the NRZI (zero complement) data format is selected. DF = '010' selects the FM0 data format, DF = '011' the FM1 data format, and DF = '100' the Manchester data format. Not applicable Using this setting, you can configure the clock source for DPLL to one of the following pins: TxC, RxC, MCLK, BRGOUT1, or BRGOUT2. To select one of these pins, set the DPLLCLK bits to '000', '001', '010', '011', or '100', respectively. [5] Tx Little-Endian mode (TxLittle) [7:6] [10:8] Reserved Tx preamble length(TxPL) Reserved Data formats (DF) [11] [14:12] [15] [18:16] Reserved DPLL clock select (DPLLCLK) 8-26 S3C4510B HDLC CONTROLLERS Table 8-7. HMODE Register Description (Continued) Bit Number [19] Bit Name BRG clock select (BRGCLK) Description If this bit is '1', MCLK2 is selected as the source clock for the baud rate generator (BRG). If this bit is '0', the external clock at the RXC pin is selected as the BRG source clock. [22:20] Tx clock select (TxCLK) Using this setting, you can configure the transmit clock source to one of the following pins: TxC, RxC, DPLLOUTT, BRGOUT1, or BRGOUT2. To select one of these pins, set the TxCLK bits to '000', '001', '010', '011', or '100', respectively. [26:24] Rx clock select (RxCLK) Using this setting, you can configure the receive clock source to one of the following pins: TXC, RXC, DPLLOUTR, BRGOUT1, or BRGOUT2. To select one of these pins, set the RxCLK bits to '000', '001', '010', '011', or '100', respectively. [30:28] TxC output pin select (TxCOPS) If you do not use the clock at the TxC pin as the input clock, you can use the TxC pin to monitor TxCLK, RxCLK, BRGOUT1, BRGOUT2, DPLLOUTT, and DPLLOUTR. To select the clock you want to monitory, set the TXCOPS to '000', '001', '010', '011', or '100', respectively. Not applicable. [31] Reserved 8-27 HDLC CONTROLLERS S3C4510B 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 T x B L R TXC DPLL i TxPL RxCLK TxCLK G DF t OPS C CLK t L l K e 43210 R x L i t t l e T x C I N V R x C I N V M F F [0] Muilt-Frame in TxFIFO in DMA Operation (MFF) 0 = Single frame in TxFIFO 1 = Multi frame in TxFIFO [1] Reserved [2] Rx Clock Inversion (RxCINV) 0 = Rx clock rising 1 = Rx clock falling 1 = Tx clock rising [3] Tx Clock Inversion (TxCINV) 0 = Tx clock falling [4] Rx Little-Endian Mode (RxLittle) 0 = The Rx data on the system bus is in Big-Endian format. 1 = The Rx data on the system bus is in Little-Endian format. [5] Tx Little-Endian Mode (TxLittle) 0 = The Tx data on the system bus is in Big-Endian format. 1 = The Tx data on the system bus is in Little-Endian format. [7:6] Reserved [10:8] Tx Preamble Length (TxPL) 000 = 1 byte 001 = 2 byte 010 = 3 byte 011 = 4 byte 100 = 5 byte 101 = 6 byte 110 = 7 byte 111 = 8 byte [11] Reserved [14:12] Data Format (DF) 000 = NRZ data format 010 = FM0 100 = Machester 001 = NRZI 001 = FMI [15] Reserved [18:16] DPLL Clock Select (DPLLCLK) 000 = TXC pin 010 = MCLK 100 = BRGOUT2 0 = RXC pin is selected. 1 = MCLK2 is selected. 001 = RXC pin 011 = BRGOUT1 [19] BRG Clock Select (BRGCLK) [22:20] Tx Clock Select (TxCLK) 000 = TXC pin 010 = DPLLOUTT 100 = BRGOUT2 001 = RXC pin 011 = BRGOUT1 [27] Reserved [30:28] TXC Output Pin Select (TXCOPS) This pin is used for output only when it is not used as an input clock for th DPLL, TxCLK, or RxCLK. 000 = Tx clock 010 = BRGOUT1 100 = DPLLOUTT 001 = Rx clock 011 = BRGOUT2 101 = DPLLOUTR [31] Reserved Figure 8-13. HMODE Register 8-28 S3C4510B HDLC CONTROLLERS HDLC CONTROL REGISTER Table 8-8. HCONA and HCONB Register Registers HCONA HCONB Offset 0x7004 0x8004 R/W R/W R/W Description HDLC channel A control register HDLC channel B control register Reset Value 0x00000000 0x00000000 Table 8-9. HCON Register Description Bit Number [0] [1] [2] [3] [4] Bit Name Tx reset (TxRS) Rx reset (RxRS) DMA Tx reset (DTxRS) DMA Rx reset (DRxRS) Tx enable (TxEN) Description Set this bit to '1' to reset the Tx block. Tx block comprises HTxFIFO and a transmitter block. Set this bit to '1' to reset the Rx block. Rx block comprises HRXFIFO and a receiver block. Set this bit to '1' to reset the DMA Tx block. Set this bit to '1' to reset the DMA Rx block. When the TxEN bit is '0', the transmitter enters a disabled state and the line becomes high state. In this case, the transmitter block is cleared except for the HTxFIFO and the status bits associated with transmit operation are cleared. Data cannot be loaded into the HTxFIFO. If this bit is set to '1', the idle pattern is sent continuously. In this case, the data can be loaded into HTxFIFO, and then sent. [5] Rx enable (RxEN) When the RxEN bit is '0', the receiver enters a disabled state and can not detect the flag pattern, if any. In this case, receiver block is cleared except for the HRXFIFO and the status bits associated with receiver operation are cleared. Data cannot be received. If this bit is set to '1', the flag pattern is detected. In this case, the data received can be loaded into the HRXFIFO, and moved to system memory. [6] DMA Tx enable (DTxEN) The DTxEN bit lets the HDLC Tx operate on a bus system in DMA mode. When DMA Tx is enabled, an interrupt request caused by TxFA status is inhibited and the HDLC does not use the interrupt request to request a data transfer. DMA Tx monitors the HTxFIFO and fills the HTxFIFO. This bit is auto disabled when Tx underrun occurs, or CTS lost, or next buffer descriptor pointer reach null, or the owner bit is not DMA mode when DTxSTSK bit is set. If Tx underrun occurs, DTxABT(in HSTAT) bit set, and abort signal sended. If CTS lost occurs, DTxABT bit set and TxD output goes high state as long as CTS remains high level. 8-29 HDLC CONTROLLERS S3C4510B Table 8-9. HCON Register Description (Continued) Bit Number [7] Bit Name DMA Rx enable (DRxEN) Description The DRxEN bit lets the HDLC Rx operate on a bus system in DMA mode. When DMA Rx is enabled, an interrupt request caused by the RxFA status is inhibited, and the HDLC does not use the interrupt request to request a data transfer. DMA Rx monitors the HRXFIFO and moves the data from the HRXFIFO to memory. This bit is automatically disabled when the next buffer descriptor pointer becomes null, or the owner bit is not in DMA mode when the DTxSTSK bit is set. [8] DPLL enable (DPLLEN) Setting this bit enables the DPLL, causing the DPLL to enter search mode. In Search mode, the DPLL searches for a locking edge in the incoming data stream. After DPLL is enabled (in NRZI mode for example), the DPLL starts sampling immediately after the first edge is detected. (In FM mode, the DPLL examines the clock edge of every other bit to decide what correction must be made to remain in sync.) If the DPLL does not detect an edge during the expected window, it sets the one clock missing bit. If the DPLL does not detect an edge after two successive attempts, it sets the two clock missing bit and the DPLL automatically enters the Search mode. To reset both clocks missing latches, you can disable and re-enable the DPLL using the reset Rx status. [9] BRG enable (BRGEN) This bit controls the operation of the baud rate generator (BRG). To enable the BRG counter, set the BRGEN bit to '1'. To inhibit counting, clear the bit to '0'. When this bit is '0', and TxFA bit in status register is '1', it is indicated that Tx FIFO is empty for 1 word. It means that 1-word data can be loaded to Tx FIFO. Similarly, when this bit is '1', the same status register bit indicate that 4 words of data can be loaded to Tx FIFO without reading the status bit for a second time. Specifically, the status register bit affected by the 1-word or 4-word transfer setting are the transmit data available (TxFA) bit. [10] Tx 4 word mode (Tx4WD) [11] Rx 4 word mode (Rx4WD) When this bit is '0', and the RxFA bit in the status register is '1', it is indicated that Rx FIFO has 1-word data. It means that 1 word data can be moved to memory. Similarly, when this bit is '1', the same status register bit indicates that 4 words of data can be moved in the memory without reading the status bit for a second time. Specifically, the status register bit affected by the 1-word or 4-word transfer setting are the receive data available (RxFA) bit, and the residue bytes status bits, RxRB[3:0]. 8-30 S3C4510B HDLC CONTROLLERS Table 8-9. HCON Register Description (Continued) Bit Number [13:12] Bit Name Rx widget alignment (RxWA) Description These bits determine how many bytes are invalid in the first memory word of the frame to be received. The invalid bytes are inserted when the word is assembled in the HRXFIFO. '00' =No Invalid bytes; '01' = 1 invalid byte, '10' = 2 invalid bytes, '11' = 3 invalid bytes. [14] DMA Tx stop or skip (DTxSTSK) DMA Rx stop or skip (DRxSTSK) DMA Rx memory address decrement (DRxMADEC) Tx flag idle (TxFLAG) This bit determines a DMA Tx stop or skip when DMA has not the ownership associated with the Tx buffer descriptor. DMA Tx is disabled in this condition when this bit is set. This bit determines a DMA Rx stop or skip when DMA has not the ownership associated with the Rx buffer descriptor. If this bit is set, DMA Rx is disabled. This bit determines whether the address is incremented or decremented. If this bit is set to '1', then the address will be decremented. This bit selects the flag 'time fill' mode (active idle) or the mark idle mode (inactive idle) for the transmitter. The selected active or inactive idle state continues until data is sent (after nRESET has return to High level). The flag idle pattern is 7EH; the mark idle pattern is FFH. This bit controls whether separate closing and opening flags are transmitted in succession to delimit frames. When this bit is '0', independent opening and closing flags are transmitted in order to separate frame. When this bit is set to '1', the closing flag of the current frame serves as the opening flag of the next frame. [19] Tx loop-back mode (TxLOOP) This bit is used for self-testing. If this bit is set to '1', the transmit data output (TxD) is internally connected to the receiver data input (RxD). In Loop-back mode, nCTS and nDCD inputs are ignored. For normal operation, this bit should always be '0'. Setting this bit to '1' selects the auto-echo mode of operation. In this mode, the TxD pin is connected to RxD as in local loop-back mode, but the receiver still monitors the RxD input. When this bit is set to '1', the abort pattern that is initiated when TxABT = '1' is extended to at least 16 bits of 1s in succession, and the mark idle state is entered. When this bit is set to '1', an abort sequence of at least eight bits of 1s is transmitted. The abort is initiated and the HTxFIFO is cleared. TxABT is then cleared automatically by hardware. [15] [16] [17] [18] Tx single flag (TxSFLAG) [20] Rx echo mode (RxECHO) Tx abort extension (TxABTEXT) Tx abort (TxABT) [21] [22] 8-31 HDLC CONTROLLERS S3C4510B Table 8-9. HCON Register Description (Continued) Bit Number [23] Bit Name Description Tx preamble (TxPRMB) When this bit is set to '1', the content of the HPRMB register is transmitted as many TxPL bit values in interrupt mode instead of mark idle or time fill mode. This is useful for sending the data needed by the DPLL to lock the phase. In DMA mode, this bit is meaningless. Tx data terminal ready (TxDTR) Rx frame discontinue (RxDISCON) The TxDTR bit directly controls the nDTR output state. Setting this bit forces the nDTR pin to Low level. When you clear the TxDTR bit, nDTR goes High. When this bit is set, the frame currently received is ignored and the data in this frame is discarded. Only the last frame received is affected. There is no effect on subsequent frames, even if the next frame enters the receiver when the discontinue bit is set. This bit is automatically cleared after a cycle. [24] [25] [26] [27] [28] Tx no CRC (TxNOCRC) When this bit is set to '1', the CRC is not appended to the end of a frame by hardware. Rx no CRC (RxNOCRC) When this bit is set to '1', the receiver does not check for CRC by hardware. (CRC data is always moved to the HRxFIFO.) Auto enable (AutoEN) This bit programs the function of both nDCD and nCTS. However, TxEN and RxEN must be set before the nCTS and nDCD pins can be used. When this bit is '0', if the nCTS becomes high, the transmitter sends mark idle pattern. However, though the nDCD becomes high, the receiver can receive the data. When this bit is '1', if the nCTS becomes high, the transmitter send mark idle but clears the HTxFIFO and the Tx block. If nDCD becomes high, the receiver can't operate, and the HRxFIFO and Rx blocks are cleared. [31:29] Reserved Not applicable. 8-32 S3C4510B HDLC CONTROLLERS 31 30 29 28 A u t o E N 27 R x N O C R C 26 T x N O C R C 25 R x D I S C O N 24 T x D T R 23 T x P R M B 22 T x A B T 21 20 TR xx AE BC TH EO X T 19 T x L O O P 18 T x S F L A G 17 T x F L A G 16 D R x M A D E C 15 D R x S T S K 14 13 12 D R T x xW S A T S K 11 R x 4 W D 10 T x 4 W D 9 B R G E N D P L L E N 8765 DDR RTx xxE EEN NN 43210 T x E N D R x R S D T x R S R x R S T x R S [0] Tx reset (TxRS) 0 = Normal 1 = TxFIFOmand Tx block are reset. 1 = RxFIFO and Rx block are reset. 1 = DMA Tx block is reset. 1 = DMA Rx block is reset. 1 = Tx enabled 1 = Rx enabled 1 = DMA Tx enabled 1 = DMA Rx enabled [1] Rx reset (RxRS) 0 = Normal operation [2] DMA Tx reset (DTxRS) 0 = Normal operation [3] DMA Rx reset (DRxRS) 0 = Normal operation [4] Tx enable (TxEN) 0 = Tx disabled [5] Rx enable (RxEN) 0 = Rx disabled 0 = DMA Tx disabled 0 = DMA Rx disabled [6] DMA Tx enable (DTxEN) [7] DMA Rx enable (DRxEN) [8] DPLL enable (DPLLEN) 0 = Disable 1 = Enable; DPLL enters search mode for a locking edge in the incoming data stream. [9] BRG enable (BRGEN) 0 = BRG counter is inbibited. 1 = BRG counter is enabled. [10] Tx 4 word burst mode (Tx4WD) 0 = 1-word mode selected. 0 = 1-word mode selected. 00 = No invalid byte 01 = 1 invalid byte 10 = 2 invalid byte 11 = 3 invalid byte 1 = 4-word mode selected. 1 = 4-word mode selected. [11] Rx 4 word burst mode (Rx4WD) [13:12] Rx widget algnment (RxWA) [14] DMA Tx stop or skip (DTxSTSK) 0 = DMA Tx skips when DMA not owner bit is set. 1 = DMA Tx stops when DMA not owner bit is set. [15] DMA Rx stop or skip (DRxSTSK) 0 = DMA Rx skips when DMA not owner bit is set. 1 = DMA Rx stops when DMA not owner bit is set. [16] DMA Rx memory address decrement (DRxMADEC) 0 = Address is incremented. 1 = Address is decremented. [17] Tx flag idle (TxFLAG) 0 = Enter mark idle mode (a bit pattern of consecutive ones) 1 = Enter time fill mode (a bit pattern of consecutive opening (closing) flag, as in string 01111110 01111110...... Figure 8-14. HDLC Control Register (HCON) 8-33 HDLC CONTROLLERS S3C4510B 31 30 29 28 A u t o E N 27 26 25 RTR xxx NND OO I CCS RRC CCO N 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 TTTTRTTTDDD R RTBDDDR xxxxxxxxRRT x xxRPRTx DPAAELSFxxx W 44GLxxE TRBBCOFLMSS A WWE L E E N RMT THOLAATT DDNENN B EOPAGDSS N G EKK X C T 43210 T x E N D R x R S D T x R S R x R S T x R S [18] Tx single flag (TxSFLAG) 0 = Double flag mode (a closing & opening flags are used to separate frames) 1 = Single flag mode (only one flags are used to separate frames) [19] Tx loop-back mode (TxLOOP) 0 = Normal operation. 1= The tramsmit data output is internally connected to the receiver data input for self testing. [20] Rx echo mode (RxECHO) 0 = Disable Tx auto-echo mode. 1 = Enable Rx DMA Tx block is reset. [21] Tx abort extension (TxABTEXT) 0 = At least consecutive eigth 1s are transferred. 1 = At least 16 consecutive 1s are transferred. [22] Tx abort (TxABT) 0 = Normal 1 = Enable (at least eight consecutive 1s are transmitted.) [23] Tx preamble (TxPRMB) 0 = Transmit a mark idle is time fill bit pattern. 1 = Transmit the content of HPRMB [24] Tx data terminal ready (TxDTR) 0 = nDTR goes high level. 1 = nDTR goes low level. [25] Rx frame discontinue (TxDISCON) 0 = Normal 1 = Ignore the currently received frame [26] Tx No CRC (TxNOCRC) 0 = Disable 1 = CRC is not appended by hardware. [27] Rx No CRC (RxNOCR) 0 = Disable 1 = Receiver does not check CRC by hardware. (CRC is treated as data in any case) [28] Auto enable (AutoEN) 0 = Normal operation. The nCTS and nDCD become high, the transmitter sends mark idle and receiver receives data. 1 = The nDCD and nCTS become high, RxFIFO, Rx block, TxFIFO, and Tx block are cleared. The transmitter sends mark idle, and the receiver does not operate. [31:29] Reserved Figure 8-15. HDLC Control Register (HCON) (Continued) 8-34 S3C4510B HDLC CONTROLLERS HDLC STATUS REGISTER (HSTAT) NOTE Reading the HDLC status register is a non-destructive process. The method used to clear a High-level status condition depends on the bit's function and operation mode (DMA or interrupt). For details, please see the description of each status register. Table 8-10. HSTATA and HSTATB Register Registers HSTATA HSTATB SUMMARY There are two kinds of bits in a status register. 1. TxFA, TxCTS, RxFA, RxDCD, RxFV, RxCRCE, RxNO, RxIERR, and RxOV bits are show each bit's status. These bits are set or cleared automatically according to the each bit status. 2. All other bits are cleared by the CPU writing '1' to each bit. Offset 0x7008 0x8008 R/W R/W R/W Description HDLC Channel A Status Register HDLC Channel B Status Register Reset Value 0X00000000 0X00000000 8-35 HDLC CONTROLLERS S3C4510B Table 8-11. HSTAT Register Description Bit Number [3:0] Bit Name Rx remaining bytes (RxRB) Description (RxRB + 1) indicates how many data bytes are valid in a 1-word or 4-word boundary when the receiver has received a complete frame. In 1-word transfer mode, the RxRB value is either 0, 1, 2, or 3. In 4-word mode, it is 0, 1, ..., 14, or 15. This status bit is automatically set to '1' when the two conditions are met: 1) there is no data in the Tx FIFO, and 2) either an abort or a closing flag is transmitted. You can clear this bit by writing '1' to this bit. If this bit is '1', the data to be sent can be loaded into the HTxFIFO register. In 1-word transfer mode, the TxFA status bit is set to '1' when the first register of the HTxFIFO is empty. In 4-word transfer mode, TxFA = '1' when the first four 32-bit registers of the HTxFIFO are empty. The TxFA status condition is automatically cleared when HTxFIFO is no longer available. During DMA Tx operation, this bit is always '0', so not generating interrupt. [6] Tx clear-to-send (TxCTS) Tx stored clear-to-send (TxSCTS) Tx under-run (TxU) The nCTS input is projected to this status bit. If the level at the nCTS input pin is Low, this status bit is'1'. If nCTS input pin is High level, TxCTS is '0'. This bit does not generate an interrupt. [7] [8] This bit is set to '1' each time a transition in nCTS input occurs. You can clear this bit by writing '1' to this bit. When the transmitter runs out of data during a frame transmission, an underrun occurs and the frame is automatically terminated by transmitting an abort sequence. The underrun condition is indicated when TxU is '1'. You can clear this bit by writing a '1' to this bit. This status bit indicates when the data received can be read from the Rx FIFO. When RxFA is '1', it indicates that data (other than an address or a final data word) is available in the HRXFIFO. In 1-word transfer mode, RxFA bit set to '1' when received data is available in the last FIFO register. In 4-word transfer mode, it is set to '1' when the data received is available in the last four 32-bit FIFO registers. Even if the data reside in FIFO for only two words, when the Last bit is set, Rx FIFO is regarded as valid. (The received data available condition is cleared automatically when the data received is no longer available.) During DMA Rx operation, this bit is always '0', so does not generate an interrupt. No applicable. [4] Tx frame complete (TxFC) Tx FIFO available (TxFA) [5] [9] Rx FIFO available (RxFA) [10] Reserved 8-36 S3C4510B HDLC CONTROLLERS Table 8-11. HSTAT Register Description (Continued) Bit Number [11] Bit Name Description Rx flag detected (RxFD) This bit is set to '1' when the last bit of the flag sequence is received. This bit generates an interrupt if enabled. You can clear this bit by writing a '1' to this bit. Rx data carrier detected The DCD status bit mirrors the state of the nDCD input pin. If nDCD input (RxDCD) pin is low, this status bit is '1'. If nDCD input pin is High, it is '0'. This bit does not generate an interrupt. Rx stored data carrier detected (RxSDCD) Rx frame valid (RxFV) This bit is set to '1' when a transition in nDCD input occurs, and can generate interrupt, if enabled. You can clear this bit by writing a '1' to this bit. This bit signals frame's ending boundary to the CPU and also indicates that no frame error occurred. It is set when the last data byte of a frame is transferred into the last location of the Rx FIFO and is available to be read. The RxIDLE status bit indicates that a minimum of 15 consecutive 1s have been received. The event is stored in the status register and can be used to trigger a receiver interrupt. The RxIDLE bit continues to reflect the inactive idle condition until a '0' is received. You can clear this bit by writing a '1' to this bit. The RxABT status bit is set to '1' when seven or more consecutive 1s (abort sequence) have been received. When an abort is received in an 'inframe' condition, the event is stored in the status register triggering an interrupt request. You can clear this bit by writing a '1' to this bit. The RxCRCE status bit is set a frame is completed with a CRC error. The RxNO bit is set to '1', if received data is non-octet aligned frame. The RxOV status bit is set to '1', if the data received is transferred into the HRXFIFO when it is full, resulting in a loss of data. Continued overruns destroy data in the first FIFO register. This bit is set when there is no more buffer during receiving data. If this bit is set, DRxEN bit is cleared. You can clear this bit by writing '1' to this bit. Not applicable. This bit is set to '1' when abort signal is sent due to the Tx underrun or CTS lost occurred. If this bit is set, DTxEN(in HCON) bit cleared. You can clear this bit by writing '1' to this bit. [12] [13] [14] [15] Rx idle (RxIDLE) [16] Rx abort (RxABT) [17] [18] [19] Rx CRC error (RxCRCE) Rx non-octet align (RxNO) Rx overrun (RxOV) [20] [21] [22] DMA Rx memory overflow (RxMOV) Reserved. DMA Tx abort (DTxABT) 8-37 HDLC CONTROLLERS S3C4510B Table 8-11. HSTAT Register Description (Continued) Bit Number [23] [24] Bit Name Rx internal error (RxIERR) DMA Rx frame done every received frame (DRxFD) DMA Rx null list (DRxNL) Description This bit is set to '1' when received frame will be detected error possibility due to the receive clock is unstable. This bit is set when a DMA Rx operation has successfully operated a frame to memory from HRXFIFO, and when the last byte of a frame has been written to memory. This bit generate interrupt when set to '1' to know a frame is received. You can clear this bit by writing '1' to this bit. If this bit is set, the DMA Rx buffer descriptor pointer has a null address. In this case, DMA Rx is disabled and the data transfer from the Rx FIFO to buffer memory is discontinued. So the HRXFIFO is cleared. You can clear this bit by writing '1' to this bit. This bit is set, when DMA is not owner of the current buffer descriptor, and DRxSTSK bit was set. In this case, DMA Rx is disabled and can generate interrupt, if enabled. If DRxSTSK bit is zero, this bit is always zero. You can clear this bit by writing '1' to this bit. In case of MFF bit is '0' (default), when DNA Tx operation has successfully transferred rest byte of frame from Tx FIFO to destination, this bit will be set to '1'. But if MFF is set to '1', transceiver will keep sending the data until there is no data transfer from memory to TxFIFO. If this bit is set '1', the DMA Tx buffer descriptor pointer has a null address. In this case, DMA Tx is disabled and the data to be transferred discontinued from the buffer memory to Tx FIFO. You can clear this bit by writing '1' to this bit. This bit is set, when DMA is not owner of the current buffer descriptor, and DTxSTSK bit was set. In this case, DMA Tx disabled and can generate interrupt, if enabled. If DTxSTSK bit is zero, this bit is always zero. You can clear this bit by writing '1' to this bit. [25] [26] DMA Rx not owner (DRxNO) [27] DMA Tx frame done (DTxFD) [28] DMA Tx null list (DTxNL) [29] DMA Tx not owner (DTxNO) [30] DPLL one clock missing When operating in FM/Manchester mode, the DPLL sets this bit to '1' if it (DPLLOM) does not detect an edge in its first attempt. You can clear this bit by writing a '1' to this bit. DPLL two clock missing (DPLLTM) When it is operating in the FM/Manchester mode, the DPLL sets this bit to '1' if it does not detect an edge in two successive attempts. At the same time the DPLL enters Search mode. In NRZ/NRZI mode, and while the DPLL is disabled, this bit is always '0'. You can clear this bit by writing a '1' to this bit. [31] 8-38 S3C4510B HDLC CONTROLLERS 31 30 29 28 DDDD PPTT LLxx LLNN TOOL MM 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 DDDDRD RRRRRRRRRR RTTTT TRRRxT xxxxxxxxxx xxxxx xxxxIx MONCA I FSDF FUSCF FNNFEA OVORBDVDCD A CTA DOLDRB V CTL CD TS RT E E D S 43210 T x F C R x R B [3:0] Rx remaining bytes (RxRB) At 1-word boundary: 0000 = Valid data byte is 1 0001 = Valid data byte is 2 0010 = Valid data byte is 3 0011 = Valid data byte is 4 At 4-word boundary: 0000 = Valid data byte is 1 . . 1111 = Valid data byte is 16 [4] Tx frame complete (TxFC) 0 = Normal operation 1 = Automatically set; if two conditions are met: 1) Tx FIFO is empty. 2) An abort or a closing flag is transmitted. [5] Tx FIFO available (TxFA) 0 = Tx FIFO is not available. 1 = Tx FIFO is available. (that is, the data to be transmitted can now be loaded into the Tx FIFO.) [6] Tx clear-to send (TxCTS) 0 = Level at the nCTS input pin is High. 1 = Level at the nCTS input pin is Low. [7] Tx stored clear-to-send (TxSCTS) 0 = Normal operation 1 = A transition occured at the nCTS input. (This transition can be used to trigger an interrupt.) [8] Tx underrun (TxU) 0 = Normal operation 1 = The transmitter ran out of data during transmission. [9] Rx FIFO available (RxFA) 0 = Normal operation 1 = Data is available in the RxFIFO. [10] Reserved [11] Rx flag detected (RxFD) 0 = Normal operation 1 = This bit is set, when the last bit of the flag sequence is received. [12] Rx data-carrier-detected (RxDCD) 0 = nDCD input pin is High 1 = nDCD input pin is Low [13] Rx stored data-carrier-detected (RxSDCD) 0 = Normal operation 1 = When a transition of the nDCD input occurs, this bit is set. [14] Rx frame valid (RxFV) 0 = Normal operation 1 = The last data byte if a frame is transgerred into the last location of RxFIFO. [15] Rx idle (RxIDLE) 0 = Normal operation 1 = A minimum 15 consecutive 1s have been reveived. Figure 8-16. HDLC Status Register 8-39 HDLC CONTROLLERS S3C4510B 31 30 DD PP LL LL TO MM 29 D T x N O 28 D T x N L 27 D T x F D 26 D R x N O 25 D R x N L 24 D R x F D 23 R x I E R R 22 21 20 19 18 17 16 15 D RRRRRR T xxxxxx x MONCA I A OVORBD B V CTL T E E 14 R x F V 13 R x S D C D 12 R x D C D 11 10 9 8 7 6 5 R RTTTT x xxxxx F FUSCF D A CTA TS S 43210 T x F C R x R B [16] Rx abort (RxABT) 0= Normal operation 1 = Seven or more consecutive 1s have been received, in-frame condition. [17] Rx CRC error (RxCRCE) 0 = Normal operation 1 = A frame Rx operation is completed with a CRC error. [18] Rx non-octet align (RxNO) 0 = Received frame is octet. 1 = Received frame is not octet. [19] Rx overrun (RxOV) 0 = Normal operation 1 = Received data is transferred into the RxFIFO when it is full. [20] Rx memory overflow (RxMOV) 0 = Normal operation 1 = Indicates memory overflow when Rx buffer descriptor next pointer has null address. [21] Reserved [22] DMA Tx abort (DTxABT) 0 = Normal operation 1 = Abort signal is sended and DMA Tx enable bit is cleared. [23] Rx internal error (RxIERR) 0 = Normal operation 1 = Received frame is not stable due to receive clock is unstable. [24] DMA Rx frame done every received frame (DRxFD) 0 = Normal operation 1 = DMA Rx operation has successfully transferred a frame from RxFIFO to buffer memory. [25] DMA Rx null list (DRxNL) 0 = Normal operation 1 = DMA Rx buffer descriptor pointer has a null address. [26] DMA Rx not owner (DRxNO) 0 = DMA has the ownership. 1 = CPU has the ownership. [27] DMA Tx frame done (DTxFD) 0 = Normal operation 1 = DMA Tx operation has successfully transferred a frame from memory to TxFIFO. [28] DMA Tx null list (DTxNL) 0 = Normal operation 1 = DMA Tx buffer descriptor pointer has a null address. [29] DMA Tx not owner (DTxNO) 0 = DMA has the ownership. 1 = CPU has the ownership. [30] DPLL one clock missing (DPLLOM) 0 = Normal operation 1 = Set in FM/Machester mode when DPLL does not detect an edge on the first entry. [31] DPLL two clock missing (DPLLTM) 0 = Normal operation 1 = DPLL was not detected on two consecutive edges and search mode was entered. Figure 8-17. HDLC Status Register (Continued) 8-40 S3C4510B HDLC CONTROLLERS HDLC INTERRUPT ENABLE REGISTER (HINTEN) Table 8-12. HINTENA and HINTENB Register Registers HINTENA HINTENB Offset 0x700c 0x800c R/W R/W R/W Description HDLC Interrupt Enable Register HDLC Interrupt Enable Register Reset Value 0X00000000 0X00000000 Table 8-13. HINTEN Register Description Bit Number [3:0] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] Bit Name Reserved TxFCIE TxFAIE Reserved TxSCTSIE TxUIE RxFAIE Reserved RxFDIE Reserved RxSDCDIE RxFVIE RxIDLEIE RxABTIE RxCRCEIE RxNOIE RxOVIE RxMOVIE Reserved DTxABTIE RxIERRIE DRxFDIE DRxNLIE DRxNOIE DTxFDIE DTxNLIE DTxNOIE DPLLOMIE DPLLTMIE Description - Tx frame complete interrupt enable Tx FIFO available to write interrupt enable - CTS transition has occurred interrupt enable Tx under-run has occurred interrupt enable Rx FIFO available to read interrupt enable - Rx flag detected interrupt enable - DCD transition interrupt enable Rx frame valid interrupt enable Idle detected interrupt enable Abort detected interrupt enable CRC error frame interrupt enable Non-octet aligned frame interrupt enable Rx overrun interrupt enable Rx memory overflow interrupt enable - DMA Tx abort interrupt enable Rx internal error interrupt enable DMA Rx frame done interrupt enable DMA Rx null list interrupt enable DMA Rx not owner interrupt enable DMA Tx frame done every transmitted frame interrupt enable DMA Tx null list interrupt enable DMA Tx not owner interrupt enable DPLL one clock missing interrupt enable DPLL two clocks missing interrupt enable 8-41 HDLC CONTROLLERS S3C4510B 31 D P L L T M I E 30 D P L L O M I E 29 D T x N O I E 28 D T x N L I E 27 D T x F D I E 26 D R x N O I E 25 24 DD RR xx NF LD II EE 23 R x I E R R I E 22 21 20 19 18 17 16 15 D RRRRRR T xxxxxx x MONCA I A OVORBD B VI ICTL T IEEEIE I E IEI E E E 14 R x F V I E 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R R RTT TT x x xxx xx S F FUS FF D D AIC AC C I IET II D E E EE S I I E E [3:0] Reserved [4] Tx frame complete interrupt enable (TxFCIE) [5] Tx FIFO available to write interrupt enable (TxFAIE) [6] Reserved [7] CTS transition has occurred interrupt enable (TxSCTIE) [8] Transmit underrun has occured interrupt enable (TxUIE) [9] RxFIFO available to read interrupt enable (RxFAIE) [10] Reserved [11] Flag detected interrupt enable (RxFDIE) [12] Reserved [13] DCD transition interrupt enable (RxSDCDIE) [14] Valid frame interruopt enable (RxFVIE) [15] Idle detected interruot enable (RxIDLEIE) [16] Abort detected interrupt enable (RxABTIE) [17] CRC error frame interrupt enable (RxCRCEIE) [18] Non-dctet aligned frame interrupt enable (RxNOIE) [19] Rx overrun interrupt enable (RxOVIE) [20] Rx memory overflow interrupt enable (RxMOVIE) [21] Reserved [22] DMA Tx abort interrupt enable (DTxABTIE) [23] Rx internal error interrupt enable (RxIERRIEN) [24] DMA Rx frame done every received frame interrupt enable (DRxFDIE) [25] DMA Rx null list interrupt enable (DRxNLIE) [26] DMA Rx not owner interrupt enable (DRxNOIE) [27] DMA Tx frame done every received frame interrupt enable (DTxFDIE) [28] DMA Tx null list interrupt enable (DTxNLIE) [29] DMA Tx not owner interrupt enable (DTxNOIE) [30] DPLL one missing interrupt enable (DPLLOMIE) [31] DPLL two missing interrupt enable (DPLLTMIE) Figure 8-18. HDLC Interrupt Enable Register 8-42 S3C4510B HDLC CONTROLLERS HDLC TX FIFO (HTXFIFO) The Tx FIFO consists of eight 32-bit registers that are used for buffer storage of data to be transmitted. Data is always transferred from a full register to an empty adjacent register. The Tx FIFO can be addressed at two different register addresses: the 'frame continue' address and the 'frame terminate' address. Each register has four pointers, data valid pointer bit (4 bits), last pointer bit, NoCRC pointer bit, Preamble pointer bit. The data valid pointer bit indicates whether each byte is valid or not. The last byte pointer bit indicates whether the frame to be sent has the frame last byte or not. The NoCRC pointer bit determines whether the CRC data is to be appended or not by hardware. When a valid data byte is written to the 'frame continue' address, the data valid pointer is set, but the last byte pointer is not set. When a valid data byte is written to the 'frame terminate' address, the data valid pointer and last byte pointer are set together. To reset these pointers, you write a '1' to either the TxABT bit or the TxRS bit in the HCON register. In DMA mode, when the DMA controller writes data to the HTxFIFO, Tx buffer descriptor Buffer Length field value must be pre-set. However, if the Last bit is set in buffer descriptor, the last byte pointer in HTxFIFO is also set. This means the last byte of the frame is in HTxFIFO. If the transmitted frame is longer than the Buffer Length field value, the last byte pointer will not be set, and the next buffer descriptor having the last byte pointer bit will be used. The pointers continue shifting through the FIFO. When the transmitter detects a positive transition in the data valid pointer at the last location of the FIFO, it initiates a frame with an opening flag. When it detects a negative transition in the last byte pointer at the last location of the FIFO, it closes the frame, appending the CRC and a closing flag follows. The status of the Tx FIFO is indicated by the transmitter FIFO register available (TxFA) status bit. When TxFA = '1', the Tx FIFO is available for loading data and data can be loaded into it. (This function is controlled by the Tx4WD bit.) The HTxFIFO is reset by writing a '1' to the Tx reset, or the TxABT bit or by the nRESET. During a reset operation, the TxFA status bit is suppressed and data loading is inhibited. TxFIFO 8-bit 8-bit 8-bit 8-bit Data Valid (4-bit) Last (1-bit) NoCRC Preamble 8 Tx Data Figure 8-19. HDLC Tx FIFO Function Diagram 8-43 HDLC CONTROLLERS S3C4510B HDLC RX FIFO (HRXFIFO) The Rx FIFO consists of eight 32-bit registers that are used for the buffer storage of the data received. Data bytes are always transferred from a full register to an adjacent empty register. Each register has pointer bits that indicate the frame status. When these pointers appear at the last 1-word or 4-word FIFO location, they update the LAST bit(indicating the last of a frame), the OVERRUN bit, the CRC error bit, or Non-octet aligned bit. The HRXFIFO data available (RxFA) status bits indicate the current state of the HRXFIFO. When the HRXFIFO data status bit is '1', the HRXFIFO is ready to be read. The HRXFIFO data status is controlled by the 4-word or 1word transfer selection bit (Rx4WD). When an overrun occurs, the overrun frame of the HRXFIFO is no longer valid. An 'in frame' abort or a High level on nDCD input with the AutoEN bit in HCON is set to '1', the frame is cleared in the HRXFIFO. (The last byte of the previous frame, which is separated by the frame boundary pointer, is retained). Data in HRXFIFO should be read by word size. The HRXFIFO is cleared by the Rx reset bit set to '1', an abort signal received, or nRESET. RxFIFO 8-bit 8-bit 8-bit 8-bit Data Valid Last OV CRCE NO Rx Data Figure 8-20. HDLC Rx FIFO Function Diagram 8-44 S3C4510B HDLC CONTROLLERS HDLC BRG TIME CONSTANT REGISTERS (HBRGTC) Table 8-14. HBRGTCA and HBRGTCB Register Registers HBRGTCA HBRGTCB Offset 0x701c 0x801c R/W R/W R/W Description HDLC BRG Time Constant Register HDLC BRG Time Constant Register Reset Value 0x00000000 0x00000000 The HDLC BRG time constant register value can be changed at any time, but the new value does not take effect until the next time the constant is loaded into the down counter. No attempt is made to synchronize the loading of the time constant into HBRGTC while the clock is driving the down counter. For this reason, you should first disable the baud rate generator before loading the new time constant into the HBRGTC register. The formula for determining the appropriate time constant for a given baud rate is shown below. The desired rate is shown in bits per second. This formula shows how the counter decrements from N down to zero-plus-one cycles for reloading the time constant. This value is then fed to a toggle flip-flop to generate the square wave output. BRGOUT1 = (MCLK2 or RXC)/(CNT0 + 1)/(16CNT1) BRGOUT2 = BRGOUT1/(1 or 16 or 32 according to CNT2 value of the HBRGTC) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT0 CNT1 CNT2 [1:0] Time constant value for CNT2 00 = divide by 1 01 = adivide by 16 10 = divide by 32 [3:2] Time constant value for CNT1 00 = divide by 1 01 = divide by 16 [15:4] Time constant value for CNT0 Figure 8-21. HDLC BRG Time Constant Register 8-45 HDLC CONTROLLERS S3C4510B HDLC PREAMBLE CONSTANT REGISTER (HPRMB) The HPRMB register is used to meet the DPLL requirements for phase-locking. The preamble pattern is transmitted as many Tx preamble length bit values in HMODE[10:8] when the Tx preamble bit (TxPRMB) is '1', and then the Tx preamble bit is cleared automatically. The opening flag follows this preamble pattern, and the data will be transmitted. Table 8-15. HPRMBA and HPRMBB Register Registers HPRMBA HPRMBB Offset 0x7020 0x8020 R/W R/W R/W Description HDLC Preamble Constant Register HDLC Preamble Constant Register Reset Value 0x00000000 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Preamble Pattern [7:0] Preamble Pattern Figure 8-22. HDLC Preamble Constant Register The reference for the preamble pattern of each data mode is as follows: Table 8-16. Preamble Reference Pattern Data Mode NRZ NRZI FM0 FM1 MANCHESTER Preamble Pattern AA 00 FF 00 AA 8-46 S3C4510B HDLC CONTROLLERS HDLC STATION ADDRESS REGISTERS (HSADR0-3) AND HMASK REGISTER Each HDLC controller has five 32-bit registers for address recognition: four station address registers and one mask register. Generally, the HDLC controller reads the address of the frame from the receiver, to check it against the four station address values, and then masks the result with the user-defined HMASK register. A "1" in the HMASK register represents a bit position for which an address comparison should occur. A "0" represents a masked bit position. If you check the address up to four bytes, the HMASK register value should be 0xffffffff. Dependent on the HMASK register value, the frame's address is compared. If the address is not matched, this frame is discarded. Table 8-17. HSADR and HMASK Register Registers HSADR0A HSADR1A HSADR2A HSADR3A HMASKA HSADR0B HSADR1B HSADR2B HSADR3B HMASKB Offset 0x7024 0x7028 0x702c 0x7030 0x7034 0x8024 0x8028 0x802c 0x8030 0x8034 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description HDLC station address 0 HDLC station address 1 HDLC station address 2 HDLC station address 3 HDLC address mask register HDLC station address 0 HDLC station address 1 HDLC station address 2 HDLC station address 3 HDLC address mask register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 HMASK HSADR0 HSADR1 HSADR2 HSADR3 0xFFFFFFFF 0xABCDEFGH 0xFFFFFFFF 0xABCDEFGH 0xABCDEFGH HMASK HSADR0 HSADR1 HSADR2 HSADR3 0xFF0000 00 0x55XXXX XX 0x55XXXX XX 0x55XXXX XX 0x55XXXX XX NOTE: Recognize one 32-bit address and the 32-bit broadcast address NOTE: Recognize a single 8-bit address Figure 8-23. Address Recognition 8-47 HDLC CONTROLLERS S3C4510B 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 First byte Second byte Third byte Fourth byte Station address byte register and MASK register [31:24] First address byte [23:16] Second address byte [15:8] Third address byte [7:0] Fourth address byte Figure 8-24. HDLC Station Address and HMASK Register DMA TX BUFFER DESCRIPTOR POINTER REGISTER The DMA transmit buffer descriptor pointer register contains the address of the Tx buffer data pointer on the data to be sent. During a DMA operation, the buffer descriptor pointer is updated by the next buffer data pointer. Table 8-18. DMA Tx Buffer Descriptor Pointer Registers Registers HDMATXPTRA HDMATXPTRB Offset 0x7038 0x8038 R/W R/W R/W Description DMA Tx Buffer Descriptor Pointer DMA Tx Buffer Descriptor Pointer Reset Value 0xFFFFFFFF 0xFFFFFFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMA Tx Buffer Descriptor Pointer [25:0] DMA Tx Buffer Descriptor Pointer Figure 8-25. DMA Tx Buffer Descriptor Pointer 8-48 S3C4510B HDLC CONTROLLERS DMA RX BUFFER DESCRIPTOR POINTER REGISTER The DMA receive buffer descriptor pointer register contains the address of the Rx buffer data pointer on the data to be received. During a DMA operation, the buffer descriptor pointer is updated by the next buffer data pointer. Table 8-19. DMA Rx Buffer Descriptor Pointer Registers Registers HDMARXPTRA HDMARXPTRB Offset 0x703c 0x803c R/W R/W R/W Description DMA Rx Buffer Descriptor Pointer DMA Rx Buffer Descriptor Pointer Reset Value 0xFFFFFFFF 0xFFFFFFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMA Rx Buffer Descriptor Pointer [25:0] DMA Rx Buffer Descriptor Pointer Figure 8-26. DMA Rx Buffer Descriptor Pointer MAXIMUM FRAME LENGTH REGISTER The HDLC controller checks the length of an incoming frame against the user-defined value in DMA mode. If the frame received exceeds this register value, the frame is discarded, and FLV(Frame Length Violated) bit is set in the buffer descriptor belonging to that frame. Table 8-20. HDMATXCNT and HDMARXCNT Registers Registers HMFLRA HMFLRB Offset 0x7040 0x8040 R/W R/W R/W Description Maximum Frame Length Maximum Frame Length Reset Value 0xXXXX0000 0xXXXX0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Maximum Frame Length [15:0] Maximum Frame Length Figure 8-27. Maximum Frame Length Register 8-49 HDLC CONTROLLERS S3C4510B RECEIVE BUFFER SIZE REGISTER The Rx buffer size register contains the 16-bit user-defined value. This user-defined count value determines the buffer size for one Buffer Descriptor. If incoming HDLC frame is longer than the Rx buffer size register value, the next buffer descriptor having the Rx buffer size value will be used. Table 8-21. DMA Rx Buffer Size Register Registers HRBSRA HRBSRB Offset 0x7044 0x8044 R/W R/W R/W Description Receive Buffer Size Register Receive Buffer Size Register Reset Value 0xXXXX0000 0xXXXX0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Receive Buffer Size [15:0] Receive Buffer Size Register Figure 8-28. DMA Receive Buffer Size Register 8-50 S3C4510B DMA CONTROLLER 9 OVERVIEW DMA CONTROLLER The S3C4510B has a two-channel general DMA controller, called the GDMA. The two-channel GDMA performs the following data transfers without CPU intervention: -- Memory-to-memory (memory to/from memory) -- UART-to-memory (serial port to/from memory) The on-chip GDMA can be started by software and/or by an external DMA request (nXDREQ). Software can also be used to restart a GDMA operation after it has been stopped. The CPU can recognize when a GDMA operation has been completed by software polling and/or when it receives an appropriate internally generated GDMA interrupt. The S3C4510B GDMA controller can increment or decrement source or destination addresses and conduct 8-bit (byte), 16-bit (half-word), or 32-bit (word) data transfers. System BUS Mode Selection nXDREQ 0 UART0 UART1 nDACK nXDACK 0 GDMA Port 14 Data GDMA Channel 1 nDREQ nXDREQ 1 Mode Selection nDACK nXDACK 1 GDMA Port 15 Data IOPCON [29:28] IOPCON [27:26] GDMA Channel 0 nDREQ Figure 9-1. GDMA Controller Block Diagram 9-1 DMA CONTROLLER S3C4510B GDMA SPECIAL REGISTERS Table 9-1. GDMA Special Registers Overview Registers GDMACON0 GDMACON1 GDMASRC0 GDMADST0 GDMASRC1 GDMADST1 GDMACNT0 GDMACNT1 Offset 0xB000 0xC000 0xB004 0xB008 0xC004 0xC008 0xB00C 0xC00C R/W R/W R/W R/W R/W R/W R/W R/W R/W Description GDMA controller channel 0 control register GDMA controller channel 1 control register GDMA channel 0 source address register GDMA channel 0 destination address register GDMA channel 1 source address register GDMA channel 1 destination address register GDMA channel 0 transfer count register GDMA channel 1 transfer count register Reset Value 0x00000000 0x00000000 Undefined Undefined Undefined Undefined Undefined Undefined GDMA CONTROL REGISTERS Table 9-2. GDMACON0 and GDMACON1 Registers Registers GDMACON0 GDMACON1 Offset 0xB000 0xC000 R/W R/W R/W Description GDMA controller channel 0 control register GDMA controller channel 1 control register Reset Value 0x00000000 0x00000000 Table 9-3. GDMA Control Register Description Bit Number [0] Bit Name Run enable/disable Reset Value Setting this bit to "1", starts a DMA operation. To stop DMA, you must clear this bit to "0". You can use the GMA run bit control address (GDMACON offset address + 0x20) to manipulate this bit. By using the run bit control address, other GDMA control register values are not affected. When DMA starts, this read-only status bit is automatically set to "1". When it is "0", DMA is idle. Four sources can initiate a DMA operation: 1) software (memoryto-memory), 2) an external DMA request (nXDREQ), 3) the UART0 block, and 4) the UART1 block. The mode selection setting determines which source can initiate a DMA operation at any given time. This bit controls whether the destination address will be decremented ("1") or incremented ("0") during a DMA operation. [1] [3:2] Busy status GDMA mode selection [4] [5] Destination address direction Source address direction This bit controls whether the source address will be decremented ("1") or incremented ("0") during a DMA operation. 9-2 S3C4510B DMA CONTROLLER Table 9-3. GDMA Control Register Description (Continued) Bit Number [6] Bit Name Destination address fix Reset Value This bit determines whether or not the destination address will be changed during a DMA operation. You use this feature when transferring data from multiple sources to a single destination. This bit determines whether or not the source address will be changed during a DMA operation. You use this feature when transferring data from a single source to multiple destinations. To start/stop a DMA operation, you set/clear the run enable bit. If the stop interrupt enable bit is "1" when DMA starts, a stop interrupt is generated when DMA operation stops. If this bit is "0", the stop interrupt is not generated. If this bit is set to one, GDMA operates under 4-data burst mode. under the 4-data burst mode, 4 consecutive source addresses are read and then are written to the consecutive destination addresses. If 4-data burst mode is set to one, "transfer count register" should be set carefully because the 4-data burst move is executed during decreasing of the transfer count. The 4-data burst mode can be used only when GMDA mode is software or external DMA request mode. This bit is used to specify the direction of a DMA operation when the mode bits [3:2] are set to '10' (UART0 from/to memory) or '11' (UART1 from/to memory). If this bit is "1", DMA operates in the memory-to-peripheral direction (e.g., to the parallel port or UART). When it is "0", DMA operates in the peripheral-to-memory direction. This bit determines the number of external DMA requests (nXDREQs) that are required for a DMA operation. In Single mode, when [11] = "0", the S3C4510B requires an external DMA request for every DMA operation. In Block mode, when [11] = "1", the S3C4510B requires only one external DMA request during the entire DMA operation. An entire DMA operation is defined as the operation of DMA until the counter value is zero. NOTE: You should not use block mode together with demand mode, or single mode in conjunction with continuous mode. These bits determine the transfer data width to be one byte, one half-word, or one word. If you select a byte transfer operation, the source/destination address will be incremented or decremented by one with each transfer. Each half-word transfer increments or decrements the address by two, and each word transfer by four. This bit lets the DMA controller hold the system bus until the DMA transfer count value is zero. You must therefore manipulate this bit carefully so that DMA transfer operations do not exceed a acceptable time interval (as, for example, in a DRAM refresh operation). NOTE: You can use continuous mode together with a software request mode. [7] Source address fix [8] Stop interrupt enable [9] Four-data burst enable [10] Peripheral direction [11] Single/Block mode [13:12] Transfer width [14] Continuous mode 9-3 DMA CONTROLLER S3C4510B Table 9-3. GDMA Control Register Description (Continued) Bit Number [15] Bit Name Demand mode Reset Value Setting this bit speeds up external DMA operations. When [15]="1", the DMA transfers data when the external DMA request signal (nXDREQ) is active. The amount of data transferred depends on how long nXDREQ is active. When nXDREQ is active and DMA gets the bus in Demand mode, DMA holds the system bus until the nXDREQ signal becomes non-active. Therefore, the period of the active nXDREQ signal should be carefully timed so that the entire operation does not exceed an acceptable interval (as, for example, in a DRAM refresh operation). NOTE: In demand mode, you must clear the single/block and continuous mode control bits to "0". NOTE: To ensure the reliability of DMA operations, the GDMA control register bits must be configured independently and carefully. 9-4 S3C4510B DMA CONTROLLER 31 16 15 14 13 12 11 10 9 8 7 DC MN T W 6543 M O D E 21 0 STFSSDSD BDBI FFAA BR SE [0] Run enable (RE) 0 = Disable DMA operation [1] Busy status (BS) 0 = DMA is idle 1 = Enable DMA operation 1 = DMA is active [3:2] Mode selection (MODE) 00 = Software mode (memory to memory) 01 = External EXTDREQ mode (for external devices) 10 = UART0 block 11 = UART1 block [4:] Destination address direction (DA) 0 = Increase source address 1 = Decrease source address [5] Source address direction (SA) 0 = Increase source address 1 = Decrease source address [6] Destination address fix (DF) 0 = Increase/decrease destination address 1 = Do not change destination address (fix) [7] Source address fix (SF) 0 = Increase/decrease source address 1 = Do not change source address (fix) [8] Stop interrupt enable (SI) 0 = Do not generate a stop interrupt when DMA stops 1 = Generate a stop interrupt when DMA stops [9] Four-data burst enable (FB) 0 = Disable 4-data burst mode 1 = Enable 4-data burst mode [10] Transfer direction (for UART0/UART1 only) (TD) 0 = UART0/UART1 to memory 1 = Memory to UART0/UART1 [11] Single/block mode (SB) 0 = One nXDREQ initiates a single DMA operation 1 = One nXDREQ initiates a whole DMA operation [13:12] Transfer width (TW) 00 = Byte (8 bits) 10 = Word (32 bits) 01 = Half-word (16 bits) 11 = No use [14] Continuous mode (CN) 0 = Normal operation 1 = Hold system bus until the whole DMA operation stops [15] Demand mode (DM) 0 = Normal external DMA mode 1 = Demand mode Figure 9-2. GDMA Control Register 9-5 DMA CONTROLLER S3C4510B GDMA SOURCE/DESTINATION ADDRESS REGISTERS The GDMA source/destination address registers contain the 26-bit source/destination addresses for GDMA channels 0 and 1. Depending on the settings you make to the GDMA control register (GDMACON), the source or destination addresses will either remain the same, or they will be incremented or decremented. Table 9-4. GDAMSRC0/1 and GDMADST0/1 Registers Registers GDMASRC0 GDMADST0 GDMASRC1 GDMADST1 Offset 0xB004 0xB008 0xC004 0xC008 R/W R/W R/W R/W R/W Description GDMA channel 0 source address register GDMA channel 0 destination address register GDMA channel 1 source address register GDMA channel 1 destination address register Reset Value Undefined Undefined Undefined Undefined 31 26 25 Source/Destination Address 0 [25:0] Source/destination address Figure 9-3. GDMA Source/Destination Address Register 9-6 S3C4510B DMA CONTROLLER DMA TRANSFER COUNT REGISTERS The DMA transfer count registers contain the 24-bit current count value of the number of DMA transfers completed for GDMA channels 0 and 1. The count value is always decremented by one for each completed DMA operation, regardless of the GDMA data transfer width or four-data burst mode. NOTE At the 4-data burst mode, actual transfer data size will be "Transfer Count x4." Table 9-5. GDMACNT0/1 Registers Registers GDMACNT0 GDMACNT1 Offset 0xB00C 0xC00C R/W R/W R/W Description GDMA channel 0 transfer count register GDMA channel 1 transfer count register Reset Value Undefined Undefined 31 24 23 Transfer Count 0 [23:0] Transfer count Figure 9-4. DMA Transfer Count Register 9-7 DMA CONTROLLER S3C4510B GDMA FUNCTION DESCRIPTION The following sections provide a functional description of the GDMA controller operations. GDMA TRANSFERS The GDMA transfers data directly between a requester and a target. The requester and target are memory,UART or external devices. An external device requests GDMA service by activating nXDREQ signal. A channel is programmed by writing to registers which contain requester address, target address, the amount of data, and other control contents. UART, external I/O, or Software(memory) can request GDMA service. UART is internally connected to the GDMA. STARTING/ENDING GDMA TRANSFERS GDMA starts to transfer data after the GDMA receives service request from nXDREQ signal, UART, or Software. When the entire buffer of data has been transferred, the GDMA becomes idle. If you want to preform another buffer transfer, the GDMA must be reprogrammed. Although the same buffer transfer wii be preformed again, the GDMA must be reprogrammed. DATA TRANSFER MODES Single Mode A GDMA request (nXDREQ or an internal request) causes one byte, one half-word, or one word to be transmitted if 4-data burst mode is disable state, or four times of transfer width if 4-data burst mode is enable state. Single mode requires a GDMA request for each data transfer. The nXDREQ signal can be de-asserted after checking that nXDACK has been asserted. nXDREQ nXDACK RD/WR Cycle Figure 9-5. External DMA Requests (Single Mode) 9-8 S3C4510B DMA CONTROLLER Block Mode The assertion of only one GDMA request (nXDREQ or an internal request) causes all of the data, as specified by the control register settings, to be transmitted in a single operation. The GDMA transfer is completed when the transfer counter value reaches zero. The nXDREQ signal can be de-asserted after checking that nXDACK has been asserted. nXDREQ nXDACK RD/WR Cycle Figure 9-6. External DMA Requests (Block Mode) Demand Mode In demand mode, the GDMA continues transferring data as long as the GDMA request input (nXDREQ) is held active. nXDREQ nXDACK RD/WR Cycle Figure 9-7. External DMA Requests (Demand Mode) 9-9 DMA CONTROLLER S3C4510B DMA TRANSFER TIMING DATA Figure 9-8 provides detailed timing data for GDMA data transfers that are triggered by external DMA requests. Please note that read/write timing depends on which memory banks are selected. To access ROM banks, which is in multiplexing bus mode, by 4-data burst mode, refer to Figure A-1 and Figure A-2 of appendix A for read/write timing of ROM bank 5. SCLK (In_MCLK) tEMRs tEMRh nXDREQ tEMAf tEMAr nXDACK Min.3 cycles worst tEMRS tEMRh tEMAf tEMAr setup time hold time delay (falling) delay (rising) 9.55 ns 9.30 ns 3.90 ns 0 ns best 23.30 ns 22.70 ns Figure 9-8. External DMA Requests Detailed Timing (S3C4510X) 9-10 S3C4510B DMA CONTROLLER SCLK (In_MCLK) tEMRs tEMRh nXDREQ tEMAf tEMAr nXDACK Min.3 cycles worst tEMRS tEMRh tEMAf tEMAr setup time hold time delay (falling) delay (rising) 12.19 ns 9.33 ns 6.31 ns 0 ns best 28.54 ns 21.87 ns Figure 9-9. External DMA Requests Detailed Timing (S3C4510B) 9-11 DMA CONTROLLER S3C4510B CLOCK DESCRIPTION The internal clock(In_MCLK; This is the operating clock on the S3C4510B) differs from mclko(pad out clock). For more clear description, internal clock(In_MCLK) is used at this timing diagram. Following Figure 9-9 is the relationship of internal clock(In_MCLK) and mclko(pad out clock). You must think one more step that is the concern with mclko. In_MCLK MCLKO MIN 4.03 ns MAX 10.57 ns NOTE: Each clock periol is 20 ns. Figure 9-10. MCLKO and SCLK (In_MCLK) 9-12 S3C4510B DMA CONTROLLER SINGLE AND ONE DATA BURST MODE (GDMACON[11] = 0, [9] = 0 ) DREQ and DACK signals are active low. Recommand Deasserted Time In_MCLK DREQ a DACK b c Source Address Source Data Destination Address Destination data Address Data NOTES: 1. In this region, DMA operation is independent of the number of DREQ signal pulse. For example, although DREQ signal pulses 3 times in the 'I' region, GDMAC transfers data only one time from source address to destination address. Current DREQ signal is idle state(deasserted) when DACK siganl is idle state (high). Otherwise, GDMAC recognizes current DREQ signal as next one and transfers next data. I recommand that DREQ signal is deasserted when DACK signal is active. 2. 'I' is three more cycles(3+a cycles). The 'a' is internal system bus acquistion time. 3. 'I' signal falls at negative edge In_MCLK clock after source data is valid. Figure 9-11. Single and One Data Burst Mode Timing 9-13 DMA CONTROLLER S3C4510B SINGLE AND FOUR DATA BURST MODE (GDMACON[11] = 0, [9] = 1 ) DREQ & DACK signals are active low. In the four data burst mode, GDMA COUNT Register(GDMA CNT) value decreases by 1 after 4 data transfer. Recommand Deasserted Time In_MCLK DREQ DACK Address S0 S1 S2 S3 D0 D1 D2 D3 S4 Data GDMA CNT N N-1 NOTE: Address order is source address0 -> source address1 -> source address 2 -> source address3 -> destination address0 -> destination address1 -> destination address2 -> destination address3, and Data order is source data0 -> source data1 -> source data2 -> source data3 -> destination data0 -> destination data1 -> destination data2 -> destination data3. Figure 9-12. Single and Four Data Burst Mode Timing 9-14 S3C4510B DMA CONTROLLER BLOCK AND ONE DATA BURST MODE (GDMACON[11] = 1, [9] = 0 ) DREQ and DACK signals are active low. GDMAC transfers data from DREQ signal is active till GDMA COUNT Register consumes. Recommand Deasserted Time In_MCLK DREQ a DACK Address Source Address Source Data Destination Address Destination Data Source Address Source Data Destination Address Destination Data Data NOTE: 'I' is in the block mode, GDMAC starts to operate with first DREQ signal. So in the ideal case, GDMAC don't care the number of DREQ signal pulse. But I recommand that DREQ siganl is deasserted when DACK signal is active state. Figure 9-13. Block and One Data Burst Mode Timing BLOCK AND FOUR DATA BURST (GDMACON[11] = 1, [9] = 1 ) This timing diagram is the same with Single and one data burst exception four data burst. one data burst; source address0 and source data0 destination address0 and destination data0 .... four data burst; source address0 and source data0 source address1 and source data1 source address2 and source data2 source address3 and source data3 destination address0 and destination data0 destination address1 and destination data1 destination address2 and destination data2 destination address3 and destination data3 source address4 and source data4 .... NOTE In the four data burst mode, GDMA COUNT Register value decreases by 1 after 4 data transfer. 9-15 DMA CONTROLLER S3C4510B CONTINUOUS AND ONE BURST MODE (GDMACON[14] = 1, [9] = 0 ) DREQ and DACK signals are active low. Recommand Time In_MCLK DREQ DACK Address S0 D0 S1 D1 S2 D2 S3 D3 Data GDMA CNT 8 7 6 5 4 3 2 1 0 NOTE: S# is source address#, and D# is destination address#. Figure 9-14. Continuous and One Burst Mode Timing CONTINUOUS AND FOUR DATA BURST MODE (GDMACON[14] = 1, [9] = 1 ) This timing diagram is the same with Continuous and one data burst exception four data burst. one data burst; source address0 and source data0 destination address0 and destination data0 source address1 and source data1 destination address1 and destination data1 ... four data burst; source address0 and source data0 source address1 and source data1 source address2 and source data2 source address3 and source data3 destination address0 and destination data0 destination address1 and destination data1 destination address2 and destination data2 destination address2 and destination data2 destination address3 and destination data3 ... NOTE In the four data burst mode, GDMA COUNT Register value decreases by 1 after 4 data transfer. 9-16 S3C4510B DMA CONTROLLER DEMAND AND ONE DATA BURST MODE (GDMACON[15] = 1, [9] = 0 ) DREQ and DACK signals are active low. In_MCLK DREQ DACK Address S0 D0 S1 D1 S2 D2 S3 D3 Data GDMA CNT 8 7 6 5 4 3 2 1 0 NOTE: S# is source address#, and D# is destination address#. If GDMA CNT is zero, GDMAC do not transfer data although DREQ signal asserted. Figure 9-15. Demand and One Data Burst Mode Timing DEMAND & FOUR DATA BURST MODE ( GDMACON[15] = 1, [9] = 1 ) This timing diagram is the same with Demand & one data burst exception four data burst. one data burst; source address0 and source data0 destination address0 and destination data0 ... four data burst; source address0 and source data0 source address1 and source data1 source address2 and source data2 source address3 and source data3 destination address0 and destination data0 destination address1 and destination data1 destination address2 and destination data2 destination address2 and destination data2 destination address3 and destination data3 ... NOTE If you want to use continuous mode, you must set block mode not single mode. If you want to use demand mode, you must set single mode not block mode. 9-17 DMA CONTROLLER S3C4510B NOTES 9-18 S3C4510B UART 10 OVERVIEW SERIAL I/O (UART) The S3C4510B UART (Universal Asynchronous Receiver/Transmitter) unit provides two independent asynchronous serial I/O (SIO) ports. Each port can operate in interrupt-based or DMA-based mode. That is, the UART can generate internal interrupts or DMA requests to transfer data between the CPU and the serial I/O ports. The most important features of the S3C4510B UART include: -- Programmable baud rates -- Infra-red (IR) transmit/receive -- Insertion of one or two Stop bits per frame -- Selectable 5-bit, 6-bit, 7-bit, or 8-bit data transfers -- Parity checking Each SIO unit has a baud rate generator, transmitter, receiver, and a control unit, as shown in Figure 10-1. The baud-rate generator can be driven by the internal system clock, MCLK, or by the external clock, UCLK. The transmitter and receiver blocks have independent data buffer registers and data shifters. Transmit data is written first to the transmit buffer register. From there, it is copied to the transmit shifter and then shifted out by the transmit data pin, UATXDn. Receive data is shifted in by the receive data pin, UARXDn. It is then copied from the shifter to the receive buffer register when one data byte has been received. The SIO control units provide software controls for mode selection, and for status and interrupt generation. NOTE For the UART Tx interrupt method, you should write dummy byte to UART Tx buffer register before initialize UART. With this, you can generate UART Tx interrupt when Tx Buffer empty. 10-1 UART S3C4510B Transmit Buffer Register (UTXBUFn) Baud Rate Divisor (UTBUFn) Baud Rate Generator UATxDn Transmit Shift Register IR Tx Decoder Line Control Register (ULCONn) UART Control Register (UCONn) UART Status Register (USTATn) 0 1 SYSTEM BUS 10-2 nUADTRn nUADSRn Receive Buffer Register (URXBUFn) 0 1 UARxDn IR Rx Decoder Receive Shift Register Figure 10-1. Serial I/O Block Diagram S3C4510B UART UART SPECIAL REGISTERS Table 10-1. UART Special Registers Overview Register ULCON0 ULCON1 UCON0 UCON1 USTAT0 USTAT1 UTXBUF0 UTXBUF1 URXBUF0 URXBUF1 UBRDIV0 UBRDIV1 BRDCNT0 BRDCNT1 BRDCLK0 BRDCLK1 Offset Address 0xD000 0xE000 0xD004 0xE004 0xD008 0xE008 0xD00C 0xE00C 0xD010 0xE010 0xD014 0xE014 0xD018 0xE018 0xD01C 0xE01C R/W R/W R/W R/W R/W R R W W R R R/W R/W W W W W Description UART0 line control register UART1 line control register UART0 control register UART1 control register UART0 status register UART1 status register UART0 transmit buffer register UART1 transmit buffer register UART0 receive buffer register UART1 receive buffer register UART0 baud rate divisor register UART1 baud rate divisor register UART0 baud rate count register UART1 baud rate count register UART0 baud rate clock monitor UART1 baud rate clock monitor Reset Value 0x00 0x00 0x00 0x00 0xC0 0xC0 0xXX 0xXX 0xXX 0xXX 0x00 0x00 0x00 0x00 0x0 0x0 10-3 UART S3C4510B UART LINE CONTROL REGISTERS Table 10-2. ULCON0 and ULCON1 Registers Registers ULCON0 ULCON1 Offset Address 0xD000 0xE000 R/W R/W R/W Description UART0 line control register UART1 line control register Reset Value 0x00 0x00 Table 10-3. UART Line Control Register Description Bit Number [1:0] Bit Name World length (WL) Reset Value This two-bit word length value indicates the number of data bits to be transmitted or received per frame: '00' = 5 bits, '01' = 6 bits, '10' = 7 bits, and '11' = 8 bits. This bit specifies how many Stop bits are used to signal end-offrame (EOF): "0" = one Stop bit per frame and "1" = two Stop bits per frame. The 3-bit parity mode value specifies how parity generation and checking are to be performed during UART transmit and receive operations: '0xx' = no parity, '100' = odd parity, '101' = even parity, '110' = parity is forced/checked as a "1", and '111' = parity forced/checked as a "0". This selection bit specifies the clock source. 0 = Internal (MCLK) 1 = External (UCLK) The S3C4510B UART block supports infra-red (IR) transmit and receive operations. In IR mode, the transmit period is pulsed at a rate of 3/16 that of the normal serial transmit rate (when the transmit data value in the UTXBUF register is zero). To enable IR mode operation, you set ULCON[7] to "1". Otherwise, the UART operates in normal mode. In IR receive mode, the receiver must detect the 3/16 pulsed period to recognize a zero value in the receiver buffer register, URXBUF, as the IR receive data. When bit [7] is "0", normal UART mode is selected. When it is "1", infra-red Tx/Rx mode is selected. [2] Number of Stop bits [5:3] Parity mode (PMD) [6] Serial Clock Selection [7] Infra-red mode 10-4 S3C4510B UART 31 876543210 S IX PMD T WL R B [1:0] Word length per frame (WL) 00 = 5 bits 10 = 7 bits 01 = 6 bits 11 = 8 bits [2] Number of Stop bits at the end of frame (STB) 0 = One stop bit per frame 1 = Two stop bits per frame [5:3] Parity mode (PMD) 0xx = No parity 100 = Odd parity 101 = Even parity 110 = Parity forced/ checked as 1. 111 = Parity forced/checked as 0. [6] Serial clock selection (SC) 0 = Internal (MCLK) 1 = External (UCLK) [7] Infra-red mode selection (IR) 0 = Normal mode operation 1 = Infra-red Tx/Rx mode Figure 10-2. UART Line Control Registers 10-5 UART S3C4510B UART CONTROL REGISTERS Table 10-4. UCON0 and UCON1 Registers Registers UCON0 UCON1 Offset Address 0xD004 0xE004 R/W R/W R/W Description UART0 control register UART1 control register Reset Value 0x00 0x00 Table 10-5. UART Control Register Description Bit Number [1:0] Bit Name Receive mode (RxM) Reset Value This two-bit value determines which function is currently able to read data from the UART receive buffer register, RBR: '00' = disable Rx mode, '01' = interrupt request, '10' = GDMA channel 0 request, and '11' = GDMA channel 1 request. This bit lets the UART generate an interrupt if an exception (a break, frame error, parity error, or overrun error) occurs during a receive operation. If this bit is set to "1", the UART generates a receive status interrupt. If this bit is "0", the receive status interrupt is not generated. [4:3] Transmit mode (TxM) This two-bit value determines which function is currently able to write Tx data to the UART transmit buffer register, UTXBUF. '00' = disable Tx mode, '01' = interrupt request, '10' = GDMA channel 0 request, and '11' = GDMA channel 1 request. Setting UCON[5] causes the S3C4510B to assert its data set ready (DSR) signal output, nUADSR. Clearing this bit to "0" causes the DSR output to be de-asserted. Setting UCON0/1[6] to "1" causes the UART to send a break. If it is "0", a break is not sent. A break is defined as a continuous Low level signal on the transmit data output with a duration of more than one frame transmission time. By setting this bit when the transmitter is empty (transmitter empty bit, USTAT[7] = "1"), you can use the transmitter to time the frame. When USTAT[7] is "1", write the transmit buffer register, UTXBUF, with the data to be transmitted. Then, poll the USTAT[7] value. When USTAT[7] returns to "1", clear (reset) the send break bit, UCON0/1[6]. [7] Look-back mode Setting this bit causes the UART to enter Loop-back mode. In Loop-back mode, the transmit data output is sent High level and the transmit buffer register, UTXBUF, is internally connected to the receive buffer register, URXBUF. NOTE: This mode is provided for test purposes only. For normal operation, this bit should always be "0". [2] Rx status interrupt enable [5] Data set ready (DSR) [6] Send break 10-6 S3C4510B UART 31 876543210 R LSD P B S TxM x RxM S BKR I [1:0] SIO receive mode selection (RxM) 00 = Disable 01 = Interrupt request 10 = GDMA channel 0 request 11 = GDMA channel 1 request [2] Receive status interrupt enable (RxSI) 0 = Do not generate receive status interrupt 1 = Generate receive status interrupt [4:3] SIO transmit mode selection (TxM) 00 = Disable 01 = Interrupt request 10 = GDMA channel 0 request 11 = GDMA channel 1 request [5] Data set ready (DSR) 0 = Deassert S3C4510B DSR output (nUADSR) 1 = Assert S3C4510B DSR output (nUADSR) [6] Send break (SBK) 0 = Do not send break 1 = Send break [7] Loop-back enable (LPB) 0 = Normal operation mode 1 = Enable look-up mode (for testing only) Figure 10-3. UART Control Registers 10-7 UART S3C4510B UART STATUS REGISTER Table 10-6. UCON0 and UCON1 Registers Registers USTAT0 USTAT1 Offset Address 0xD008 0xE008 R/W R R Description UART0 status register UART1 status register Reset Value 0xC0 0xC0 Table 10-7. UART Status Register Description Bit Number [0] Bit Name Overrun error Reset Value USTAT[0] is automatically set to "1" whenever an overrun error occurs during a serial data receive operation. The overrun error indicates that the new received data has overwritten old received data before the old data could be read. If the receive status interrupt enable bit, UCON[2] is "1", a receive status interrupt is generated if an overrun error occurs. This bit is automatically cleared to "0" whenever the UART status register (USTAT) is read. [1] Parity error USTAT[1] is automatically set to "1" whenever a parity error occurs during a serial data receive operation. If the receive status interrupt enable bit, UCON[2], is "1", a receive status interrupt is generated if a parity error occurs. This bit is automatically cleared to "0" whenever the UART status register (USTAT) is read. [2] Frame error USTAT[2] is automatically set to "1" whenever a frame error occurs during a serial data receive operation. A frame error occurs when a zero is detected instead of the Stop bit(s). If the receive status interrupt enable bit, UCON[2] is "1", a receive status interrupt is generated if a frame error occurs. The frame error bit is automatically cleared to "0" whenever the UART status register (USTAT) is read. [3] Break interrupt USTAT[3] is automatically set to "1" to indicate that a break signal has been received. If the receive status interrupt enable bit, UCON[2], is "1", a receive status interrupt is generated if a break occurs. The break interrupt bit is automatically cleared to "0" when you read the UART status register. [4] Data terminal ready (DTR) The USTAT[4] bit indicates the current signal level at the data terminal ready (DTR) pins (nUADTR). When this bit is "1", the level at the DTR pin (nUADTR) is Low. When it is "0", the DTR pin is High level. 10-8 S3C4510B UART Table 10-7. UART Status Register Description (Continued) Bit Number [5] Bit Name Receive data ready Reset Value USTAT[5] is automatically set to "1" whenever the receive data buffer register (URXBUF) contains valid data received over the serial port. The receive data can then be read from the URXBUF. When this bit is "0", the URXBUF does not contain valid data. Depending on the current setting of the UART receive mode bits, UCON[1:0], an interrupt or a DMA request is generated when USTAT[5] is "1". [6] Tx Buffer register empty USTAT[6] is automatically set to "1" when the transmit buffer register (UTXBUF) does not contain valid data. In this case, the UTXBUF can be written with the data to be transmitted. When this bit is "0", the UTXBUF contains valid Tx data that has not yet been copied to the transmit shift register. In this case, the UTXBUF cannot be written with new Tx data. Depending on the current setting of the SIO transmit mode bits, UCON[4:3], an interrupt or a DMA request will be generated whenever USTAT[6] is "1". [7] Transmit complete (TC) USTAT[7] is automatically set to "1" when the transmit buffer register has no valid data to transmit and when the Tx shift register is empty. When the transmitter empty bit is "1", it indicates to software that it can now disable the transmitter function block. 10-9 UART S3C4510B 31 876 TT CB E 5 R D R 4 D T R 3210 BFPO KEEV D [0] Overrun error (OV) 0 = No overrun error during receive 1 = Overrun error (generate receive status interrupt if UCON[2] is 1) [1] Parity error (PE) 0 = No parity error during receive 1 = Parity error (generate receive status interrupt if UCON[2] is 1) [2] Frame error (FE) 0 = No frame error during receive 1 = Frame error (generate receive status interrupt if UCON[2] is 1) [3] Break detect (BKD) 0 = No break received 1 = Break received (generate receive stauts interrupt if UCON[2] is 1) [4] Data terminal ready (DTR) 0 = DTR pin (nUADTR) is High 1 = DTR pin (nUADTR) is Low [5] Receive data ready (RDR) 0 = No vaild data in the receive buffer register 1 = Vaild data present in the receive buffer register (issue interrupt or DMa request if UCON[1:0] is set) [6] Transmit buffer register empty (TBE) 0 = Vaild data in transmit holding register 1 = No data in transmit holdign register (as the setting of UCON[4:3], interrupt or GDMA request is generated) [7] Transmit complete (TC) 0 = Transmit in progress 1 = Transmit complete; no data for Tx Figure 10-4. UART Status Registers 10-10 S3C4510B UART UART TRANSMIT BUFFER REGISTER The UART transmit buffer registers, UTXBUF0 and UTXBUF1, contain an 8-bit data value to be transmitted over the UART channel. Table 10-8. UXTBUF0 and UXTBUF1 Registers Registers UTXBUF0 UTXBUF1 Offset Address 0xD00C 0xE00C R/W W W Description UART0 transmit buffer register UART1 transmit buffer register Reset Value 0xXX 0xXX Table 10-9. UART Status Register Description Bit Number [7:0] Bit Name Transmit data Reset Value This field contains the data to be transmitted over the single channel UART. When this register is written, the transmit buffer register empty bit in the status register, USTAT[6], should be "1". This is to prevent overwriting of transmit data that may already be present in the UTXBUF. Whenever the UTXBUF is written with a new value, the transmit register empty bit, USTAT[6], is automatically cleared to "0". 31 876543210 Transmit Data [7:0] Transmit data for UART Figure 10-5. UART Transmit Buffer Registers 10-11 UART S3C4510B UART RECEIVE BUFFER REGISTER The UART receive buffer registers, URXBUF0 and URXBUF1, contain an 8-bit data value for received serial data. Table 10-10. UXRBUF0 and UXRBUF1 Registers Registers URXBUF0 URXBUF1 Offset Address 0xD010 0xE010 R/W R R Description UART0 receive buffer register UART1 receive buffer register Reset Value 0xXX 0xXX Table 10-11. UART Transmit Register Description Bit Number [7:0] Bit Name Receive data Reset Value This field contains the data received over the single channel UART. When the UART finishes receiving a data frame, the receive data ready bit in the UART status register, USTAT[5], should be "1". This prevents reading invalid receive data that may already be present in the URXBUF. Whenever the URXBUF is read, the receive data ready bit(USTAT[5]) is automatically cleared to "0". 31 876543210 Receive Data [7:0] Receive data for UART Figure 10-6. UART Receive Buffer Registers 10-12 S3C4510B UART UART BAUD RATE DIVISOR REGISTER The values stored in the baud rate divisor registers, UBRDIV0 and UBRDIV1, let you determine the serial Tx/Rx clock rate (baud rate) as follows: BRGOUT = (MCLK2 or UCLK)/(CNT0 + 1)/(16^CNT1)/16 Table 10-12. UBRDIV0 and UBRDIV0 Registers Registers UBRDIV0 UBRDIV1 Offset Address 0xD014 0xE014 R/W R/W R/W Description UART0 baud rate divisor register UART1 baud rate divisor register Reset Value 0x00 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT0 CNT1 [3:0] Baud reate divisor value CNT1 xxx0 = divide by 1 xxx1 = divide by 16 [15:4] Time constant value for CNT0 Figure 10-7. UART Baud Rate Divisor Registers 10-13 UART S3C4510B UART BAUD RATE COUNT AND CLOCK REGISTERS For test purpose only, the internal baud rate up counters, BRDCNT0 and BRDCNT1, can be directly accessed using register addressing. In addition, the baud rate clock can be monitored through the UART data set ready ports, nUADSR. If the BRDCLKn monitor value is "1", the baud rate clock can be monitored at the nUADSR pin. If it is "0" (its default value), or if you write a "0" to the BRDCLKn address, the UARD DSR signal output to the nUADSR port depends on the current setting of UART control register bit 5. Table 10-13. BRDCNTn and BRDCLKn Registers Register BRDCNT0 BRDCNT1 BRDCLK0 BRDCLK1 Offset Address 0xD018 0xE018 0xD01C 0xE01C R/W W W W W Description UART0 baud rate count register UART1 baud rate count register UART0 baud rate clock monitor UART1 baud rate clock monitor Reset Value 0x0 0x0 0x0 0x0 Baud Rate Divisor (UBRDIVn) Baud Rate Clock Compare Logic Match Generator Baud Rate up Counter (URDCNTn) BRDCLKn MCLK nUADSR Chip Internal Chip External Figure 10-8. UART Baud Rate Clock Test Scheme 10-14 S3C4510B UART UART BAUD RATE EXAMPLES UART BRG input clock, MCLK2 is the system clock frequency divided by 2. If the system clock frequency is 50 MHz and MCLK2 is selected, the maximum BRGOUT output clock rate is MCLK2/16 (= 1.5625 MHz). UCLK is the external clock input pin for UART0, UART1. UART BRG input clock, MCLK2, UCLK can be selected by UCCON[6] register. CNT0 MCLK2 UCLK 12-bit Counter CNT1 BRGOUT Sample Clock Divide by 1 or 16 Divide by 16 SC NOTE: CNT0 = UBTDIVn [15:4], CNT1 = UBRDIVn [3:0], SC = ULCON [6] Figure 10-9. UART Baud Rate Generator (BRG) Table 10-14. Typical Baud Rates Examples of UART Baud Rates (BRGOUT) 1200 2400 4800 9600 19200 38400 57600 115200 230400 460860 CNT0 1301 650 324 162 80 40 26 13 6 2 MCLK2 = 25 MHz CNT1 0 0 0 0 0 0 0 0 0 0 Freq. 1200.1 2400.2 4807.7 9585.9 19290.1 38109.8 57870.4 111607.1 223214.28 520833.34 Dev.(%) 0.0 0.0 0.2 - 0.1 0.5 - 0.8 0.5 - 3.1 3.12 13.01 CNT0 1735 867 433 216 108 53 35 17 8 4 UCLK = 33 MHz CNT1 1 1 0 0 0 0 0 0 0 0 Freq. 1200.08 2400.15 4800.31 9600.61 19113.15 38580.15 57870.37 115740.74 231481.48 416666.66 Dev.(%) 0.0064 0.0064 0.0064 0.0064 0.45 0.47 0.47 0.47 0.47 9.59 10-15 UART S3C4510B < Receiver > UTXDn Start Data Bits (5-8) Parity Stop (1-2) Start THRE WR_THR INT_TXD < Receiver > Stop (1-2) URXDn Start Data Bits (5-8) Parity Start Data Bits INT_RXD URXBUF Previous Receive Data Valid Receive Data Figure 10-10. Interrupt-Based Serial I/O Timing Diagram (Tx and Rx Only) 10-16 S3C4510B UART TxD Start Data Bits (5-8) Parity THRE WR_THR nXDREQ nXDACK Figure 10-11. DMA-Based Serial I/O Timing Diagram (Tx Only) < Receiver > RxE Select DMA Mode URXDn Start Data Bits (5-8) Parity Stop (1-2) Start Data Bits URXBUFn Previous Receive Data Valid Receive Data nXDREQ nXDACK Figure 10-12. DMA-Based Serial I/O Timing Diagram (Rx Only) 10-17 UART S3C4510B SIO Frame Start Bit Stop Bit Data Bits 0 1 0 1 0 0 1 1 0 1 Figure 10-13. Serial I/O Frame Timing Diagram (Normal UART) IR Transmit Frame Start Bit Stop Bit Data Bits 3/16T 0 1 0 1 0 0 1 1 0 1 Bit frame = T 7/16T 6/16T Figure 10-14. Infra-Red Transmit Mode Frame Timing Diagram 10-18 S3C4510B UART IR Receive Frame Start Bit Stop Bit Data Bits 3/16T 0 1 0 1 0 0 1 1 0 1 Bit frame = T 13/16T Figure 10-15. Infra-Red Receive Mode Frame Timing Diagram 10-19 UART S3C4510B NOTES 10-20 S3C4510B 32-BIT TIMERS 11 OVERVIEW 32-BIT TIMERS The S3C4510B has two 32-bit timers. These timers can operate in interval mode or in toggle mode. The output signals are TOUT0 and TOUT1, respectively. You enable or disable the timers by setting control bits in the timer control register, TCON. An interrupt request is generated whenever a timer count-out (down count) occurs. INTERVAL MODE OPERATION In interval mode, a timer generates a one-shot pulse of a preset timer clock duration whenever a time-out occurs. This pulse generates a time-out interrupt that is directly output at the timer's configured output pin (TOUTn). In this case, the timer frequency monitored at the TOUTn pin is calculated as: f TOUT = fMCLK / Timer data value TOGGLE MODE OPERATION In toggle mode, the timer pulse continues to toggle whenever a time-out occurs. An interrupt request is generated whenever the level of the timer output signal is inverted (that is, when the level toggles). The toggle pulse is output directly at the configured output pin. Using toggle mode, you can achieve a flexible timer clock range with 50% duty. In toggle mode, the timer frequency monitored at the TOUTn pin is calculated as follows: f TOUT = fMCLK / (2 * Timer data value) fTOUT Interval Mode Time-out Toggle Mode (Initial TOUTn is 0) Time-out fTOUT Time-out Figure 11-1. Timer Output Signal Timing 11-1 32-BIT TIMERS S3C4510B TIMER OPERATION GUIDELINES The block diagram in Figure 11-2 shows how the 32-bit timers are configured in the S3C4510B. The following guidelines apply to timer functions. -- When a timer is enabled, it loads a data value to its count register and begins decrement the count register value. -- When the timer interval expires, the associated interrupt is generated. The base value is then reloaded and the timer continues decrement its count register value. -- If a timer is disabled, you can write a new base value into its registers. -- If the timer is halted while it is running, the base value is not automatically re-loaded. 32-Bit Timer Data Register (TDATAn) Auto Re-load INTPND and INTMSK fMCLK TMOD.TEn 32-Bit Timer Count Register (TCNTn) [Down Counter] PND Interrupt Request TMOD.TMDn TMOD.TCLRn Pulse Generator TOUTn Port 16, Port 17 Data Out IOPCON.TOENn Figure 11-2. 32-Bit Timer Block Diagram 11-2 S3C4510B 32-BIT TIMERS TIMER MODE REGISTER The timer mode register, TMOD, is used to control the operation of the two 32-bit timers. TMOD register settings are described in Figure 11-3. Table 11-1. TMOD Register Register TMOD Offset Address 0x6000 R/W R/W Description Timer mode register Reset Value 32'h00000000 31 65 T C L R 1 432 TTT DEC M1L R 1 0 10 TT DE M0 0 [0] Timer 0 enable (TE0) 0 = Disable timer 0 1 = Enable timer 0 [1] Timer 0 mode selection (TMD0) 0 = Interval mode 1 = Toggle mode [2] Timer 0 initial TOUT0 value (TCLR0) 0 = Initial TOUT0 is 0 in toggle mode 1 = Initial TOUT0 is 1 in toggle mode [3] Timer 1 enable (TE1) 0 = Disable timer 1 1 = Enable timer 1 [4] Timer 1 mode selection (TMD1) 0 = Interval mode 1 = Toggle mode [5] Timer 1 initial TOUT1 value (TCLR1) 0 = Initial TOUT1 is 0 in toggle mode 1 = Initial TOUT1 is 1 in toggle mode Figure 11-3. Timer Mode Register (TMOD) 11-3 32-BIT TIMERS S3C4510B TIMER DATA REGISTERS The timer data registers, TDATA0 and TDATA1, contain a value that specifies the time-out duration for each timer. The formula for calculating the time-out duration is: (Timer data + 1) cycles. Table 11-2. TDATA0 and TDATA1 Registers Register TDATA0 TDATA1 Offset Address 0x6004 0x6008 R/W R/W R/W Description Timer 0 data register Timer 1 data register Reset Value 0x00000000 0x00000000 31 Receive Data 0 [31:0] Timer 0/1 data value Figure 11-4. Timer Data Registers (TDATA0, TDATA1) TIMER COUNT REGISTERS The timer count registers, TCNT0 and TCNT1, contain the current timer 0 and 1 count value, respectively, during normal operation. Table 11-3. TCNT0 and TCNT1 Registers Register TCNT0 TNCT1 Offset Address 0x600C 0x6010 R/W R/W R/W Description Timer 0 counter register Timer 1 counter register Reset Value 0xFFFFFFFF 0xFFFFFFFF 31 Timer Count 0 [31:0] Timer 0/1 count value Figure 11-5. Timer Counter Registers (TCNT0, TCNT1) 11-4 S3C4510B I/O PORTS 12 OVERVIEW I/O PORTS The S3C4510B has 18 programmable I/O ports. You can configure each I/O port to input mode, output mode, or special function mode. To do this, you write the appropriate settings to the IOPMOD and IOPCON registers. User can set filtering for the input ports using IOPCON register. The modes of the ports from port0 to port7 are determined only by the IOPMOD register. But port[11:8] can be used as xINTREQ[3:0], port[13:12] as nXDREQ[1:0], port[15:14] as nXDACK[1:0], port[16] as TOUT0, or port[17] as TOUT1 depending on the settings in IOPCON register. IOPMOD IOPCON Alternate Functions Output Latch IOPDATA (Write) SYSTEM BUS VDD Port0 - Port7 Port8/xINTREQ0 Port11/xINTREQ3 Port12/nXDREQ0 Port13/nXDREQ1 Port14/nXDACK0 Port15/nXDACK1 Port16/TOUT0 Port17/TOUT1 Active On/Off & Edge Detection Filter On/Off IOPDATA (Read) Input Latch Interrupt or DMA Request IOPCON IOPCON Figure 12-1. I/O Port Function Diagram 12-1 I/O PORTS S3C4510B I/O PORT SPECIAL REGISTERS Three registers control the I/O port configuration: IOPMOD, IOPCON, and IOPDATA. These registers are described in detail below. I/O PORT MODE REGISTER (IOPMOD) The I/O port mode register, IOPMOD, is used to configure the port pins, P17-P0. NOTE If the port is used for a special function such as an external interrupt request, an external DMA request, or acknowledge signal and timer outputs, its mode is determined by the IOPCON register, not by IOPMOD. Table 12-1. IOPMOD Register Register IOPMOD Offset Address 0x5000 R/W R/W Description I/O port mode register Reset Value 0x00000000 31 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 xxxxxxxxxxxxxxxxxx [0] I/O port mode bit for port 0 0 = Input 1 = Output [1] I/O port mode bit for port 1 0 = Input 1 = Output [2] I/O port mode bit for port 2 0 = Input 1 = Output [17] I/O port mode bit for port 17 0 = Input 1 = Output Figure 12-2. I/O Port Mode Register (IOPMOD) 12-2 S3C4510B I/O PORTS I/O PORT CONTROL REGISTER (IOPCON) The I/O port control register, IOPCON, is used to configure the port pins, P17-P8. NOTE If the port is used for a special function such as an external interrupt request, an external DMA request, or acknowledge signal and timer outputs, its mode is determined by the IOPCON register, not by IOPMOD. For the special input ports, S3C4510A provides 3-tap filtering. If the input signal levels are same for the three system clock periods, that level is taken as input for dedicated signals such as external interrupt requests and external DMA requests. Table 12-2. IOPCON Register Register IOPCON Offset Address 0x5004 R/W R/W Description I/O port control register Reset Value 0x00000000 12-3 I/O PORTS S3C4510B 31 T O E N 1 30 29 28 27 26 25 23 22 20 19 T D D D D OA A R R E K K Q Q N 1 0 1 0 0 15 14 X I R Q 3 X I R Q 2 10 9 X I R Q 1 543210 X I R Q 1 [4:0] Control external interrupt request 0 input for port 8 (xIRQ0) [4] Port 8 for xINTREQ0 0 = Disable [3] 0 = Active Low [2] 0 = Filtering off [1:0] 00 = Level detection 10 = Falling edge detection 1 = Enable 1 = Active High 1 = Filtering on 01 = Rising edge detection 11 = Both edge detection [9:5] Control external interrupt request 1 input for port 9 (xIRQ1) (See control external interrupt request 1.) [14:10] Control external interrupt request 2 input for port 10 (xIRQ2) (See control external interrupt request 2.) [19:15] Control external interrupt request 3 input for port 11 (xIRQ3) (See control external interrupt request 3.) [22:20] Control external DMA request 0 input for port 12 (DRQ0) [22] Port 12 for nXDREQ0 0 = Disable [21] 0 = Filtering off [20] 0 = Active Low 1 = Enable 1 = Filtering on 1 = Active High [25:23] Control external DMA request 1 input for port 13 (DRQ1) [25] Port 13 for nXDREQ1 0 = Disable [24] 0 = Filtering off [23] 0 = Active Low 1 = Enable 1 = Filtering on 1 = Active High [27:26] Control external DMA acknowledge 0 output for port 14 (DAK0) [27] Port 14 for nXDACK0 0 = Disable [26] 0 = Active Low 1 = Enable 1 = Active High [29:28] Control external DMA acknowledge 1 output for port 15 (DAK1) [29] Port 15 for nXDACK1 0 = Disable [28] 0 = Active Low 1 = Enable 1 = Active High [30] Control timeout 0 for port 16 (TOEN0) 0 = Disable 1 = Enable [31] Control timeout 1 for port 17 (TOEN1) 0 = Disable 1 = Enable Figure 12-3. I/O Port Control Register (IOPCON) 12-4 S3C4510B I/O PORTS I/O PORT DATA REGISTER (IOPDATA) The I/O port data register, IOPDATA, contains one-bit read values for I/O ports that are configured to input mode and one-bit write values for ports that are configured to output mode. Bits[17:0] of the 18-bit I/O port register value correspond directly to the 18 port pins, P17-P0. Table 12-3. IOPDATA Register Register IOPDATA Offset Address 0x5008 R/W R/W Description I/O port data register Reset Value Undefined 31 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PPPPPPPPPPPPPPPPPP 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [17:0] I/O port read/write values for ports 17-0 (P0-P17) NOTE: The values in the I/O port data register reflect the signal level on the respective I/O port pins. When the ports are configured to output mode, the bit reflects the ports write value. When the port is configured to input mode, the bit reflects the ports read value. Figure 12-4. I/O Port Data Register (IOPDATA) 12-5 I/O PORTS S3C4510B MCLKO xINTREQn Internal INTREQn IOPCON.xIRQn [1:0] (= 00) IOPCON.xIRQn [1:0] (= 01) IOPCON.xIRQn [1:0] (= 11) Figure 12-5. External Interrupt Request Timing (Active High) MCLKO xINTREQn Internal INTREQn IOPCON.xIRQn [1:0] (= 00) IOPCON.xIRQn [1:0] (= 01) IOPCON.xIRQn [1:0] (= 10) IOPCON.xIRQn [1:0] (= 11) Figure 12-6. External Interrupt Request Timing (Active Low) 12-6 S3C4510B INTERRUPT CONTROLLER 13 OVERVIEW INTERRUPT CONTROLLER The S3C4510B interrupt controller has a total of 21 interrupt sources. Interrupt requests can be generated by internal function blocks and at external pins. The ARM7TDMI core recognizes two kinds of interrupts: a normal interrupt request (IRQ), and a fast interrupt request (FIQ). Therefore all S3C4510B interrupts can be categorized as either IRQ or FIQ. The S3C4510B interrupt controller has an interrupt pending bit for each interrupt source. Four special registers are used to control interrupt generation and handling: -- Interrupt priority registers. The index number of each interrupt source is written to the pre-defined interrupt priority register field to obtain that priority. The interrupt priorities are pre-defined from 0 to 20. -- Interrupt mode register. Defines the interrupt mode, IRQ or FIQ, for each interrupt source. -- Interrupt pending register. Indicates that an interrupt request is pending. If the pending bit is set, the interrupt pending status is maintained until the CPU clears it by writing a "1" to the appropriate pending register. When the pending bit is set, the interrupt service routine starts whenever the interrupt mask register is "0". The service routine must clear the pending condition by writing a "1" to the appropriate pending bit. This avoids the possibility of continuous interrupt requests from the same interrupt pending bit. -- Interrupt mask register. Indicates that the current interrupt has been disabled if the corresponding mask bit is "1". If an interrupt mask bit is "0" the interrupt will be serviced normally. If the global mask bit (bit 21) is set to "1", no interrupts are serviced. However, the source's pending bit is set if the interrupt is generated. When the global mask bit has been set to "0", the interrupt is serviced. 13-1 INTERRUPT CONTROLLER S3C4510B INTERRUPT SOURCES The 21 interrupt sources in the S3C4510B interrupt structure are listed, in brief, as follows: Table 13-1. S3C4510B Interrupt Sources Index Values [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] I2C-bus Interrupt Sources interrupt Ethernet controller MAC Rx interrupt Ethernet controller MAC Tx interrupt Ethernet controller BDMA Rx interrupt Ethernet controller BDMA Tx interrupt HDLC channel B Rx interrupt HDLC channel B Tx interrupt HDLC channel A Rx interrupt HDLC channel A Tx interrupt Timer 1 interrupt Timer 0 interrupt GDMA channel 1 interrupt GDMA channel 0 interrupt UART 1 receive and error interrupt UART 1 transmit interrupt UART 0 receive and error interrupt UART 0 transmit interrupt External interrupt 3 External interrupt 2 External interrupt 1 External interrupt 0 13-2 S3C4510B INTERRUPT CONTROLLER INTERRUPT CONTROLLER SPECIAL REGISTERS INTERRUPT MODE REGISTER Bit settings in the interrupt mode register, INTMOD, specify if an interrupt is to be serviced as a fast interrupt (FIQ) or a normal interrupt (IRQ). Table 13-2. INTMOD Register Register INTMOD Offset Address 0x4000 R/W R/W Description Interrupt mode register Reset Value 0x00000000 31 INTMOD 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 xxxxxxxxxxxxxxxxxxxxx [20:0] Interrupt mode bits NOTE: Each of the 21 bits in the interrupt mode enable register, INTMOD, corresponds to an interrupt source. When the source interrupt mode bit is set to 1, the interrupt is processed by the ARM7TDMI core in FIQ (fast interrupt) mode. Otherwise, it is processed in IRQ mode (normal interrupt). The 21 interrupt sources are mapped as follows: [20] I2C interrupt [19] Ethernet controller MAC Rx interrupt [18] Ethernet controller MAC Tx interrupt [17] Ethernet controller BDMA Rx interrupt [16] Ethernet controller BDMA Tx interrupt [15] HDLC channel B Rx interrupt [14] HDLC channel B Tx interrupt [13] HDLC channel A Rx interrupt [12] HDLC channel A Tx interrupt [11] Timer 1 interrupt [10] Timer 0 interrupt [9] GDMA channel 1 interrupt [8] GDMA channel 0 interrupt [7] UART1 receive and error interrupt [6] UART1 transmit interrupt [5] UART0 receive and error interrupt [4] UART0 transmit interrupt [3] External interrupt 3 [2] External interrupt 2 [1] External interrupt 1 [0] External interrupt 0 Figure 13-1. Interrupt Mode Register (INTMOD) 13-3 INTERRUPT CONTROLLER S3C4510B INTERRUPT PENDING REGISTER The interrupt pending register, INTPND, contains interrupt pending bits for each interrupt source. This register has to be cleared at the top of an interrupt service routine. Table 13-3. INTPND Register Register INTPND Offset Address 0x4004 R/W R/W Description Interrupt pending register Reset Value 0x00000000 31 INTPND 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 xxxxxxxxxxxxxxxxxxxxx [20:0] Interrupt pending bits NOTE: Each of the 21 bits in the interrupt mode pending register, INTPND, corresponds to an interrupt source. When an interrupt request is generated, its pending bit is set to 1. The service routine must then clear the pending condition by writing a 1 to the apropriate pending bit at start. The 21 interrupt sources are mapped as follows: [20] I2C interrupt [19] Ethernet controller MAC Rx interrupt [18] Ethernet controller MAC Tx interrupt [17] Ethernet controller BDMA Rx interrupt [16] Ethernet controller BDMA Tx interrupt [15] HDLC channel B Rx interrupt [14] HDLC channel B Tx interrupt [13] HDLC channel A Rx interrupt [12] HDLC channel A Tx interrupt [11] Timer 1 interrupt [10] Timer 0 interrupt [9] GDMA channel 1 interrupt [8] GDMA channel 0 interrupt [7] UART1 receive and error interrupt [6] UART1 transmit interrupt [5] UART0 receive and error interrupt [4] UART0 transmit interrupt [3] External interrupt 3 [2] External interrupt 2 [1] External interrupt 1 [0] External interrupt 0 Figure 13-2. Interrupt Pending Register (INTPND) 13-4 S3C4510B INTERRUPT CONTROLLER INTERRUPT MASK REGISTER The interrupt mask register, INTMSK, contains interrupt mask bits for each interrupt source. Table 13-4. INTMSK Register Register INTMSK Offset Address 0x4008 R/W R/W Description Interrupt mask register Reset Value 0x003FFFFF 31 INTMSK 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GXXXXXXXXXXXXXXXXXXXXX [20:0] Individual interrupt mask bits NOTE: Each of the 21 bits in the interrupt mask register, INTMSK, (except for the global mask bit, G) corresponds to an interrupt source. When a source interrupt mask bit is 1, the interrupt is not serviced by the CPU when the corresponding interrupt request is generated. If the mask bit is 0, the interrupt is serviced upon request. And if global mask bit (bit 21) is 1, no interrupts are serviced. (However, the source pending bit is set whenever the interrupt is generated.) After the global mask bit is cleared, the interrupt is serviced. The 21 interrupt sources are mapped as follows: [20] I2C interrupt [19] Ethernet controller MAC Rx interrupt [18] Ethernet controller MAC Tx interrupt [17] Ethernet controller BDMA Rx interrupt [16] Ethernet controller BDMA Tx interrupt [15] HDLC channel B Rx interrupt [14] HDLC channel B Tx interrupt [13] HDLC channel A Rx interrupt [12] HDLC channel A Tx interrupt [11] Timer 1 interrupt [10] Timer 0 interrupt [9] GDMA channel 1 interrupt [8] GDMA channel 0 interrupt [7] UART1 receive and error interrupt [6] UART1 transmit interrupt [5] UART0 receive and error interrupt [4] UART0 transmit interrupt [3] External interrupt 3 [2] External interrupt 2 [1] External interrupt 1 [0] External interrupt 0 [21] Global interrupt mask bit 0 = Enable interrupt requests 1 = Disable all interrupt requests Figure 13-3. Interrupt Mask Register (INTMSK) 13-5 INTERRUPT CONTROLLER S3C4510B INTERRUPT PRIORITY REGISTERS The interrupt priority registers, INTPRI0-INTPRI5, contain information about which interrupt source is assigned to the pre-defined interrupt priority field. Each INTPRIn register value determines the priority of the corresponding interrupt source. The lowest priority value is priority 0, and the highest priority value is priority 20. The index value of each interrupt source is written to one of the above 21 positions (see Figure 13-4). The position value then becomes the written interrupt's priority value. The index value of each interrupt source is listed in Table 13-1. Table 13-5. Interrupt Priority Register Overview Register INTPRI0 INTPRI1 INTPRI2 INTPRI3 INTPRI4 INTPRI5 Offset Address 0x400C 0x4010 0x4014 0x4018 0x401C 0x4020 R/W R/W R/W R/W R/W R/W R/W Description Interrupt priority register 0 Interrupt priority register 1 Interrupt priority register 2 Interrupt priority register 3 Interrupt priority register 4 Interrupt priority register 5 Reset Value 0x03020100 0x07060504 0x0B0A0908 0x0F0E0D0C 0x13121110 0x00000014 INTPRI0 INTPRI1 INTPRI2 INTPRI3 INTPRI4 INTPRI5 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRIORITY0 PRIORITY1 PRIORITY2 PRIORITY3 000 000 000 000 000 000 000 000 PRIORITY7 PRIORITY11 PRIORITY15 PRIORITY19 High Priority 000 000 000 000 PRIORITY6 PRIORITY10 PRIORITY14 PRIORITY18 000 000 000 000 PRIORITY5 PRIORITY9 PRIORITY13 PRIORITY17 000 000 000 000 PRIORITY4 PRIORITY8 PRIORITY12 PRIORITY16 PRIORITY20 Low Priority 000000000000000000000000000 High Priority Low Priority Figure 13-4. Interrupt Priority Register (INTPRIn) 13-6 S3C4510B INTERRUPT CONTROLLER INTERRUPT OFFSET REGISTER The interrupt offset register, INTOFFSET, contains the interrupt offset address of the interrupt, which has the highest priority among the pending interrupts. The content of the interrupt offset address is "bit position value of the interrupt source << 2". If all interrupt pending bits are "0" when you read this register, the return value is "0x00000054". This register is valid only under the IRQ or FIQ mode in the ARM7TDMI. In the interrupt service routine, you should read this register before changing the CPU mode. INTOSET_FIQ/INTOSET_IRQ register can be used to get the highest priority interrupt without CPU mode change. Other usages are similar to INTOFFSET. NOTE If the lowest interrupt priority (priority 0) is pending, the INTOFFSET value will be "0x00000000". The reset value will, therefore, be changed to "0x00000054" (to be differentiated from interrupt pending priority 0). Table 13-6. INTOFFSET Register Register INTOFFSET INTOSET_FIQ INTOSET_IRQ Offset Address 0x4024 0x4030 0x4034 R/W R R R Description Interrupt offset register FIQ interrupt offset register IRQ interrupt offset register Reset Value 0x00000054 0x00000054 0x00000054 13-7 INTERRUPT CONTROLLER S3C4510B INTERRUPT PENDING BY PRIORITY REGISTER The interrupt pending by priority register, INTPNDPRI, contains interrupt pending bits, which are re-ordered by the INTPRIn register settings. INTPNDPRI[20] is mapped to the interrupt source of whichever bit index is written into the priority 20 field of the INTPRIn registers. This register is useful for testing. To validate the interrupt pending by priority value, you can obtain the highest priority pending interrupt from the interrupt offset register, INTOFFSET. Table 13-7. INTPNDPRI Register Register INTPNDPRI Offset Address 0x4028 R/W R Description Interrupt pending by priority Reset Value 0x00000000 INTERRUPT PENDING TEST REGISTER The interrupt pending test register, INTPNDTST, is used to set or clear INTPND and INTPNDPRI. If user writes data to this register, it is written into both the INTPND register and INTPNDPRI register. The interrupt pending test register, INTPNDTST, is also useful for testing. For INTPND, the same bit position is updated with the new coming data. For INTPNDPRI, the mapping bit position by INTPRIn registers is updated with the new coming data to keep with the contents of the INTPND register. Table 13-8. INTPNDTST Register Register INTPNDTST Offset Address 0x402C R/W W Description Interrupt pending test register Reset Value 0x00000000 13-8 S3C4510B ELECTRICAL DATA 14 OVERVIEW Parameter Supply Voltage DC input Voltage ELECTRICAL DATA This chapter describes the S3C4510B and S3C4510X electrical data. ABSOLUTE MAXIMUM RATINGS Table 14-1. Absolute Maximum Ratings Symbol VDD/VDDA VIN IIN TOPR T STG 3.3 V I/O 5 V-tolerant DC input current Operating temperature Storage temperature 10 0 to 70 - 40 to 125 Rating - 0.3 to 3.8 - 0.3 to VDD + 0.3 - 0.3 to 5.5 mA C C Units V V ABSOLUTE MAXIMUM RATINGS Table 14-2. Recommended Operating Conditions Parameter Supply Voltage Oscillator frequency External loop filter capacitance Commercial temperature Symbol VDD/VDDA f OSC LF TA Rating 3.0 to 3.6 upto 50 820 0 to 70 Units V MHz pF C NOTE: It is strongly recommended that all the supply pins (VDD/VDDA) be powered from the same source to avoid power latch-up. 14-1 ELECTRICAL DATA S3C4510B D.C. ELECTRICAL CHARACTERISTICS Table 14-3. D.C Electrical Characteristics VDD = 3.3 V 0.3 V, VEXT = 5 0.25 V, TA = 0 to 70 C (in case of 5 V-tolerant I/O) Parameter High level input voltage Low level input voltage Switching threshold Schmitt trigger positive-going threshold Schmitt trigger negative-going threshold High level input current Input buffer Input buffer with pull-up Low level input current Input buffer Input buffer with pulldown High level output voltage Type B1 to B16(2) Type B1 Type B2 Type B4 Type B6 Low level output voltage Type B1 to B16(2) Type B1 Type B2 Type B4 Type B6 Tri-state output leakage current Maximum operating current IOZ IDD VOL VOH IOH = - 1 A IOH = - 1 mA IOH = - 2 mA IOH = - 4 mA IOH = - 6 mA IOL = 1 A IOL = 1 mA IOL = 2 mA IOL = 4 mA IOL = 6 mA VOUT = VSS or VDD VDD = 3.6 V, f MCLK = 50MHz - 10 10 230 A mA 0.05 0.4 V IIL VIN = VSS LVCMOS interface LVCMOS interface Symbol VIH (1) Conditions - - LVCMOS LVCMOS LVCMOS VIN = VDD Min 2.0 - - - 0.8 - 10 10 - 10 - 60 Typ - - 1.4 - - - 30 - - 30 Max - 0.8 - 2.0 - 10 60 10 - 10 Unit V V V VIL (1) VT VT+ VT- IIH A A VDD - 0.05 2.4 - - V NOTES: 1. All 5 V-tolerant inputs have less than 0.2 V hysterics. 2. Type B1 means 1 mA output driver cells, and Type B6/B24 means 6 mA/24 mA output driver cells. 14-2 S3C4510B ELECTRICAL DATA Table 14-4. A.C Electrical Characteristics for S3C4510X (TA = 0 to 70 C, VDD = 3.0 V to 3.6 V) Signal Name tMCLKOd tEMZ tEMRs tEMRh tEMAr tEMAf tADDRh tADDRd tNRCS tNROE tNWBE tRDs tRDh tWDd tWDh tNRASf tNRASr tNCASf tNCASr tNCASwf tNCASwr tNDWE tNDOE tNECS tWDDd tWDDh tWs tWh Description MCLKO delay for Internal Positive Edge Clock (MCLK) Memory Control Signal High-Z Time ExtMREQ Setup Time ExtMREQ Hold Time ExtMACK Rising Edge Delay Time ExtMACK Falling Edge Delay Time Address Hold Time Address Delay Time ROM/SRAM/Flash Bank Chip Select Delay Time ROM/SRAM or External I/O Bank Output Enable Delay ROM/SRAM or External I/O Bank Write Byte Enable Delay Read Data Setup Time Read Data Hold Time Write Data Delay Time (SRAM or External I/O) (ref:nWBE) Write Data Hold Time (SRAM or External I/O) (ref:MCLK) DRAM Row Address Strobe Active Delay DRAM Row Address Strobe Release Delay DRAM Column Address Strobe Read Active Delay DRAM CAS Signal Release Read Delay Time DRAM Column Address Strobe Write Active Delay DRAM CAS Signal Release Write Delay Time DRAM Bank Write Enable Delay Time DRAM Bank Out Enable Delay Time External I/O Bank Chip Select Delay Time DRAM Write Data Delay Time (DRAM) DRAM Write Data Hold Time (DRAM) External Wait Setup Time External Wait Hold Time Min 4.03 4.99 0 9.55 9.30 4.75 6.76 3.24 3.81 3.36 0 1.86 2.05 3.53 4.95 3.58 3.57 3.60 3.62 3.93 3.80 3.58 4.96 2.70 0 Max 10.57 12.02 3.90 23.30 22.70 11.50 16.53 7.90 9.24 8.13 10.82 4.49 4.86 8.59 11.99 8.70 8.62 8.72 8.73 9.54 9.26 8.74 11.97 6.42 4.82 Edge P N P P N N N N N N P N N N N P N P P N N N N N N N N N NOTE: The edge (N) is calculated from SCLK(MCLK) falling and (P) is rising. 14-3 ELECTRICAL DATA S3C4510B Table 14-5. A.C Electrical Characteristics for S3C4510B (TA = 0 to 70 C, VDD = 3.0 V to 3.6 V) Signal Name tMCLKOd tEMZ tEMRs tEMRh tEMAr tEMAf tADDRh tADDRd tNRCS tNROE tNWBE tRDs tRDh tWDd tWDh tNRASf tNRASr tNCASf tNCASr tNCASwf tNCASwr tNDWE tNDOE tNECS tWDDd tWDDh tWs tWh Description MCLKO delay for Internal Positive Edge Clock(MCLK) Memory Control Signal High-Z Time ExtMREQ Setup Time ExtMREQ Hold Time ExtMACK Rising Edge Delay Time ExtMACK Falling Edge Delay Time Address Hold Time Address Delay Time ROM/SRAM/Flash Bank Chip Select Delay Time ROM/SRAM or External I/O Bank Output Enable Delay ROM/SRAM or External I/O Bank Write Byte Enable Delay Read Data Setup Time Read Data Hold Time Write Data Delay Time (SRAM or External I/O) (ref:nWBE) Write Data Hold Time (SRAM or External I/O) (ref:MCLK) DRAM Row Address Strobe Active Delay DRAM Row Address Strobe Release Delay DRAM Column Address Strobe Read Active Delay DRAM CAS Signal Release Read Delay Time DRAM Column Address Strobe Write Active Delay DRAM CAS Signal Release Write Delay Time DRAM Bank Write Enable Delay Time DRAM Bank Out Enable Delay Time External I/O Bank Chip Select Delay Time DRAM Write Data Delay Time (DRAM) DRAM Write Data Hold Time (DRAM) External Wait Setup Time External Wait Hold Time Min 4.07 5.08 0 12.19 9.33 5.16 6.13 3.96 3.82 4.70 0 2.50 1.94 3.84 5.70 3.77 4.23 3.78 4.27 4.81 4.15 4.12 7.00 3.27 0 Max 9.37 11.76 6.31 28.54 21.87 12.08 14.35 9.29 8.96 11.13 12.46 5.65 4.45 9.00 13.31 8.84 9.88 8.86 9.99 11.25 9.71 9.63 16.32 7.58 4.46 Edge P N P P N N N N N N P N N N N P N P P N N N N N N N N N NOTE: The edge (N) is calculated from SCLK(MCLK) falling and (P) is rising. 14-4 S3C4510B MECHANICAL DATA 15 OVERVIEW MECHANICAL DATA This section describes the mechanical data for the S3C4510B 208-pin QFP package. 15-1 MECHANICAL DATA S3C4510B 30.60 BSC 28.00 BSC 0-7 + 0.05 0.15 - 0.06 30.60 BSC 28.00 BSC 208-QFP-2828B 0.08 MAX #144 #1 0.50 BSC 0.20 + 0.07 - 0.03 0.08 MAX 0.25 MIN (1.25) 3.40 0.20 4.10 MAX NOTE : Dimensions are in millimeters. Figure 15-1. 208-QFP-2828B Package Dimensions 15-2 0.45-0.75 S3C4510B APPENDIX A APPENDIX A TEST ACCESS PORT This section describes relevant sections of the IEEE Standard 1149.1 Compatible Test Access Port (TAP). This standard applies to the Test Access Port and Boundary Scan (JTAG) specification, which is supported by the S3C4510B microcontoller. In test mode, package pads are monitored by the serial scan circuitry. This is done to support connectivity testing during manufacturing, as well as system diagnostics. JTAG control is not used to drive internal data out of the S3C4510B. To conform with IEEE 1194.1, the S3C4510B has a TAP controller, an instruction register, a bypass register, and an ID register. These components are described in detail below. A-1 APPENDIX A S3C4510B TAP CONTROLLER The TAP controller is responsible for interpreting the sequence of logical values on the TMS signal. It is a synchronous state machine which controls the JTAG logic (see Figure B-1). In Figure B-1, the value shown next to each curved arrow represents the value of the TMS signal as it is sampled on the rising edge of the TCK signal. Test Login Reset 1 0 Run-Test/Idle 0 1 Select-DR_Scan 0 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 Exit2-DR 1 Update-DR 1 0 1 Select-IR_Scan 0 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 0 Figure A-1. TAP Controller State Machine A-2 S3C4510B APPENDIX A BOUNDARY SCAN REGISTER The S3C4510B scan chain implementation uses a 233-bit boundary scan register. This register contains bits for all device signals and clock pins, and for associated control signals. All bi-directional pins have two register bits in the boundary scan register for pin data. Each pin is controlled by an associated control bit in the boundary scan register. The twenty-three bits in the boundary scan register define the output enable signals for associated groups of bi-directional and tri-stateable pins. The control bits and their bit positions are listed in Table B-1. Table A-1. Boundary Scan Control Bits Name penb [17] penb [16] penb [15] penb [14] penb [13] penb [12] penb [11] penb [10] Bit Number 9 12 15 18 21 24 27 30 Name penb [9] penb [8] penb [7] penb [6] penb [5] penb [4] penb [3] penb [2] Bit Number 33 36 39 42 45 48 51 54 Name penb [1] penb [0] d_enb dis_bus mdio_oe txcben txcaen Bit Number 57 60 127 184 192 211 222 BOUNDARY SCAN DEFINITIONS The boundary scan bit definitions are listed in Tables B-2 through B-5: -- The first column in the table defines the bit's ordinal position in the boundary scan register. The shift register cell nearest TDO (that is, the first bit to be shifted out) is defined as bit 0. The last bit to be shifted out is bit number 232. -- The second column refers to one of the four S3C4510B cell types: jtin1, jtbi1, and jtout1. -- The third column lists the pin name of pin-related cells or defines the name of bi-directional control register bits. -- The fourth column lists the pin type. TS-Output indicates a tri-stateable output pin, and OD-I/O denotes an open-drain bi-directional pin. -- The fifth column indicates the associated boundary scan register control bit for bi-directional, tri-state output. A-3 APPENDIX A S3C4510B Table A-2. Boundary Scan Definitions (Page 1) Bit Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Cell Type jtin 1 jtout 1 jtout 1 jtin 1 jtin 1 jtbi 1 jtbi 1 jtbi 1 jtbi 1 jtout 1 jtbi 1 jtbi 1 jtout 1 jtbi 1 jtbi 1 jtout 1 jtbi 1 jtbi 1 jtout 1 jtbi 1 jtbi 1 jtout 1 jtbi 1 jtbi 1 jtout 1 jtbi 1 jtbi 1 jtout 1 jtbi 1 jtbi 1 jtout 1 jtbi 1 Pin/Cell Name UARXD1 nUADSR0 UATXD0 UADTR0 UARXD0 SDA SDA SCL SCL pend[17] P[17] P[17] penb[16] P[16] P[16] penb[15] P[15] P[15] penb[14] P[14] P[14] penb[13] P[13] P[13] penb[12] P[12] P[12] penb[11] P[11] P[11] penb[10] P[10] Pin Type Input Output Output Input Input ODOutput OD-Input ODOutput OD-Input - Input - Input - Input - Input - Input - Input - Input - Output Bit CTL Cell Number - - - - - - - - - - - - - - - - - - - - - - - - 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Cell Type jtbi1 jtout1 jtbi1 jtbi1 jtout1 jtbi1 jtbi1 jtout1 jtbi1 jtbi1 jtout1 jtbi1 jtbi1 jtout1 jtbi1 jtbi1 jtout1 jtbi1 jtbi1 jtout1 jtbi1 jtbi1 jtout1 jtbi1 jtbi1 jtout1 jtbi1 jtbi1 jtout1 jtbi1 jtbi1 jtbi1 Pin/Cell Name P[10] penb[9] P[9]o P[9]i penb[8] P[8] P[8] penb[7] P[7] P[7] penb[6] P[6] P[6] penb[5] P[5] P[5] penb[4] P[4] P[4] penb[3] P[3] P[3] penb[2] P[2] P[2] penb[1] P[1]o P[1]i penb[0] P[0] P[0] XDATA[31] Pin Type Input - TS-Output Input - TS-Output Input - TS-Output Input - TS-Output Input - TS-Output Input - TS-Output Input - TS-Output Input - TS-Output Input - TS-Output Input - TS-Output Input TS-Output Output CTL Cell - - penb[9] - - - - - penb[7] - - penb[6] - - penb[5] - - penb[4] - - penb[3] - - penb[2] - - penb[1] - - penb[0] - denb TS-Output penb[17] TS-Output penb[16] TS-Output penb[15] TS-Output penb[14] TS-Output penb[13] TS-Output penb[12] TS-Output penb[11] TS-Output penb[10] A-4 S3C4510B APPENDIX A Table A-3. Boundary Scan Definitions (Page 2) Bit Number 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 Cell Type jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 Pin/Cell Name XDATA[31] XDATA[30] XDATA[29] XDATA[28] XDATA[27] XDATA[26] XDATA[25] XDATA[24] XDATA[23] XDATA[22] XDATA[21] XDATA[20] XDATA[19] XDATA[18] XDATA[17] XDATA[16] Pin Type Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Bit CTL Cell Number - denb - denb - denb - denb - denb - denb - denb - denb - denb - denb - denb - denb - denb - - denb - denb 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 Cell Type jtbi1 jbti1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtbi1 jtout1 Pin/Cell Name XDATA[15] XDATA[14] XDATA[13] XDATA[12] XDATA[11] XDATA[10] XDATA[9] XDATA[8] XDATA[7] XDATA[6] XDATA[5] XDATA[4] XDATA[3] XDATA[2] XDATA[1] XDATA[0] denb Pin Type Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input - Output CTL Cell - denb - denb - denb - denb - denb - denb - denb - denb - denb - denb - denb - denb - denb - denb - denb - - XDATA[30] TS-Output XDATA[29] TS-Output XDATA[28] TS-Output XDATA[27] TS-Output XDATA[26] TS-Output XDATA[25] TS-Output XDATA[24] TS-Output XDATA[23] TS-Output XDATA[22] TS-Output XDATA[21] TS-Output XDATA[20] TS-Output XDATA[19] TS-Output XDATA[18] TS-Output XDATA[17] TS-Output XDATA[16] TS-Output XDATA[15] TS-Output XDATA[14] TS-Output XDATA[13] TS-Output XDATA[12] TS-Output XDATA[11] TS-Output XDATA[10] TS-Output XDATA[9] TS-Output XDATA[8] TS-Output XDATA[7] TS-Output XDATA[6] TS-Output XDATA[5] TS-Output XDATA[4] TS-Output XDATA[3] TS-Output XDATA[2] TS-Output XDATA[1] TS-Output XDATA[0] TS-Output A-5 APPENDIX A S3C4510B Table A-4. Boundary Scan Definitions (Page 3) Bit Number 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 Cell Type jtout1 jtout1 jtout1 jtout1 jtout1 jtout1 jtout1 jtout1 jtout1 jtout1 jtout1 jtout1 jtout1 jtout1 jtout1 jtout1 jtout1 jtout1 jtout1 jtout1 jtout1 jtout1 jtout1 jtin1 jtout1 jtout1 jtout1 jtout1 jtout1 jtout1 jtout1 jtout1 Pin/Cell Name PADDR[21] PADDR[20] PADDR[19] PADDR[18] PADDR[17] PADDR[16] PADDR[15] PADDR[14] PADDR[13] PADDR[12] PADDR[11] PADDR[10] PADDR[9] PADDR[8] PADDR[7] PADDR[6] PADDR[5] PADDR[4] PADDR[3] PADDR[2] PADDR[1] PADDR[0] EXTMACK EXTMREQ nWBE[3] nWBE[2] nWBE[1] nWBE[0] nDWE nCAS[3] nCAS[2] nCAS[1] Pin Type TS-O TS-O TS-O TS-O TS-O TS-O TS-O TS-O TS-O TS-O TS-O TS-O TS-O TS-O TS-O TS-O TS-O TS-O TS-O TS-O TS-O TS-O Output TS-O TS-O TS-O TS-O TS-O TS-O TS-O TS-O TS-O Output Bit CTL Cell Number dis_bus dis_bus dis_bus dis_bus dis_bus dis_bus dis_bus dis_bus dis_bus dis_bus dis_bus dis_bus dis_bus dis_bus dis_bus dis_bus dis_bus dis_bus dis_bus dis_bus dis_bus dis_bus - - dis_bus dis_bus dis_bus dis_bus dis_bus dis_bus dis_bus dis_bus 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 Cell Type jtout1 jtout1 jtout1 jtout1 jtout1 jtout1 jtout1 jtout1 jtout1 jtout1 jtin1 jtin1 jtck jtout1 jtin1 jtout1 jtin1 jtin1 jtout1 jtin1 jtout jtout1 jtout1 jtout1 jtout1 jtin1 jtin1 jtout1 jtin1 jtout1 jtbi1 jtbi1 Pin/Cell Name nCAQS[0] nRAS[3] nRAS[2] nRAS[1] nRAS[0] nRCS[5] nRCS[4] nRCS[3] nRCS[2] nRCS[1] CLKSEL nRESET MCLK MCLKO CLKOEN nRCS[0] B0SIZE[1] B0SIZE[0] nOE nEWAIT nECS[3] nECS[2] nECS[1] nECS[0] dis_bus UCLK TMODE MDC LITTLE mdio_oe MDIO MDIO Pin Type TS-O TS-O TS-O TS-O TS-O TS-O TS-O TS-O TS-O TS-O Input Input Input Output Input TS-O Input Input TS-O Input TS-O TS-O TS-O TS-O - Input Input Output - - TS-O Input Output CTL Cell dis_bus dis_bus dis_bus dis_bus dis_bus dis_bus dis_bus dis_bus dis_bus dis_bus - - - - - dis_bus - - dis_bus - dis_bus dis_bus dis_bus dis_bus - - - - - - mdio_oe - A-6 S3C4510B APPENDIX A Table A-5. Boundary Scan Definitions (Page 4) Bit Number 192 193 Cell Type jtout1 jtin1 Pin/Cell Name TX_EN/ TXEN_10M TX_CLK/ TXCLK_10 M TX_ERR/ PCOMP_1 0M TXD3 TXD2 TXD1/ LOOP10 TXD0/ TXD_10M COL/ COL_10M RX_CLK/ RXCLK_10 M RX_ERR RXD3 RXD2 RXD1 RXD0/ RXD_10M RX_DV/ LINK10 CRS/ CRS_10M txcben TXCB TXCB nSYNCB RXCB Pin Type Output Input Output Bit CTL Cell Number - - 213 214 Cell Type jtin1 jtin1 Pin/Cell Name nDCDB nCTSB Pin Type Input Input Output CTL Cell - - 194 jtout1 Output - 215 jtout1 TXDB Output - 195 196 197 198 199 200 jtout1 jtout1 jtout1 jtout1 jtin1 jtin1 Output Output Output Output Input Input - - - - - - 216 217 218 219 220 221 jtout1 jtin1 jtout1 jtout1 jtbi1 jtbi1 nRTSB RXDB nDTRB txcaen TXCA TXCA Output Input Output - Output Input - - - - txcaen - 201 202 203 204 205 206 207 208 209 210 211 212 jtin1 jtin1 jtin1 jtin1 jtin1 jtin1 jtin1 jtout1 jtbi1 jtbi1 jtout1 jtin1 Input Input Input Input Input Input Input - TS-Out Input Output Input - - - - - - - - txcben - - - 222 223 224 225 226 227 228 229 230 231 232 jtout1 jtin1 jtin1 jtin1 jtout1 jtout1 jtin1 jtout1 jtout1 jtout1 jtin1 nSYNCA RXCA nDCDA nCTSA TXDA nRTSA RXDA nDTRA nUADSR1 UATXD1 UADTR1 Output Input Input Input Output Output Input Output Output Output Input - - - - - - - - - - - NOTE : TS-O is tri-state output. A-7 APPENDIX A S3C4510B JTBI1 JTIN1 SHIFT DINP0N MODE 0 0 MUX TDI0 1 Q D Q 1 MUX D TDO0 SETN 0 DOUT0 JTOUT1 DINP1 0 MUX TDI0 1 Q D MODE 1 TDO1 0 DOUT1 D Q 1 MUX TCK UPDATE JTCK SHIFT 0 MUX TDI 1 TCK Q D TDO Figure A-2. S3C4510B Scan Cells A-8 S3C4510B APPENDIX A INSTRUCTION REGISTER The instruction register is four bits in length. There is no parity bit. The fixed value '0001' is loaded into the instruction register during the CAPTURE-IR controller state. The TAP machines supports the following public instructions. However, the S3C4510B boundary scan logic only supports EXTEST, IDCODE, BYPASS, and SAMPLE/PRELOAD instructions. The remaining instructions are used for ARM7TDMI core testing and debugging. Table A-6. Public Instructions Instruction EXTEST SCAN_N INTEST IDCODE BYPASS CLAMP HIGHZ CLAMPZ SAMPLE/PRELOAD RESTART Binary Code 0000 0010 1100 1110 1111 0101 0111 1001 0011 0100 A-9 APPENDIX A S3C4510B -Samsung Electronics Co. -- S3C4510B BSDL --- Version 1.1 01-27-99 -- Revision List: --1) Pin name NC changed to LITTLE 2) 1194 -> 1149 -- Package Type: QFP2828B -- entity S3C4510B is generic (PHYSICAL_PIN_MAP : string := "QFP2828B"); port ( nUADTR1 UATXD1 nUADSR1 nDTRA RXDA nRTSA TXDA nCTSA nDCDA RXCA nSYNCA TXCA nDTRB RXDB nRTSB TXDB nCTSB nDCDB RXCB nSYNCB TXCB : in bit; : outbit; : outbit; : : : : : : : : : : : : : : : : : : outbit; inbit; outbit; outbit; inbit; inbit; inbit; outbit; inoutbit; outbit; inbit; outbit; outbit; inbit; inbit; inbit; outbit; inoutbit; A-10 S3C4510B APPENDIX A CRS_CRS_10M RX_DV_LINK10 RXD RX_ERR RX_CLK_RXCLK_10M COL_COL_10M TXD TX_ERR_PCOMP_10M TX_CLK_TXCLK_10M TX_EN_TXEN_10M MDIO LITTLE MDC TCK TMS TDI TDO nTRST TMODE UCLK nECS nEWAIT nOE B0SIZE CLKOEN MCLKO MCLK nRESET CLKSEL nRCS nRAS nCAS nDWE nWBE ExtMREQ ExtMACK ADDR XDATA : inbit; : : : : : : : : : inbit; inbit_vector(0 to 3); inbit; inbit; inbit; outbit_vector(0 to 3); outbit; inbit; outbit; : inoutbit; : inbit; : outbit; : : : : : : : inbit; inbit; inbit; outbit; inbit; inbit; inbit; : outbit_vector(0 to 3); : inbit; : outbit; : inbit_vector(0 to 1); : : : : : : : : : : inbit; outbit; inbit; inbit; inbit; outbit_vector(0 to 5); outbit_vector(0 to 3); outbit_vector(0 to 3); outbit; outbit_vector(0 to 3); : inbit; : outbit; : outbit_vector(0 to 21); : inoutbit_vector(0 to 31); A-11 APPENDIX A S3C4510B P SCL SDA UARXD0 nUADTR0 UATXD0 nUADSR0 UARXD1 VDDP VDDI VSSP VSSI ); : : : : : : : : : : : : inoutbit_vector(0 to 17); inoutbit; inoutbit; inbit; inbit; outbit; outbit; inbit; linkagebit_vector(0 to 10); linkagebit_vector(0 to 10); linkagebit_vector(0 to 11); linkagebit_vector(0 to 10) A-12 S3C4510B APPENDIX A use STD_1149_1_1149.all; attribute PIN_MAP of S3C4510B : entity is PHYSICAL_PIN_MAP; -- QFP2828B Pin Map --- No-connects: 49 -constant QFP2828B : PIN_MAP_STRING := "nUADTR1 : 3, " & "UATXD1 : 4, " & "nUADSR1 : 5, " & "nDTRA : 6, " & "RXDA : 7, " & "nRTSA : 8, " & "TXDA : 9, " & "nCTSA : 10, " & "nDCDA : 13, " & "RXCA : 14, " & "nSYNCA : 15, " & "TXCA : 16, " & "nDTRB : 17, " & "RXDB : 18, " & "nRTSB : 19, " & "TXDB : 20, " & "nCTSB : 23, " & "nDCDB : 24, " & "RXCB : 25, " & "nSYNCB : 26, " & "TXCB : 27, " & "CRS_CRS_10M : 28, " & "RX_DV_LINK10 : 29, " & "RXD : (30, 33, 34, 35), " & "RX_ERR : 36, " & "RX_CLK_RXCLK_10M : 37, " & A-13 APPENDIX A S3C4510B "COL_COL_10M : 38, " & "TXD : (39, 40, 43, 44), " & "TX_ERR_PCOMP_10M : 45, " & "TX_CLK_TXCLK_10M : 46, " & "TX_EN_TXEN_10M : 47, " & "MDIO : 48, " & "LITTLE : 49, " & "MDC : 50, " & "TCK : 58, " & "TMS : 59, " & "TDI : 60, " & "TDO : 61, " & "nTRST : 62, " & "TMODE : 63, " & "UCLK : 64, " & "nECS : (67, 68, 69, 70), " & "nEWAIT : 71, " & "nOE : 72, " & "B0SIZE : (73, 74), " & "CLKOEN : 76, " & "MCLKO : 77, " & "MCLK : 80, " & "nRESET : 82, " & "PCLKSEL : 83, " & "nRCS : "nRAS : "nCAS : "nDWE : "nWBE : (75, 84, 85, 86, 87, 88), " & (89, 90, 91, 94), " & (95, 96, 97, 98), " & 99, " & (100, 101, 102, 107), " & "ExtMREQ : 108, " & "ExtMACK : 109, " & -- A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 "ADDR : (110, 111, 112, 113, 114, 115, 116, 117, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 132, 133, 134, 135), " & -- D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 "XDATA : (136, 137, 138, 139, 140, 141, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 159, 160, 161,162, 163, 164, 165, 166, 169, 170, 171, 172, 173, 174, 175), " & A-14 S3C4510B APPENDIX A -- P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 "P : (176, 179, 180, 181, 182, 183, 184, 185, 186, 189, 190, 191, 192, 193, 194, 195, 196, 199), " & "SCL : 200, " & "SDA : 201, " & "UARXD0 : 202, " & "nUADTR0 : 203, " & "UATXD0 : 204, " & "nUADSR0 : 205, " & "UARXD1 : 206, " & "VDDP : 1, 21, 41, 53, 78, 103, 118, 142, 157, 177, 197, " & "VDDI : 11, 31, 51, 65, 92, 105, 130, 155, 167, 187, 207, " & "VSSP : 2, 22, 42, 54, 79, 93, 106, 131, 156, 168, 188, 208, " & "VSSI : 12, 32, 52, 66, 81, 104, 119, 143, 158, 178, 198 "; A-15 APPENDIX A S3C4510B attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_RESET of nTRST : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is true; attribute INSTRUCTION_LENGTH of S3C4510B : entity is 4; attribute INSTRUCTION_OPCODE of S3C4510B : entity is "EXTEST (0000)," & "SCAN_N (0010)," & "INTEST (1100)," & "IDCODE (1110)," & "BYPASS (1111)," & "CLAMP (0101)," & "HIGHZ (0111)," & "CLAMPZ (1001)," & "SAMPLE (0011)," & "RESTART (0100)"; -- S3C4510B's IDCODE is the ARM7TDMI's IDCODE. attribute REGISTER_ACCESS of S3C4510B : entity is "0001" & -- version "111100" & -- design center "0011110000" & -- sequence number "11110000111" & -- Samsung "1"; -- required by 1149.1 attribute REGISTER_ACCESS of S3C4510B : entity is "IDCODE (IDCODE)," & "BOUNDARY (INTEST, SAMPLE, EXTEST)," & "BYPASS (CLAMP, HIGHZ, BYPASS)"; attribute BOUNDARY_CELLS of S3C4510B : entity is "BC_4, BC_2, BC_1"; attribute BOUNDARY_LENGTH of S3C4510B : entity is 233; attribute BOUNDARY_REGISTER of S3C4510B : entity is -- num "0 "1 "2 "3 cell port function safe [ccell disval rslt] input, X) ," & output2, X) ," & output2, X) ," & input, X) ," & ( BC_2, UARXD1, ( BC_1, nUADSR0, ( BC_1, UATXD0, ( BC_2, nUADTR0, A-16 S3C4510B APPENDIX A "4 ( BC_2, UARXD0, "5 ( BC_1, SDA, "6 ( BC_2, SDA, "7 ( BC_1, SCL, "8 ( BC_2, SCL, "9 ( BC_1, *, "10 ( BC_1, P(17), "11 ( BC_2, P(17), "12 ( BC_1, *, "13 ( BC_1, P(16), "14 ( BC_2, P(16), "15 ( BC_1, *, "16 ( BC_1, P(15), "17 ( BC_2, P(15), "18 ( BC_1, *, "19 ( BC_1, P(14), "20 ( BC_2, P(14), "21 ( BC_1, *, "22 ( BC_1, P(13), "23 ( BC_2, P(13), "24 ( BC_1, *, "25 ( BC_1, P(12), "26 ( BC_2, P(12), "27 ( BC_1, *, "28 ( BC_1, P(11), "29 ( BC_2, P(11), "30 "31 "32 "33 "34 "35 ( BC_1, *, ( BC_1, P(10), ( BC_2, P(10), ( BC_1, *, ( BC_1, P(9), ( BC_2, P(9), input, X) ," & output3, 1, 5, 1, Z) ," & -- Open-drain Output input, X) ," & output3, 1, 7, 1, Z) ," & -- Open-drain Output input, X) ," & controlr, 1) ," & --P_ENB(17) output3, X, 9, 1, Z) ," & input, X) ," & controlr, 1) ," & --P_ENB(16) output3, X, 12, 1, Z) ," & input, X) ," & controlr, 1) ," & --P_ENB(15) output3, X, 15, 1, Z) ," & input, X) ," & controlr, 1) ," & --P_ENB(14) output3, X, 18, 1, Z) ," & input, X) ," & controlr, 1) ," & --P_ENB(13) output3, X, 21, 1, Z) ," & input, X) ," & controlr, 1) ," & --P_ENB(12) output3, X, 24, 1, Z) ," & input, X) ," & controlr, 1) ," & --P_ENB(11) output3, X, 27, 1, Z) ," & input, X) ," & controlr, 1) ," & --P_ENB(10) output3, X, 30, 1, Z) ," & input, X) ," & controlr, 1) ," & --P_ENB(9) output3, X, 33, 1, Z) ," & input, X) ," & controlr, 1) ," & --P_ENB(8) output3, X, 36, 1, Z) ," & input, X) ," & controlr, 1) ," & --P_ENB(7) output3, X, 39, 1, Z) ," & input, X) ," & "36 ( BC_1, *, "37 ( BC_1, P(8), "38 ( BC_2, P(8), "39 ( BC_1, *, "40 ( BC_1, P(7), "41 ( BC_2, P(7), A-17 APPENDIX A S3C4510B "42 ( BC_1, *, "43 ( BC_1, P(6), "44 ( BC_2, P(6), "45 ( BC_1, *, "46 ( BC_1, P(5), "47 ( BC_2, P(5), "48 ( BC_1, *, "49 ( BC_1, P(4), "50 ( BC_2, P(4), "51 ( BC_1, *, "52 ( BC_1, P(3), "53 ( BC_2, P(3), "54 ( BC_1, *, "55 ( BC_1, P(2), "56 ( BC_2, P(2), "57 ( BC_1, *, "58 ( BC_1, P(1), "59 ( BC_2, P(1), "60 ( BC_1, *, "61 ( BC_1, P(0), "62 ( BC_2, P(0), controlr, 1) ," & --P_ENB(6) output3, X, 42, 1, Z) ," & input, X) ," & controlr, 1) ," & --P_ENB(5) output3, X, 45, 1, Z) ," & input, X) ," & controlr, 1) ," & --P_ENB(4) output3, X, 48, 1, Z) ," & input, X) ," & controlr, 1) ," & --P_ENB(3) output3, X, 51, 1, Z) ," & input, X) ," & controlr, 1) ," & --P_ENB(2) output3, X, 54, 1, Z) ," & input, X) ," & controlr, 1) ," & --P_ENB(1) output3, X, 57, 1, Z) ," & input, X) ," & controlr, 1) ," & --P_ENB(0) output3, X, 60, 1, Z) ," & input, X) ," & output3, X, 127, 1, Z) ," & input, X) ," & output3, X, 127, 1, Z) ," & input, X) ," & output3, X, 127, 1, Z) ," & input, X) ," & output3, X, 127, 1, Z) ," & input, X) ," & output3, X, 127, 1, Z) ," & input, X) ," & output3, X, 127, 1, Z) ," & input, X) ," & output3, X, 127, 1, Z) ," & input, X) ," & "63 ( BC_1, XDATA(31), "64 ( BC_2, XDATA(31), "65 ( BC_1, XDATA(30), "66 ( BC_2, XDATA(30), "67 ( BC_1, XDATA(29), "68 ( BC_2, XDATA(29), "69 ( BC_1, XDATA(28), "70 ( BC_2, XDATA(28), "71 ( BC_1, XDATA(27), "72 ( BC_2, XDATA(27), "73 ( BC_1, XDATA(26), "74 ( BC_2, XDATA(26), "75 ( BC_1, XDATA(25), "76 ( BC_2, XDATA(25), A-18 S3C4510B APPENDIX A "77 ( BC_1, XDATA(24), "78 ( BC_2, XDATA(24), "79 ( BC_1, XDATA(23), "80 ( BC_2, XDATA(23), "81 ( BC_1, XDATA(22), "82 ( BC_2, XDATA(22), "83 ( BC_1, XDATA(21), "84 ( BC_2, XDATA(21), "85 ( BC_1, XDATA(20), "86 ( BC_2, XDATA(20), "87 ( BC_1, XDATA(19), "88 ( BC_2, XDATA(19), "89 ( BC_1, XDATA(18), "90 ( BC_2, XDATA(18), "91 ( BC_1, XDATA(17), "92 ( BC_2, XDATA(17), "93 ( BC_1, XDATA(16), "94 ( BC_2, XDATA(16), "95 ( BC_1, XDATA(15), "96 ( BC_2, XDATA(15), "97 ( BC_1, XDATA(14), "98 ( BC_2, XDATA(14), "99 ( BC_1, XDATA(13), "100 ( BC_2, XDATA(13), "101 ( BC_1, XDATA(12), "102 ( BC_2, XDATA(12), "103 ( BC_1, XDATA(11), "104 ( BC_2, XDATA(11), "105 ( BC_1, XDATA(10), "106 ( BC_2, XDATA(10), "107 ( BC_1, XDATA(9), "108 ( BC_2, XDATA(9), "109 ( BC_1, XDATA(8), output3, X, 127, 1, Z) ," & input, X) ," & output3, X, 127, 1, Z) ," & input, X) ," & output3, X, 127, 1, Z) ," & input, X) ," & output3, X, 127, 1, Z) ," & input, X) ," & output3, X, 127, 1, Z) ," & input, X) ," & output3, X, 127, 1, Z) ," & input, X) ," & output3, X, 127, 1, Z) ," & input, X) ," & output3, X, 127, 1, Z) ," & input, X) ," & output3, X, 127, 1, Z) ," & input, X) ," & output3, X, 127, 1, Z) ," & input, X) ," & output3, X, 127, 1, Z) ," & input, X) ," & output3, X, 127, 1, Z) ," & input, X) ," & output3, X, 127, 1, Z) ," & input, X) ," & output3, X, 127, 1, Z) ," & input, X) ," & output3, X, 127, 1, Z) ," & input, X) ," & output3, X, 127, 1, Z) ," & input, X) ," & output3, X, 127, 1, Z) ," & A-19 APPENDIX A S3C4510B "110 ( BC_2, XDATA(8), "111 ( BC_1, XDATA(7), "112 ( BC_2, XDATA(7), "113 ( BC_1, XDATA(6), "114 ( BC_2, XDATA(6), "115 ( BC_1, XDATA(5), "116 ( BC_2, XDATA(5), "117 ( BC_1, XDATA(4), "118 ( BC_2, XDATA(4), "119 ( BC_1, XDATA(3), "120 ( BC_2, XDATA(3), "121 ( BC_1, XDATA(2), "122 ( BC_2, XDATA(2), "123 ( BC_1, XDATA(1), "124 ( BC_2, XDATA(1), "125 ( BC_1, XDATA(0), "126 ( BC_2, XDATA(0), "127 ( BC_1, *, "128 ( BC_1, ADDR(21), "129 ( BC_1, ADDR(20), "130 ( BC_1, ADDR(19), "131 ( BC_1, ADDR(18), "132 ( BC_1, ADDR(17), "133 ( BC_1, ADDR(16), "134 ( BC_1, ADDR(15), "135 ( BC_1, ADDR(14), "136 ( BC_1, ADDR(13), "137 ( BC_1, ADDR(12), "138 ( BC_1, ADDR(11), "139 ( BC_1, ADDR(10), "140 ( BC_1, ADDR(9), "141 ( BC_1, ADDR(8), "142 ( BC_1, ADDR(7), "143 ( BC_1, ADDR(6), "144 ( BC_1, ADDR(5), "145 ( BC_1, ADDR(4), "146 ( BC_1, ADDR(3), "147 ( BC_1, ADDR(2), "148 ( BC_1, ADDR(1), "149 ( BC_1, ADDR(0), input, X) ," & output3, X, 127, 1, Z) ," & input, X) ," & output3, X, 127, 1, Z) ," & input, X) ," & output3, X, 127, 1, Z) ," & input, X) ," & output3, X, 127, 1, Z) ," & input, X) ," & output3, X, 127, 1, Z) ," & input, X) ," & output3, X, 127, 1, Z) ," & input, X) ," & output3, X, 127, 1, Z) ," & input, X) ," & output3, X, 127, 1, Z) ," & input, X) ," & controlr, 1) ," & --DATAOUT_ENB output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, X, X, X, X, X, X, X, X, X, X, X, X, X, X, X, X, X, X, X, X, X, X, 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & A-20 S3C4510B APPENDIX A "150 ( BC_1, ExtMACK, "151 ( BC_2, ExtMREQ, "152 ( BC_1, nWBE(3), "153 ( BC_1, nWBE(2), "154 ( BC_1, nWBE(1), "155 ( BC_1, nWBE(0), "156 ( BC_1, nDWE, "157 ( BC_1, nCAS(3), "158 ( BC_1, nCAS(2), "159 ( BC_1, nCAS(1), "160 ( BC_1, nCAS(0), "161 ( BC_1, nRAS(3), "162 ( BC_1, nRAS(2), "163 ( BC_1, nRAS(1), "164 ( BC_1, nRAS(0), "165 ( BC_1, nRCS(5), "166 ( BC_1, nRCS(4), "167 ( BC_1, nRCS(3), "168 ( BC_1, nRCS(2), "169 ( BC_1, nRCS(1), "170 ( BC_2, CLKSEL, "171 ( BC_2, nRESET, "172 ( BC_4, MCLK, "173 ( BC_1, MCLKO, "174 ( BC_2, CLKOEN, "175 ( BC_1, nRCS(0), "176 ( BC_2, B0SIZE(1), "177 ( BC_2, B0SIZE(0), "178 ( BC_1, nOE, "179 ( BC_2, nEWAIT, "180 ( BC_1, nECS(3), "181 ( BC_1, nECS(2), "182 ( BC_1, nECS(1), "183 ( BC_1, nECS(0), output2, X) ," & input, X) ," & output3, output3, output3, output3, X, X, X, X, 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & output3, X, output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, X, X, X, X, X, X, X, X, X, X, X, X, X, input, X) ," & input, X) ," & input, X) ," & output2, X) ," & input, X) ," & output3, X, input, input, 184, 1, Z) ," & X) ," & X) ," & 184, 1, Z) ," & output3, X, input, output3, output3, output3, output3, X) ," & X, X, X, X, 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & 184, 1, Z) ," & A-21 APPENDIX A S3C4510B "184 ( BC_1, *, "185 ( BC_2, UCLK, "186 ( BC_2, TMODE, "187 ( BC_1, MDC, "188 ( BC_2, LITTLE, "189 ( BC_1, *, "190 ( BC_1, MDIO, "191 ( BC_2, MDIO, controlr, 1) ," & --DIS_BUS input, X) ," & input, X) ," & output2, X) ," & input, X) ," & controlr, 1) ," & --MDIO_OE output3, X, 189, 1, Z) ," & input, X) ," & "192 ( BC_1, TX_EN_TXEN_10M, output2, X) ," & "193 ( BC_2, TX_CLK_TXCLK_10M, input, X) ," & "194 ( BC_1, TX_ERR_PCOMP_10M, output2, X) ," & "195 ( BC_1, TXD3, output2, X) ," & "196 ( BC_1, TXD2, output2, X) ," & "197 ( BC_1, TXD1_LOOP10, output2, X) ," & "198 ( BC_1, TXD0_TXD_10M, output2, X) ," & "199 ( BC_2, COL_COL_10M, input, X) ," & "200 ( BC_2, RX_CLK_RXCLK_10M, input, X) ," & "201 ( BC_2, RX_ERR, input, X) ," & "202 ( BC_2, RXD3, input, X) ," & "203 ( BC_2, RXD2, input, X) ," & "204 ( BC_2, RXD1, input, X) ," & "205 ( BC_2, RXD0_RXD_10M, input, X) ," & "206 ( BC_2, RX_DV_LINK10, input, X) ," & "207 ( BC_2, CRS_CRS_10M, input, X) ," & "208 ( BC_1, *, "209 ( BC_1, TXCB, "210 ( BC_2, TXCB, "211 ( BC_1, nSYNCB, "212 ( BC_2, RXCB, "213 ( BC_2, nDCDB, "214 ( BC_2, nCTSB, "215 ( BC_1, TXDB, "216 ( BC_1, nRTSB, "217 ( BC_2, RXDB, "218 ( BC_1, nDTRB, "219 ( BC_1, *, "220 ( BC_1, TXCA, "221 ( BC_2, TXCA, controlr, 1) ," & --TXCBEN output3, X, 208, 1, Z) ," & input, X) ," & output2, X) ," & input, X) ," & input, X) ," & input, X) ," & output2, X) ," & output2, X) ," & input, X) ," & output2, X) ," & controlr, 1), " & --TXCAEN output3, X, 219, 1, Z) ," & input, X) ," & A-22 S3C4510B APPENDIX A "222 ( BC_1, nSYNCA, "223 ( BC_2, RXCA, "224 ( BC_2, nDCDA, "225 ( BC_2, nCTSA, "226 ( BC_1, TXDA, "227 ( BC_1, nRTSA, "228 ( BC_2, RXDA, "229 ( BC_1, nDTRA, "230 ( BC_1, nUADSR1, "231 ( BC_1, UATXD1, "232 ( BC_2, nUADTR1, end S3C4510B; output2, X) ," & input, X) ," & input, X) ," & input, X) ," & output2, X) ," & output2, X) ," & input, X) ," & output2, X) ," & output2, X) ," & output2, X) ," & input, X) "; A-23 APPENDIX A S3C4510B NOTES A-24 |
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