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| CXD2408AR Timing Generator for Progressive Scan CCD Image Sensor Description The CXD2408AR is an IC developed to generate the timing pulses required by the Progressive Scan CCD image sensors as well as signal processing circuits. Features * EIA support * Electronic shutter function * Random trigger shutter function * Sync signal generator * Supports external synchronization * Supports non-interlaced operation * Base oscillation 1560fh (24.5454MHz) Applications Progressive Scan CCD cameras Structure Silicon gate CMOS IC Applicable CCD Image Sensors ICX074AK, ICX074AL 64 pin LQFP (Plastic) Absolute Maximum Ratings V * Supply voltage VDD VSS - 0.5 to +7.0 * Input voltage VI VSS - 0.5 to VDD + 0.5 V * Output voltage VO VSS - 0.5 to VDD + 0.5 V * Operating temperature Topr -20 to +75 C * Storage temperature Tstg -55 to +150 C Recommended Operating Conditions * Supply voltage VDD 4.75 to 5.25 * Operating temperature Topr -20 to +75 V C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E96402A68 CXD2408AR Block Diagram XCPDM XCPOB REVH REND SYNC OCTL HDO O2FH PBLK WEN RDM VDO VDI RM CLD BLK EXT HDI FLD 47 46 45 44 43 42 41 39 38 37 36 59 58 61 60 57 54 53 51 50 49 CL ID RG 11 XH1 13 XH2 14 XSHP 28 XSHD 29 XRS 30 XV1 26 XV2 25 XV3 22 XSG 27 XHHG1A 15 XHHG1B 16 XHHG2 17 XVOG 18 XVHOLD 19 DECODE 1/2 COUNTER TG OUTPUT CONTROL 63 VRI 62 HRI GATE V-CONTROL PULSE GENERATOR H-DECODER 1/390 V-DECODER 1/525 20 TEST1 21 TEST2 31 TEST3 32 TEST4 48 TEST8 TEST CIRCUIT 35 TEST7 34 TEST6 33 TEST5 GATE 52 NC 64 1 2 8 10 3 4 5 6 7 9 12 23 24 40 55 56 SMD1 VSS OSCO VDD CKI VSS PS VSS VSS TRIG ED0 ED1 24.5MHz -2- SMD2 XSUB OSCI ED2 VDD CXD2408AR Pin Configuration XCPDM XCPOB TEST8 WEN PBLK RDM REVH RM ID 48 CL CLD O2FH NC FLD BLK VSS VDD SYNC HDI VDI HDO VDO HRI VRI CKI 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 47 46 45 44 43 42 41 40 39 38 37 EXT VSS TEST7 36 35 34 33 32 31 30 29 28 27 26 TEST4 TEST3 XRS XSHD XSHP XSG XV1 XV2 VDD VSS XV3 TEST2 TEST1 XVHOLD XVOG XHHG2 TEST6 TEST5 25 24 23 22 21 20 19 18 17 16 CXD2408AR (G/A) REND OCTL 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -3- XHHG1A XHHG1B OSCO SMD1 SMD2 XSUB OSCI ED1 ED0 VSS RG PS ED2 TRIG XH1 XH2 CXD2408AR Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Symbol OSCO OSCI PS ED0 ED1 ED2 SMD1 Vss SMD2 TRIG RG XSUB XH1 XH2 XHHG1A XHHG1B XHHG2 XVOG XVHOLD TEST1 TEST2 XV3 Vss VDD XV2 XV1 XSG XSHP XSHD XRS TEST3 TEST4 TEST5 TEST6 TEST7 I/O O I I I I I I -- I I O O O O O O O O O O O O -- -- O O O O O O O O O O I Inverter output for oscillation. Inverter input for oscillation. Switching for electronic shutter speed input method. (With pull-down resistor) Low: Parallel input, High: Serial input Shutter speed setting. Strobe input for serial mode. (With pull-up resistor) Shutter speed setting. Clock input for serial mode. (With pull-up resistor) Shutter speed setting. Data input for serial mode. (With pull-up resistor) Shutter mode setting. (With pull-up resistor) GND Shutter mode setting. (With pull-up resistor) Trigger input for random trigger shutter. Reset gate pulse output. CCD discharge pulse output. Clock output for CCD horizontal register drive. Clock output for CCD horizontal register drive. Clock output for transfer between CCD horizontal registers. Clock output for transfer between CCD horizontal registers. Clock output for transfer between CCD horizontal registers. Clock output for transfer from CCD vertical register to CCD horizontal register. Clock output for adjusting timing of transfer to CCD horizontal register. Test output. Normally open. Test output. Normally open. Clock output for CCD vertical register drive. GND Power supply. Clock output for CCD vertical register drive. Clock output for CCD vertical register drive. CCD sensor charge readout pulse output. Precharge level sample-and-hold pulse. Data sample-and-hold pulse. Sample-and-hold pulse. Test output. Normally open. Test output. Normally open. Test output. Normally open. Test output. Normally open. Test input. Set at Low in normal operation. (With pull-down resistor) -4- Description CXD2408AR Pin No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Symbol EXT REND REVH OCTL Vss RDM RM XCPDM XCPOB PBLK ID WEN TEST8 CL CLD O2FH NC FLD BLK Vss VDD SYNC HDI VDI HDO VDO HRI VRI CKI I/O I I I I -- I I O O O O O I O O O -- O O -- -- O I I O O I I I Field pulse output. Composite blanking output. GND Power supply. Composite sync output. Horizontal sync signal input. Vertical sync signal input. Horizontal sync signal output. Vertical sync signal output. Horizontal reset signal input. Vertical reset signal input. 2 fck clock input. Description Internal synchronization/external synchronization switching. (With pull-down resistor) Low: Internal synchronization, High: External synchronization Normal reset/direct reset switching. (With pull-down resistor) Low: Normal reset, High: Direct reset V reset/HV reset switching. (With pull-down resistor) Low: V reset, High: HV reset O2FH output control. (With pull-down resistor) Low: No output, High: Output GND Normal operation/random trigger shutter switching. (With pull-down resistor) Low: Normal operation, High: Random trigger shutter Switching for output mode. (With pull-down resistor) Low: Non-interlaced, High: Interlaced Clamp pulse output. Clamp pulse output. Blanking cleaning pulse output. Line identification output. Write enable output. Test input. (With pull-down resistor) fck clock output. (0) fck clock output. (180) 2 fH output. -5- CXD2408AR Electrical Characteristics DC Characteristics Item Supply voltage Input voltage 1 (Input pins other than those below) Input voltage 2 (Pins 7, 9, 10, 58, 59, 62, 63, and 64) Output voltage 1 (Output pins other than those below) Output voltage 2 (Pins 28, 29, 30, 31, 32, 33, 34, 49 and 50) Output voltage 3 (Pins 11, 13, and 14) Output voltage 4 (Pin 1) Feedback resistor Pull-up resistor Pull-down resistor Current consumption Symbol VDD VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 RFB RPU RPD IDD IOH = -2mA IOL = 4mA IOH = -4mA IOL = 8mA IOH = -12mA IOL = 12mA IOH = -12mA IOL = 12mA VIN = Vss or VDD VIL = 0V VIN = VDD Conditions (VDD = 4.75 to 5.25V, Topr = -20 to +75C) Min. 4.75 0.7VDD 0.3VDD 0.7VDD 0.3VDD -0.8 0.4 -0.8 0.4 VDD - 0.8 0.4 VDD/2 VDD/2 250k 1M 50k 50k 35 2.5M Typ. 5.0 Max. 5.25 Unit V V V V V V V V V V V V V mA VDD = 5V ICX074AL in normal operating state I/O Pin Capacitances Item Input pin capacitance Output pin capacitance Symbol CIN COUT Min. -- -- (VDD = VI = 0V, fM = 1MHz) Typ. -- -- Max. 9 11 Unit pF pF -6- CXD2408AR AC Characteristics 1) Phase characteristics of XH1, RG, XSHP, XSHD, XRS, CL, and CLD tCK CK Vpp/2 tpd1 tpd2 0.7VDD 0.3VDD tpd3 tpd4 0.7VDD 0.3VDD tpd5 tpd6 0.7VDD tpd7 tpd8 XH1 RG XSHP 0.3VDD XSHD 0.3VDD tpd9 0.7VDD tpd10 0.7VDD XRS tpd11 0.3VDD tpd12 CL 0.7VDD 0.3VDD tpd14 tpd13 CLD 0.3VDD 0.7VDD (VDD = 5.0V, Topr = 25C, Load capacity of CL and CLD = 30pF, Load capacity of XH1, XSHP, XSHD, XRS, and RG = 10pF) Symbol Definition CK cycle XH1 rising delay, activated by the falling edge of CK XH1 falling delay, activated by the falling edge of CK RG falling delay, activated by the rising edge of CK RG rising delay, activated by the falling edge of CK XSHP falling delay, activated by the rising edge of CK XSHP rising delay, activated by the falling edge of CK XSHD falling delay, activated by the rising edge of CK XSHD rising delay, activated by the falling edge of CK XRS falling delay, activated by the falling edge of CK XRS rising delay, activated by the rising edge of CK CL falling delay, activated by the rising edge of CK CL rising delay, activated by the rising edge of CK CLD falling delay, activated by the rising edge of CK CLD rising delay, activated by the falling edge of CK -7- Typ. 41 28 29 27 33 36 30 36 29 34 28 15 17 30 33 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tCK tpd1 tpd2 tpd3 tpd4 tpd5 tpd6 tpd7 tpd8 tpd9 tpd10 tpd11 tpd12 tpd13 tpd14 CXD2408AR Waveform Characteristics of XH1 and RG 0.9VDD XH1 0.1VDD tfH1 trH1 0.9VDD RG 0.1VDD trRG tfRG (VDD = 5.0V, Topr = 25C, Load capacity of XH1 = 10pF, Load capacity of RG = 10pF) Symbol Definition XH1 rise time XH1 fall time RG rise time RG fall time Typ. 2 2 2 2 Unit ns ns ns ns trH1 tfH1 trRG tfRG -8- CXD2408AR * In the normal reset mode, the signal output is reset to ODD or EVEN field depending on the input timing of the vertical reset signal as shown in the figure below. Field identification VRI 1 2 HDO tp2 tp3 tp1 fH tp4 tp5 fH L: ODD H: EVEN VDO 1 259H ODD VDO 2 259H EVEN Symbol Definition Range of resetting to ODD Range of resetting to EVEN Range of resetting to ODD Prohibited area Prohibited area Specified value 21.9 31.6 9.7 200 200 Unit s s s ns ns tp1 tp2 tp3 tp4 tp5 -9- CXD2408AR * In the direct reset mode, the signal output is reset to ODD or EVEN field depending on the input timing of the vertical reset signal as shown in the figure below. Field identification VRI 1 2 HDO tp2 tp3 tp1 fH tp4 tp5 fH L: ODD H: EVEN VDO 1 ODD VDO 2 EVEN Symbol Definition Range of resetting to ODD Range of resetting to EVEN Range of resetting to ODD Prohibited area Prohibited area Specified value 21.9 31.6 -- 200 200 Unit s s s ns ns tp1 tp2 tp3 tp4 tp5 In the direct reset mode, the cycle of HD can be arbitrary. Therefore, tp3 is not specified. - 10 - CXD2408AR Description of Operation 1. Mode Control Symbol RM RDM PS EXT REND REVH Pin No. 42 41 3 36 37 38 L 1/30s non-interlaced Normal operation Parallel Internal synchronization Normal reset V reset H 1/60s interlaced Random trigger shutter Serial External synchronization Direct reset HV reset Electronic shutter speed input method Remarks 2. Mode Relationships RM L Internal synchronization L RDM Normal operation H Random trigger shutter Normal operation L 1/30s non-interlaced H External synchronization L Internal synchronization L Normal operation H Random trigger shutter Normal operation L REND Direct reset L REVH V reset : Disabled H HV reset Normal reset H Direct reset L V reset H HV reset H 1/60s interlaced H External synchronization EXT - 11 - CXD2408AR 3. Electronic Shutter Flickerless: Eliminates fluorescent frequency-induced flicker. High-speed shutter: Shutter speed faster than 1/60 Low-speed shutter: Shutter speed slower than 1/60 No shutter operation Shutter speed is 1/30s in 1/30s mode, and 1/60s in 1/60s mode. - 12 - CXD2408AR 3-2. Serial input * For serial input (PS = High), SMD1 and SMD2 bits within ED2 (DATA) take priority over SMD1 (Pin 7) and SMD2 (Pin 9) pins as SMD1 and SMD2 (shutter mode control). In this case, control by SMD1 and SMD2 pins is invalid. ED1 (CLK) ED2 (DATA) D0 D1 D2 D3 D4 D5 D6 D7 D8 SMD1 SMD2 Dummy ED0 (STB) ED2 data is latched to the register at the rise of ED1, and transferred to the within at the rise of ED0. AC Characteristics ED2 ts2 th2 ED1 tw1 ED0 tw0 ts1 ts0 Symbol Definition ED2 set-up time, activated by the falling edge of ED1 ED2 hold time, activated by the rising edge of ED1 ED1 rising set-up time, activated by the rising edge of ED0 ED0 pulse width ED0 rising set-up time, activated by the rising edge of ED1 ED1 pulse width (serial input) Min. 20ns 20ns 20ns 20ns 20ns 20ns Max. -- -- -- 50s -- -- ts2 th2 ts1 tw0 ts0 tw1 - 13 - CXD2408AR 3-3. Shutter speed calculation formula High-speed shutter T = [26210 - (1FF16 - L16)] x 63.56 + 34.78 (s) (L16 = Load value) Load value 0FA16 0FC16 10016 10816 11816 13716 17616 19616 Shutter speed 1/10000 1/4000 1/2000 1/1000 1/500 1/250 1/125 1/100 Calculated value 1/10169 1/4435 1/2085 1/1012 1/499 1/252 1/125 1/100 Low-speed shutter N = 2 x (1FF16 - L16) FLD However, the load value of FF16 cannot be used . Load value Shutter speed (FLD) 1FE16 1FD16 : 10116 10016 2 4 : 508 510 In case of starting with serial input setting (PS = H), be sure to transfer shutter speed data in the range of specification after power is turned on, and then use it.. - 14 - CXD2408AR 4. Random Trigger Shutter The random trigger shutter is different from the conventional electronic shutter in that the exposure beginning can be freely set. The exposure period (shutter speed) can be set as with the conventional electronic shutter. In this mode, XSUB rises for each 1H, and the charge stored in the sensor is discharged. Because the V clock (XV1 to XV3) is continuously operating, any unneeded charge in the vertical CCD is eliminated. XSG pulse is stopped until the external trigger is detected. The image cannot be monitored until the external trigger is detected and the signal is read out. When an external trigger is input in this state, HD is forcibly reset when the trigger falls, and XSUB falls once to clear the charge and then halts. XV1 to XV3, XCPDM, XCPOB, and PBLK are reset with HD. From this point, exposure begins, and after the preset exposure period has passed, the XSG pulse falls, the charge is transferred from the sensor to the vertical CCD, and exposure ends. The XSG pulse falls with the time set as in conventional electronic shutters, regardless of VD. Because HD is reset, the exposure period is accurate in 1H units. The WEN pulse is generated synchronously with the XSG pulse. As the WEN pulse specifies the signal start, it can be used as the sync signal for writing image data into the frame memory. In the random trigger shutter mode, V-direction functions of a sync signal generator are halted. As a result, sync signals VD and FLD are also halted. TRIG HD reset HD XSG XSUB reset XSUB Shutter speed XV1 XV2 XV3 WEN - 15 - CXD2408AR 5. External Synchronization - Reset HD and VD are reset to synchronize with the external sync signal. Resetting is done to synchronize a plural number of camera systems whose clock frequencies are the same. There are two reset inputs: HRI and VRI. When their falling edge is detected, resetting is carried out. The CXD2408AR has two reset modes: normal reset and direct reset. Details of the reset modes are described in the following pages. In the 1/30s non-interlaced readout mode, the normal reset mode is not supported, and although the direct reset mode is supported, the field is not identified. - 16 - CXD2408AR 5-1. Normal reset In the normal reset mode, the reset signal is input for resetting, and the sync signal is output continuously from that time. Only the mode which resets both HD and VD (HV reset) is supported. When the H reset signal HRI is continuously with an H cycle, resetting is triggered at the first falling edge, and after that point no resets are triggered at edges unless HD after resetting exceeds 2bits (163ns) on the internal clock. In other words, the HRI input jitter is absorbed when it is up to 163 ns. The HRI minimum reset pulse width is 0.3s. In the V direction, counting begins from VRI fall, and V is reset to cause VDO to fall after 262.5 - 3.5 = 259H. The VRI minimum reset pulse width is 2H. Resetting is done for ODD or EVEN field, depending on the input timing of the V reset signal. The identification timing is shown in Electrical Characteristics (Field identification). FIELD.E HRI FIELD.O HDO VRI 9H VDO 259H FIELD.O HRI FIELD.E HDO VRI 9H VDO 259H H reset 57.1 to 57.2s (701 to 702 bit) HRI HD OUT Reset 6.3 to 6.37s - 17 - CXD2408AR 5-2. Direct reset In the direct reset mode, when the reset signal is input for resetting, a sync signal is output, but there is no continuous output. There are two direct reset modes: one to direct reset VD only (V reset), and one to reset both HD and VD (HV reset). (However, note that even for V reset, the HRI signal is acceptable and the reset timing is the same as in normal reset mode.) In both modes, the VD reset timing is the same. When the external input V reset signal VRI fall is detected, a judgment is made as to ODD or EVEN. If ODD, V is reset to cause VDO to fall simultaneously with HD fall, and if EVEN, V is reset to cause VDO to fall simultaneously in the middle of HD. VRI requires a minimum pulse width of 2H. H direct reset detects the fall of H reset signal HRI, and resets H so that HDO falls at the next CL falling edge. The minimum HRI reset pulse width is 0.3s. Resetting is done for ODD or EVEN field, depending on the input timing of the V reset signal. The identification timing is shown in Electrical Characteristics (Field identification). 5-2-1. V reset FIELD.E HRI HDO FIELD.O VRI 9H VDO FIELD.O HRI FIELD.E HDO VRI 9H VDO - 18 - CXD2408AR 5-2-2. HV reset (1/60s interlaced readout mode) FIELD.E HDO FIELD.O HRI 9H VDO VRI XSG ID FIELD.O HDO FIELD.E HRI 9H VDO VRI XSG ID CL HRI HDO - 19 - CXD2408AR 5-2-3. HV reset (1/30s non-interlaced readout mode) HDO HRI 9H VDO VRI XSG ID HDO HRI 9H VDO VRI XSG ID CL HRI HDO - 20 - CXD2408AR Timing Chart (1) FLD VDO BLK HDO 525 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 260 261 262 263 264 265 275 270 280 285 XV1 XV2 XV3 494 493 1 3 5 7 1 3 5 7 9 11 13 15 493 XSG XVHOLD XVOG XHHG1A XHHG1B XHHG2 PBLK XCPOB XCPDM ID WEN 2 4 6 8 2 4 6 8 10 12 14 16 - 21 - 1 3 5 7 1 3 5 7 9 11 13 15 OUT2 494 2 4 6 8 2 4 6 8 10 12 14 16 OUT1 CXD2408AR Timing Chart (2) FLD VDO BLK HDO 525 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 493 494 1 2 3 4 5 6 7 8 1 2 3 525 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 XV1 XV2 XV3 OUT1 493 494 1 2 3 4 5 6 7 8 1 2 3 4 XSG XVHOLD XVOG XHHG1A XHHG1B XHHG2 PBLK XCPOB XCPDM ID WEN - 22 - Timing Chart (3) 20 30 70 80 100 110 120 132 130 78 90 40 50 60 0 10 BLK/HD CL XV1 41 77 65 101 95 89 101 95 Dummy (16 bits) 100 75 65 83 78 63 59 77 76 58 56 69 47 77 52 83 95 47 47 37 35 35 59 35 53 71 89 XV2 XV3 XVHOLD XVOG XHHG1A XHHG1B - 23 - 72 35 31 93 93 XHHG2 OPB (31 bits) OPB (2 bits) XH1 XH2 RG XSHP XSHD 95 115 XSUB PBLK XCPOB 13 XCPDM 105 114 ID CXD2408AR WEN Timing Chart (4) 20 30 70 80 100 110 120 132 130 78 90 40 50 60 0 10 BLK/HD CL 35 65 47 77 59 59 89 65 101 95 Dummy (16 bits) 100 35 35 35 89 XV1 XV2 XV3 XVHOLD XVOG XHHG1A XHHG1B XHHG2 OPB (31 bits) OPB (2 bits) - 24 - 72 35 31 95 93 93 XH1 XH2 RG XSHP XSHD XSUB PBLK 115 XCPOB 13 XCPDM 105 114 ID CXD2408AR WEN CXD2408AR Timing Chart (5) HD 2.53s (31 bits) 42.4s (520 bits) 2.53s (31 bits) 2.94s (36 bits) 16.1s (198 bits) ODD Field XV1 XV2 XV3 XSG EVEN Field XV1 XV2 XV3 XSG Timing Chart (6) HD 2.53s (31 bits) 42.4s (520 bits) 2.53s (31 bits) 16.1s (198 bits) 2.94s (36 bits) ODD Field XV1 XV2 XV3 XSG - 25 - CXD2408AR Timing Chart (7) HD CKI CL XH1 XH2 RG XSHP XSHD XRS CLD - 26 - CXD2408AR Timing Chart (8) O : ODD E : EVEN Field E HDO Field O 9H VDO SYNC 20H BLK FLD Field O Field E HDO 9H VDO SYNC 20H BLK FLD - 27 - CXD2408AR Timing Chart (9) HDO 6.36s (78 bits) BLK 1.47s (18 bits) HSYNC 10.76s (132 bits) 4.89s (60 bits) EQ 2.45s (30 bits) VSYNC 26.89s (330 bits) VDO 4.89s (60 bits) FLD ODD 11.82s (145 bits) EVEN 2FH 9.86s (121 bits) 10.14s (124 bits) 63.56s (780 bits) 1/2H 31.78s (390 bits) 9.78s (120 bits) FH 22.00s (27 bits) - 28 - Application Circuit (1/60s interlaced, internal synchronization, normal continuous operation) 47p 47p 47p 47p 2.2K 47p 2.2K 2.2K 2.2K 2.2K N.C. N.C. N.C. 48 43 32 N.C. 15 24 14 22 21 31 N.C. 30 29 28 27 26 0.01 CXD2408AR 24 23 22 21 N.C. 20 N.C. 19 18 17 5 8 15 6 7 9 10 16 11 12 13 14 10/10V 13 15 25 42 41 34 40 38 39 35 33 47 46 45 44 37 36 13 49 50 22 CXD2311AR CXA1690Q N.C. 51 53 47p 2.2K 54 47p 2.2K 10/10V 55 0.01 56 ANALOG OUT1 N.C. 52 57 DIGITAL OUT1 (10bit) 47p 2.2K 58 59 64 1000p 1 2 3 4 21 ANALOG OUT2 - 29 - CXD1250M CXD1268M 74HC04 VSUB ADJ. ICX074AK/AL 60 47p 2.2K 22 24 14 22 CXA1690Q CXD2311AR 47p 61 2.2K N.C. 62 N.C. 63 DIGITAL OUT2 (10bit) 12p 20p +5V Input only for random trigger shutter mode. CCD OUT1 CCD OUT2 To MEMORY CONTROLLER CXD2408AR Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. CXD2408AR Package Outline Unit: mm 64PIN LQFP (PLASTIC) 12.0 0.2 48 49 10.0 0.1 33 32 A 64 1 0.5 b 16 0.13 M + 0.2 1.5 - 0.1 17 (0.22) 0.5 0.2 0.1 b = 0.18 0.03 0.1 0.1 + 0.08 b = 0.18 - 0.03 ( 0.18 ) + 0.05 0.127 - 0.02 (11.0) 0.5 0.2 0 to 10 (0.127) DETAIL B : SOLDER DETAIL A DETAIL B : PALLADIUM NOTE: Dimension "" does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-64P-L01 LQFP064-P-1010 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.3g - 30 - 0.125 0.04 Sony Corporation |
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