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1CY M74 SP5 4/55
PRELIMINARY
CYM74BP54 CYM74P54/55 CYM74SP54/55
Intel(R) 82430NX Chipset Level II Cache Module Family
Features
* Pin-compatible secondary cache module family * Asynchronous (CYM74BP54), synchronous pipelined (CYM74P54, CYM74P55), or synchronous (CYM74SP54, CYM74SP55) configurations with presence and configuration detect pins * Ideal for Intel(R) P54C-based systems with the 82430NX (Neptune) chipset * Operates at 60 and 66 MHz * Uses cost-effective CMOS asynchronous SRAMs or high-performance synchronous SRAMs * 160-position Burndy DIMM CELP2X80SC3Z48 connector * 3.3V inputs/outputs dustry standard 5V SRAMs and 3.3V level translators for CPU bus speeds up to 66 MHz. The CYM74BP54 is organized as 32K by 64-bits. The synchronous modules are available with low-cost synchronous pipelined RAMs or higher performance synchronous burst RAMs. The synchronous pipelined modules are based on a 16Kx64 RAM. The CYM74P54 is a 256-KB module while the CYM74P55 is a 512-KB module. Both are modules without byte parity. The CYM74SP54 and CYM74SP55 are synchronous burst cache modules that provide zero wait-state performance at a bus speed of 66 MHz. The CYM74SP54 is a 256-Kbyte cache module with byte parity. The CYM74SP55 is a 512-Kbyte cache module with byte parity. Multiple ground pins and on-board decoupling capacitors ensure high performance with maximum noise immunity. All components on the cache modules are surface mounted on a multi-layer epoxy laminate (multifunctional) substrate. The contact pins are plated with 150 micro-inches of nickel covered by 10 micro-inches of gold flash.
Functional Description
This family of secondary cache modules is designed for Intel P54C systems with the 82430NX (Neptune) chipset. CYM74BP54 is an asynchronous 256-Kbyte cache module that provides a low-cost, high-performance solution with in-
Logic Block Diagram - CYM74BP54
A17 -A 7 A6-0-A 5- 0 CALE LE ADDRESS LATCH D0-D 7 D8-D 15 D16 -D 23 D24 -D 31
LA17-LA 5 32K x 8 D 32K x 8 D A CE OE WE2 A CE OE WE3 32K x 8 D
32K x 8 D A CE OE WE1
A4- -A 3- 0 0
A CE OE WE0
CE0 OE0 WE0-WE 3 D32 -D D40 -D D48 -D D56 -D
39 47 55 63
32K x 8 D A CE OE WE4 CE1 OE1 WE4-WE 7
Intel is a registered trademark of Intel Corporation.
32K x 8 D A CE OE WE5
32K x 8 D A CE OE WE6
32K x 8 D A CE OE WE7
A4- -A 3- 1 1
74BP54-1
A
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 May 1994 - Revised October 1995
PRELIMINARY
Block Diagram: 5V to 3.3V Level Conversion (CYM74BP54)
5.0Volts
CYM74BP54 CYM74P54/55 CYM74SP54/55
100ohms Vcc 4.3Vzener 5%tolerance
5VSRAM
64BitBusSwitch (uses7CYBUS3384)
D
3.3VcompliantI/O B
GND
BE[2:1]
74BP54-2
Logic Block Diagram - CYM74P54, CYM74P55
CYM74P54 CYM74P55 CYM74P55ONLY CLK1 CLK0 CK D A16 7 -A A6- -A 3- 0 0 WE7-WE 0 ADSP0 ADSC0 ADV0 CE0 OE0 A A 8 BE0-BE 7 ADSP ADSC ADV CS0 OE A A BE0-BE 7 ADSP ADSC ADV CS 0 OE CK D A A BE0-BE 7 ADSP ADSC ADV CS 0 OE CK D A A BE0-BE 7 ADSP ADSC ADV CS0 OE CK D
PD2 TBD TBD
PD1 TBD TBD
PD0 TBD TBD
D63 0 -D
A6- -A 3- 1 1 ADSP1 ADSC1 ADV1 CE1 OE1
CS1 CS2
CS4 VCC CS3 VCC
GND CS 1 CS 2
CS 4 CS 3 VCC
CS 1 GND CS 2
CS 4 VCC CS 3
GND CS1 GND CS2
CS4 CS3
A17 CYM74P54(GND) CYM74P55 (A18)
16Kx64
16Kx64
16Kx64
16Kx64
74BP54-3
2
PRELIMINARY
Logic Block Diagram - CYM74SP54/CYM74SP55
CYM74BP54 CYM74P54/55 CYM74SP54/55
D0-D 15 DP0-DP 1 D16-D 31 DP2-DP 3 D32-D 47 DP4-DP 5 D48-D 63 DP6-DP 7
Note:A 18 isnotusedbyCYM74SP54
(CYM74SP54)32K x 18 (CYM74SP55)64Kx18 D A18-A 7 A6- -A 3- 0 0 ADSP0 ADSC0 ADV0 A ADSP ADSC ADV CE OE WE0/1 CLK0 CLK1 CE0 OE0 CE1 OE1 WE0-WE 7 A ADSP ADSC ADV CE OE WE2/3 D A6- -A 3- A 1 1 ADSP1 ADSP ADSC1 ADSC ADV1 ADV CE OE WE4/5 D A ADSP ADSC ADV CE OE WE6/7 D
74BP54-4
Selection Guide
Asynchronous Cache Modules Part Number Cache Size (KB) System Clock (MHz) RAM Speed 60 tAA=15 ns Synchronous Pipelined Cache Modules Part Number Cache Size (KB) System Clock (MHz) RAM Speed 60 tCDV=10.5 ns CYM74P54-60 256 66 tCDV=8.5 ns CYM74P54-66 CYM74P55-60 512 60 tCDV=10.5 ns 66 tCDV=8.5 ns CYM74P55-66 CYM74BP54-60 256 66 tAA=12 ns CYM74BP54-66
Synchornous Burst Cache Modules Part Number Cache Size (KB) System Clock (MHz) RAM Speed 60 tCDV=10.5 ns CYM74SP54-60 256 66 tCDV=8.5 ns CYM74SP54-66 CYM74SP55-60 512 60 tCDV=10.5 ns 66 tCDV=8.5 ns CYM74SP55-66
3
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Pin Configuration
Dual Read-Out SIMM (DIMM) Top View
GND D63 VCC D61 VCC D59 D57 GND (74P5X, 74SP5X) DP7 / (74BP54) NC D55 D53 D51 GND D49 D47 D45 D43 GND D41 (74P5X, 74SP5X) DP5 / (74BP54) NC D39 D37 D35 GND D33 D31 D29 D27 D25 GND (74P5X, 74SP5X) DP3 / (74BP54) NC D23 D21 VCC D19 GND D17 VCC D15 D13 GND D11 VCC D9 (74P5X, 74SP5X) DP1 / (74BP54) NC VCC D7 D5 D3 D1 GND A3- 1 A4- 1 (74P5X, 74SP5X) A5- / (74BP54) NC 1 (74P5X, 74SP5X) A6- / (74BP54) NC 1 A7 GND A9 A11 A13 A15 A17 GND (ReservedA 19) NC PD1 (74P5X, 74SP5X) CLK0 / (74BP54) NC (Reserved CLK2) NC GND WE7 WE5 WE3 WE1 GND (74P55, 74SP5X) ADSC1 / (74BP54, 74P54) NC CE1 (74P55, 74SP5X) ADV1 / (74BP54, 74P54) NC OE1 VCC (74P55, 74SP5X) ADSP1 / (74BP54, 74P54) NC GND 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
CYM74BP54 CYM74P54/55 CYM74SP54/55
GND D62 NC (74BP54) / VCCQ (74P5X, 74SP5X) D60 NC (74BP54) / VCCQ (74P5X, 74SP5X) D58 D56 GND NC (74BP54) / DP6 (74P5X, 74SP5X) D54 D52 D50 GND D48 D46 D44 D42 GND D40 NC (74BP54) / DP4 (74P5X, 74SP5X) D38 D36 D34 GND D32 D30 D28 D26 D24 GND NC (74BP54) / DP2 (74P5X, 74SP5X) D22 D20 NC (74BP54) / VCCQ (74P5X, 74SP5X) D18 GND D16 NC (74BP54) / VCCQ (74P5X, 74SP5X) D14 D12 GND D10 NC (74BP54) / VCCQ (74P5X, 74SP5X) D8 NC (74BP54) / DP0 (74P5X, 74SP5X) NC (74BP54) / VCCQ (74P5X, 74SP5X) D6 D4 D2 D0 GND A3- 0 A4- 0 A5- 0 A6- 0 A8 GND A10 A12 A14 A16 NC (74BP54, 74SP54) / GND (74P54) / A18 (74P55, 74SP55) GND PD0 PD2 NC (74BP54, 74P54) / CLK1 (74P55, 74SP5X) NC (Reserved CLK3) GND WE6 WE4 WE2 WE0 GND CALE (74BP54) / ADSC0 (74P5X, 74SP5X) CE0 NC (74BP54) / ADV0 (74P5X, 74SP5X) OE0 NC (74BP54) / VCCQ (74P5X, 74SP5X) NC (74BP54) / ADSP0 (74P5X, 74SP5X) 74BP54-5 GND
4
PRELIMINARY
Pin Definitions
Common Signals VCC GND A7-A19 A3-0, A4-0 A3-1, A4-1 A5-0, A6-0 CE0, CE1 OE0, OE1 WE0, WE1,WE2,WE3 WE4,WE5,WE6,WE7 PD0-PD2 D0-D63 NC CYM74BP54 Only Signals CALE CYM74P5X, CYM74SP5X Signals VCCQ DP0-DP7 ADSP0, ADSP1 ADSC0,ADSC1 ADV0, ADV1 A5-1, A6-1 CLK0, CLK1, CLK2, CLK3 3.3V Supply Data Parity lines (Optional) Processor Address Strobe, ADSP1 not used on CYM74P54 Latch Enable Description 5V Supply Ground Addresses from processor Description
CYM74BP54 CYM74P54/55 CYM74SP54/55
Lower address from chipset, identical to the bank1 addresses Lower address from chipset, identical to the bank0 addresses, A3-1, A4-1 not used on CYM74P54 Lower address from processor (CYM74P5X, CYM74SP5X- identical to the bank1 addresses) Chip Enable (same signal), CE1 not used on CYM74P54 Output Enable (same signal), OE1 not used on CYM74P54 Byte Write Enables Presence Detect pins Data lines from processor Signal not connected on module. Description
Cache Controller Address Strobe, ADSC1 not used on CYM74P54 Burst Address Advance, ADV1 not used on CYM74P54 Lower address from processor, identical to the bank0 addresses, A5-1, A6-1 not used on CYM74P54 Clock signals (each should be given own clk driver); CLK0 used on CYM74P5X, CYM74SP5X; CLK1 not used on CYM74P54; CLK2 and CLK3 are RSVD
Presence Detect Pins
PD2 Asynchronous - CYM74BP54 Synchronous Pipelined - CYM74P54 Synchronous Pipelined - CYM74P55 Synchronous Burst - CYM74SP54 Synchronous Burst - CYM74SP55 NC TBD TBD GND GND PD1 GND TBD TBD GND GND PD0 NC TBD TBD NC GND
5
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested. Storage Temperature ................................. -55C to +125C Ambient Temperature with Power Applied ......................................... -0C to +70C 3.3V Supply Voltage to Ground Potential..... -0.5V to +5.25V 5V Supply Voltage to Ground Potential........ -0.5V to +5.25V DC Voltage Applied to Outputs in High Z State ............................................... -0.5V to +4.6V DC Input Voltage............................................ -0.5V to +4.6V
CYM74BP54 CYM74P54/55 CYM74SP54/55
Output Current into Outputs (LOW)............................. 20 mA
Operating Range
Range Commercial (CYM74BP54) Commercial (CYM74P5X, CYM74SP5X) Ambient Temperature 0C to +70C 0C to +70C VCC 5V 5% 5V 5% VCCQ N/A 5V 5% 3.3V + 10% - 5%
Electrical Characteristics Over the Operating Range
Parameter VIH VIL VIL VOH VOL ICC (74BP54) ICC (74P54) ICC (74P55) ICC (74SP54) ICC (74SP55) Description Input HIGH Voltage Input LOW Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage VCC Operating Supply Current VCC Operating Supply Current VCC Operating Supply Current VCC Operating Supply Current VCC Operating Supply Current CYM74BP54 CYM74P5X, CYM74SP5X VCC=Min. IOH = -4 mA VCC=Min. IOL = 8 mA VCC=Max., IOUT=0 mA, f=fMAX=1/tRC VCC=Max., IOUT=0 mA, f=fMAX=1/tRC VCC=Max., IOUT=0 mA, f=fMAX=1/tRC VCC=Max., IOUT=0 mA, f=fMAX=1/tRC VCC=Max., IOUT=0 mA, f=fMAX=1/tRC Test Condition Min. 2.2 -0.5 -0.3 2.4 0.4 1700 TBD TBD 1100 1400 0.8 0.8 Max. Unit V V V V V mA mA mA mA mA
Ordering Information
Speed (MHz) 60 Ordering Code CYM74BP54PM-60 CYM74P54PM-60 CYM74P55PM-60 CYM74SP54PM-60 CYM74SP55PM-60 66 CYM74BP54PM-66 CYM74P54PM-66 CYM74P55PM-66 CYM74SP54PM-66 CYM74SP55PM-66 Document #: 38-M-00070-B Package Name PM36 TBD TBD PM26 PM26 PM36 TBD TBD PM26 PM26 Package Type 160-Pin Dual-Readout SIMM 160-Pin Dual-Readout SIMM 160-Pin Dual-Readout SIMM 160-Pin Dual-Readout SIMM 160-Pin Dual-Readout SIMM 160-Pin Dual-Readout SIMM 160-Pin Dual-Readout SIMM 160-Pin Dual-Readout SIMM 160-Pin Dual-Readout SIMM 160-Pin Dual-Readout SIMM Description Asynchronous 256KB Synch Pipelined 256KB Synch Pipelined 512KB Synch Burst 256KB Synch Burst 512KB Asynchronous 256KB Synch Pipelined 256KB Synch Pipelined 512KB Synch Burst 256KB Synch Burst 512KB Commercial Operating Range Commercial
6
PRELIMINARY
Package Diagrams
160-Pin Dual-Readout SIMM PM26
CYM74BP54 CYM74P54/55 CYM74SP54/55
160-Pin Dual Readout SIMM PM36
(c) Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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