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DA
C75
45
DAC
754
5
DAC7545
CMOS 12-Bit Multiplying DIGITAL-TO-ANALOG CONVERTER Microprocessor Compatible
FEATURES
q FOUR-QUADRANT MULTIPLICATION q LOW GAIN TC: 2ppm/C typ q MONOTONICITY GUARANTEED OVER TEMPERATURE q SINGLE 5V TO 15V SUPPLY q TTL/CMOS LOGIC COMPATIBLE q LOW OUTPUT LEAKAGE: 10nA max q LOW OUTPUT CAPACITANCE: 70pF max q DIRECT REPLACEMENT FOR AD7545, PM-7545
DESCRIPTION
The DAC7545 is a low-cost CMOS, 12-bit fourquadrant multiplying, digital-to-analog converter with input data latches. The input data is loaded into the DAC as a 12-bit data word. The data flows through to the DAC when both the chip select (CS) and the write (WR) pins are at a logic low. Laser-trimmed thin-film resistors and excellent CMOS voltage switches provide true 12-bit integral and differential linearity. The device operates on a single +5V to +15V supply and is available in 20-pin plastic DIP or 20-lead plastic SOIC packages. Devices are specified over the commercial. The DAC7545 is well suited for battery or other low power applications because the power dissipation is less than 0.5mW when used with CMOS logic inputs and VDD = +5V.
RFB 20
1 VREF 19 12-Bit Multiplying DAC 2
OUT 1 AGND
12 WR 17 CS 16 Input Data Latches 12 DB11-DB0 (Pins 4-15)
18 3
VDD DGND
International Airport Industrial Park * Mailing Address: PO Box 11400, Tucson, AZ 85734 * Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 * Tel: (520) 746-1111 * Twx: 910-952-1111 Internet: http://www.burr-brown.com/ * FAXLine: (800) 548-6133 (US/Canada Only) * Cable: BBRCORP * Telex: 066-6491 * FAX: (520) 889-1510 * Immediate Product Info: (800) 548-6132
(c)
1987 Burr-Brown Corporation
PDS-747F 1
Printed in U.S.A. DAC7545 August, 1997
SPECIFICATIONS
ELECTRICAL
VREF = +10V, VOUT 1 = 0V, ACOM = DCOM, unless otherwise specified. DAC7545 VDD = +5V PARAMETER STATIC PERFORMANCE Resolution Accuracy GRADE All J K L GL J K L GL J K L GL All TA = +25C 12 2 1 1/2 1/2 4 1 1 1 20 10 5 2 5 TMAX-TMIN(1) 12 2 1 1/2 1/2 4 1 1 1 20 10 6 3 5 VDD = +15V TA = +25C 12 2 1 1/2 1/2 4 1 1 1 25 15 10 6 10 TMAX-TMIN(1) 12 2 1 1/2 1/2 4 1 1 1 25 15 10 7 10 UNITS TEST CONDITIONS/COMMENTS Bits LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB
Differential Nonlinearity
Gain Error (with internal RFB)(2)
10-Bit Monotonic, TMIN to TMAX 10-Bit Monotonic, TMIN to TMAX 12-Bit Monotonic, TMIN to TMAX 12-Bit Monotonic, TMIN to TMAX D/A register loaded with FFFH. Gain error is adjustable using the circuits in Figures 2 and 3.
Gain Temperature Coefficient(3) (Gain/Temperature) DC Supply Rejection(3) (Gain/VDD) Output Leakage Current at Out 1 DYNAMIC PERFORMANCE Current Settling Time(3)
ppm/C Typical value is 2ppm/C for VDD = +5 %/% nA s VDD 5% DB0-DB11 = 0V; WR, CS = 0V To 1/2LSB. Out1 Load = 100 DAC output measured from falling edge of WR. CS = 0V
All J, K, L, GL All
0.015 10 2
0.03 50 2
0.01 10 2
0.02 50 2
Propagation Delay(3) (from digital input change to 90% of final analog output) Glitch Energy AC Feedback at IOUT 1 REFERENCE INPUT Input Resistance (pin 19 to AGND) AC OUTPUTS Output Capacitance(3): COUT 1 COUT 2 DIGITAL INPUTS VIH (Input HIGH Voltage) VIL (Input LOW Voltage) IIN (Input Current)(7) Input Capacitance(3): DB0-DB11 WR, CS SWITCHING CHARACTERISTICS(8) Chip Select to Write Setup Time, tCS Chip Select to Write Hold Time, tCH Write Pulse Width, tWR Data Setup Time, tDS Data Hold Time, tDH POWER SUPPLY, IDD
All All All All 300 400 5 7 25 70 200 2.4 0.8 1 5 20 280 200 0 250 175 140 100 10 2 100 10 250 250 5 7 25 70 200 13.5 1.5 1 5 20 180 120 0 160 100 90 60 10 2 100 10 ns Out1 Load = 100. CEXT = 13pF(4) nV-s(5) VREF = ACOM mVp-p(5) VREF = 10V, 10kHz Sine Wave k(6) k pF pF V(6) V A pF pF ns(6) ns(5) ns(6) ns(6) ns(5) ns(6) ns(5) ns(6) mA A A(5) Input resistance TC = 300ppm/C(5)
5 7 25 70 200 2.4 0.8 10 5 20 380 270 0 400 280 210 150 10 2 500 10
5 7 25 70 200 13.5 1.5 10 5 20 200 150 0 240 170 120 80 10 2 500 10
All All All All All All All All All All All All All All All
DB0-DB11 = 0V; WR, CS = 0V DB0-DB11 = VDD; WR, CS = 0V
VIN = 0 or VDD VIN = 0V VIN = 0V See Timing Diagram
tCS tWR, tCH 0
All Digital Inputs VIL or VIH All Digital Inputs 0V or VDD All Digital Inputs 0V or VDD
NOTES: (1) Temperature ranges--J, K, L, GL: -40C to +85C. (2) This includes the effect of 5ppm max, gain TC. (3) Guaranteed but not tested. (4) DB0-DB11 = 0V to VDD or VDD to 0V. (5) Typical. (6) Minimum. (7) Logic inputs are MOS gates. Typical input current (+25C) is less than 1nA. (8) Sample tested at +25C to ensure compliance.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
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ABSOLUTE MAXIMUM RATINGS(1)
TA = +25C, unless otherwise noted. VDD to DGND ........................................................................... -0.3V, +17 Digital Input to DGND ............................................................... -0.3V, VDD VRFB, VREF, to DGND ........................................................................ 25V VPIN 1 to DGND ......................................................................... -0.3V, VDD AGND to DGND ........................................................................ -0.3V, VDD Power Dissipation: Any Package to +75C .................................... 450mW Derates above +75C by ................................ 6mW/C Operating Temperature: Commercial J, K, L, GL .................................................. -40C to +85C Storage Temperature ...................................................... -65C to +150C Lead Temperature (soldering, 10s) ................................................ +300C NOTE: (1) Stresses above those listed above may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
PIN CONNECTIONS
Top View DIP/SOIC
OUT 1 AGND DGND (MSB) DB11 DB10 DB9 DB8 DB7 DB6
1 2 3 4 5 6 7 8 9 DAC7545
20 RFB 19 VREF 18 VDD 17 WR 16 CS 15 DB0 (LSB) 14 DB1 13 DB2 12 DB3 11 DB4
DB5 10
ELECTROSTATIC DISCHARGE SENSITIVITY
Any integral circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. ORDERING INFORMATION
PRODUCT DAC7545JP DAC7545KP DAC7545LP DAC7545GLP DAC7545JU DAC7545KU DAC7545LU DAC7545GLU PACKAGE Plastic DIP Plastic DIP Plastic DIP Plastic DIP Plastic SOIC Plastic SOIC Plastic SOIC Plastic SOIC TEMPERATURE RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
PACKAGE INFORMATION
PRODUCT DAC7545JP DAC7545KP DAC7545LP DAC7545GLP DAC7545JU DAC7545KU DAC7545LU DAC7545GLU PACKAGE 20-Pin PDIP 20-Pin PDIP 20-Pin PDIP 20-Pin PDIP 20-Pin SOIC 20-Pin SOIC 20-Pin SOIC 20-Pin SOIC PACKAGE DRAWING NUMBER(1) 222 222 222 222 221 221 221 221
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.
RELATIVE ACCURACY (LSB) 2 1 1/2 1/2 2 1 1/2 1/2
GAIN ERROR (LSB) VDD = +5V 20 10 5 2 20 10 5 2
3
DAC7545
WRITE CYCLE TIMING DIAGRAM
CS tCS tCH VDD 0 WR tWR VDD tDH 0 VDD 0
Write Mode CS and WR low, DAC responds to Data Bus (DB0-DB11) inputs. Mode Selection Hold Mode Either CS or WR high, data bus (DB0-DB11) is locked out; DAC holds last data present when WR or CS assumed high state.
tDS Data In (DB0-DB11)
VIH VIL
Data Valid
NOTES: VDD = +5V, tR = tF = 20ns. VDD = +15V, tR = tF = 40ns. All inputs signal rise and fall times measured from 10% to 90% of VDD. Timing measurement reference level is (VIH + VIL)/2.
23
22
PAD 1 2 3 4 5 6 7 8 9 10 11 12
FUNCTION OUT 1 AGND AGND DGND DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
PAD 13 14 15 16 17 18 19 20 21 22 23
FUNCTION DB3 DB2 DB1 (LSB) DB0 CS WR XYR VDD VREF RFB OUT1
Substrate Bias: Isolated. NC: No Connection
MECHANICAL INFORMATION
MILS (0.001") Die Size Die Thickness Min. Pad Size 136 x 134 5 20 3 4x4 MILLIMETERS 3.45 x 3.40 0.13 0.51 0.08 0.10 x 0.10 Aluminum
DAC7545 DIE TOPOGRAPHY
Metalization
DISCUSSION OF SPECIFICATIONS
Relative Accuracy This term (also known as end point linearity) describes the transfer function of analog output to digital input code. Relative accuracy describes the deviation from a straight line after zero and full scale have been adjusted. Differential Nonlinearity Differential nonlinearity is the deviation from an ideal 1LSB change in the output, for adjacent input code changes. A differential nonlinearity specification of 1LSB guarantees monotonicity. Gain Error Gain error is the difference in measure of full-scale output versus the ideal DAC output. The ideal output for the DAC7545 is -(4095/4096)(VREF). Gain error may be adjusted to zero using external trims as shown in the applications section. Output Leakage Current The current which appears at OUT 1 with the DAC loaded with all zeros. Multiplying Feedthrough Error The AC output error due to capacitive feedthrough from VREF to OUT 1 with the DAC loaded with all zeros. This test is performed using a 10kHz sine wave. Output Current Settling Time The time required for the output to settle within 0.5LSB of final value from a change in code of all zeros to all ones, or all ones to all zeros.
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Propagation Delay The delay of the internal circuitry is measured as the time from a digital code change to the point at which the output reaches 90% of final value. Digital-to-Analog Glitch Impulse The area of the glitch energy measured in nanovolt-seconds. Key contributions to glitch energy are internal circuitry timing differences and charge injected from digital logic. The measurement is performed with VREF = GND and an OPA600 as the output op amp and G1 (phase compensation) = 0pF. Monotonicity Monotonicity assures that the analog output will increase or stay the same for increasing digital input codes. The DAC7545 is guaranteed monotonic to 12 bits, except the J grade is specified to be 10-bit monotonic. Power Supply Rejection Power supply rejection is the measure of the sensitivity of the output (full scale) to a change in the power supply voltage.
current than normal. Minimizing this transition time through the linear region and insuring that the digital inputs are operated as close to the rails as possible will minimize the supply drain current.
APPLICATIONS
UNIPOLAR OPERATION Figure 2 shows the DAC7545 connected for unipolar operation. The high-grade DAC7545 is specified for a 1LSB gain error, so gain adjust is typically not needed. However, the resistors shown are for adjusting full-scale errors. The value of R1 should be minimized to reduce the effects of mismatching temperature coefficients between the internal and external resistors. A range of adjustment of 1.5 times the desired range will be adequate. For example, for a DAC7545JP, the gain error is specified to be 25LSB. A range of adjustment of 37LSB will be adequate. The equation below results in a value of 458 for the potentiometer (use 500). R1 = RLADDER (3 x Gain Error) 4096
CIRCUIT DESCRIPTION
Figure 1 shows a simplified schematic of the digital-toanalog converter portion of the DAC7545. The current from the VREF pin is switched from OUT 1 to AGND by the FET switch. This circuit architecture keeps the resistance at the reference pin constant and equal to RLDR, so the reference could be provided by either a voltage or current, AC or DC, positive or negative polarity, and have a voltage range up to 20V even with VDD = 5V. The RLDR is equal to "R" and is typically 11k.
VREF R R R R
The addition of R1 will cause a negative gain error. To compensate for this error, R2 must be added. The value of R2 should be one-third the value of R1. The capacitor across the feedback resistor is used to compensate for the phase shift due to stray capacitances of the circuit board, the DAC output capacitance, and op amp input capacitance. Eliminating this capacitor will result in excessive ringing and an increase in glitch energy. This capacitor should be as small as possible to minimize settling time. The circuit of Figure 2 may be used with input voltages up to 20V as long as the output amplifier is biased to handle the excursions. Table I represents the analog output for four codes into the DAC for Figure 2.
+5V R2 C1 33pF OUT 1 AGND DGND VOUT OPA604
2R
2R
2R
2R
2R
RFB
VIN VDD VREF R1 RFB
OUT 1
DAC7545
AGND DB11 (MSB) DB10 DB9 DB0 (LSB)
DB0-DB11
FIGURE 1. Simplified DAC Circuit of the DAC7545. The output capacitance of the DAC7545 is code dependent and varies from a minimum value (70pF) at code 000H to a maximum (200pF) at code FFFH. The input buffers are CMOS inverters, designed so that when the DAC7545 is operated from a 5V supply (VDD), the logic threshold is TTL-compatible. Being simple CMOS inverters, there is a range of operation where the inverters operate in the linear region and thus draw more supply 5
FIGURE 2. Unipolar Binary Operation.
BINARY CODE MSB LSB 1111 1111 1111 1000 0000 0000 0000 0000 0001 0000 0000 0000 ANALOG OUTPUT -VIN (4095/4096) -VIN (2048/4096) = -1/2VIN -VIN (1/4096) 0V
TABLE I. Unipolar Codes.
DAC7545
R2 +5V 18 VIN R1 VDD 19 VREF DB11 4 11 U1 (See Text) Analog Common 12 Data Input 20 RFB OUT 1 DAC7545 DB10-DB0 AGND 2 C1 33pF 1 OPA604 or 1/2 OPA2604 R3 10k R6 5k 10%
R4 20k
R5 20k VOUT OPA604 or 1/2 OPA2604
FIGURE 3. Bipolar Operation (Two's Complement Code). BIPOLAR OPERATION Figure 3 and Table II illustrate the recommended circuit and code relationship for bipolar operation. The D/A function itself uses offset binary code. The inverter, U1, on the MSB line converts two's complement input code to offset binary code. If the inversion is done in software, U1 may be omitted. R3, R4, and R5 must match within 0.01% and should be the same type of resistors (preferably wire-wound or metal foil), so that their temperature coefficients match. Mismatch of R3 value to R4 causes both offset and full-scale error. Mismatch of R5 to R4 and R3 causes full-scale error.
DATA INPUT MSB LSB 0111 1111 1111 0000 0000 0001 0000 0000 0000 1111 1111 1111 1000 0000 0000 ANALOG OUTPUT +VIN (2047/2048) +VIN (1/2048) 0V -VIN (1/2048) -VIN (2048/2048)
VOUT +5V VOUT = -VIN DB11 2 + DB10 4 + DB9 8 + *** + DB0 4096 VIN RFB 17 18 19 DAC7545 DGND NOTE: There must be at least 1LSB loaded in the DAC or the amp will saturate due to the lack of feedback. OPA111 16 20 OUT 1 AGND
DB0-DB11 WR CS
TABLE II. Two's Complement Code Table for Circuit of Figure 3. DIGITALLY CONTROLLED GAIN BLOCK Figure 4 shows a circuit for digitally controlled gain block. The feedback for the op amp is made up of the FET switch and the R-2R ladder. The input resistor to the gain block is the RFB of the DAC7545. Since the FET switch is in the feedback loop, a "zero code" into the DAC will result in the op amp having no feedback, and a saturated op amp output.
FIGURE 4. Digitally Controlled Gain Block. connected to an external op amp with its noninverting input connected to AGND. The op amp selected should have a low input bias current and low VOS and VOS drift over temperature. The op amp offset voltage should be less than (25 x 10-6)(VREF) over operating conditions. Suitable op amps are the Burr-Brown OPA37 and the OPA627 for fixed reference applications and low bandwidth requirement. The OPA37 has low VOS and will not require an offset trim. For wide bandwidth, high slew rate, or fast settling applications, the Burr-Brown OPA604 or 1/2 OPA2604 are recommended. Unused digital inputs should be connected to VDD or to DGND. This prevents noise form triggering the high impedance digital input. It is suggested that the unused digital inputs also be given a path to ground or VDD through a 1M resistor to prevent the accumulation of static charge if the PC card is unplugged from the system. In addition, in systems where the AGND to DGND connection is on a backplane, it is recommended that two diodes be connected in inverse parallel between AGND and DGND.
APPLICATIONS HINTS
CMOS DACs, such as the DAC7545, exhibit a code-dependent out resistance. The effect of this is a code-dependent differential nonlinearity at the amplifier output which depends on the offset voltage, VOS, of the amplifier. Thus linearity depends upon the potential of OUT 1 and AGND being exactly equal to each other. Usually the DAC is
DAC7545
6
INTERFACING TO MICROPROCESSORS
The DAC7545 can be directly interfaced to either an 8- or 16-bit microprocessor through its 12-bit wide data latch using the CS and WR controls. An 8-bit processor interface is shown in Figure 5. It uses two memory addresses, one for the lower 8 bits and one for the upper 4 bits of data into the DAC via the latch.
A15 A0 Address Decode CPU Q0(1) Q1(2)
Address Bus
CS CS 4 Latch 4 WR DB11 DB8 DAC7545 WR 8 DB7 DB0
WR
DB7 DB0
8-Bit Data Bus NOTES: (1) Q0 = Decoded Address for DAC. (2) Q1 = Decoded Address for Latch.
FIGURE 5. 8-Bit Processor Interface.
7
DAC7545

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