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NE57814 DDR memory termination regulator with standby mode and enhanced efficiency
Product data Supersedes data of 2003 Jan 22 2003 Apr 03
Philips Semiconductors
Philips Semiconductors
Product data
DDR memory termination regulator with standby mode and enhanced efficiency
NE57814
DESCRIPTION
The NE57814 is designed to provide power for termination of a DDR memory bus. It significantly reduces parts count, board space, and overall system cost over previous switching solutions. The NE57814 has an independent power source pin (VD) for further reducing the operational power and a standby low-power mode for energy-sensitive portable applications. The DDR terminator regulator provides a very accurate reference (RefOut) and termination voltage (VTT) which is one-half of the RAM supply voltage over wide range of current demand.
HSO8 (TOP)
HSO8 (BOTTOM)
FEATURES
* Fast transient response time * Over-temperature protection * Over-current protection * Commercial (0 C to 70 C) temperature range * High bandwidth drivers minimize requirement for output hold-up
filter capacitors
APPLICATIONS
* Internal divider maintains termination voltage at 1/2 memory
supply voltage
* RefOut output pin for other memory and control components
* Laptop computers * Desktop microcomputer systems * Workstations * Set-top boxes * Servers * Networking routers and switches * Video display systems * Personal video recorders * Game machines * Embedded systems
SIMPLIFIED SYSTEM DIAGRAM
DIMM0 DIMM1
RefOut 0.1 F
VD
VDD
Control & Address VTT SENSE MEMORY CONTROLLER STANDBY (OPTIONAL)
NE57814
Data VTT 100 F RS 20 (typical) RT 27 (typical) TERMINATION POWER
ExtRefIn (OPTIONAL)
SL01877
Figure 1. Simplified system diagram.
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Philips Semiconductors
Product data
DDR memory termination regulator with standby mode and enhanced efficiency
NE57814
ORDERING INFORMATION
PACKAGE TYPE NUMBER NAME NE57814DD HSO8 DESCRIPTION plastic thermal enhanced small outline package; 8 leads; body width 3.9 mm; exposed die pad VERSION SOT786-2 TEMPERATURE RANGE 0 C to +70 C
PIN CONFIGURATION
PIN DESCRIPTION
PIN 1 SYMBOL VSS VTT SENSE VTT VD VDD ExtRefIn STANDBY RefOut DESCRIPTION Terminator ground VTT remote sense. Connect to pin 3 (VTT) Terminator voltage output VTT output MOSFET drain DDRAM supply voltage Reference node used for external control of VTT Places device into standby mode (active-LOW) Buffered VTT reference output, used for cascading terminators
VSS 1 VTT SENSE VTT VD 2 3 4
8 7 6 5
RefOut STANDBY ExtRefIn VDD
2 3 4 5
SL01878
6 Figure 2. Pin configuration. 7 8
NOTE: 1. The thermal heatspreader connects electrically to VSS internally and provides enhancement to thermal conductivity, but it should not be used as the primary connection to ground. Device specifications apply to use of the VSS pin as the connection to ground.
MAXIMUM RATINGS
SYMBOL VDD Tamb Tstg Tj Rth(j-a) P VDD to VSS voltage Operating ambient temperature Storage temperature Junction temperature Thermal resistance, junction to ambient (Note 1) Power dissipation (Note 1) PARAMETER MIN. -0.3 0 -40 - - - TYP. - - - - 38.5 - MAX. +3.6 +70 +165 160 - 2.1 UNIT V C C C C/W W
NOTE: 1. Tested on a minimum footprint on a four-layer PCB per JEDEC specification JESD51-7.
2003 Apr 03
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Philips Semiconductors
Product data
DDR memory termination regulator with standby mode and enhanced efficiency
NE57814
ELECTRICAL CHARACTERISTICS
Tamb = 0 C to +70 C; VDD = 2.5 V; VD = 2.5 V, unless otherwise specified. SYMBOL VTT PARAMETER Output voltage Output voltage accuracy error VDD VD IQ(OP) ITT Supply voltage Supply voltage on pin VD Operating supply current Output current (Note 5) ITT = 0 A VD = VDD = 2.5 V to 3.6 V VD = VDD = 1.6 V IQ(SD) VTT Standby quiescent current Load regulation Standby asserted ITT = 1.0 A ITT = 3.5 A CLOAD Min. load capacitance (Note 2) Stable operation CONDITIONS ExtRefIn not connected VTT - VDD/2; ITT = 0 A MIN. - -15 1.6 1.6 - -3.5 -2.5 - - -18 50 TYP. VDD/2 - - - 14 - - 1.2 6 - 100 MAX. - +15 3.6 3.6 30 +3.5 +2.5 1.35 - +18 - UNIT V mV V V mA A A mA mV mV F
External Reference In VExtRefIn Rin VExtRefIn-VTT ExtRefIn voltage range ExtRefIn input impedance Output voltage accuracy Line regulation Reference Out VERRREF IRefOut CLOAD Power Stage Ilim Rds(on) Tlim Current limit Source transistor on-resistance Temperature shutdown Temperature shutdown hysteresis 3.6 - - - 4.5 0.18 +150 20 6.5 0.32 - - A C C Voltage reference out (Note 4) accuracy error, VExtRefIn - VRefOut Reference Out current limit Load capacitance IRefOut = 0 A source or sink Stable operation -15 2.2 0.1 - 3 - +15 - - mV mA F ITT = 0 A VExtRefIn = 1.25 V; VDD = 2.25 V to 3.6 V 0.8 35 -15 -6 - 50 - - VDD - 0.8 - +15 +6 V k mV mV
NOTE: 1. Limits are 100% production tested at 25 C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. 2. Ceramic capacitors. Low ESR Electrolytic capacitors are not required for stability, but may be needed for the application. 3. Voltage Accuracy referred to voltage at the center node of the Vref resistor divider. 4. RefOut voltage referenced to 1/2 VDD. 5. See Figure 15 for the Safe Operating Area versus Temperature.
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Philips Semiconductors
Product data
DDR memory termination regulator with standby mode and enhanced efficiency
NE57814
TYPICAL PERFORMANCE CURVES
SL01687
SL01688
Figure 3. VTT transient response (output filter 50 F ceramic)
Figure 4. VDD-to-VTT response (output filter 50 F ceramic)
SL01686
SL01685
Figure 5. Vref-to-VTT transient response (output filter 820 F + 50 F ceramic)
Figure 6. Vref-to-VTT transient response (output filter 50 F ceramic)
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Philips Semiconductors
Product data
DDR memory termination regulator with standby mode and enhanced efficiency
NE57814
1.300
1.290 NORMAL OPERATING REGION 1.280
1.270
1.260
1.250 Volts 1.240 1.230 OUTPUT SINK 1.220 OUTPUT SOURCE 1.210 1.200 -6 -5 -4 -3 -2 -1 0 Amps 1 2 3 4 5 6
SL01684
Figure 7. Output regulation.
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Philips Semiconductors
Product data
DDR memory termination regulator with standby mode and enhanced efficiency
NE57814
TECHNICAL DISCUSSION
The NE57814 supplies power to the DDR memory bus termination resistors at one-half the voltage supplied to the memory ICs or DIMMs. The DDR memory bus can only have one output drive any one bus line at any one time. So the load on the DDR termination system is a matter of the number of bus lines being terminated and the termination resistor values. The memory size (that is the MB) of memory space is not relevant. A typical DDR memory system is seen in Figure 8. Each bus input/output pin on the bus has a series 20 resistor connected to it. The bus is terminated to the DDR terminator though a 27 to 50 resistance. The memory system will then require current from the terminator output only when the instantaneous value of the aggregate bus does not correspond to equal amounts of 1s and 0s. When memory bus speeds are in the 200-300 MHz region, the period of any single bus state is extremely small. This creates two bus loading conditions: the high frequency condition which is caused by the instantaneous numbers of 1s and 0s, and the low frequency condition caused by mainly the address bus being oriented towards the top or bottom of the memory space. This creates two relatively independent output-filtering situations for the DDR terminator: the high frequency bus speed, and the low-frequency address skew of the processor system. Each should be examined separately.
VDD 5 VD 4 VTT RT 100 k OVERCURRENT CONTROL RT RS VTT
Figure 9 models the VTT loading condition of each bus line equivalent circuit during operation and with terminating resistors. This yields the worst case current loading equation:
I O(max) +
Where:
N DDR V DD 2(R T ) R S)
NDDR is the total number of terminated control, address and data lines within the DDR memory system (typically 192). RT is the value of the terminating resistors. RS is the value of the series resistors from the active output driver. Hence the worst-case current loading condition for the typical DDR memory is 194 terminated bus lines, and there are either all 1s or all 0s for an instant. If the terminator resistances are RT = 27 and RS = 20 , then this results in a momentary instantaneous output current of either + or - 3.3 Amperes.
VD
VD
VDD
OVERTEMP CONTROL
RS
ExtRefIn
6 3 VTT VSS VSS VSS
VTT SENSE 2
A. "1" DATA
100 k 8 STANDBY 7 POWER MANAGER RefOut
B. "0" DATA
SL01880
Figure 9. The model for a single bus line for the DDR system.
1 VSS
SL01879
Figure 8. Functional diagram.
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Philips Semiconductors
Product data
DDR memory termination regulator with standby mode and enhanced efficiency
NE57814
APPLICATION INFORMATION
The NE57814 is intended for DDR memory termination systems which require small space, low cost, high output transient current dynamic range, and higher efficiency than the traditional linear DDR terminator. The increased efficiency is gained by being able to draw its output current from a lower voltage than the DDR RAM VDD voltage. As much as a 40 percent in the overall efficiency can be gained by operating the output stage from a voltage source of 0.25 V above the output VTT voltage. This gives it a distinct benefit in portable applications. The standby mode turns OFF the VTT amplifier and 3-states the VTT output. The RefOut pin is still active for use elsewhere within the system. an equal number of 1s and 0s. All electrolytic and tantalum capacitors appear inductive at the high frequencies. Therefore two types of capacitors are needed for the output filtering. For a 256 MB memory space, for example, approximately 100 F of ceramic surface mount ceramic capacitors should be evenly distributed across the physical memory layout. Depending upon the PCB noise environment, this could be 10 pieces of 10 F, 20 pieces of 5 F, and so on. These are the high frequency filter, represented by Cout (HF) in the illustrations. One half of the high frequency filter capacitors should be connected to VDD and the other half to VSS so that the output will better track any variations in the VDD voltage. Filtering the lower frequencies of the DDR load usually requires larger, low-ESR capacitors such as tantalum or low-ESR electrolytic capacitors, shown as Cout (LF) in the illustrations. This is where the NE57814 excels. Because of its fast input and output transient responses, very small or no additional large capacitors are needed. Worst-case system analysis has shown that an additional 110 F of capacitance is needed for each microsecond lag in the response time of the DDR regulator. The NE57814 responds in within one microsecond, so this requirement can be filled by the 100 F of ceramic capacitors already on the output. Additional studies have shown that other regulators, which cannot directly source the maximum instantaneous current demanded from the termination system, must have an additional 75 F of capacitance for each ampere of insufficient output drive. Together, the fast output response and peak drive current capabilities make the NE57814 the ideal choice for DDR termination.
Using the STANDBY signal
The NE57814 provides a STANDBY pin that can be used to put the device into low-power mode. When STANDBY is asserted (LOW), the VTT power amplifier is turned off and the VTT output is 3-stated. This brings the quiescent current of the entire device to less than 800 A. The internal reference divider (ExtRefIn pin) and the reference amplifier will remain active, allowing those circuits requiring a reference during the STANDBY state to remain active. If STANDBY is not externally connected, an internal 10 k resistor biases the control logic to VDD causing the output sections to be turned on and the NE57814 operates normally.
Output filtering
There are two components to the memory signal load: a high frequency component caused by the 266 MHz plus speed of the address, data, and control buses, and a low frequency component caused by the time-average skew of all of the bus states away from
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Philips Semiconductors
Product data
DDR memory termination regulator with standby mode and enhanced efficiency
NE57814
High efficiency operating mode
The NE57814 is designed for portable applications such as laptop computers and other battery operated computer systems requiring DDR memory. The standby mode 3-states the VTT output and unpowers most of the NE57814, which is very desirable for portable applications. The RefOut pin is still active for use elsewhere within the system. The VD pin on the NE57814 allows the DDR termination system to operate with reduced output power dissipation. The VD voltage can be lowered to approximately +0.25 volts above the VTT output voltage. The high-efficiency method draws its VTT current, not from the memory VDD line but from a lower voltage, VD. This will decrease the loss within the terminator when it sources current to the VTT line. The VD voltage required depends on the load current sourced and is given by VD(min) = VTT + 0.3(ITT(source)). ITT is expressed in amps. The VDD voltage is still used to set the Vref voltage to the memory devices.
As much as a 65 percent overall efficiency can be gained by operating the output stage from a voltage source of 0.25 V above the output VTT voltage during the sourcing condition. This gives it a distinct benefit in portable applications. The efficiency of the DDR terminator during the sourcing and sinking states of the NE57814 can be determined by the following calculations: Sourcing:
Efficiency(sourcing) +
(V TT) (I TT) (I Q) (V DD) ) (V D * V TT) (I TT)
100
This can be between 81 and 82.5 percent when the NE57814 is sourcing current. Sinking:
Efficiency(sinking) +
(V TT) (I TT) (I Q) (V DD) ) (V TT) (I TT)
100
This is approximately 49.5 percent.
INPUT VOLTAGE ( > VTT + 0.25 V )
470 F (Electro)
4 VD RefOut 8 0.1 F (Y5V) Vref
VDD VOLTAGE 10 F (Y5V) 0.1 F (Y5V)
5 VDD
NE57814
VTT SENSE 2 3 50 F (Y5V) VTT
6 0.1 F (Y5V)
ExtRefIn VSS 1
VTT
SL01884
Figure 10. High efficiency operation.
Less than +0.25 V between VD and VTT
TERMINATION CURRENT (A), I TT
A voltage difference between VD and VTT of less than +0.25 V reduces the maximum sourcing current capability of the VTT power amplifier. This reduction in output sourcing current capability can many times be compensated for within the termination system by adding additional low ESR electrolytic capacitors on the VTT output. The typical performance of the NE57814 as the VD voltage approaches VTT voltage (decreasing headroom voltage) can be seen in Figure 11.
2.5
2.0
1.5
1.0
0.5
0 0 50 100 150 200 250
HEADROOM VOLTAGE (mV)
SL01885
Figure 11. Typical output source current versus VD (at 25 C).
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Philips Semiconductors
Product data
DDR memory termination regulator with standby mode and enhanced efficiency
NE57814
Single-supply operating mode (VDD supply only)
For single-supply operation, connect the VD pin to the VDD pin. This is suitable for use in a desktop computer or other non efficiency-sensitive application (see Figure 12).
Externally setting VTT
The NE57814 allows use of an external reference voltage applied to the ExtRefIn pin to set the VTT output voltage. This pin is used for applications where the VTT voltage is not equal to VDD divided by 2. The needed VTT voltage and current may be drawn from a power supply bus that is not the DDR RAM supply voltage. This may have some advantages when the system designer is attempting to better match the power being drawn from the outputs emerging from main system power supply.
The internal reference voltage is set by two matched 100 k resistors connected in a resistor divider between the VDD and Vss pins of the NE57814. Setting the value of Vref or VTT can be done in two ways: by using an external resistor divider whose resistor values are less than 5 k each or by connecting the output of an operational amplifier which is outputting the reference voltage to the ExtRefIn pin. If the external resistor divider is used, place a 0.01 F ceramic bypass capacitor between the ExtRefIn pin (pin 6) and the VSS pin (pin 1). The accuracy of the new reference voltage when the external resistor divider is used will be about 0.5 percent PLUS the sum of the tolerances of the resistors used in the divider. Please note that when the NE57814 is operating in this fashion, the power dissipation of the part may increase.
470 F (Electro)
4 VD RefOut 8 0.1 F (Y5V) 5 VDD
NE57814
VTT SENSE 2 3 50 F (Y5V) 100 F (Electro)
10 F (Y5V)
0.1 F (Y5V) 6 0.1 F (Y5V) ExtRefIn VSS 1
VTT
SL01886
Figure 12. Single-supply operation.
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Philips Semiconductors
Product data
DDR memory termination regulator with standby mode and enhanced efficiency
NE57814
Cascading the NE57814 for complex memory systems
For high-performance computer systems, such as workstations and servers, where two or more banks of independent memory arrays are needed, the NE57814 can be cascaded to provide two independent, but slaved termination systems. This type of architecture allows the termination voltages to be within 12 mV of one another, and the VTT can be controlled from a single node. Cascading NE57814 terminators offers two advantages; memory SIMMs can be brought closer to the terminator, which improves the
system noise, and it will better distribute any heat generated by the terminator system. Use the RefOut pin from one NE57814 to the ExtRefIn pin for the other NE57814(s) in the system to ensure that the VTT voltages are identical. The output of the NE57814 is a very low impedance voltage source which means that the VTT outputs should never be wired together. That is, NE57814s should never be wired in parallel. This is because the terminators would "fight" one another if their output were different by only a few millivolts. The cascading method can be seen in Figure 13.
INPUT VOLTAGE ( > VTT + 0.25 V )
470 F (Electro)
VD RefOut 0.1 F (Y5V) VDD Vref
NE57814
VTT SENSE
10 F (Y5V)
0.1 F (Y5V) ExtRefIn 0.1 F (Y5V) VSS
VTT 50 F (Y5V)
VTT 100 F (Electro)
INPUT VOLTAGE ( > VTT + 0.25 V )
VD
ExtRefIn RefOut 0.1 F (Y5V)
VDD
NE57814
VTT SENSE VTT VSS 50 F (Y5V)
SL01887
Figure 13. Cascading terminator systems for complex memory systems.
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Philips Semiconductors
Product data
DDR memory termination regulator with standby mode and enhanced efficiency
NE57814
THERMAL DESIGN
Designing the thermal system for the NE57814 is important for its reliable operation. The NE57814 will be operating at an average power level less than the maximum rating of the part. In a typical DDR terminator system the average power dissipation is between 0.8 and 1.5 watts. It is important to make sure that this average power dissipation is less than the power capability of the package. The terminator heatsink must be designed to accommodate the average power as a steady state condition and be able to withstand momentary periods of increased dissipation, say from 1-2 seconds. For the single-supply application, the power dissipated by the terminator can be calculated: After the power is estimated, the minimum PCB area can be determined by calculating the worst-case thermal resistance and referring to Figure 8 to determine the PCB area. This is done by:
R th(j-a)(min) +
Where:
T j * T amb P
Eqn. (2)
Tj is the maximum desired junction temperature. Tamb is the highest expected local ambient temperature. P is the estimated average power The junction temperature should be kept below the over-temperature cutoff threshold temperature (+140 C ) in normal operation. Using the power dissipation formula above, the highest ambient temperature, 1.5 watts power dissipation (used only as an example) and a junction temperature of +125 C, calculate the maximum thermal resistance as follows:
O O R th(j-a)(min) + 140 C * 70 C + 47 O C W 1.5W
P D + I DD
V TT Watts
Eqn. (1)
The thermal resistance of a surface mount package is given as Rth(j-a) (thermal resistance from the junction to air). JESD51-7 specifies a 4-layer PCB (2oz/1oz/1oz/2oz copper) that is 4 inches on each side. This is probably the best (or lowest thermal resistance) one will see in any application. Most applications cannot afford the PCB area to create this situation, but the thermal performance of a multi-layer PCB will still provide a significant heat sinking effect. The actual thermal resistance will be higher than the 38.5 C/W given for the 4-layer JEDEC PCB. Figure 14 shows what thermal resistance one can expect for heat sinking PCB areas less than the JEDEC specification. The resistance can be decreased by using a double-sided PCB with some plated through holes (vias) to help transfer the heat to the bottom side. The thermal resistance decreases by about 3-4 C/W for a double-sided board with vias.
60 55 50
Eqn. (3)
Looking at Figure 15, a minimum PCB island area of 225 mm2 (15 mm length and width) is required at this power dissipation. Of course, increasing this area will allow the NE57814 to operate at cooler temperatures, enhancing the long-term reliability and allowing the terminator to better handle any transient output current demands.
10
THERMAL RESISTANCE ( C/W)
0.5 s I DD (A) 45 40 35 30 25 0 20 40 60 80 100 0.1 1 2 3 VDD (V) 4 5 6 7 8 9 10 1 DC
LENGTH OF SIDE OF 2 oz. COPPER AREA (mm)
SL01888
SL01873
Figure 14. Thermal resistance versus PCB area.
Figure 15. Safe operating area of the NE57814.
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Philips Semiconductors
Product data
DDR memory termination regulator with standby mode and enhanced efficiency
NE57814
PACKING METHOD
The NE57814 is packed in reels, as shown in Figure 16.
GUARD BAND
TAPE REEL ASSEMBLY
TAPE DETAIL
COVER TAPE
CARRIER TAPE
BARCODE LABEL
BOX
SL01305
Figure 16. Tape and reel packing method.
2003 Apr 03
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Philips Semiconductors
Product data
DDR memory termination regulator with standby mode and enhanced efficiency
NE57814
HSO8: plastic thermal enhnaced small outline package; 8 leads; body width 3.9 mm; exposed die pad
SOT786-2
2003 Apr 03
14
Philips Semiconductors
Product data
DDR memory termination regulator with standby mode and enhanced efficiency
NE57814
REVISION HISTORY
Rev _3 Date 20030403 Description Product data (9397 750 11217); ECN 853-2399 29610 of 03 March 2003; supersedes data of 2003 Jan 22 (9397 750 10984).
* Description on page 2, second paragraph: delete second sentence. * Electrical Characteristics table on page 4:
- Symbol IQ(OP): change Typ. value from 20 mA to 14 mA. - Symbol IQ(SD): change Typ. value from (-) to 1.2 mA. - Add new Note 1, and renumber following notes and their references. _2 _1 20030122 20021107 Product data (9397 750 10984); ECN 853-2399 29323 dated 2002 Dec 19; supersedes Objective data of 2002 Nov 07 (9397 750 10618). Objective data; initial version (9397 750 10618).
Modifications:
2003 Apr 03
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Philips Semiconductors
Product data
DDR memory termination regulator with standby mode and enhanced efficiency
NE57814
Data sheet status
Level
I
Data sheet status [1]
Objective data
Product status [2] [3]
Development
Definitions
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data
Qualification
III
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2003 All rights reserved. Printed in U.S.A. Date of release: 04-03
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 11217
Philips Semiconductors
2003 Apr 03 16

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