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CCD
CCDIC NN12067A
NN12067AIC( CCD)CCD(CDSGCAA/D ) CCD
* GCA-2dB 34dB * 5dB * * * * 171SUB * SSG * :36MHz * :fck/2fck * TG: * LLGA
MLGA107-L2-0909
CCD()
MN39720 MN39750 MN39830
NN12067A V
MN103SA10EYD
SDRAM 256M
CCD

RGB
2005725 M00696AC
Block Diagram
OV2 VM VM VHH VH VH VMSUB OV5C OV1B OV5L OV3B OV5A OV6 OV1S OV3L OSUB OV1A OV1C OV3A OV3C OV5B OV4 OV3R OV5R
74 96
93 73 72 94 71 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 95 CCD Vertical Driver 70
VL VL
RESET
AN20110
SUB, SUBCNT
V1 to V6, V1S, V3L, V3R, V5L, V5R
CH1 to CH9
EXDS1 EXDS2 EXADCLK VSS DC_DET 1 DC_DET 2
13 14 15 69 68 67
35 32 29 36 33 30
DVSS3 DVSS3 DVSS3 DVDD3 DVDD3 DVDD3 HL H2 H1 R FCKSW TEST2 TEST1 SUBSW SHUT STO DVSS2 DVSS2 DVSS2 DVSS2 DVSS2 DVSS2 DVDD2 DVDD2 DVDD2 DVDD2 DVDD2
AFE + TG AN12067
VDD 66 CCDOUT
PBLK CPOB CPOB2 DS1 DS2 clamp clamp GC S/H S/H
37 34 31 27 8 7 CCD Timing Generator 6 18 4 1 41
65
DC_DET 3 63 VDD 64 DC_DET4 VSS AUX VRB VRT VSSSUB CLR CS DCLK DATA
62 61 59 60 58 97 5 19 20 21 39 40 56 57 55 54 53 52 51 50 48 49 47 46 45 44 43 42 Clock Generator ADC SERIAL I/O
VrefL VrefH
+ GC - AMP DC Cont
28 25 17 10 3
XI XO DVDD1 DVSS1
ADCLK
38 24 16 9
22
VD
23
HD
26
11
12
2
DRVSS D0 D1 D2 D3 D4 D5 DRVDD D6 D7 D8 D9 D10 D11
CLKO SSGSW CCDSW
Pin Arrangement (Top View)
TOP VIEW 13 12 11 10 9 8 7 6 5 4 3 2 1 A 90 54 93 94 95 62 65 68 96 97 B 97 89 92 56 58 60 63 66 69 N.C. 52 53 51 91 55 57 59 61 64 67 N.C. 1 2 4 3 C D 5 7 6 E 8 10 9 F 11 12 13 G 14 15 N.C. H 16 18 17 J 19 N.C. 20 K 49 50 48 87 88 86 84 85 47 46 45 44 43 42 83 82 81 80 79 41 40 39 38 76 73 36 33 71 70 26 N.C. 21 23 22 L M 78 75 37 35 31 29 27 25 N.C. 97 N 97 77 74 72 34 32 30 28 24 N.C.
TOP VIEW 13 12 11 10 9 8 7 6 5 4 3 2 1
OV6 D1 VM VH VL OV1A OV2 DVDD1 VRT VRB D3 VSSSUB D2 D4 OV4 D0 DVSS1 AUX VSS VDD DC_DET2 N.C. STO VSSSUB DVSS2 TEST1 DVDD2 EXDS1 N.C. DVSS2 DCLK VD DVDD2 SHUT CLR TEST2 FCKSW DVSS2 CCDSW EXDS2 DVDD2 CS N.C. D5 DRVDD OV1B OV1S OV3R D6 D8 D9 D11 OV5R OV3A OV3B DVSS2 XO DVDD2 OV5C VM DVDD3 DVDD3 VH VL CLKO N.C. DATA HD VSSSUB OV5A OSUB HL DVSS3 H1 DVSS3 R DVSS2 N.C. OV5B VMSUB VHH H2 DVSS3 DVDD3 DVSS2 DVDD2 N.C. DRVSS OV1C OV3L D7 D10 OV5L OV3C XI VSSSUB
DC_DET4 DC_DET3 CCDOUT DC_DET1 RESET VDD VSS N.C.
SSGSW EXADCLK SUBSW
A
B
C
D
E
F
G
No land
H
N.C.
J
K
L
M
N
Thermal / dummy land
Land without wire connection
NN12067A XXXXX JAPAN
The direction recognition mark corresponds to the direction of A1 land
Pin Descriptions1
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Pin name STO DVDD2 DVSS2 SHUT CLR TEST1 TEST2 FCKSW DVDD2 DVSS2 CCDSW SSGSW EXDS1 EXDS2 EXADCLK DVDD2 DVSS2 SUBSW CS DCLK DATA VD HD DVDD2 DVSS2 CLKO R DVSS2 DVSS3 DVDD3 H1 DVSS3 DVDD3 H2 Pin C2 D3 D1 D2 E3 E1 E2 F3 F1 F2 G3 G2 G1 H3 H2 J3 J1 J2 K3 K1 L3 L1 L2 N4 M4 L5 M5 N5 M6 N6 M7 N7 L8 N8 Type I/O -- -- Output Input Input Input Input -- -- Input Input I/O I/O I/O -- -- I/O Input Input Input I/O I/O -- -- Output Output -- -- -- Output -- -- Output Strobe trigger output Power supply for timing generator block Ground for timing generator block Mechanical shutter control pulse All clear input Test input 1 (Normally set low) Test input 2 (Normally set low) Master clock setting input Power supply for timing generator block Ground for timing generator block CCD setting input SSG setting input Pre-charge S/H pulse output Data S/H pulse output A/D clock output Power supply for timing generator block Ground for timing generator block SUB bias voltage control pulse output Data latch input for serial data communications Clock input for serial data communications Data input for serial data communications Vertical sync pulse input/output Horizontal sync pulse input/output Power supply for timing generator block Ground for timing generator block FCK clock output fR pulse output (positive logic) Ground for timing generator block Ground for fH driver and fR driver Power supply for fH driver and fR driver fH1 pulse output (positive logic) Ground for fH driver and fR driver Power supply for fH driver and fR driver fH2 pulse output (positive logic) Description
Pin Descriptions2
No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 Pin name DVSS3 DVDD3 HL DVDD2 XI XO DVSS2 D11 D10 D9 D8 D7 D6 DRVDD DRVSS D5 D4 D3 D2 D1 D0 DVDD1 DVSS1 VRT AUX VRB VSS DC_DET4 DC_DET3 VDD CCDOUT VDD DC_DET2 Pin M8 L9 M9 L12 L13 K11 K12 H12 H13 G11 G12 G13 F11 D11 D13 D12 C11 C13 C12 A10 C9 B9 C8 B8 C7 B7 C6 A6 B6 C5 A5 B5 C4 Type -- -- Output -- Input Output -- Output Output Output Output Output Output -- -- Output Output Output Output Output Output -- -- -- -- -- -- -- -- -- -- -- -- Description Ground for fH driver and fR driver Power supply for fH driver and fR driver fHL pulse output (positive logic) Power supply for timing generator block Crystal oscillator input (FCK or 2FCK) Crystal oscillator output (FCK/2FCK) with 3 times multiplier and external feedback resistor Ground for timing generator block A/D output (MSB) A/D output A/D output A/D output A/D output A/D output Digital driver power supply for signal processing block Digital driver ground for signal processing block A/D output A/D output A/D output A/D output A/D output A/D output (LSB) Power supply for signal processing block Ground for signal processing block VRT External signal input VRB Analog ground for signal processing block Bias stabilization 2 Bias stabilization 1 Analog power supply for signal processing block CDS signal input Analog power supply for signal processing block GCA output DC level stabilization
Pin Descriptions3
No. 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 Pin name DC_DET1 VSS VL VH VHH VM VMSUB OSUB OV5C OV5B OV5A OV3C OV3B OV3A OV5L OV5R OV3L OV3R OV1S OV1C OV1B OV1A OV6 OV4 OV2 VM VH VL RESET VSSSUB Pin A4 B4 L6 L7 N9 L10 N10 M10 L11 N11 M11 K13 J11 J12 J13 H11 F13 F12 E11 E13 E12 B11 A11 C10 B10 A9 A8 A7 A3 A1, A13 N1, N13 Type -- -- -- -- -- -- -- Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output -- -- -- Input -- Description CDS output DC level stabilization Analog ground for signal processing block (V-Driver) Low-level power supply (V-Driver) High-level power supply for vertical driver (V-Driver) High-level power supply for fSUB driver (V-Driver) Middle-level power supply for vertical driver (V-Driver) Middle-level power supply for fSUB driver (V-Driver) SUB pulse output (V-Driver) fV5C transfer pulse output (V-Driver) fV5B transfer pulse output (V-Driver) fV5A transfer pulse output (V-Driver) fV3C transfer pulse output (V-Driver) fV3B transfer pulse output (V-Driver) fV3A transfer pulse output (V-Driver) fV5L transfer pulse output (V-Driver) fV5R transfer pulse output (V-Driver) fV3L transfer pulse output (V-Driver) fV3R transfer pulse output (V-Driver) fV1S transfer pulse output (V-Driver) fV1C transfer pulse output (V-Driver) fV1B transfer pulse output (V-Driver) fV1A transfer pulse output (V-Driver) fV6 transfer pulse output (V-Driver) fV4 transfer pulse output (V-Driver) fV2 transfer pulse output (V-Driver) Middle-level power supply for vertical driver (V-Driver) High-level power supply for vertical driver (V-Driver) Low-level power supply (V-Driver) Reset pulse input Ground for analog front end chip substrate
Absolute Maximum Ratings
A No.
Parameter
Symbol VDD, DRVDD, DVDD1, DVDD2 DVDD3 VHH - VL VH - VL VL VMSUB ICC PD Topr Tstg
Rating
Unit
Notes
1
Supply voltage 1
4.6
V
*1
2 3 4 5 6 7 8 9 10
Supply voltage 2 Supply voltage 3 Supply voltage 4 Supply voltage 5 Supply voltage 6 Supply current Power dissipation Operating ambient temperature Storage temperature
4.6 25 25 - 9.0 (VL+2.0) to 5.5 -- 249 - 20 to + 75 - 50 to + 125
V V V V V mA mW C C
*1 *1 *1 *1 *1 *2 *3 *3
Note) *1 : The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2 : The above power dissipation shows the package individual power dissipation at Ta = 75C, in free-air. Refer to the Pd-Ta diagram on sheet No. 45, and use this IC under the condition not exceeding the allowable value. *3 : Ta = 25C except storage temperature and operating ambient temperature . *4 : This IC operates with the load capacitance of less than 5 500 pF, but this IC is tested only with load of sheet No.20. Care should be taken.
Operating supply voltage range
Parameter Symbol VDD, DRVDD, DVDD1, DVDD2 DVDD3 VHH VH VL VMSUB VM Range Unit Notes
Supply voltage 1
2.9 V to 3.6
V
*1
Supply voltage 2 Supply voltage 3 Supply voltage 4 Supply voltage 5 Supply voltage 6 Supply voltage 7
2.9 V to 3.6 11.3 V to 15.5 11.3 V to 15.5 -8.5 V to -4.0 (VL+2.0) to 5.0 --
V V V V V --
*1 *1 *1 *1 *1 *2
Note) *1 :The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2 : VM should be used at the same potential as the ground pins.

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