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TPS62110 TPS62111 TPS62112
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SLVS585 - JULY 2005
17-V, 1.5-A, SYNCHRONOUS STEP-DOWN CONVERTER
FEATURES
* * * * * * * * * * * * * * High-Efficiency Synchronous Step-Down Converter With up to 95% Efficiency 3.1-V to 17-V Operating Input Voltage Range Adjustable Output Voltage Range From 1.2 V to 16 V Fixed Output Voltage Options Available in 3.3 V and 5 V Synchronizable to External Clock Signal up to 1.4 MHz Up to 1.5-A Output Current High Efficiency Over a Wide Load Current Range Due to PFM/PWM Operation Mode 100% Maximum Duty Cycle for Lowest Dropout 20-A Quiescent Current (Typical) Overtemperature and Overcurrent Protected Available in 16-Pin QFN Package
DESCRIPTION
The TPS6211x devices are a family of low-noise synchronous step-down dc-dc converters that are ideally suited for systems powered from a 2-cell Li-ion battery or from a 12-V or 15-V rail. The TPS6211x is a synchronous PWM converter with integrated - and P-channel power MOSFET switches. Synchronous rectification is used to increase efficiency and to reduce external component count. To achieve highest efficiency over a wide load current range, the converter enters a power-saving, pulse-frequency modulation (PFM) mode at light load currents. Operating frequency is typically 1 MHz, allowing the use of small inductor and capacitor values. The device can be synchronized to an external clock signal in the range of 0.8 MHz to 1.4 MHz. For low noise operation, the converter can be operated in PWM-only mode. In the shutdown mode, the current consumption is reduced to less than 2 A. The TPS6211x is available in the 16-pin (RSA) QFN package, and operates over a free-air temperature range of -40C to 85C.
TPS62111 Efficiency vs Output Current
100 4.2 V 90
APPLICATIONS
Point-of-Load Regulation From 12-V Bus Organizers, PDAs, and Handheld PCs Handheld Scanners
TYPICAL APPLICATION
VI = 3.8 V to 17 V VIN VIN EN VINA CI = 10 mF 25 V 1 mF LBO AGND LBI SYNC GND GND PwPD PGND PGND FB 6.8 mH TPS62111 1M PG CO = 22 mF 6.3 V
80 70 5V 8.4 V
VO = 3.3 V
Efficiency - %
SW SW
60 50
12 V 40 30 20 10 0 0.0001 VO = 3.3 V o TA = 25 C PFM Mode 0.001 0.01 0.1 1 10
IO - Output Current- A
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2005, Texas Instruments Incorporated
TPS62110 TPS62111 TPS62112
SLVS585 - JULY 2005
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This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges; HBM according to EIA/JESD22-A114-B, MM according EIA/JESD22-A115-A, and CDM according EIA/JESD22C101C; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriate logic voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments. ORDERING INFORMATION
PLASTIC QFN 16 (RSA) TPS62110 TPS62111 TPS62112 (1) PIN (1) OUTPUT VOLTAGE Adjustable 1.2 V to 16 V 3.3 V 5V LBI/LBO FUNCTIONALITY Standard Standard Standard MARKING TPS62110 TPS62111 TPS62112
The RSA package is available in tape and reel. Add R suffix (TPS62110RSAR) to order quantities of 3000 parts per reel. Add T suffix (TPS62110RSAT) to order quantities of 250 parts per reel.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
UNIT VCC VI IO TJ TA Tstg Supply voltage at VIN, VINA Voltage at SW Voltage at EN, SYNC, LBO, PG Voltage at LBI, FB Output current at SW Maximum junction temperature Operating free-air temperature Storage temperature Lead temperature 1,6 mm (1/16-inch) from case for 10 seconds (1) -0.3 V to 20 V -0.3 V to VI -0.3 V to 20 V -0.3 V to 7 V 2400 mA 150C -40C to 85C -65C to 150C 300C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS (1)
PACKAGE RSA (1) TA 25C POWER RATING 2.5 W DERATING FACTOR ABOVE TA = 25C 25 mW/C TA = 70C POWER RATING 1.375 W TA = 85C POWER RATING 1W
Based on a thermal resistance of 40 K/W soldered onto a high K board.
RECOMMENDED OPERATING CONDITIONS
MIN VCC TJ Supply voltage at VIN , VINA Maximum voltage at power-good, LBO, EN, SYNC Operating junction temperature -40 3.1 NOM MAX 17 17 125 UNIT V V C
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TPS62110 TPS62111 TPS62112
SLVS585 - JULY 2005
ELECTRICAL CHARACTERISTICS
VI = 12 V, VO = 3.3 V, IO = 600 mA, EN = VI, TA = -40C to 85C (unless otherwise noted)
PARAMETER SUPPLY CURRENT VI I(Q) Input voltage range Operating quiescent current IO = 0 mA, SYNC = GND, VI = 7.2 V, TA = 25C (1) IO = 0 mA, SYNC = GND, VI = 17 V I(SD) ENABLE VIH VIL IIKG I(EN) V(UVLO) EN high-level input voltage EN low-level input voltage EN trip-point hysteresis EN input leakage current EN input current Undervoltage lockout threshold Undervoltage lockout hysteresis POWER SWITCH VI 5.4 V; IO = 350 mA rDS(ON) P-channel MOSFET on-resistance P-channel MOSFET leakage current P-channel MOSFET current limit rDS(ON) N-channel MOSFET on-resistance N-channel MOSFET leakage current POWER GOOD OUTPUT , LBI, LBO V(PG) Power good trip voltage VO ramping positive VO ramping negative V(FB) = 0.8 x VO nominal, IOL = 1 mA 1 V(FB) = VO nominal, V(LBI) = VI 0.01 3 Input voltage falling 1.256 10 100 1.5% 25 900 CMOS-logic clock signal on SYNC pin 800 1.5 0.3 1000 1100 1400 mV kHz kHz V V 0.25 VO 1.6% 50 200 0.3 V VI = 3.5 V; IO = 200 mA VI = 3 V; IO = 100 mA VDS = 17 V VI = 7.2 V, VO = 3.3 V VI 5.4 V; IO = 350 mA VI = 3.5 V; IO = 200 mA VI = 3 V; IO = 100 mA VDS = 17 V 165 340 490 0.1 2400 145 170 200 0.1 2 A 200 m 1 A mA 250 m EN = GND or VI, VI = 12 V 0.6 V V(EN) 4 V Input voltage falling 2.8 170 0.01 10 3 250 0.2 20 3.1 300 1.3 0.3 V V mV A A V mV Shutdown current EN = GND EN = GND, TA = 25C, VI = 7.2 V
(1)
TEST CONDITIONS
MIN 3.1
TYP
MAX 17
UNIT V A
20 23 1.5 1.5 26 5 3 A
Power good delay time VOL IOL PG, LBO output low voltage PG, LBO sink current PG, LBO output leakage current Minimum supply voltage for valid power good, LBI, LBO signal VLBI ILBI Low battery input trip voltage LBI input leakage current Low battery input trip-point accuracy VLBI,HYS Low battery input hysteresis OSCILLATOR fS f(SYNC) VIH VIL (1) Oscillator frequency Synchronization range SYNC high-level input voltage SYNC low-level input voltage Device is not switching.
s V mA A V V nA
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TPS62110 TPS62111 TPS62112
SLVS585 - JULY 2005
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ELECTRICAL CHARACTERISTICS (continued)
VI = 12 V, VO = 3.3 V, IO = 600 mA, EN = VI, TA = -40C to 85C (unless otherwise noted)
PARAMETER Ilkg SYNC input leakage current SYNC trip-point hysteresis SYNC input current Duty cycle of external clock signal OUTPUT VO VFB Adjustable output voltage range Feedback voltage FB leakage current Feedback voltage tolerance TPS62110 TPS62110 TPS62110 TPS62110 TPS62111 Fixed output voltage tolerance (3) TPS62112 VI = 3.1 V to 17 V; 0 mA < IO < 1500 mA (2) VI = 3.8 V to 17 V; 0 mA < IO < 1500 mA (2) VI = 5.5 V to 17 V; 0 mA < IO < 1500 mA (2) -2% -3% -3% 100 500 1200 1500 5 VI = 7.2 V; VO = 3.3 V; IO = 600 mA VI = 12 V, Vo = 5 V, Io = 600 mA at 1 MHz 10% 100 145 IO = 800 mA, VI = 12 V, Vo = 3.3 V 1 92% 100% ns C ms A mA 1.153 1.153 10 100 2% 3% 3% 16 V V nA 0.6 V V(SYNC) 4 V 30% TEST CONDITIONS SYNC = GND or VIN MIN TYP 0.01 170 10 20 90% MAX 0.2 UNIT A mV A
VI 3 V (once undervoltage lockout voltage exceeded) IO Maximum output current VI 3.5 V VI 4.3 V VI 6 V Current into internal voltage divider for fixed voltage versions Efficiency Duty cycle range for main switches Minimum ton time for main switch Shutdown temperature Start-up time (2) (3)
The maximum output current depends on the input voltage. See the maximum output current for further restrictions on the minimum input voltage. The output voltage accuracy includes line and load regulation over the full temperature range TA = -40C to 85C. See the section for no-load operation in this data sheet.
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TPS62110 TPS62111 TPS62112
SLVS585 - JULY 2005
DEVICE INFORMATION PIN ASSIGNMENT TOP VIEW
PGND SW SW PG
16 15 14 13 12
Exposed Thermal Pad
PGND VIN VIN EN
1 2 3 4
11 10 9
5678
GND GND FB AGND
SYNC LBO LBI
TERMINAL NAME EN FB LBO GND LBI SW PG PGND AGND SYNC NO. 4 10 6 11, 12 7 14, 15 13 1, 16 9 5 I/O I I O I I O O I I I
TERMINAL FUNCTIONS
DESCRIPTION Enable. A logic high enables the converter; logic low forces the device into shutdown mode reducing the supply current to less than 2 A. Feedback pin for the fixed output voltage option. For the adjustable version, an external resistive divider is connected to this pin. The internal voltage divider is disabled for the adjustable version. Open-drain, low-battery output. This pin is pulled low if LBI is below its threshold. Ground Low-battery input Connect the inductor to this pin. This pin is the switch pin and connected to the drain of the internal power MOSFETS. Power good comparator output. This is an open-drain output. A pullup resistor should be connected between PG and VOUT. The output goes active high when the output voltage is greater than 98.4% of the nominal value. Power ground. Connect all power grounds to this pin. Analog ground, connect to GND and PGND Input for synchronization to external clock signal. Synchronizes the converter switching frequency to an external clock signal with CMOS level: SYNC = HIGH: Low-noise mode enabled, fixed frequency PWM operation is forced SYNC = LOW (GND): Power save mode enabled, PFM/PWM Mode enabled VIN VINA PowerPADTM 2, 3 8 I I Supply voltage input (power stage) Supply voltage input (support circuits) Connect to AGND
VINA
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TPS62110 TPS62111 TPS62112
SLVS585 - JULY 2005
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FUNCTIONAL BLOCK DIAGRAM
VI Current Limit Comparator Vina Undervoltage Lockout Bias Supply + _ REF
Thermal Shutdown + _ Soft Start IAVG Comparator REF
V I
V(COMP)
1-MHz Oscillator P-Channel Power MOSFET Comparator + _ Comparator High Comparator Low Comparator High 2 Load Comparator + _ + _ + _ S R Control Logic Driver Shoot-Through Logic N-Channel Power MOSFET SW
Sawtooth Generator
SKIP Comparator
PG
Comparator High + Gm _ Comparator Low EN Compensation R2 VREF = 1.153 V + _
(See Note A)
R1
_ + + _ 1.256 V
LBO
FB
LBI
PGND
GND
A.
For the adjustable version (TPS62110), the internal feedback divider is disabled and the FB pin is directly connected to the internal GM amplifier.
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TPS62110 TPS62111 TPS62112
SLVS585 - JULY 2005
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE Efficiency Efficiency Maximum output current Efficiency Efficiency Line transient response Load transient response Output ripple Start-up timing Switching frequency Quiescent current vs vs Input voltage Input voltage vs vs vs vs vs Output current (5 V) Output current (3.3 V) Input voltage Output current (1.8 V) Output current (1.5 V) 1, 2 3, 4, 5 6 7, 8 9, 10 11 12 13 14 15 16
Graphs with VO = 1.8 V were taken using the circuit according to Figure 20.
TPS62112 EFFICIENCY vs OUTPUT CURRENT
100 90 80 8.4 V 70 70 100 90 80 8.4 V
TPS62112 EFFICIENCY vs OUTPUT CURRENT
Efficiency - %
Efficiency - %
12 V 60 50 40 30 15 V
60 12 V 50 15 V 40 30 20 10 0 0.0001 VO = 5 V o TA = 25 C PWM Mode
20 10
VO = 5 V o TA = 25 C PFM Mode 0.001 0.01 0.1 1 10
0.001
0.01
0.1
1
10
0 0.0001
IO - Output Current- A
IO - Output Current- A
Figure 1.
Figure 2.
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TPS62110 TPS62111 TPS62112
SLVS585 - JULY 2005
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TPS62111 EFFICIENCY vs OUTPUT CURRENT
100 90 80 4.2 V 70 70 8.4 V 60 5V 50 12 V 40 30 20 10 0 0.0001 VO = 3.3 V o TA = 25 C PWM Mode 0.001 0.01 0.1 1 10 100 4.2 V 90 80
TPS62111 EFFICIENCY vs OUTPUT CURRENT
5V 8.4 V
Efficiency - %
Efficiency - %
60 50
12 V 40 30 20 10 0 0.0001 VO = 3.3 V o TA = 25 C PFM Mode 0.001 0.01 0.1 1 10
IO - Output Current- A
IO - Output Current- A
Figure 3. TPS62111 EFFICIENCY vs OUTPUT CURRENT
100 90 80 70 VO = 3.3 V SYNC = 1.4 MHz o TA = 25 C PFM Mode 2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 3.2 3.6 4
Figure 4. TPS62111 MAXIMUM OUTPUT CURRENT vs INPUT VOLTAGE
8.4 V 60 5V 50 12 V 40 30 20 10 0 0.0001
IO - Output Current - mA
Efficiency - %
0.001
0.01
0.1
1
10
4.4
4.8
5.2
5.6
6
IO - Output Current- A
VI - Input Voltage- V
Figure 5.
Figure 6.
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TPS62110 TPS62111 TPS62112
SLVS585 - JULY 2005
TPS62110 EFFICIENCY vs OUTPUT CURRENT
100 90 80 4.2 V 70 70 100 90 80 4.2 V
TPS62110 EFFICIENCY vs OUTPUT CURRENT
5V
Efficiency - %
Efficiency - %
60 50 40 30 20 10 0 0.0001
5V
8.4 V
60 50 40 30
8.4 V
12 V
12 V
VO = 1.8 V o TA = 25 C PWM Mode 0.001 0.01 0.1 1 10
20 10 0 0.0001
VO = 1.8 V o TA = 25 C PFM Mode 0.001 0.01 0.1 1 10
IO - Output Current- A
IO - Output Current- A
Figure 7. TPS62110 EFFICIENCY vs OUTPUT CURRENT
100 90 80 70 4.2 V 100 90 80 70 5V 60 50 40 30 20 10 0 0.0001 VO = 1.5 V o TA = 25 C PWM Mode 0.001 0.01 0.1 1 10 12 V 8.4 V 4.2 V
Figure 8. TPS62110 EFFICIENCY vs OUTPUT CURRENT
Efficiency - %
Efficiency - %
5V 8.4 V
60 50 40 30 20 10 0 0.0001 VO = 1.5 V o TA = 25 C PFM Mode 0.001 0.01 0.1 1 10 12 V
IO - Output Current- A
IO - Output Current- A
Figure 9.
Figure 10.
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TPS62110 TPS62111 TPS62112
SLVS585 - JULY 2005
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TPS62111 LINE TRANSIENT
TPS62111 LOAD TRANSIENT
VI = 8.4 V VO = 3.3 V ILOAD = 150 mA to 1350 mA TA = 25C
C1 = 5 V/div
VO = 50 mV/div
C2 = 50 mV/div IO = 500 mA/div
VI = 7.2 V to 12 V VO = 3.3 V ILOAD = 800 mA TA = 25C
t - Time = 2 ms/div
t - Time = 20 s/div
Figure 11. TPS62111 OUTPUT RIPPLE
VI = 8.4 V, VO = 3.3 V CH1 = 20 mV/div CH1 = 10 V/div ILOAD = 100 mA, TA = 25C VI = 12 V, VO = 3.3 V
Figure 12. TPS62111 START-UP TIMING
ILOAD = 800 mA, TA = 25C
CH2 = 5 V/div CH2 = 1 V/div
CH3 = 5 V/div
CH4 = 500 mA/div
CH4 = 200 mA/div
t - Time = 5 s/div
t - Time = 200 s/div
Figure 13.
Figure 14.
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TPS62110 TPS62111 TPS62112
SLVS585 - JULY 2005
SWITCHING FREQUENCY vs INPUT VOLTAGE
1000 990 VO = 12 V IO = 100 mA 50 45 85 C 40 25 C
o o
QUIESCENT CURRENT vs INPUT VOLTAGE
Switching Frequency - kHz
980 970 960 -40 C 950 940 930 920 910 900 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 VI - Input Voltage - V
o
Quiescent Current - mA
35 30 85 C 25 20 15 10 5 0 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 VI - Input Voltage - V -40 C
o o
25 C
o
Figure 15.
Figure 16.
The graphs were generated using the EVM with the setup according to Figure 17 unless otherwise noted. The output voltage divider was adjusted according to Table 4. Graphs for an output voltage of 5 V and 3.3 V were generated using TPS62111 and TPS62112 with R1 = 0 and R2 = open.
TDK 6.8 mH SLF7032T-6R8M1R6 Vbat VIN VIN EN open CI 10 mF / 25 V TDK C3225X5R1E106K VINA 1 mF LBO AGND LBI 261 kW VIN or GND SYNC GND GND PwPD PGND PGND FB R2 PG CO 22 mF / 16 V TDK C3225X7R1C226M TPS62110 SW SW 1 MW 1 MW R1 Cff VO
Figure 17. Test Setup
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TPS62110 TPS62111 TPS62112
SLVS585 - JULY 2005
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DETAILED DESCRIPTION OPERATION
The TPS6211x is a synchronous step-down converter that operates with a 1-MHz fixed frequency pulse width modulation (PWM) at moderate-to-heavy load currents and enters the power save mode at light load current. During PWM operation, the converter uses a unique fast response voltage mode control scheme with input voltage feedforward. Good line and load regulation is achieved with the use of small input and output ceramic capacitors. At the beginning of each clock cycle initiated by the clock signal (S), the P-channel MOSFET switch is turned on, and the inductor current ramps up until the comparator trips and the control logic turns the switch off. The switch is turned off by the current limit comparator if the current limit of the P-channel switch is exceeded. After the dead time prevents current shoot through, the N-channel MOSFET rectifier is turned on, and the inductor current ramps down. The next cycle is initiated by the clock signal turning off the N-channel rectifier, and turning on the P-channel switch. The error amplifier as well as the input voltage determines the rise time of the sawtooth generator. Therefore, any change in input voltage or output voltage directly controls the duty cycle of the converter giving a very good line and load transient regulation.
CONSTANT FREQUENCY MODE OPERATION (SYNC = HIGH)
In constant frequency mode, the output voltage is regulated by varying the duty cycle of the PWM signal in the range of 100% to 10%. Connecting the SYNC pin to a voltage greater than 1.5 V forces the converter to operate permanently in the PWM mode even at light or no-load currents. The advantage is that the converter operates with a fixed switching frequency that allows simple filtering of the switching frequency for noise-sensitive applications. In this mode, the efficiency is lower compared to the power save mode during light loads. The N-MOSFET of the devices stay on even when the current into the output drops to zero. This prevents the device from going into discontinuous mode, and the device transfers unused energy back to the input. Therefore, there is no ringing at the output, which usually occurs in discontinuous mode. The duty cycle range in constant frequency mode is 100% to 10%. It is possible to switch from forced PWM mode to the power save mode during operation by pulling the SYNC pin LOW. The flexible configuration of the SYNC pin during operation of the device allows efficient power management by adjusting the operation of the TPS6211x to the specific system requirements.
POWER SAVE MODE OPERATION (SYNC = LOW)
As the load current decreases, the converter enters the power save mode operation. During power save mode, the converter operates with reduced switching frequency in pulse frequency modulation (PFM), and with a minimum quiescent current to maintain high efficiency. Whenever the average output current goes below the skip threshold, the converter enters the power save mode. The average current depends on the input voltage. It is about 200 mA at low input voltages and up to 400 mA with maximum input voltage. The average output current must be below the threshold for at least 32 clock cycles to enter the power save mode. During the power save mode, the output voltage is monitored with a comparator and the output voltage is regulated in to a typical value between the nominal output voltage and 0.8% above the nominal output voltage. When the output voltage falls below the nominal output voltage, the P-channel switch turns on. The P-channel switch is turned off as the peak switch current is reached. The N-channel rectifier is turned on, and the inductor current ramps down. As the inductor current approaches zero, the N-channel rectifier is turned off and the switch is turned on starting the next pulse. When the output voltage can not be reached with a single pulse, the device continues to switch with its normal operating frequency until the comparator detects the output voltage to be 0.8% above the nominal output voltage. This control method reduces the quiescent current to 20 A (typical), and reduces the switching frequency to a minimum that achieves the highest converter efficiency.
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TPS62110 TPS62111 TPS62112
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DETAILED DESCRIPTION (continued)
1.6% 0.8% VO (nominal)
-1.6% t
Figure 18. Power Save Mode Output Voltage Thresholds The typical PFM (SKIP) current threshold for the TPS6211x is given by:
VI I S K IP 25 W
(1)
Equation 1 is valid for input voltages up to 7 V. For higher voltages, the skip current threshold is not increased further. The converter enters the fixed frequency PWM mode as soon as the output voltage falls below VO - 1.6% (nominal).
SOFT START
The TPS6211x has an internal soft-start circuit that limits the inrush current during start-up. This prevents possible voltage drops of the input voltage when a battery or a high-impedance power source is connected to the input of the TPS6211x. The soft start is implemented as a digital circuit increasing the switch current in steps of 300 mA, 600 mA, 1200 mA. The typical switch current limit is 2.4 A. Therefore, the start-up time depends on the output capacitor and load current. Typical start-up time with a 22-F output capacitor and 800-mA load current is 1 ms.
100% DUTY CYCLE LOW DROPOUT OPERATION
The TPS6211x offers the lowest possible input to output voltage difference while still maintaining operation with the use of the 100% duty cycle mode. In this mode, the P-channel switch is constantly turned on. This is particularly useful in battery-powered applications to achieve the longest operation time, taking full advantage of the whole battery voltage range. The minimum input voltage to maintain regulation depends on the load current and output voltage, and is calculated as:
V I min = VO max + I O max x rDS ( on ) max + R( L )
(
)
(2)
with: IOmax = maximum output current plus inductor ripple current rDS(on)max = maximum P-channel switch rDS(on) R(L) = dc resistance of the inductor VOmax = nominal output voltage plus maximum output voltage tolerance
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DETAILED DESCRIPTION (continued) ENABLE
Logic low on EN forces the TPS6211x into shutdown. In shutdown, the power switch, drivers, voltage reference, oscillator, and all other functions are turned off. The supply current is reduced to less than 2 A in the shutdown mode. When the device is in thermal shutdown, the bandgap is forced to be switched on even if the device is set into shutdown by pulling EN to GND. If an output voltage is present when the device is disabled, which could be due to an external voltage source or a super capacitor, the reverse leakage current is specified under electrical characteristics. Pulling the enable pin high starts up the TPS6211x with the soft start. If the EN pin is connected to any voltage other than VI or GND, an increased leakage current of typically 10 A and up to 20 A can occur.
UNDERVOLTAGE LOCKOUT
The undervoltage lockout circuit prevents the device from misoperation at low-input voltages. It prevents the converter from turning on the switch or rectifier MOSFET under undefined conditions. The minimum input voltage to start up the TPS6211x is 3.4 V (worst case). The device shuts down at 2.8 V minimum.
SYNCHRONIZATION
If no clock signal is applied, the converter operates with a typical switching frequency of 1 MHz. It is possible to synchronize the converter to an external clock within a frequency range from 0.8 MHz to 1.4 MHz. The device automatically detects the rising edge of the first clock and synchronizes immediately to the external clock. If the clock signal is stopped, the converter automatically switches back to the internal clock and continues operation. The switch over is initiated if no rising edge on the SYNC pin is detected for a duration of four clock cycles. Therefore, the maximum delay time can be 6.25 s if the internal clock has its minimum frequency of 800 kHz If the device is synchronized to an external clock, the power save mode is disabled, and the devices stay in forced PWM mode. Connecting the SYNC pin to the GND pin enables the power save mode. The converter operates in the PWM mode at moderate-to-heavy loads, and in the PFM mode during light loads which maintains high efficiency over a wide load current range.
POWER GOOD COMPARATOR
The power good (PG) comparator has an open-drain output capable of sinking 1 mA (typical). The PG is only active when the device is enabled (EN=high). When the device is disabled (EN=low), the PG pin is pulled to GND. The PG output is only valid after a 250-s delay when the device is enabled, and the supply voltage is greater than the undervoltage lockout V(UVLO). PG is low during the first 250 s after shutdown and in shutdown. The PG pin becomes active high when the output voltage exceeds 98.4% (typical) of its nominal value. Leave the PG pin unconnected when not used.
LOW-BATTERY DETECTOR
The low-battery output (LBO) is an open-drain type which goes low when the voltage at the low-battery input (LBI) falls below the trip point of 1.256 V 1.5%. The voltage at which the low-battery warning is issued can be adjusted with a resistive divider as shown in Figure 19. The sum of resistors (R1 + R2) as well as the sum of (R5 + R6) is recommended to be in the 100-k to 1-M range for high efficiency at low output current. An external pullup resistor can be connected to OUT, or any other voltage rail in the voltage range of 0 V to 16 V. During start-up, the LBO output signal is invalid for the first 500 s. LBO is high impedance when the device is disabled. If the low-battery comparator function is not used, connect LBI to ground. The low-battery detector is disabled when the device is disabled. The logic level of the LBO pin is not defined for the first 500 s after EN is pulled high. When the LBI is used to supervise the battery voltage and shut down the TPS62111 at low-input voltages, the battery voltage rises when the current drops to zero. The implemented hysteresis on the LBI pin may not be sufficient for all types of batteries. Figure 19 shows how an additional external hysteresis can be implemented.
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TPS62110 TPS62111 TPS62112
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DETAILED DESCRIPTION (continued)
VI = 4.3 V to 17 V 6.8 mH
2 3 4
TPS62110 VIN VIN EN VINA SW SW
15 14
VO = 3.3 V R3 R4 R1 560 k Cff 10 pF CO = 22 mF 6.3 V
R5
8
PG LBO
13 6 10
CI = 10 mF 25 V
1 mF
9 7 5
AGND LBI SYNC GND GND PwPD PGND PGND
11 12 1 16
FB
R6
R7
R2 300 k
Figure 19. LBI With Increased Hysteresis
NO LOAD OPERATION
When the converter operates in the forced PWM mode and there is no load connected to the output, the converter regulates the output voltage by allowing the inductor current to reverse for a short time.
THEORY OR OPERATION / DESIGN PROCEDURE
Table 1. List of Inductors
MANUFACTURER Coilcraft Epcos Sumida TDK
(1)
TYPE MSS6132-682 B82462G4682M CDRH5D28-6R2 SLF6028T-6R8M1R5 SLF7032T-6R8M1R6 7447789006 7447779006 744053006
INDUCTANCE 6.8 H 6.8 H 6.2 H 6.8 H 6.8 H 6.8 H 6.8 H 6.2 H
DC RESISTANCE 65 mR (max) 50 mR (max) 33 mR (typ) 35 mR (typ) 41 mR (typ) 44 mR (typ) 33 mR (typ) 45 mR (typ)
SATURATION CURRENT 1.5 A 1.5 A 1.8 A 1.5 A 1.6 A 2.75 A 3.3 A 1.8 A
Wurth
(1)
The manufacturer's part numbers are used for test purposes only.
Inductor Selection
The control loop of the TPS6211x family requires a certain value for the output inductor and the output capacitor for stable operation. As long as the nominal value of L x C 6.2 H x 22 F, the control loop has enough phase margin and the device is stable. Reducing the inductor value without increasing the output capacitor (or vice versa) may cause stability problems. There are applications where it may be useful to increase the value of the output capacitor, e.g., for a low transient output voltage change. From a stability point of view, the inductor value could be decreased to keep the L x C product constant. However, there are drawbacks if the inductor value is decreased. A low inductor value causes a high inductor ripple current and therefore reduces the maximum dc output current. Table 2 gives the advantages and disadvantages when designing the inductor and output capacitor.
15
TPS62110 TPS62111 TPS62112
SLVS585 - JULY 2005
www.ti.com
Table 2. Advantages and Disadvantages When Designing the Inductor and Output Capacitor
INFLUENCE ON STABILITY Increase Cout (>22 F) Uncritical ADVANTAGE Less output voltage ripple Less output voltage overshoot / undershoot during load transient None Higher output voltage ripple Decrease Cout (<22 F) Critical Increase inductor value >6.8 H also Uncritical None High output voltage overshoot / undershoot during load transient Less gain and phase margin Less inductor current ripple More energy stored in the inductor higher voltage overshoot during load transient Smaller current rise higher voltage undershoot during load transient do not decrease the value of Cout due to these effects DISADVANTAGE
Increase L (>6.8 H)
Higher dc output current possible if operated close to the current limit
Critical Decrease L (<6.8 H) Increase output capacitor value > 22 F also
High inductor current ripple esSmall voltage overshoot / undershoot dur- pecially at high input voltage ing load transient and low output voltage
As it is shown in Table 2, the inductor value can be increased to higher values. For good performance, the peak-to-peak inductor current ripple should be less than 30% of the maximum dc output current. Especially at input voltages above 12 V, it makes sense to increase the inductor value in order to keep the inductor current ripple low. In such applications, the inductor value can be increased to 10 H or 22 H. Values above 22 H should be avoided in order to keep the voltage overshoot during load transient in an acceptable range. After choosing the inductor value, two additional inductor parameters should be considered: 1. current rating of the inductor 2. dc resistance The dc resistance of the inductance directly influences the efficiency of the converter. Therefore, an inductor with lowest dc resistance should be selected for highest efficiency. In order to avoid saturation of the inductor, the inductor should be rated at least for the maximum output current plus the inductor ripple current which is calculated as:
1DIL = VO L VO VI f
IL m ax =
IO
m ax +
DIL 2
(3)
Where: f = Switching frequency (1000 kHz typical) L = Inductor value IL = Peak-to-peak inductor ripple current IL(max) = Maximum inductor current The highest inductor current occurs at maximum VI. A more conservative approach is to select the inductor current rating just for the maximum switch current of the TPS6211x which is 2.4 A (typically). See Table 1 for recommended inductors.
OUTPUT CAPACITOR SELECTION
A 22-F (typical) output capacitor is needed with a 6.8-H inductor. For an output voltage greater than 5 V, a 33-F (minimum) output capacitor is required for stability. For best performance, a low ESR ceramic output capacitor is needed. Just for completeness, the RMS ripple current is calculated as:
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TPS62110 TPS62111 TPS62112
SLVS585 - JULY 2005
1I R M S (C O ) = V O
VO VI L f
1 2 3
(4)
The overall output ripple voltage is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charge and discharging the output capacitor:
1DV O = VO VO VI L f ae 1 c + RESR c8 C Of e o / / o
(5)
Where the highest output voltage ripple occurs at the highest input voltage VI.
INPUT CAPACITOR SELECTION
The nature of the buck converter is a pulsating input current; therefore, a low ESR input capacitor is required for best input voltage filtering, and minimizing the interference with other circuits caused by high input voltage spikes. The input capacitor should have a minimum value of 10 F and can be increased without any limit for better input voltage filtering. The input capacitor should be rated for the maximum input ripple current calculated as:
IRM S = IO m ax VO VI ae VO o / c1 c VI / e o
(6)
The worst-case RMS ripple current occurs at D = 0.5 and is calculated as: IRMS = IO/2. Ceramic capacitors show a good performance because of their low ESR value, and they are less sensitive against voltage transients compared to tantalum capacitors. Place the input capacitor as close as possible to the input pin of the IC for best performance
FEEDFORWARD CAPACITOR SELECTION
The feedforward capacitor (Cff) is needed to compensate for parasitic capacitance from the feedback pin to GND. Typically, a value of 4.7 pF to 22 pF is needed for an output voltage divider with a equivalent resistance (R1 in parallel with R2) in the 150-k range. The value can be chosen based on best transient performance and lowest output voltage ripple in PFM mode.
RECOMMENDED CAPACITORS
It is recommended that only X5R or X7R ceramic capacitors be used as input/output capacitors. Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is applied across a ceramic capacitor, as on the output and input capacitor of a dc/dc converter. The effect may lead to a significant capacitance drop especially for high input/output voltages and small capacitor packages. See the manufacturer's data sheet about the performance with a dc bias voltage applied. It may be necessary to choose a higher voltage rating or nominal capacitance value in order to get the required value at the operating point. The capacitors listed in Table 3 have been tested with the TPS62110 with good performance. Table 3. List of Capacitors
MANUFACTURER Taiyo Yuden PART NUMBER TMK316BJ106KL EMK325BJ226KM C3225X5R1E106M TDK C3225X7R1C226M C3216X5R1E106MT SIZE 1206 1210 1210 1206 VOLTAGE 25 V 16 V 25 V 16 V 25 V CAPACITANCE 10 F 22 F 10 F 22 F 10 F Ceramic TYPE Ceramic
17
TPS62110 TPS62111 TPS62112
SLVS585 - JULY 2005
www.ti.com
APPLICATION INFORMATION
VI = 3.5 V to 17 V 6.8 mH
2 3 4
TPS62110 VIN VIN EN VINA SW SW
15 14
VO = 1.8 V R3 1 MW R4 1 MW R1 220 kW Cff 10 pF CO = 2 x 22 mF 6.3 V
R5
8
PG LBO
13 6 10
CI = 10 mF 25 V
1 mF
9 7 5
AGND LBI SYNC GND GND PwPD PGND PGND
11 12 1 16
FB
R6
R2 390 kW
A.
For an output voltage lower than 2.5 V, an output capacitor of 33 F or greater is recommended to improve load transient.
Figure 20. Standard Connection for Adjustable Version
VO = VFB R1 + R 2 R2
ae VO R1 = R 2 c cV e FB
o /- R2 / o
(7)
VFB = 1.153 V Table 4. Recommended Resistors
OUTPUT VOLTAGE 9V 5V 3.3 V 2.5 V 1.8 V 1.5 V R1 680 k 510 k 560 k 390 k 220 k 100 k R2 100 k 150 k 300 k 330 k 390 k 330 k NOMINAL VOLTAGE 8.993 V 5.073 V 3.305 V 2.515 V 1.803 V 1.502 V
6.8 mH
2 3 4 8
TYPICAL Cff 22 pF 10 pF 10 pF 10 pF 10 pF 10 pF
VI = 5.5 V to 17 V
TPS62112 VIN VIN EN VINA SW SW
15 14
VO = 5 V 1 MW
PG LBO
13 6 10
CI = 10 mF 25 V
1 mF
9 7 5
AGND LBI SYNC GND GND PwPD PGND PGND
11 12 1 16
CO = 22 mF 10 V
FB
Figure 21. Standard Connection for Fixed Voltage Version
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TPS62110 TPS62111 TPS62112
SLVS585 - JULY 2005
6.8 mH
2 3 4 8
VI = 9.3 V to 17 V
TPS62110 VIN VIN EN VINA SW SW
15 14
VO = 9 V 1 MW Cff R1 680 kW
PG LBO
13 6 10
22 pF
CO = 33 mF 16 V
CI = 10 mF 25 V
1 mF
9 7 5
AGND LBI SYNC GND GND PwPD PGND PGND
11 12 1 16
FB
R2 100 kW
A.
For an output voltage greater than 5 V, an output capacitor of 33 F minimum is required for stability.
Figure 22. Application With 9-V Output
19
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2005
PACKAGING INFORMATION
Orderable Device TPS62110RSAR TPS62110RSARG4 TPS62110RSAT TPS62110RSATG4 TPS62111RSAR TPS62111RSARG4 TPS62111RSAT TPS62111RSATG4 TPS62112RSAR TPS62112RSARG4 TPS62112RSAT TPS62112RSATG4
(1)
Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type QFN QFN QFN QFN QFN QFN QFN QFN QFN QFN QFN QFN
Package Drawing RSA RSA RSA RSA RSA RSA RSA RSA RSA RSA RSA RSA
Pins Package Eco Plan (2) Qty 16 16 16 16 16 16 16 16 16 16 16 16 3000 Green (RoHS & no Sb/Br) 3000 Green (RoHS & no Sb/Br) 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU
MSL Peak Temp (3) Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR
3000 Green (RoHS & no Sb/Br) 3000 Green (RoHS & no Sb/Br) 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
3000 Green (RoHS & no Sb/Br) 3000 Green (RoHS & no Sb/Br) 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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