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| Z86D73 40/44/48-Pin Low-Voltage IR OTP Preliminary Product Specification PS019402-1103 ZiLOG Worldwide Headquarters * 532 Race Street * San Jose, CA 95126-3432 Telephone: 408.558.8500 * Fax: 408.558.8300 * www.ZiLOG.com This publication is subject to replacement by a later edition. To determine whether a later edition exists, or to request copies of publications, contact: ZiLOG Worldwide Headquarters 532 Race Street San Jose, CA 95126-3432 Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG.com ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. Document Disclaimer (c)2003 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Devices sold by ZiLOG, Inc. are covered by warranty and limitation of liability provisions appearing in the ZiLOG, Inc. Terms and Conditions of Sale. ZiLOG, Inc. makes no warranty of merchantability or fitness for any purpose. Except with the express written approval of ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights. P R E L I M I N A R Y PS019402-1103 Z86D73 40/44/48-Pin Low-Voltage IR OTP iii Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS (Output, Active Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AS (Output, Active Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XTAL1 Crystal 1 (Time-Based Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XTAL2 Crystal 2 (Time-Based Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . R/W Read/Write (Output, Write Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . R/RL (Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 0 (P07-P00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 1 (P17-P10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 2 (P27-P20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 3 (P37-P31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RESET (Input, Active Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Expanded Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Counter/Timer Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 18 18 19 19 19 19 19 21 22 23 26 26 26 26 28 31 32 33 42 Expanded Register File Control Registers (0D) . . . . . . . . . . . . . . . . . . . . . . . . 68 Expanded Register File Control Registers (0F) . . . . . . . . . . . . . . . . . . . . . . . . . 72 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Precharacterization Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP iv List of Figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Counter/Timers Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 40-Pin DIP Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 44-Pin QFP Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 44-Pin PLCC Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 48-Pin SSOP Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Test Load Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 External I/O or Memory Read/Write Timing . . . . . . . . . . . . . . . . . . . 13 Additional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Port 0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Port 1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Port 2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Port 3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Port 3 Counter/Timer Output Configuration . . . . . . . . . . . . . . . . . . . 25 Program Memory Map (32K OTP) . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Expanded Register File Architecture . . . . . . . . . . . . . . . . . . . . . . . . 29 Register Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Register Pointer--Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Glitch Filter Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Transmit Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8-Bit Counter/Timer Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 T8_OUT in Single-Pass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 T8_OUT in Modulo-N Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Demodulation Mode Count Capture Flowchart . . . . . . . . . . . . . . . . 47 Demodulation Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 16-Bit Counter/Timer Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 T16_OUT in Single-Pass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 T16_OUT in Modulo-N Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Ping-Pong Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Output Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Oscillator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Port Configuration Register (PCON) (Write Only) . . . . . . . . . . . . . . 58 Stop-Mode Recovery Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP v Figure 35. SCLK Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 36. Stop-Mode Recovery Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 37. Stop-Mode Recovery Register 2 ((0F) DH:D2-D4, D6 Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 38. Watch-Dog Timer Mode Register (Write Only) . . . . . . . . . . . . . . . . Figure 39. Resets and WDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 40. TC8 Control Register ((0D) OH: Read/Write Except Where Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 41. T8 and T16 Common Control Functions ((0D) 1h: Read/Write) . . . Figure 42. T16 Control Register ((0D) 2h: Read/Write Except Where Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 43. Low-Voltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 44. Stop-Mode Recovery Register ((0F) 0Bh: D6-D0=Write Only, D7=Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 45. Stop-Mode Recovery Register 2 ((0F) 0Dh:D2-D4, D6 Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 46. Watch-Dog Timer Register ((0F) 0Fh: Write Only) . . . . . . . . . . . . . Figure 47. Port Configuration Register (PCON) ((0F) 0h: Write Only) . . . . . . . Figure 48. Port 2 Mode Register (F6h: Write Only) . . . . . . . . . . . . . . . . . . . . . Figure 49. Port 3 Mode Register (F7h: Write Only) . . . . . . . . . . . . . . . . . . . . . Figure 50. Port 0 and 1 Mode Register (F8h: Write Only) . . . . . . . . . . . . . . . . Figure 51. Interrupt Priority Register (F9h: Write Only) . . . . . . . . . . . . . . . . . . Figure 52. Interrupt Request Register (FAh: Read/Write) . . . . . . . . . . . . . . . . . Figure 53. Interrupt Mask Register (FBh: Read/Write) . . . . . . . . . . . . . . . . . . . Figure 54. Flag Register (FCh: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 55. Register Pointer (FDh: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . Figure 56. Stack Pointer High (FEh: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . Figure 57. Stack Pointer Low (FFh: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . Figure 58. 40-Pin DIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 59. 44-Pin PLCC Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 60. 44-Pin QFP Package Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 61. 48-Pin SSOP Package Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 61 63 64 66 68 69 70 71 72 73 74 75 75 76 77 78 79 79 80 80 81 81 82 82 83 84 PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP vi List of Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 External I/O or Memory Read and Write Timing (Preliminary) . . . . 14 Additional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Expanded Register Group D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CTR0 (D)00 Counter/Timer8 Control Register . . . . . . . . . . . . . . . . 35 CTR(D)01h T8 and T16 Common Functions . . . . . . . . . . . . . . . . . 37 CTR2 (D)02h: Counter/Timer16 Control Register . . . . . . . . . . . . . . 39 SMR2(F)0Dh: Stop-Mode Recovery Register 2* . . . . . . . . . . . . . . . 41 Interrupt Types, Sources, and Vectors . . . . . . . . . . . . . . . . . . . . . . 55 IRQ Register* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Stop-Mode Recovery Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 WDT Time Select* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Mask Selectable Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Z86D73 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 1 Features Table 1 shows the features of the Z86D73. Table 1. Features Device Z86D73 OTP (KB) RAM* (Bytes) I/O Lines Voltage Range 32 236 31 2.0 V-3.6 V Note: *General purpose * * Low power consumption-40 mW (typical) Three standby modes - Stop--2 A (typical) - Halt--0.8 mA (typical) - Low voltage Special architecture to automate both generation and reception of complex pulses or signals: - One programmable 8-bit counter/timer with two capture registers and two load registers - One programmable 16-bit counter/timer with one 16-bit capture register pair and one 16-bit load register pair - Programmable input glitch filter for pulse reception Six priority interrupts - Three external - Two assigned to counter/timers - One low-voltage detection interrupt Low-voltage detection with flag Programmable watch-dog/power-on reset circuits Two independent comparators with programmable interrupt polarity Mask selectable pull-up transistors on ports 0, 1, 2 Programmable mask options - Oscillator selection: RC oscillator versus crystal or other clock source * * * * * * * PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 2 - - - - - - - Oscillator operational mode: normal high-frequency operation enabled or 32-KHz operation enabled Port 0: 0-3 pull-ups Port 0: 4-7 pull-ups Port 1: 0-3 pull-ups Port 1: 4-7 pull-ups Port 2: 0-7 pull-ups Port 0: 0-3 mouse mode: normal mode (.5VDD input threshold) versus mouse mode (.4VDD input threshold) Note: The mask option pull-up transistor has a typical equivalent resistance of 200 K 50% at VCC=3 V and 450 K 50% at VCC=2 V. General Description The Z86D73 is an OTP-based member of the MCU family of IR (infrared) microcontrollers. With 237 bytes of general-purpose RAM and 32 KB of ROM, ZiLOG's CMOS microcontrollers offer fast executing, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, automated pulse generation/ reception, and internal key-scan pull-up transistors. The Z86D73 architecture is based on ZiLOG's 8-bit microcontroller core with an Expanded Register File to allow access to register-mapped peripherals, input/output (I/O) circuits, and powerful counter/timer circuitry. The Z8 offers a flexible I/O scheme, an efficient register and address space structure, and a number of ancillary features that are useful in many consumer, automotive, computer peripheral, and battery-operated hand-held applications. There are four basic address spaces available to support a wide range of configurations: Program Memory, Register File, Expanded Register File, and External Memory. The register file is composed of 256 bytes of RAM. It includes 4 I/O port registers, 16 control and status registers, and 236 general-purpose registers. The Expanded Register File consists of two additional register groups (F and D). To unburden the program from coping with such real-time problems as generating complex waveforms or receiving and demodulating complex waveform/pulses, the Z86D73 offers a new intelligent counter/timer architecture with 8-bit and 16-bit counter/timers (see Figure 1). Also included are a large number of userselectable modes and two on-board comparators to process analog signals with separate reference voltages (see Figure 2). PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 3 Note: All signals with an overline, " ", are active Low. For example, B/W, in which WORD is active Low, and B/W, in which BYTE is active Low. Power connections use the conventional descriptions listed in Table 2. Table 2. Power Connections Connection Power Ground Circuit VCC GND Device VDD VSS HI16 8 LO16 8 16-Bit T16 Timer 16 1248 8 SCLK 16 8 TC16L Clock Divider TC16H And/Or Logic HI8 8 LO8 8 Timer 8/16 Input Glitch Filter Edge Detect Circuit 8-Bit T8 8 8 TC8L Timer 8 TC8H Figure 1. Counter/Timers Diagram PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 4 Figure 2. Functional Block Diagram PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 5 Pin Description The pins are shown in Figure 3, Figure 4, Figure 5, and Figure 6. The pins are described in Table 3. R/W P25 P26 P27 P04 P05 P06 P14 P15 P07 VDD P16 P17 XTAL2 XTAL1 P31 P32 P33 P34 AS 1 40 DS P24 P23 P22 P21 P20 P03 P13 P12 VSS P02 P11 P10 P01 P00 Pref1 P36 P37 P35 RESET Z86D73 DIP 20 21 Figure 3. 40-Pin DIP Pin Assignment PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 6 33 P21 P22 P23 P24 DS R/RL R/W P25 P26 P27 P04 34 P20 P03 P13 P12 VSS VSS P02 P11 P10 P01 P00 23 22 Z86D73 QFP 44 1 12 11 Pref1 P36 P37 P35 RESET VSS AS P34 P33 P32 P31 Figure 4. 44-Pin QFP Pin Assignment P21 P22 P23 P24 DS R/RL R/W P25 P26 P27 P04 7 P20 P03 P13 P12 VSS VSS P02 P11 P10 P01 P00 6 1 40 39 P05 P06 P14 P15 P07 VDD VDD P16 P17 XTAL2 Z86D73 PLCC 17 18 29 28 Pref1 P36 P37 P35 RESET VSS AS P34 P33 P32 P31 Figure 5. 44-Pin PLCC Assignment PS019402-1103 P05 P06 P14 P15 P07 VDD VDD P16 P17 XTAL2 XTAL1 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 7 R/W P25 P26 P27 P04 N/C P05 P06 P14 P15 P07 VDD VDD N/C P16 P17 XTAL2 XTAL1 P31 P32 P33 P34 AS VSS 1 48 Z86D73 SSOP 24 25 ROM/ROMLESS DS P24 P23 P22 P21 P20 P03 P13 P12 VSS VSS N/C P02 P11 P10 P01 P00 N/C PREF1 P36 P37 P35 RESET Figure 6. 48-Pin SSOP Assignment Table 3. Pin Identification 40-Pin DIP # 26 27 30 34 5 6 7 10 28 44-Pin PLCC # 40 41 44 5 17 18 19 22 42 44-Pin QFP # 23 24 27 32 44 1 2 5 25 48-Pin SSOP # 31 32 35 41 5 7 8 11 33 Symbol P00 P01 P02 P03 P04 P05 P06 P07 P10 PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 8 Table 3. Pin Identification (Continued) 40-Pin DIP # 29 32 33 8 9 12 13 35 36 37 38 39 2 3 4 16 17 18 19 22 24 23 20 40 1 21 15 14 11 44-Pin PLCC # 43 3 4 20 21 25 26 6 7 8 9 10 14 15 16 29 30 31 32 36 38 37 33 11 13 35 28 27 23, 24 44-Pin QFP # 26 30 31 3 4 8 9 33 34 35 36 37 41 42 43 12 13 14 15 19 21 20 16 38 40 18 11 10 6, 7 48-Pin SSOP # 34 39 40 9 10 15 16 42 43 44 45 46 2 3 4 19 20 21 22 26 28 27 23 47 1 25 18 17 12, 13 Symbol P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 P31 P32 P33 P34 P35 P36 P37 AS DS R/W RESET XTAL1 XTAL2 VDD PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 9 Table 3. Pin Identification (Continued) 40-Pin DIP # 31 25 44-Pin PLCC # 1, 2, 34 39 12 44-Pin QFP # 17, 28, 29 22 39 48-Pin SSOP # 24, 37, 38 29 48 Symbol VSS Pref1 R/RL Absolute Maximum Ratings Stresses greater than those listed in Table 4 might cause permanent damage to the device. This rating is a stress rating only. Functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period might affect device reliability. Table 4. Absolute Maximum Ratings Symbol VCC TSTG TA Notes: Description Supply Voltage (*) Storage Temperature Oper. Ambient Temperature. Min -0.3 -65 Max +7.0 +150 Units V C C *Voltage on all pins with respect to GND. See Ordering Information on page 85. PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 10 Standard Test Conditions The characteristics listed in this product specification apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (see Figure 7). Figure 7. Test Load Diagram Capacitance The capacitances are listed in Table 5. Table 5. Capacitance Parameter Input capacitance Output capacitance I/O capacitance Max 12 pF 12 pF 12 pF Note: TA = 25 C, VCC = GND = 0 V, f = 1.0 MHz, unmeasured pins returned to GND PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 11 DC Characteristics Table 6. DC Characteristics TA = 0C to +70C Sym Parameter Max Input Voltage VCH Clock Input High Voltage VCC 2.0 V 3.6 V 2.0 V 3.6 V VCL Clock Input Low Voltage 2.0 V 3.6 V VIH VIL VOH1 VOH2 Input High Voltage Input Low Voltage Output High Voltage Output High Voltage (P36, P37, P00, P01) 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V VOL1 VOL2* VOL2 Output Low Voltage Output Low Voltage Output Low Voltage (P00, P01, P36, P37) VOFFSET Comparator Input VREF IIL Offset Voltage Comparator Reference Voltage Input Leakage 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V 0 0 -1 -1 0.8 VCC 0.8 VCC VSS-0.3 VSS-0.3 0.7 VCC 0.7 VCC VSS-0.3 VSS-0.3 VCC-0.4 VCC-0.4 VCC-0.8 VCC-0.8 0.4 0.4 0.8 0.8 0.8 0.8 25 25 VDD-1.75 VDD-1.75 1 1 Min Max 7 7 VCC+0.3 VCC+0.3 0.2 VCC 0.2 VCC VCC+0.3 VCC+0.3 0.2 VCC 0.2 VCC Units Conditions V V V V V V V V V V V V V V V V V V V V mV mV mV mV IOH = -0.5 mA IOH = -0.5 mA IOH = -7 mA IOH = -7 mA IOL = 1.0 mA IOL = 4.0 mA IOL = 5.0 mA IOL = 7.0 mA IOL = 10 mA IOL = 10 mA IIN <250 A IIN <250 A Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Notes A A VIN = 0 V, VCC VIN = 0 V, VCC PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 12 Table 6. DC Characteristics (Continued) TA = 0C to +70C Sym IOL ICC Parameter Output Leakage Supply Current VCC 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V ICC1 Standby Current (HALT Mode) 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V Min -1 -1 Max 1 1 10 15 250 850 3 5 2 4 8 Units Conditions Notes A A mA mA VIN = 0 V, VCC VIN = 0 V, VCC at 8.0 MHz at 8.0 MHz at 32 kHz at 32 kHz VIN = 0 V, VCC at 8.0 MHz Same as above Clock Divide-by-16 at 8.0 MHz Same as above VIN = 0 V, VCC WDT is not Running Same as above VIN = 0 V, VCC WDT is Running Same as above VCC < VBO 1, 2 1, 2 1, 2, 3 1, 2, 3 1, 2 1, 2 1, 2 1, 2 4, 5 A A mA mA mA mA ICC2 Standby Current (STOP Mode) A A A A A A Note: WDT, Comparators, Low Voltage Detection, and ADC (if 3.6 V applicable are disabled. The IC 2.0 V might draw more current if any of the above peripherals is enabled. 3.6 V ICC2 Standby Current (Low Voltage) Power-On Reset VCC Low Voltage Protection Vcc Low Voltage Detection 2.0 V 3.6 V VBO VLVD 12 5 10 500 800 25 4, 5 4, 5 4, 5 6 TPOR 75 20 2.15 VBO + 0.4 ms ms V V 8 MHz max Ext. CLK Freq. VLVD = VBO + 0.4 7 8 Notes: *All outputs excluding P00, P01, P36, and P37. 1. All outputs unloaded, inputs at rail. 2. CL1 = CL2 = 100 pF. 3. 32-kHz clock driver input. 4. The VBO increases as the temperature decreases, except inputs at VCC. 5. Oscillator stopped. 6. Oscillator stops when VCC falls below VLV limit. 7. VBO increases as the temperature decreases. 8. Variance is 300 mV. PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 13 AC Characteristics Figure 9 and Table 8 describe the external I/O or memory read and write timing. Figure 8. External I/O or Memory Read/Write Timing PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 14 Table 7. External I/O or Memory Read and Write Timing (Preliminary) TA = 0 C to +70 C 8.0 MHz* No Symbol 1 2 3 4 5 6 7 8 9 TdA(AS) TdAS(A) TdAS(DR) TwAS Td TwDSR TwDSW TdDSR(DR) ThDR(DS) Parameter Address Valid to AS Rising Delay AS Rising to Address Float Delay AS Rising to Read Data Required Valid AS Low Width Address Float to DS Falling DS (Read) Low Width DS (Write) Low Width DS Falling to Read Data Required Valid VCC 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V 0 0 85 95 60 70 70 70 70 70 80 80 70 80 475 475 80 80 0 0 300 300 165 165 260 260 Min 55 55 70 70 400 400 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1, 2 1, 2 1, 2 2 2 2 2 2 2 2 1, 2 Notes 2 2 2 1, 2 2 Read Data to DS Rising 2.0 V Hold Time 3.6 V DS Rising to Address Active Delay DS Rising to AS Falling Delay R/W Valid to AS Rising Delay DS Rising to R/W Not Valid Write Data Valid to DS Falling (Write) Delay DS Rising to Write Data Not Valid Delay Address Valid to Read Data Required Valid 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V 10 TdDS(A) 11 TdDS(AS) 12 TdR/W(AS) 13 TdDS(R/W) 14 TdDW(DSW) 15 TdDS(DW) 16 TdA(DR) PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 15 Table 7. External I/O or Memory Read and Write Timing (Preliminary) (Continued) TA = 0 C to +70 C 8.0 MHz* No Symbol 17 TdAS(DS) 18 TdDM(AS) 19 TdDS(DM) 20 ThDS(A) Parameter AS Rising to DS Falling Delay DM Valid to AS Falling Delay DS Rise to DM Valid Delay DS Rise to Address Valid Hold Time VCC 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V Min 100 100 55 55 70 70 70 70 Max Units ns ns ns ns ns ns ns Notes 2 2 Notes: 1.When using extended memory timing, add 2 TpC. 2. Timing numbers given are for minimum TpC. * Standard Test Load: All timing references use 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0. Figure 9 and Table 8 describe additional timing characteristics. PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 16 1 Clock 2 7 3 2 3 7 TIN 4 6 5 IRQN 8 9 Clock Setup 11 Stop Mode Recovery Source Figure 9. Additional Timing 10 PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 17 Table 8. Additional Timing TA = 0 C to +70 C 8.0 MHz No Sym 1 TpC Parameter Input Clock Period VCC 2.0 V 3.6 V 2 TrC,TfC Clock Input Rise and 2.0 V Fall Times 3.6 V Input Clock Width 2.0 V 3.6 V 4 TwTinL Timer Input Low Width Timer Input High Width Timer Input Period 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V 7 TrTin,TfTin Timer Input Rise and 2.0 V Fall Timers 3.6 V Interrupt Request Low Time Interrupt Request Low Time Interrupt Request Input High Time Stop-Mode Recovery Width Spec Oscillator Start-Up Time 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V 100 70 5TpC 5TpC 5TpC 5TpC 12 12 5TpC 5TpC ns ns 4 4 37 37 100 70 3TpC 3TpC 8TpC 8TpC 100 100 ns ns ns ns Min 121 121 Max DC DC 25 25 Stop-Mode Recovery Units Notes (D1, D0) ns ns ns ns ns ns ns ns 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1, 2 1, 2 1, 3 1, 3 1, 2 1, 2 3 TwC 5 TwTinH 6 TpTin 8A TwIL 8B TwIL 9 TwIH 10 Twsm 11 Tost PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 18 Table 8. Additional Timing (Continued) TA = 0 C to +70 C 8.0 MHz No Sym 12 Twdt Parameter Watch-Dog Timer Delay Time VCC 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V Min 12 5 25 10 50 20 200 80 Max Stop-Mode Recovery Units Notes (D1, D0) ms ms ms ms ms ms ms ms 5 5 5 5 5 5 5 5 1, 1 1, 0 0, 1 0, 0 Notes: 1. Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0. 2. Interrupt request through Port 3 (P33-P31). 3. Interrupt request through Port 3 (P30). 4. SMR - D5 = 0. 5. For internal RC oscillator. Pin Functions DS (Output, Active Low) The Data Strobe is activated one time for each external memory transfer. For a READ operation, data must be available prior to the trailing edge of DS. For WRITE operations, the falling edge of DS indicates that output data is valid. AS (Output, Active Low) Address Strobe is pulsed one time at the beginning of each machine cycle. Address output is through Port 0/Port 1 for all external programs. Memory address transfers are valid at the trailing edge of AS. Under program control, AS is placed in the high-impedance state along with Ports 0 and 1, Data Strobe, and Read/ Write. PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 19 XTAL1 Crystal 1 (Time-Based Input) This pin connects a parallel-resonant crystal, ceramic resonator, LC, or RC network to the on-chip oscillator input. Additionally, an optional external single-phase clock can be coded to the on-chip oscillator input. XTAL2 Crystal 2 (Time-Based Output) This pin connects a parallel-resonant, crystal, ceramic resonant, LC, or RC network to the on-chip oscillator output. R/W Read/Write (Output, Write Low) The R/W signal is Low when the CCP is writing to the external program or data memory. R/RL (Input) This pin, when connected to GND, disables the internal ROM and forces the device to function as a ROMless Z8. Note: When left unconnected or pulled high to VCC, the part functions normally as a Z8 ROM version. Port 0 (P07-P00) Port 0 is an 8-bit, bidirectional, CMOS-compatible port. These eight I/O lines are configured under software control as a nibble I/O port or as an address port for interfacing external memory. The output drivers are push-pull or open-drain controlled by bit D2 in the PCON register. For external memory references, Port 0 can provide address bits A11-A8 (lower nibble) or A15-A8 (lower and upper nibble), depending on the required address space. If the address range requires 12 bits or less, the upper nibble of Port 0 can be programmed independently as I/O while the lower nibble is used for addressing. If one or both nibbles are needed for I/O operation, they must be configured by writing to the Port 0 mode register. After a hardware reset, Port 0 is configured as an input port. Port 0 is set in the high-impedance mode (if selected as an address output), along with Port 1 and the control signals AS, DS, and R/W through P3M bits D4 and D3 (see Figure 10). A ROM mask option is available to program 0.4 VDD CMOS trip inputs on P00- P03. This option allows direct interface to mouse/trackball IR sensors. PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 20 An optional pull-up transistor is available as a mask option on all Port 0 bits with nibble select. Note: Internal pull-ups are disabled on any given pin or group of port pins when programmed into output mode. 4 Z86D73 OTP Port 0 (I/O or A15-A8) 4 Open-Drain I/O Mask VCC Option Resistive transistor pull-up Pad Out In In 0.4 VDD Trip Point Buffer (P00 to P03 only) Figure 10. Port 0 Configuration *Mask Selectable PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 21 Port 1 (P17-P10) Port 1 (see Figure 11) is a multiplexed Address (A7-A0) and Data (D7-D0), CMOS-compatible port. Port 1 is dedicated to the ZiLOG ZBus(R)-compatible memory interface. The operations of Port 1 are supported by the Address Strobe (AS) and Data Strobe (DS) lines and by the Read/Write (R/W) and Data Memory (DM) control lines. Data memory read/write operations are done through this port. If more than 256 external locations are required, Port 0 outputs the additional lines. Port 1 can be placed in the high-impedance state along with Port 0, AS, DS, and R/W, allowing the Z86D73 to share common resources in multiprocessor and DMA applications. Port 1 can also be configured for standard port output mode. After POR, Port 1 is configured as an input port. The output drivers are either push-pull or open-drain and are controlled by bit D1 in the PCON register. Z86D73 OTP 8 Port 1 (I/O or AD7-AD0) Open-Drain OEN Mask VCC Option Resistive transistor pull-up Pad Out In Figure 11. Port 1 Configuration PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 22 Port 2 (P27-P20) Port 2 is an 8-bit, bidirectional, CMOS-compatible I/O port (see Figure 12). These eight I/O lines can be independently configured under software control as inputs or outputs. Port 2 is always available for I/O operation. A mask option is available to connect eight pull-up transistors on this port. Bits programmed as outputs are globally programmed as either push-pull or open-drain. The POR resets with the eight bits of Port 2 configured as inputs. Port 2 also has an 8-bit input OR and AND gate, which can be used to wake up the part. P20 can be programmed to access the edge-detection circuitry in demodulation mode. Z86D73 OTP Port 2 (I/O) Open-Drain I/O Mask VCC Option Resistive transistor pull-up Pad Out In Figure 12. Port 2 Configuration PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 23 Port 3 (P37-P31) Port 3 is a 7-bit, CMOS-compatible fixed I/O port (see Figure 13). Port 3 consists of three fixed input (P33-P31) and four fixed output (P37-P34), which can be configured under software control for interrupt and as output from the counter/timers. P31, P32, and P33 are standard CMOS inputs; P34, P35, P36, and P37 are pushpull outputs. Pref1 P31 P32 Z86D73 OTP P33 P34 P35 P36 P37 Port 3 (I/O) R247 = P3M D1 1 = Analog 0 = Digital P31 (AN1) Pref + Comp1 Dig. IRQ2, P31 Data Latch An. P32 (AN2) P33 (REF2) + Comp2 IRQ0, P32 Data Latch From Stop-Mode Recovery Source of SMR IRQ1, P33 Data Latch Figure 13. Port 3 Configuration PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 24 Two on-board comparators process analog signals on P31 and P32, with reference to the voltage on Pref1 and P33. The analog function is enabled by programming the Port 3 Mode Register (bit 1). P31 and P32 are programmable as rising, falling, or both edge triggered interrupts (IRQ register bits 6 and 7). Pref1 and P33 are the comparator reference voltage inputs. Access to the Counter Timer edgedetection circuit is through P31 or P20 (see "CTR1(D)01h" on page 37). Other edge detect and IRQ modes are described in Table 9. Note: Comparators are powered down by entering STOP Mode. For P31-P33 to be used in a Stop-Mode Recovery (SMR) source, these inputs must be placed into digital mode. 2 Table 9. Pin Assignments Pin Pref1 P31 P32 P33 P34 P35 P36 P37 P20 IN IN IN OUT OUT OUT OUT I/O IN T8 T16 T8/16 AO2 IN I/O C/T Comp. RF1 AN1 AN2 RF2 AO1 IRQ2 IRQ0 IRQ1 Int. Port 3 also provides output for each of the counter/timers and the AND/OR Logic (see Figure 14). Control is performed by programming bits D5-D4 of CTR1, bit 0 of CTR0, and bit 0 of CTR2. PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 25 CTR0, D0 P34 data T8_Out PCON, D0 VDD Pad P34 P31 Pref1 + Comp1 MU MUX CTR2, D0 Out 35 T16_Out VDD Pad P35 MUX CTR1, D6 Out 36 T8/T16_Out VDD Pad P36 MUX PCON, D0 P37 data VDD Pad P37 MUX P32 Pref2 + - Comp2 Figure 14. Port 3 Counter/Timer Output Configuration PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 26 Comparator Inputs In analog mode, P31 and P32 have a comparator front end. The comparator reference is supplied to P33 and Pref1. In this mode, the P33 internal data latch and its corresponding IRQ1 are diverted to the SMR sources (excluding P31, P32, and P33) as indicated in Figure 13 on page 23. In digital mode, P33 is used as D3 of the Port 3 input register, which then generates IRQ1. Note: Comparators are powered down by entering Stop Mode. For P31-P33 to be used in a Stop-Mode Recovery source, these inputs must be placed into digital mode. Comparator Outputs These channels can be programmed to be output on P34 and P37 through the PCON register. RESET (Input, Active Low) Reset initializes the MCU and is accomplished either through Power-On, WatchDog Timer, Stop-Mode Recovery, Low-Voltage detection, or external reset. During Power-On Reset and Watch-Dog Timer Reset, the internally generated reset drives the reset pin Low for the POR time. Any devices driving the external reset line need to be open-drain in order to avoid damage from a possible conflict during reset conditions. Pull-up is provided internally. Functional Description The Z86D73 incorporates special functions to enhance the Z8's functionality in consumer and battery-operated applications. Program Memory The Z86D73 addresses 32 KB of OTP memory. The first 12 bytes are reserved for interrupt vectors. These locations contain the five 16-bit vectors that correspond to the five available interrupts. RAM The Z86D73 device features 256 bytes of RAM. See Figure 15. PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 27 Location of first byte of instruction executed after RESET 32768 Not Accessible On-Chip ROM 12 11 10 9 8 7 Reset Start Address IRQ5 IRQ5 IRQ4 IRQ4 IRQ3 IRQ3 IRQ2 IRQ2 IRQ1 IRQ1 IRQ0 IRQ0 Interrupt Vector (Lower Byte) 6 5 4 Interrupt Vector (Upper Byte) 3 2 1 0 Figure 15. Program Memory Map (32K OTP) PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 28 Expanded Register File The register file has been expanded to allow for additional system control registers and for mapping of additional peripheral devices into the register address area. The Z8 register address space (R0 through R15) has been implemented as 16 banks, with 16 registers per bank. These register groups are known as the ERF (Expanded Register File). Bits 7-4 of register RP select the working register group. Bits 3-0 of register RP select the expanded register file bank. Note: An expanded register bank is also referred to as an expanded register group (see Figure 16). PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 29 Z8(R) Standard Control Registers Register* * FF FE SPL SPH RP FLAGS IMR IRQ IPR P01M P3M P2M Reserved Reserved Reserved Reserved Reserved Reserved U U 0 U 0 0 U 0 0 1 U U U U 0 0 Reset Condition D7 D6 D5 D4 D3 D2 D1 D0 U U 0 U U 0 U 1 0 1 U U U U 0 U U U 0 U U 0 U 0 0 1 U U U U 0 U U U 0 U U 0 U 0 0 1 U U U U 0 0 U U 0 U U 0 U 1 0 1 U U U U 0 0 U U 0 U U 0 U 1 0 1 U U U U 0 0 U U 0 U U 0 U 0 0 1 U U U U 0 0 U U 0 U U 0 U 1 1 1 U U U U 0 0 Register Pointer 7 6 5 4 3 2 1 0 FD FC FB FA F9 F8 Working Register Group Pointer Expanded Register Bank Pointer * F7 F6 F5 F4 F3 Z8 Register File (Bank 0) * * FF F0 F2 F1 F0 Expanded Reg. Bank/Group (F) Register* * Reset Condition * Reserved (F) 0F WDTMR (F) 0E Reserved (F) 0D SMR2 (F) 0C Reserved 0 0 0 0 1 1 0 1 U 0 U 0 0 0 U U 7F (F) 0B SMR (F) 0A Reserved (F) 09 Reserved (F) 08 Reserved (F) 07 Reserved (F) 06 Reserved 0 0 1 0 0 0 U 0 Reserved 0F 00 (F) 05 Reserved (F) 04 Reserved (F) 03 Reserved (F) 02 Reserved (F) 01 Reserved * Expanded Reg. Bank/Group (0) Register* * Reset (F) 00 PCON 1 1 1 1 1 1 1 0 Expanded Reg. Bank/Group (D) Register* * Reset Condition (D) 0C (D) 0B 0 U U U 0 U U U 0 U U U 0 U U U U U U U U U U U U U U U U (D) 0A U U U (D) 08 (D) 07 LO16 TC16H TC16L TC8H TC8L Reserved CTR2 CTR1 CTR0 0 0 0 U 0 U U U U U U U U U U U U U U U U 0 U 0 U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U (D) 09 LO8 HI16 U U U U U U U U U U U U U U U U LVD HI8 0 U 0 U 0 U 0 U 0 U 0 U 0 U 0 U * * (0) 03 P3 (0) 02 P2 (0) 01 P1 (0) 00 P0 U = Unknown * Is not reset with a Stop-Mode Recovery ** All addresses are in hexadecimal Is not reset with a Stop-Mode Recovery, except Bit 0 (D) 06 (D) 05 (D) 04 (D) 03 (D) 02 (D) 01 (D) 00 Figure 16. Expanded Register File Architecture PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 30 The upper nibble of the register pointer (see Figure 17) selects which working register group, of 16 bytes in the register file, is accessed out of the possible 256. The lower nibble selects the expanded register file bank and, in the case of the Z86D73 family, banks 0, F, and D are implemented. A 0h in the lower nibble allows the normal register file (bank 0) to be addressed. Any other value from 1h to Fh exchanges the lower 16 registers to an expanded register bank. R253 RP D7 D6 D5 D4 D3 D2 D1 D0 Expanded Register File Pointer Working Register Pointer Default Setting After Reset = 0000 0000 Figure 17. Register Pointer Example: Z86D73: (See Figure 16 on page 29) R253 RP = 00h R0 = Port 0 R1 = Port 1 R2 = Port 2 R3 = Port 3 But if: R253 RP = 0Dh R0 = CTRL0 R1 = CTRL1 R2 = CTRL2 R3 = Reserved The counter/timers are mapped into ERF group D. Access is easily performed using the following: LD LD LD LD RP, #0Dh R0,#xx 1, #xx R1, 2 ; ; ; ; ; Select ERF D for access to bank D (working register group 0) load CTRL0 load CTRL1 CTRL2CTRL1 PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 31 LD LD LD LD RP, #0Dh RP, #7Dh 71h, 2 R1, 2 ; ; ; ; ; ; Select ERF D for access to bank D (working register group 0) Select expanded register bank D and working register group 7 of bank 0 for access. CTRL2register 71h CTRL2register 71h Register File The register file (bank 0) consists of 4 I/O port registers, 237 general-purpose registers, 16 control and status registers (R0-R3, R4-R239, and R240-R255, respectively), and two expanded registers groups in Banks D (see Table 10) and F. Instructions can access registers directly or indirectly through an 8-bit address field, thereby allowing a short, 4-bit register address to use the Register Pointer (Figure 18). In the 4-bit mode, the register file is divided into 16 working register groups, each occupying 16 continuous locations. The Register Pointer addresses the starting location of the active working register group. Note: Working register group E0-EF can only be accessed through working registers and indirect addressing modes. r7 r6 r5 r4 r3 r2 r1 r0 R253 The upper nibble of the register file address provided by the register pointer specifies the active working-register group. { { { { { { { { 7F 70 6F 60 5F 50 4F 40 3F 30 2F 20 1F 10 0F 00 Specified Working Register Group The lower nibble of the register file address provided by the instruction points to the specified register. Register Group 1 Register Group 0 I/O Ports R15 to R0 R15 to R4 * R3 to R0 * * RP = 00: Selects Register Group 0, Working Register 0 Figure 18. Register Pointer--Detail PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 32 Stack The Z86D73 internal register file is used for the stack. An 8-bit Stack Pointer (R255) is used for the internal stack that resides in the general-purpose registers (R4-R239). SPH is used as a general-purpose register only when using internal stacks. Note: When SPH is used as a general-purpose register and Port 0 is in address mode, the contents of SPH are loaded into Port 0 whenever the internal stack is accessed Table 10. Expanded Register Group D (D)0Ch (D)0Bh (D)0Ah (D)09h (D)08h (D)07h (D)06h (D)05h (D)04h (D)03h (D)02h (D)01h (D)00h LVD HI8 LO8 HI16 LO16 TC16H TC16L TC8H TC8L Reserved CTR2 CTR1 CTR0 PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 33 Register Description LVD(D)0Ch Low-Voltage Detection Register Note: The LVD flag will be valid after enabling the detection for 20 S (design estimation, not tested in production). LVD does not work at STOP mode. It must be disabled during STOP mode in order to reduce current. Field LVD Bit Position 765432-------1-------0 R R/W 1 0* 1 0* Description Reserved No Effect LV flag set LV flag reset Enable LVD Disable LVD *Default after POR Note: Do not modify register P01M while checking a low-voltage condition. Switching noise of both ports 0 and 1 together might trigger the LVD flag. HI8(D)0Bh This register holds the captured data from the output of the 8-bit Counter/Timer0. Typically, this register is used to hold the number of counts when the input signal is 1. Field T8_Capture_HI Bit Position 76543210 R W Description Captured Data No Effect L08(D)0Ah This register holds the captured data from the output of the 8-bit Counter/Timer0. Typically, this register is used to hold the number of counts when the input signal is 0. Field T8_Capture_L0 Bit Position 76543210 R W Description Captured Data No Effect PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 34 HI16(D)09h This register holds the captured data from the output of the 16-bit Counter/ Timer16. This register holds the MS-Byte of the data. Field Bit Position R W Description Captured Data No Effect T16_Capture_HI 76543210 L016(D)08h This register holds the captured data from the output of the 16-bit Counter/ Timer16. this register holds the LS-Byte of the data. Field Bit Position R W Description Captured Data No Effect T16_Capture_LO 76543210 TC16H(D)07h Counter/Timer2 MS-Byte Hold Register Field T16_Data_HI Bit Position 76543210 Description R/W Data TC16L(D)06h Counter/Timer2 LS-Byte Hold Register Field T16_Data_LO Bit Position 76543210 Description R/W Data TC8H(D)05h Counter/Timer8 High Hold Register Field T8_Level_HI Bit Position 76543210 Description R/W Data PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 35 TC8L(D)04h Counter/Timer8 Low Hold Register Field T8_Level_LO Bit Position 76543210 Description R/W Data CTR0 Counter/Timer8 Control Register Table 11 lists and briefly describes the fields for this register. Table 11. CTR0 (D)00 Counter/Timer8 Control Register Field T8_Enable Bit Position 7------R W Single/Modulo-N Time_Out -6--------5-----R/W R W T8 _Clock ---43--R/W Value 0* 1 0 1 0 1 0 1 0 1 00 01 10 11 0 1 0 1 0* 1 Description Counter Disabled Counter Enabled Stop Counter Enable Counter Modulo-N Single Pass No Counter Time-Out Counter Time-Out Occurred No Effect Reset Flag to 0 SCLK SCLK/2 SCLK/4 SCLK/8 Disable Data Capture Int. Enable Data Capture Int. Disable Time-Out Int. Enable Time-Out Int. P34 as Port Output T8 Output on P34 Capture_INT_MASK Counter_INT_Mask P34_Out -----2-------1-------0 R/W R/W R/W Note: *Indicates the value upon Power-On Reset. T8 Enable This field enables T8 when set (written) to 1. PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 36 Single/Modulo-N When set to 0 (modulo-n), the counter reloads the initial value when the terminal count is reached. When set to 1 (single pass), the counter stops when the terminal count is reached. Timeout This bit is set when T8 times out (terminal count reached). To reset this bit, a 1 should be written to its location. Caution: Writing a 1 is the only way to reset the Terminal Count status condition. Therefore, reset this bit before using/enabling the counter/timers. The first clock of T8 might not have complete clock width and can occur any time when enabled. Note: Care must be taken when using the OR or AND commands to manipulate CTR0, bit 5 and CTR1, bits 0 and 1 (Demodulation Mode). These instructions use a Read-Modify-Write sequence in which the current status from the CTR0 and CTR1 registers is ORed or ANDed with the designated value and then written back into the registers. Example When the status of bit 5 is 1, a timer reset condition occurs. T8 Clock This bit defines the frequency of the input signal to T8. Capture_INT_Mask Set this bit to allow an interrupt when data is captured into either LO8 or HI8 upon a positive or negative edge detection in demodulation mode. Counter_INT_Mask Set this bit to allow an interrupt when T8 has a timeout. P34_Out This bit defines whether P34 is used as a normal output pin or the T8 output. PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 37 CTR1(D)01h This register controls the functions in common with the T8 and T16. Table 12 lists and briefly describes the fields for this register. Table 12. CTR(D)01h T8 and T16 Common Functions Field Mode P36_Out/ Demodulator_Input Bit Position 7-------6-----R/W R/W 0* 1 0 1 T8/T16_Logic/ Edge _Detect --54---R/W 00 01 10 11 00 01 10 11 Transmit_Submode/ Glitch_Filter ----32-R/W 00 01 10 11 00 01 10 11 Initial_T8_Out/ Rising Edge ------1R/W 0 1 0 1 0 1 Value 0* Description Transmit Mode Demodulation Mode Transmit Mode Port Output T8/T16 Output Demodulation Mode P31 P20 Transmit Mode AND OR NOR NAND Demodulation Mode Falling Edge Rising Edge Both Edges Reserved Transmit Mode Normal Operation Ping-Pong Mode T16_Out = 0 T16_Out = 1 Demodulation Mode No Filter 4 SCLK Cycle 8 SCLK Cycle Reserved Transmit Mode T8_OUT is 0 Initially T8_OUT is 1 Initially Demodulation Mode No Rising Edge Rising Edge Detected No Effect Reset Flag to 0 R W PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 38 Table 12. CTR(D)01h T8 and T16 Common Functions (Continued) Field Initial_T16_Out/ Falling_Edge Bit Position -------0 R/W Value 0 1 0 1 0 1 Description Transmit Mode T16_OUT is 0 Initially T16_OUT is 1 Initially Demodulation Mode No Falling Edge Falling Edge Detected No Effect Reset Flag to 0 R W Note: *Default upon Power-On Reset Mode If the result is 0, the counter/timers are in the transmit mode; otherwise, they are in the demodulation mode. P36_Out/Demodulator_Input In Transmit Mode, this bit defines whether P36 is used as a normal output pin or the combined output of T8 and T16. In Demodulation Mode, this bit defines whether the input signal to the Counter/ Timers is from P20 or P31. T8/T16_Logic/Edge _Detect In Transmit Mode, this field defines how the outputs of T8 and T16 are combined (AND, OR, NOR, NAND). In Demodulation Mode, this field defines which edge should be detected by the edge detector. Transmit_Submode/Glitch Filter In Transmit Mode, this field defines whether T8 and T16 are in the Ping-Pong mode or in independent normal operation mode. Setting this field to "Normal Operation Mode" terminates the "Ping-Pong Mode" operation. When set to 10, T16 is immediately forced to a 0; a setting of 11 forces T16 to output a 1. In Demodulation Mode, this field defines the width of the glitch that must be filtered out. Initial_T8_Out/Rising_Edge In Transmit Mode, if 0, the output of T8 is set to 0 when it starts to count. If 1, the output of T8 is set to 1 when it starts to count. When the counter is not enabled and this bit is set to 1 or 0, T8_OUT is set to the opposite state of this bit. This PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 39 ensures that when the clock is enabled, a transition occurs to the initial state set by CTR1, D1. In Demodulation Mode, this bit is set to 1 when a rising edge is detected in the input signal. In order to reset the mode, a 1 should be written to this location. Initial_T16 Out/Falling _Edge In Transmit Mode, if it is 0, the output of T16 is set to 0 when it starts to count. If it is 1, the output of T16 is set to 1 when it starts to count. This bit is effective only in Normal or Ping-Pong Mode (CTR1, D3; D2). When the counter is not enabled and this bit is set, T16_OUT is set to the opposite state of this bit. This ensures that when the clock is enabled, a transition occurs to the initial state set by CTR1, D0. In Demodulation Mode, this bit is set to 1 when a falling edge is detected in the input signal. In order to reset it, a 1 should be written to this location. Note: Modifying CTR1 (D1 or D0) while the counters are enabled causes unpredictable output from T8/16_OUT. CTR2 Counter/Timer 16 Control Register Table 13 lists and briefly describes the fields for this register. Table 13. CTR2 (D)02h: Counter/Timer16 Control Register Field T16_Enable Bit Position 7------R W Single/Modulo-N -6-----R/W 0 1 0 1 Time_Out --5----R 0 1 0 1 Value 0* 1 0 1 Description Counter Disabled Counter Enabled Stop Counter Enable Counter Transmit Mode Modulo-N Single Pass Demodulation Mode T16 Recognizes Edge T16 Does Not Recognize Edge No Counter Timeout Counter Timeout Occurred No Effect Reset Flag to 0 W PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 40 Table 13. CTR2 (D)02h: Counter/Timer16 Control Register (Continued) Field T16 _Clock Bit Position ---43--R/W Value 00 01 10 11 0 1 Counter_INT_Mask P35_Out ------1-------0 R/W R/W 0 0* 1 Description SCLK SCLK/2 SCLK/4 SCLK/8 Disable Data Capture Int. Enable Data Capture Int. Disable Timeout Int. Enable Timeout Int. P35 as Port Output T16 Output on P35 Capture_INT_Mask -----2-- R/W Note: *Indicates the value upon Power-On Reset. T16_Enable This field enables T16 when set to 1. Single/Modulo-N In Transmit Mode, when set to 0, the counter reloads the initial value when the terminal count is reached. When set to 1, the counter stops when the terminal count is reached. In Demodulation Mode, when set to 0, T16 captures and reloads on detection of all the edges. When set to 1, T16 captures and detects on the first edge but ignores the subsequent edges. For details, see the description of T16 Demodulation Mode on page 50. Time_Out This bit is set when T16 times out (terminal count reached). To reset the bit, write a 1 to this location. T16_Clock This bit defines the frequency of the input signal to Counter/Timer16. Capture_INT_Mask This bit is set to allow an interrupt when data is captured into LO16 and HI16. PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 41 Counter_INT_Mask Set this bit to allow an interrupt when T16 times out. P35_Out This bit defines whether P35 is used as a normal output pin or T16 output. SMR2 Stop-Mode Recovery Register 2 Table 14 lists and briefly describes the fields for this register. Table 14. SMR2(F)0Dh: Stop-Mode Recovery Register 2* Field Reserved Recovery Level Reserved Source Bit Position 7-------6-------5-------432-Value 0 0 1 0 000 001 010 011 100 101 110 111 00 Description Reserved (Must be 0) Low High Reserved (Must be 0) A. POR Only B. NAND of P23-P20 C. NAND of P27-P20 D. NOR of P33-P31 E. NAND of P33-P31 F. NOR of P33-P31, P00, P07 G. NAND of P33-P31, P00, P07 H. NAND of P33-P31, P22-P20 Reserved (Must be 0) W W Reserved Notes: ------10 * Port pins configured as outputs are ignored as a SMR recovery source. Indicates the value upon Power-On Reset PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 42 Counter/Timer Functional Blocks Input Circuit The edge detector monitors the input signal on P31 or P20. Based on CTR1 D5- D4, a pulse is generated at the Pos Edge or Neg Edge line when an edge is detected. Glitches in the input signal that have a width less than specified (CTR1 D3, D2) are filtered out (see Figure 19). CTR1 D5,D4 P31 MUX P20 Glitch Filter Edge Detector Pos Edge Neg Edge CTR1 D6 CTR1 D3,D2 Figure 19. Glitch Filter Circuitry T8 Transmit Mode Before T8 is enabled, the output of T8 depends on CTR1, D1. If it is 0, T8_OUT is 1; if it is 1, T8_OUT is 0. See Figure 20. PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 43 T8 (8-Bit) Transmit Mode No T8_Enable Bit Set CTR0, D7 Yes Reset T8_Enable Bit 0 Load TC8L Reset T8_OUT CTR1, D1 Value 1 Load TC8H Set T8_OUT Set Timeout Status Bit (CTR0 D5) and Generate Timeout_Int if Enabled Enable T8 No T8_Timeout Yes Single Pass Single Pass? Modulo-N 1 Load TC8L Reset T8_OUT T8_OUT Value 0 Load TC8H Set T8_OUT Enable T8 Set Timeout Status Bit (CTR0 D5) and Generate Timeout_Int if Enabled No T8_Timeout Yes Figure 20. Transmit Mode Flowchart PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 44 When T8 is enabled, the output T8_OUT switches to the initial value (CTR1, D1). If the initial value (CTR1, D1) is 0, TC8L is loaded; otherwise, TC8H is loaded into the counter. In Single-Pass Mode (CTR0, D6), T8 counts down to 0 and stops, T8_OUT toggles, the timeout status bit (CTR0, D5) is set, and a timeout interrupt can be generated if it is enabled (CTR0, D1). In Modulo-N Mode, upon reaching terminal count, T8_OUT is toggled, but no interrupt is generated. From that point, T8 loads a new count (if the T8_OUT level now is 0), TC8L is loaded; if it is 1, TC8H is loaded. T8 counts down to 0, toggles T8_OUT, and sets the timeout status bit (CTR0, D5), thereby generating an interrupt if enabled (CTR0, D1). One cycle is thus completed. T8 then loads from TC8H or TC8L according to the T8_OUT level and repeats the cycle. See Figure 21. Z8 Data Bus Positive Edge Negative Edge HI8 LO8 CTR0 D1 IRQ4 CTR0 D2 CTR0 D4, D3 Clock Select Clock 8-Bit Counter T8 SCLK T8_OUT TC8H Z8 Data Bus TC8L Figure 21. 8-Bit Counter/Timer Circuits You can modify the values in TC8H or TC8L at any time. The new values take effect when they are loaded. Caution: Do not write these registers at the time the values are to be loaded into the counter/timer to ensure known operation. An initial count of 1 is not allowed (a non-function occurs). An initial count of 0 causes TC8 to count from 0 to FFh to FEh. PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 45 Note: The letter h is used for hexadecimal values. Transition from 0 to FFh is not a timeout condition. Caution: Using the same instructions for stopping the counter/timers and setting the status bits is not recommended. Two successive commands are necessary. First, the counter/timers must be stopped. Second, the status bits must be reset. These commands are required because it takes one counter/timer clock interval for the initiated event to actually occur. See Figure 22 and Figure 23. TC8H Count Counter Enable Command; T8_OUT Switches to Its Initial Value (CTR1 D1) T8_OUT Toggles; Timeout Interrupt Figure 22. T8_OUT in Single-Pass Mode T8_OUT Toggles T8_OUT TC8L TC8H TC8L TC8H TC8L ... Counter Enable Command; T8_OUT Switches to Its Initial Value (CTR1 D1) Timeout Interrupt Timeout Interrupt Figure 23. T8_OUT in Modulo-N Mode PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 46 T8 Demodulation Mode Program TC8L and TC8H to FFh. After T8 is enabled, when the first edge (rising, falling, or both depending on CTR1, D5; D4) is detected, it starts to count down. When a subsequent edge (rising, falling, or both depending on CTR1, D5; D4) is detected during counting, the current value of T8 is complemented and put into one of the capture registers. If it is a positive edge, data is put into LO8; if it is a negative edge, data is put into HI8. From that point, one of the edge detect status bits (CTR1, D1; D0) is set, and an interrupt can be generated if enabled (CTR0, D2). Meanwhile, T8 is loaded with FFh and starts counting again. If T8 reaches 0, the timeout status bit (CTR0, D5) is set, and an interrupt can be generated if enabled (CTR0, D1). T8 then continues counting from FFh (see Figure 24 and Figure 25). PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 47 T8 (8-Bit) Count Capture No T8 Enable (Set by User) Yes No Edge Present Yes What Kind of Edge Positive Negative T8 LO8 T8 HI8 FFh T8 Figure 24. Demodulation Mode Count Capture Flowchart PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 48 T8 (8-Bit) Demodulation Mode No T8 Enable CTR0, D7 Yes FFh TC8 No First Edge Present Yes Disable TC8 Enable TC8 No T8_Enable Bit Set Yes No Edge Present Yes Set Edge Present Status Bit and Trigger Data Capture Int. If Enabled T8 Timeout Yes Set Timeout Status Bit and Trigger Timeout Int. If Enabled No Continue Counting Figure 25. Demodulation Mode Flowchart PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 49 T16 Transmit Mode In Normal or Ping-Pong Mode, the output of T16 when not enabled, is dependent on CTR1, D0. If it is a 0, T16_OUT is a 1; if it is a 1, T16_OUT is 0. You can force the output of T16 to either a 0 or 1 whether it is enabled or not by programming CTR1 D3; D2 to a 10 or 11. When T16 is enabled, TC16H * 256 + TC16L is loaded, and T16_OUT is switched to its initial value (CTR1, D0). When T16 counts down to 0, T16_OUT is toggled (in Normal or Ping-Pong Mode), an interrupt (CTR2, D1) is generated (if enabled), and a status bit (CTR2, D5) is set. See Figure 26. Z8 Data Bus Positive Edge Negative Edge HI16 LO16 CTR2 D1 IRQ3 CTR2 D2 CTR2 D4, D3 Clock Select Clock 16-Bit Counter T16 SCLK T16_OUT TC16H Z8 Data Bus TC16L Figure 26. 16-Bit Counter/Timer Circuits Note: Global interrupts override this function as described in "Interrupts" on page 53. If T16 is in Single-Pass Mode, it is stopped at this point (see Figure 27). If it is in Modulo-N Mode, it is loaded with TC16H * 256 + TC16L, and the counting continues (see Figure 28). You can modify the values in TC16H and TC16L at any time. The new values take effect when they are loaded. PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 50 Caution: Do not load these registers at the time the values are to be loaded into the counter/timer to ensure known operation. An initial count of 1 is not allowed. An initial count of 0 causes T16 to count from 0 to FFFFh to FFFEh. Transition from 0 to FFFFh is not a timeout condition. TC16H*256+TC16L Counts "Counter Enable" Command T16_OUT Switches to Its Initial Value (CTR1 D0) T16_OUT Toggles, Timeout Interrupt Figure 27. T16_OUT in Single-Pass Mode TC16H*256+TC16L TC16_OUT TC16H*256+TC16 TC16H*256+TC16L ... T16_OUT Toggles, Timeout Interrupt "Counter Enable" Command, T16_OUT Switches to Its Initial Value (CTR1 D0) T16_OUT Toggles, Timeout Interrupt Figure 28. T16_OUT in Modulo-N Mode T16 Demodulation Mode Program TC16L and TC16H to FFh. After T16 is enabled, and the first edge (rising, falling, or both depending on CTR1 D5; D4) is detected, T16 captures HI16 and LO16, reloads, and begins counting. If D6 of CTR2 Is 0 When a subsequent edge (rising, falling, or both depending on CTR1, D5; D4) is detected during counting, the current count in T16 is complemented and put into HI16 and LO16. When data is captured, one of the edge detect status bits (CTR1, D1; D0) is set, and an interrupt is generated if enabled (CTR2, D2). T16 is loaded with FFFFh and starts again. PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 51 This T16 mode is generally used to measure space time, the length of time between bursts of carrier signal (marks). If D6 of CTR2 Is 1 T16 ignores the subsequent edges in the input signal and continues counting down. A timeout of T8 causes T16 to capture its current value and generate an interrupt if enabled (CTR2, D2). In this case, T16 does not reload and continues counting. If the D6 bit of CTR2 is toggled (by writing a 0 then a 1 to it), T16 captures and reloads on the next edge (rising, falling, or both depending on CTR1, D5; D4), continuing to ignore subsequent edges. This T16 mode is generally used to measure mark time, the length of an active carrier signal burst. If T16 reaches 0, T16 continues counting from FFFFh. Meanwhile, a status bit (CTR2 D5) is set, and an interrupt timeout can be generated if enabled (CTR2 D1). Ping-Pong Mode This operation mode is only valid in Transmit Mode. T8 and T16 must be programmed in Single-Pass Mode (CTR0, D6; CTR2, D6), and Ping-Pong Mode must be programmed in CTR1, D3; D2. The user can begin the operation by enabling either T8 or T16 (CTR0, D7 or CTR2, D7). For example, if T8 is enabled, T8_OUT is set to this initial value (CTR1, D1). According to T8_OUT's level, TC8H or TC8L is loaded into T8. After the terminal count is reached, T8 is disabled, and T16 is enabled. T16_OUT then switches to its initial value (CTR1, D0), data from TC16H and TC16L is loaded, and T16 starts to count. After T16 reaches the terminal count, it stops, T8 is enabled again, repeating the entire cycle. Interrupts can be allowed when T8 or T16 reaches terminal control (CTR0, D1; CTR2, D1). To stop the Ping-Pong operation, write 00 to bits D3 and D2 of CTR1. See Figure 29. Note: Enabling Ping-Pong operation while the counter/timers are running might cause intermittent counter/timer function. Disable the counter/timers and then reset the status flags before instituting this operation. PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 52 Enable TC8 Enable Timeout Ping-Pong CTR1 D3,D2 TC16 Timeout Figure 29. Ping-Pong Mode Initiating Ping-Pong Mode First, make sure both counter/timers are not running. Set T8 into Single-Pass Mode (CTR0, D6), set T16 into Single-Pass Mode (CTR2, D6), and set the PingPong Mode (CTR1, D2; D3). These instructions do not have to be in any particular order. Finally, start Ping-Pong Mode by enabling either T8 (CTR0, D7) or T16 (CTR2, D7). See Figure 30. P34_INTERNAL MUX P34 CTR0 D0 T8_OUT T16_OUT CTR1, D2 CTR1 D5, D4 CTR1 D3 CTR2 D0 Figure 30. Output Circuit P35_INTERNAL P36_INTERNAL AND/OR/NOR/NAND Logic MUX CTR1 D6 MUX P35 P36 MUX The initial value of T8 or T16 must not be 1. If you stop the timer and start the timer again, reload the initial value to avoid an unknown previous value. PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 53 During Ping-Pong Mode The enable bits of T8 and T16 (CTR0, D7; CTR2, D7) are set and cleared alternately by hardware. The timeout bits (CTR0, D5; CTR2, D5) are set every time the counter/timers reach the terminal count. Interrupts The Z86D73 feature six different interrupts (Table 15). The interrupts are maskable and prioritized (Figure 31). The six sources are divided as follows: three sources are claimed by Port 3 lines P33-P31 and two by the counter/timers (Table 15). The Interrupt Mask Register (globally or individually) enables or disables the five interrupt requests. PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 54 P31 P32 P33 IRQ Register D6, D7 Interrupt Edge Select Timer 16 IRQ1 IRQ3 Timer 8 LowVoltage Detection IRQ2 IRQ0 IRQ4 IRQ5 IRQ IMR 5 IPR Global Interrupt Enable Interrupt Request Priority Logic Vector Select Figure 31. Interrupt Block Diagram PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 55 Table 15. Interrupt Types, Sources, and Vectors Name IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Source P32 P33 Vector Location 0,1 2,3 Comments External (P32), Rising Falling Edge Triggered External (P33), Falling Edge Triggered External (P31), Rising Falling Edge Triggered Internal Internal Internal P31, TIN 4,5 T16 T8 LVD 6,7 8,9 10,11 When more than one interrupt is pending, priorities are resolved by a programmable priority encoder controlled by the Interrupt Priority Register. An interrupt machine cycle is activated when an interrupt request is granted. As a result, all subsequent interrupts are disabled, and the Program Counter and Status Flags are saved. The cycle then branches to the program memory vector location reserved for that interrupt. All Z86D73 interrupts are vectored through locations in the program memory. This memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are masked, and the Interrupt Request register is polled to determine which of the interrupt requests require service. An interrupt resulting from AN1 is mapped into IRQ2, and an interrupt from AN2 is mapped into IRQ0. Interrupts IRQ2 and IRQ0 can be rising, falling, or both edge triggered. These interrupts are programmable by the user. The software can poll to identify the state of the pin. Programming bits for the Interrupt Edge Select are located in the IRQ Register (R250), bits D7 and D6. The configuration is indicated in Table 16. Table 16. IRQ Register* IRQ D7 0 0 1 1 D6 0 1 0 1 Interrupt Edge IRQ2 (P31) F F R R/F IRQ0 (P32) F R F R/F Notes: F = Falling Edge; R = Rising Edge *In stop mode, the comparators are turned off. PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 56 Clock The Z86D73 on-chip oscillator has a high-gain, parallel-resonant amplifier, for connection to a crystal, LC, ceramic resonator, or any suitable external clock source (XTAL1 = Input, XTAL2 = Output). The crystal must be AT cut, 1 MHz to 8 MHz maximum, with a series resistance (RS) less than or equal to 100 . The Z86D73 on-chip oscillator can be driven with a low-cost RC network or other suitable external clock source. For 32-kHz crystal operation, an external feedback (Rf) and a serial resistor (Rd) are required. See Figure 32. The crystal must be connected across XTAL1 and XTAL2 using the recommended capacitors (capacitance greater than or equal to 22 pF) from each pin to ground. The RC oscillator configuration is an external resistor connected from XTAL1 to XTAL2, with a frequency-setting capacitor from XTAL1 to ground (Figure 32). XTAL1 XTAL1 L C2 XTAL2 C2 XTAL2 LC C1, C2 = 22 pF L = 130 H * f = 3 MHz * XTAL1 R XTAL2 RC @ 3V VCC (TYP) C1 = 33 pF * R = 1K * C1 C1 C1 Ceramic Resonator or Crystal C1, C2 = 47 pF TYP * f = 8 MHz C1 XTAL1 Rf XTAL1 C2 XTAL2 Rd XTAL2 32 kHz XTAL C1 = 20 pF, C = 33 pF Rd = 56 - 470K Rf = 10 M External Clock * Preliminary value including pin parasitics Figure 32. Oscillator Configuration PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 57 Power-On Reset (POR) A timer circuit clocked by a dedicated on-board RC oscillator is used for the Power-On Reset (POR) timer function. The POR time allows VCC and the oscillator circuit to stabilize before instruction execution begins. The POR timer circuit is a one-shot timer triggered by one of three conditions: * * * Power Fail to Power OK status, including Waking up from VBO Standby Stop-Mode Recovery (if D5 of SMR = 1) WDT Timeout The POR timer is a nominal 5 ms. Bit 5 of the Stop-Mode Register determines whether the POR timer is bypassed after Stop-Mode Recovery (typical for external clock, RC and LC oscillators). HALT HALT turns off the internal CPU clock, but not the XTAL oscillation. The counter/ timers and external interrupts IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, and IRQ5 remain active. The devices are recovered by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit HALT Mode. After the interrupt service routine, the program continues from the instruction after the HALT. STOP This instruction turns off the internal clock and external crystal oscillation, thereby reducing the standby current to 10 A or less. STOP Mode is terminated only by a reset, such as WDT timeout, POR, SMR, or external reset. This condition causes the processor to restart the application program at address 000Ch. In order to enter STOP (or HALT) mode, first flush the instruction pipeline to avoid suspending execution in mid-instruction. Execute a NOP (Op Code = FFh) immediately before the appropriate sleep instruction, as follows: FF 6F NOP STOP ; clear the pipeline ; enter STOP Mode or FF 7F NOP HALT ; clear the pipeline ; enter HALT Mode PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 58 Port Configuration Register (PCON) The PCON register (Figure 33) configures the comparator output on Port 3. It is located in the expanded register 2 at Bank F, location 00. PCON (FH) 00H D7 D6 D5 D4 D3 D2 D1 D0 Comparator Output Port 3 0 P34, P37 Standard Output* 1 P34, P37 Comparator Output Port 1 0: Open-Drain 1: Push-Pull* Port 0 0: Open-Drain 1: Push-Pull* Reserved (Must be 1) * Default setting after reset Figure 33. Port Configuration Register (PCON) (Write Only) Comparator Output Port 3 (D0) Bit 0 controls the comparator used in Port 3. A 1 in this location brings the comparator outputs to P34 and P37, and a 0 releases the 0ort to its standard I/O configuration. Port 1 Output Mode (D1) Bit 1 controls the output mode of port 1. A 1 in this location sets the output to push-pull, and a 0 sets the output to open-drain. Port 0 Output Mode (D2) Bit 2 controls the output mode of port 0. A 1 in this location sets the output to push-pull, and a 0 sets the output to open-drain. PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 59 Stop-Mode Recovery Register (SMR) This register selects the clock divide value and determines the mode of StopMode Recovery (Figure 34). All bits are write only except bit 7, which is read only. Bit 7 is a flag bit that is hardware set on the condition of STOP recovery and reset by a power-on cycle. Bit 6 controls whether a low level or a high level at the XORgate input is required from the recovery source. Bit 5 controls the reset delay after recovery. Bits D2, D3, and D4 or the SMR register specify the source of the Stop-Mode Recovery signal. Bits D0 determines if SCLK/TCLK are divided by 16 or not. The SMR is located in Bank F of the Expanded Register Group at address 0Bh. SMR (0F) 0B D7 D6 D5 D4 D3 D2 D1 D0 SCLK/TCLK Divide-by-16 0 OFF * * 1 ON Reserved (Must be 0) Stop-Mode Recovery Source 000 POR Only * 001 Reserved 010 P31 011 P32 100 P33 101 P27 110 P2 NOR 0-3 111 P2 NOR 0-7 Stop Delay 0 OFF 1 ON * Stop Recovery Level * * * 0 Low * 1 High Stop Flag 0 POR * 1 Stop Recovery * * * Default setting after reset * * Default setting after reset and stop-mode recovery * * * At the XOR gate input Figure 34. Stop-Mode Recovery Register PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 60 SCLK/TCLK Divide-by-16 Select (D0) D0 of the SMR controls a divide-by-16 prescaler of SCLK/TCLK (Figure 35). The purpose of this control is to selectively reduce device power consumption during normal processor execution (SCLK control) and/or HALT Mode (where TCLK sources interrupt logic). After Stop-Mode Recovery, this bit is set to a 0. OSC /2 / 16 SMR, D0 Figure 35. SCLK Circuit SCLK TCLK Stop-Mode Recovery Source (D2, D3, and D4) These three bits of the SMR specify the wake-up source of the STOP recovery (Figure 36 and Table 17). PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 61 SMR D4 D3 D2 0 00 VCC SMR D4 D3 D2 0 10 P31 S1 SMR D4 D3 D2 0 11 P32 S2 SMR D4 D3 D2 1 00 P33 To IRQ1 S4 SMR D4 D3 D2 1 01 P27 SMR D4 D3 D2 110 P31 P32 P33 P31 P32 P33 P00 P07 P31 P32 P33 P00 P07 P31 P32 P33 P20 P21 P22 SMR2 D4 D3 D2 0 00 VCC SMR2 D4 D3 D2 0 01 P20 P23 P20 P27 SMR2 D4 D3 D2 0 10 S3 P31 P32 P33 SMR2 D4 D3 D2 0 11 SMR2 D4 D3 D2 1 00 P20 P23 P20 P27 SMR2 D4 D3 D2 1 01 SMR D4 D3 D2 1 11 SMR2 D4 D3 D2 110 SMR D6 SMR2 D4 D3 D2 1 11 To RESET and WDT Circuitry (Active Low) Figure 36. Stop-Mode Recovery Source SMR2 D6 PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 62 Table 17. Stop-Mode Recovery Source SMR:432 D4 0 0 0 0 1 1 1 1 D3 0 0 1 1 0 0 1 1 D2 0 1 0 1 0 1 0 1 Operation Description of Action POR and/or external reset recovery Reserved P31 transition P32 transition P33 transition P27 transition Logical NOR of P20 through P23 Logical NOR of P20 through P27 Note: Any Port 2 bit defined as an output drives the corresponding input to the default state. This condition allows the remaining inputs to control the AND/OR function. Refer to SMR2 register on page 63 for other recover sources. Stop-Mode Recovery Delay Select (D5) This bit, if low, disables the 5 ms RESET delay after Stop-Mode Recovery. The default configuration of this bit is 1. If the "fast" wake up is selected, the StopMode Recovery source must be kept active for at least 5 TpC. Stop-Mode Recovery Edge Select (D6) A 1 in this bit position indicates that a High level on any one of the recovery sources wakes the Z86D73 from STOP Mode. A 0 indicates Low level recovery. The default is 0 on POR. Cold or Warm Start (D7) This bit is read only. It is set to 1 when the device is recovered from Stop Mode. The bit is set to 0 when the device reset is other than Stop Mode Recovery (SMR). PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 63 Stop-Mode Recovery Register 2 (SMR2) This register determines the mode of Stop-Mode Recovery for SMR2 (Figure 37). SMR2 (0F) DH D7 D6 D5 D4 D3 D2 D1 D0 Reserved (Must be 0) Reserved (Must be 0) Stop-Mode Recovery Source 2 000 POR Only * 001 NAND P20, P21, P22, P23 010 NAND P20, P21, P22, P23, P24, P25, P26, P27 011 NOR P31, P32, P33 100 NAND P31, P32, P33 101 NOR P31, P32, P33, P00, P07 110 NAND P31, P32, P33, P00, P07 111 NAND P31, P32, P33, P20, P21, P22 Reserved (Must be 0) Recovery Level * * 0 Low * 1 High Reserved (Must be 0) Note: If used in conjunction with SMR, either of the two specified events causes a Stop-Mode Recovery. * Default setting after reset * * At the XOR gate input Figure 37. Stop-Mode Recovery Register 2 ((0F) DH:D2-D4, D6 Write Only) If SMR2 is used in conjunction with SMR, either of the specified events causes a Stop-Mode Recovery. Note: Port pins configured as outputs are ignored as an SMR or SMR2 recovery source. For example, if the NAND or P23-P20 is selected as the recovery source and P20 is configured as an output, the remaining SMR pins (P23-P21) form the NAND equation. PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 64 Watch-Dog Timer Mode Register (WDTMR) The WDT is a retriggerable one-shot timer that resets the Z8 if it reaches its terminal count. The WDT must initially be enabled by executing the WDT instruction. On subsequent executions of the WDT instruction, the WDT is refreshed. The WDT circuit is driven by an on-board RC oscillator or external oscillator from the XTAL1 pin. The WDT instruction affects the Zero (Z), Sign (S), and Overflow (V) flags. The POR clock source is selected with bit 4 of the WDT register. Bits 0 and 1 control a tap circuit that determines the minimum timeout period. Bit 2 determines whether the WDT is active during HALT, and Bit 3 determines WDT activity during STOP. Bits 5 through 7 are reserved (Figure 38). This register is accessible only during the first 61 processor cycles (122 XTAL clocks) from the execution of the first instruction after Power-On-Reset, Watch-Dog Reset, or a Stop-Mode Recovery (Figure 37). After this point, the register cannot be modified by any means (intentional or otherwise). The WDTMR cannot be read. The register is located in Bank F of the Expanded Register Group at address location 0Fh. It is organized as shown in Figure 38. WDTMR (0F) 0F D7 D6 D5 D4 D3 D2 D1 D0 WDT TAP INT RC OSC 00 5 ms min 01* 10 ms min 10 20 ms min 11 80 ms min WDT During HALT 0 OFF 1 ON * WDT During STOP 0 OFF 1 ON * Reserved (Must be 0) Reserved (Must be 0) * Default setting after reset Figure 38. Watch-Dog Timer Mode Register (Write Only) PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 65 WDT Time Select (D0, D1) This bit selects the WDT time period. It is configured as indicated in Table 18. Table 18. WDT Time Select* D1 0 0 1 1 D0 0 1 0 1 Timeout of Internal RC OSC 5 ms min 10 ms min 20 ms min 80 ms min Timeout of XTAL Clock 256 TpC 512 Tpc 1024 TpC 4096 TpC Note: *TpC = XTAL clock cycle. The default on reset is 10 ms. WDTMR During HALT (D2) This bit determines whether or not the WDT is active during HALT Mode. A 1 indicates active during HALT. The default is 1. See Figure 39. PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 66 5 Clock Filter *CLR2 CLK 18 Clock RESET RESET Generator Internal RESET Active High CK Source Select (WDTMR) XTAL INTERNAL RC OSC. VDD VBO/VLV 2V REF. WDT From Stop Mode Recovery Source Stop Delay Select (SMR) + Low Operating Voltage Det. M U X WDT TAP SELECT POR 5 ms 10 ms 20 ms 80 ms CLK WDT/POR Counter Chain *CLR1 VCC 12-ns Glitch Filter * CLR1 and CLR2 enable the WDT/POR and 18 Clock Reset timers upon a Low-to-High input translation. Figure 39. Resets and WDT WDTMR During STOP (D3) This bit determines whether or not the WDT is active during STOP Mode. Because the XTAL clock is stopped during STOP Mode, the on-board RC has to be selected as the clock source to the WDT/POR counter. A 1 indicates active during STOP. The default is 1. Clock Source for WDT (D4) This bit determines which oscillator source is used to clock the internal POR and WDT counter chain. If the bit is a 1, the internal RC oscillator is bypassed, and the POR and WDT clock source is driven from the external pin, XTAL1. The default configuration of this bit is 0, which selects the RC oscillator. PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 67 Mask Selectable Options There are seven Mask Selectable Options to choose from based on ROM code requirements. These are listed in Table 19. Table 19. Mask Selectable Options RC/Other 32 kHz XTAL Port 00-03 Pull-Ups Port 04-07 Pull-Ups Port 10-13 Pull-Ups Port 14-17 Pull-Ups Port 20-27 Pull-Ups Port 3: Pull-Ups Port 0: 0-3 Normal Mode (0.5 VDD Input Threshold) versus Mouse Mode (0.4 VDD Input Threshold) RC/XTAL On/Off On/Off On/Off On/Off On/Off On/Off On/Off Brown-Out Voltage/Standby An on-chip Voltage Comparator checks that the VCC is at the required level for correct operation of the device. Reset is globally driven when VCC falls below VBO. A small drop in VCC causes the XTAL1 and XTAL2 circuitry to stop the crystal or resonator clock. Typical Low-Voltage power consumpion in this Low Voltage Standby mode (ILV) is about 20 A. If the VCC is allowed to stay above Vram, the RAM content is preserved. When the power level is returned to above VBO, the device performs a POR and functions normally. Low-Voltage Detection and Flag A Low-Voltage Detection circuit can be used optionally when the voltage decreases to VLVD. Expanded Register Bank 0Dh register 0Ch bits 0 and 1 are used for this option. Bit D0 is used to enable/disable this function; bit D1 is the status flag bit of the LVD. PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 68 Expanded Register File Control Registers (0D) The expanded register file control registers (0D) are shown in Figure 40 through Figure 43. CTR0 (0D) 0H D7 D6 D5 D4 D3 D2 D1 D0 0 P34 as Port Output * 1 Timer8 Output 0 Disable T8 Timeout Interrupt 1 Enable T8 Timeout Interrupt 0 Disable T8 Data Capture Interrupt 1 Enable T8 Data Capture Interrupt 00 01 10 11 R R W W SCLK on T8 SCLK/2 on T8 SCLK/4 on T8 SCLK/8 on T8 0 No T8 Counter Timeout 1 T8 Counter Timeout Occurred 0 No Effect 1 Reset Flag to 0 0 Modulo-N 1 Single Pass R R W W * Default setting after reset 0 T8 Disabled * 1 T8 Enabled 0 Stop T8 1 Enable T8 Figure 40. TC8 Control Register ((0D) OH: Read/Write Except Where Noted) PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 69 CTR1 (0D) 1H D7 D6 D5 D4 D3 D2 D1 D0 Transmit Mode R/W 0 T16_OUT is 0 initially 1 T16_OUT is 1 initially Demodulation Mode R 0 No Falling Edge Detection R 1 Falling Edge Detection W 0 No Effect W 1 Reset Flag to 0 Transmit Mode R/W 0 T8_OUT is 0 initially 1 T8_OUT is 1 initially Demodulation Mode R 0 No Rising Edge Detection R 1 Rising Edge Detection W 0 No Effect W 1 Reset Flag to 0 Transmit Mode 0 0 Normal Operation 0 1 Ping-Pong Mode 1 0 T16_OUT = 0 1 1 T16_OUT = 1 Demodulation Mode 0 0 No Filter 0 1 4 SCLK Cycle Filter 1 0 8 SCLK Cycle Filter 1 1 Reserved Transmit Mode/T8/T16 Logic 0 0 AND 0 1 OR 1 0 NOR 1 1 NAND Demodulation Mode 0 0 Falling Edge Detection 0 1 Rising Edge Detection 1 0 Both Edge Detection 1 1 Reserved Transmit Mode 0 P36 as Port Output * 1 P36 as T8/T16_OUT Demodulation Mode 0 P31 as Demodulator Input 1 P20 as Demodulator Input * Default setting after reset Transmit/Demodulation Mode 0 Transmit Mode * 1 Demodulation Mode Figure 41. T8 and T16 Common Control Functions ((0D) 1h: Read/Write) PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 70 Notes: Care must be taken in differentiating Transmit Mode from Demodulation Mode. Depending on which of these two modes is operating, the CTR1 bit has different functions. Changing from one mode to another cannot be done without disabling the counter/timers. CTR2 (0D) 02H D7 D6 D5 D4 D3 D2 D1 D0 0 P35 is Port Output * 1 P35 is TC16 Output 0 Disable T16 Timeout Interrupt 1 Enable T16 Timeout Interrupt 0 Disable T16 Data Capture Interrupt 1 Enable T16 Data Capture Interrupt 0 0 1 1 R R W W 0 1 0 1 0 1 0 1 SCLK on T16 SCLK/2 on T16 SCLK/4 on T16 SCLK/8 on T16 No T16 Timeout T16 Timeout Occurs No Effect Reset Flag to 0 Transmit Mode 0 Modulo-N for T16 0 Single Pass for T16 Demodulator Mode 0 T16 Recognizes Edge 1 T16 Does Not Recognize Edge R R W W 0 1 0 1 T16 Disabled * T16 Enabled Stop T16 Enable T16 * Default setting after reset Figure 42. T16 Control Register ((0D) 2h: Read/Write Except Where Noted) PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 71 LVD (0D) 0CH D7 D6 D5 D4 D3 D2 D1 D0 Low-Voltage Detection at VBO + 0.4 V 0: Disable * 1: Enable LVD Flag (Read only) 0: LVD flag reset * 1: LVD flag set Reserved (Must be 0) * Default Figure 43. Low-Voltage Detection Note: Do not modify register P01M while checking a low-voltage condition. Switching noise of both ports 0 and 1 together might trigger the LVD flag. PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 72 Expanded Register File Control Registers (0F) The expanded register file control registers (0F) are shown in Figure 44 through Figure 57. SMR (0F) 0B D7 D6 D5 D4 D3 D2 D1 D0 SCLK/TCLK Divide-by-16 0 OFF * 1 ON Reserved (Must be 0) Stop-Mode Recovery Source 000 POR Only * 001 Reserved 010 P31 011 P32 100 P33 101 P27 110 P2 NOR 0-3 111 P2 NOR 0-7 Stop Delay 0 OFF 1 ON * Stop Recovery Level * * * 0 Low * 1 High Stop Flag 0 POR * 1 Stop Recovery * * * Default setting after reset * * Default setting after reset and stop-mode recovery * * * At the XOR gate input Figure 44. Stop-Mode Recovery Register ((0F) 0Bh: D6-D0=Write Only, D7=Read Only) PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 73 SMR2 (0F) DH D7 D6 D5 D4 D3 D2 D1 D0 Reserved (Must be 0) Reserved (Must be 0) Stop-Mode Recovery Source 2 000 POR Only * 001 NAND P20, P21, P22, P23 010 NAND P20, P21, P22, P23, P24, P25, P26, P27 011 NOR P31, P32, P33 100 NAND P31, P32, P33 101 NOR P31, P32, P33, P00, P07 110 NAND P31, P32, P33, P00, P07 111 NAND P31, P32, P33, P20, P21, P22 Reserved (Must be 0) Recovery Level * * 0 Low 1 High Reserved (Must be 0) Note: If used in conjunction with SMR, either of the two specified events causes a Stop-Mode Recovery. * Default setting after reset * * At the XOR gate input Figure 45. Stop-Mode Recovery Register 2 ((0F) 0Dh:D2-D4, D6 Write Only) PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 74 WDTMR (0F) 0F D7 D6 D5 D4 D3 D2 D1 D0 WDT TAP INT RC OSC 00 5 ms min 01* 10 ms min 10 20 ms min 11 80 ms min WDT During HALT 0 OFF 1 ON * WDT During STOP 0 OFF 1 ON * Reserved (Must be 0) Reserved (Must be 0) * Default setting after reset Figure 46. Watch-Dog Timer Register ((0F) 0Fh: Write Only) PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 75 PCON (FH) 00H D7 D6 D5 D4 D3 D2 D1 D0 Comparator Output Port 3 0 P34, P37 Standard Output * 1 P34, P37 Comparator Output Port 1 0: Open-Drain 1: Push-Pull* Port 0 0: Open-Drain 1: Push-Pull * Reserved (Must be 1) * Default setting after reset Figure 47. Port Configuration Register (PCON) ((0F) 0h: Write Only) R246 P2M D7 D6 D5 D4 D3 D2 D1 D0 P27-P20 I/O Definition 0 Defines bit as OUTPUT 1 Defines bit as INPUT * * Default setting after reset Figure 48. Port 2 Mode Register (F6h: Write Only) PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 76 R247 P3M D7 D6 D5 D4 D3 D2 D1 D0 0: Port 2 Open Drain * 1: Port 2 Push-Pull 0= P31, P32 Digital Mode 1= P31, P32 Analog Mode Reserved (Must be 0) 00: P33 = Input P34 = Output 01: P33 = Input 10: P34 = DM 11: Reserved Reserved (Must be 0) Reserved (Must be 0) * Default setting after reset Figure 49. Port 3 Mode Register (F7h: Write Only) PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 77 R248 P01M D7 D6 D5 D4 D3 D2 D1 D0 P00-P03 Mode 00: Output 01: Input * 1X: A11-A8 Stack Selection 0: External 1: Internal * P17-P10 Mode 00: Byte Output 01: Byte Input 10: AD7-AD0 11: High-Impedance AD7-AD0, AS, DS, R/W, A11-A8, A15-A12, if selected External Memory Timing 0: Normal * 1: Extended P07-P04 Mode 00: Output 01: Input * 1X: A15-A12 * Default setting after reset; only P00 and P07 are available on Z86L71 Figure 50. Port 0 and 1 Mode Register (F8h: Write Only) PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 78 R249 IPR D7 D6 D5 D4 D3 D2 D1 D0 Interrupt Group Priority 000 Reserved 001 C > A > B 010 A > B >C 011 A > C > B 100 B > C > A 101 C > B > A 110 B > A > C 111 Reserved IRQ1, IRQ4, Priority (Group C) 0: IRQ1 > IRQ4 1: IRQ4 > IRQ1 IRQ0, IRQ2, Priority (Group B) 0: IRQ2 > IRQ0 1: IRQ0 > IRQ2 IRQ3, IRQ5, Priority (Group A) 0: IRQ5 > IRQ3 1: IRQ3 > IRQ5 Reserved; must be 0 Figure 51. Interrupt Priority Register (F9h: Write Only) PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 79 R250 IRQ D7 D6 D5 D4 D3 D2 D1 D0 IRQ0 = P32 Input IRQ1 = P33 Input IRQ2 = P31 Input IRQ3 = T16 IRQ4 = T8 IRQ5 = LVD Inter Edge P31 P32 = 00 P31 P32 = 01 P31 P32 = 10 P31 P32 = 11 Figure 52. Interrupt Request Register (FAh: Read/Write) R251 IMR D7 D6 D5 D4 D3 D2 D1 D0 1 Enables IRQ5-IRQ0 (D0 = IRQ0) Reserved (Must be 0) 0 Master Interrupt Disable * 1 Master Interrupt Enable * * * Default setting after reset * * Only by using E1, D1 instruction; D1 is required before changing the IMR register Figure 53. Interrupt Mask Register (FBh: Read/Write) PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 80 R252 Flags D7 D6 D5 D4 D3 D2 D1 D0 User Flag F1 User Flag F2 Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Tag Zero Flag Carry Flag Figure 54. Flag Register (FCh: Read/Write) R253 RP D7 D6 D5 D4 D3 D2 D1 D0 Expanded Register Bank Pointer Working Register Pointer Default setting after reset = 0000 0000 Figure 55. Register Pointer (FDh: Read/Write) PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 81 R254 SPH D7 D6 D5 D4 D3 D2 D1 D0 General-Purpose Register or Stack Pointer High (SP15-SP8) if external memory is used Figure 56. Stack Pointer High (FEh: Read/Write) R255 SPL D7 D6 D5 D4 D3 D2 D1 D0 Stack Pointer Low Byte (SP7-SP0) Figure 57. Stack Pointer Low (FFh: Read/Write) PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 82 Package Information Package information is shown in Figure 58, Figure 59, Figure 60, and Figure 61. Figure 58. 40-Pin DIP Package Diagram Figure 59. 44-Pin PLCC Package Diagram PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 83 Figure 60. 44-Pin QFP Package Design PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 84 D 48 25 c E H 1 24 Detail A A2 A1 A CONTROLLING DIMENSIONS : MM LEADS ARE COPLANAR WITHIN .004 INCH SEATING PLANE e b L 0-8 Detail A Figure 61. 48-Pin SSOP Package Design Note: Please check with ZiLOG on the actual bonding diagram and coordinate for chip-on-board assembly. PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 85 Ordering Information Table 20. Z86D73 Ordering Information 8.0 MHz 40-Pin DIP Z86D7308PSC Die Form 8.0 MHz 44-Pin PLCC Z86D7308VSC Please contact ZiLOG. 8.0 MHz 44-Pin QFP Z86D7308FSC 8.0 MHz 48-Pin SSOP Z86D7308HSC For fast results, contact your local ZiLOG sales office for assistance in ordering the part desired. Codes Package P = Plastic DIP F = Plastic Quad Flat Pack H = SSOP V = Plastic Chip Carrier Speed 8 = 8 MHz Environmental C = Plastic Standard Temperature S = 0 C to +70 C Example Z 86D73 08 P S C is a Z86D73, 8 MHz, DIP, 0 C to 70 C, Plastic Standard Flow Environmental Flow Temperature Package Speed Product Number ZiLOG Prefix PS019402-1103 P R E L I M I N A R Y Z86D73 40/44/48-Pin Low-Voltage IR OTP 86 Precharacterization Product The product represented by this document is newly introduced and ZiLOG has not completed the full characterization of the product. The document states what ZiLOG knows about this product at this time, but additional features or nonconformance with some aspects of the document might be found, either by ZiLOG or its customers in the course of further application and characterization work. In addition, ZiLOG cautions that delivery might be uncertain at times, due to start-up yield issues. ZiLOG, Inc. 532 Race Street San Jose, CA 95126-3432 Telephone: (408) 558-8500 FAX: 408 558-8300 Internet: HTTP://WWW.ZILOG.COM PS019402-1103 P R E L I M I N A R Y |
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