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| 06/26/01 Errata: CS4220/21/23/24 Data Sheet Reference CS4220/21 Data Sheet revision DS284PP3 dated APR '00 and CS4223/24 Data Sheet revision DS290PP3 dated APR '00 The CS4220/21/23/24 exhibits a one-sample delay between the left and right channels. The phase difference introduced by the DAC is complementary to that introduced by the ADC so that stereo signals which pass through both converters in a loopback configuration are reconstructed with no phase error between the channels. The group delays are listed below. ADC Decimation Filter Characteristics Group Delay, left channel Group Delay, right channel tgd tgd 18 / Fs 17 / Fs s s DAC Combined Digital and Analog Filter Characteristics Group Delay, left channel Group Delay, right channel tgd tgd 26 / Fs 27 / Fs s s Workarounds: Workaround #1: In situations where software can be used to manipulate the audio content, it may be feasible to introduce a one-sample delay in one channel of the ADC output and to introduce a complementary delay in the DAC input. The input to the DSP and the output of the DAC would then both be free of errors. Workaround # 2: In situations where a normal signal must be fed to the DAC and the DAC is operating in slave mode, it is possible to eliminate the phase shift by inverting the LRCK signal and swapping the left and right DAC analog outputs. See Figure 1. We do not have a comparable hardware workaround for the ADC. Cirrus Logic P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com ER284B2 Jun '01 1 Receiver or DSP SDOUT SDIN DAC AMPLIFIER AOUT Left AOUT Right Left Input Right Input LRCK out LRCK in Figue 1. Typical application of workaround #2. Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm or email: proaudio@cystal.cirrus.com 2 ER284B2 |
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