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Integrated Circuit Systems, Inc.
ICS8344I
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
FEATURES
* 24 LVCMOS outputs, 7 typical output impedance * 2 selectable differential clock input pairs for redundant clock applications * CLKx, nCLKx pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL * Maximum output frequency up to 100MHz * Translates any single-ended input signal to LVCMOS with resistor bias on nCLK input * Multiple output enable pins for disabling unused outputs in reduced fanout applications * Output skew: 275ps (maximum) * Part-to-part skew: 600ps (maximum) * Bank skew: 150ps (maximum) * 3.3V, 2.5V or mixed 3.3V, 2.5V operating supply modes * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS8344I is a low voltage, low skew fanout buffer and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8344I has two selectable clock inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs can accept most standard differential input levels. The ICS8344I is designed to translate any differential signal levels to LVCMOS levels. The low impedance LVCMOS outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased to 48 by utilizing the ability of the outputs to drive two series terminated lines. Redundant clock applications can make use of the dual clock input. The dual clock inputs also facilitate board level testing. ICS8344I is characterized at full 3.3V, full 2.5V and mixed 3.3V input and 2.5V output operating supply modes.
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Guaranteed output and part-to-part skew characteristics make the ICS8344I ideal for those clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
PIN ASSIGNMENT
Q8 Q9 VDDO GND Q10 Q11 Q12 Q13 VDDO GND Q14 Q15
CLK_SEL CLK0 nCLK0 CLK1 nCLK1 Q16 Q17 VDDO GND Q18 Q19 Q20 Q21 VDDO GND Q22 Q23
0 1 Q0 - Q7
OE1 Q8 - Q15 OE2 Q16 - Q23 OE3
48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24
ICS8344I
Q7 Q6 VDDO GND Q5 Q4 Q3 Q2 VDDO GND Q1 Q0
48-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
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OE1 OE2 OE3 CLK0 nCLK0 VDD GND CLK1 nCLK1 VDD GND CLK_SEL
REV. A AUGUST 9, 2001
Integrated Circuit Systems, Inc.
ICS8344I
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number 1, 2, 5, 6 7, 8, 11, 12 3, 9, 28, 34, 39, 45 4, 10, 14,18, 27, 33, 40, 46 13 15, 19 16 17 20 21 22 23 24 25, 26, 29, 30 31, 32, 35, 36 37, 38, 41, 42 43, 44, 47, 48 Name Q16, Q17, Q18, Q19 Q20, Q21, Q22, Q23 VDDO GND CLK_SEL VDD nCLK1 CLK1 nCLK0 CLK0 OE3 OE2 OE1 Q0, Q1, Q2, Q3 Q4, Q5, Q6, Q7 Q8, Q9, Q10, Q11 Q12, Q13, Q14, Q15 Type Output Power Power Input Power Input Input Input Input Input Input Input Output Output Description Q16 thru Q23 outputs. 7 typical output impedance. Output supply pins. Connect 3.3V or 2.5V. Power supply ground. Connect to ground. Clock select input. When HIGH, selects CLK1, nCLK1 inputs. Pulldown When LOW, selects CLK0, nCLK0. LVTTL / LVCMOS interface levels. Positive supply pins. Connect 3.3V or 2.5V. Pullup Pullup Inver ting differential clock input. Inver ting differential clock input. Pulldown Non-inver ting differential clock input.. Pulldown Non-inver ting differential clock input.. Output enable. Controls enabling and disabling of outputs Pullup Q16 thru Q23. Output enable. Controls enabling and disabling of outputs Pullup Q8 thru Q15. Output enable. Controls enabling and disabling of outputs Pullup Q0 thru Q7. Q0 thru Q7 outputs. 7 typical output impedance. Q8 thru Q15 outputs. 7 typical output impedance.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN Parameter CLK0, nCLK0, CLK1, nCLK1 Input Capacitance CLK_SEL, OE1, OE2, OE3 Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor Output Impedance Test Conditions Minimum Typical Maximum 4 4 20 51 51 7 Units pF pF pF K K
CPD RPULLUP RPULLDOWN ROUT
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REV. A AUGUST 9, 2001
Integrated Circuit Systems, Inc.
ICS8344I
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
TABLE 3A. OUTPUT ENABLE FUNCTION TABLE
Bank 1 Input OE1 0 1 Output Q0-Q7 Hi-Z Enabled Input OE2 0 1 Bank 2 Output Q8-Q15 Hi-Z Enabled Input OE3 0 1 Bank 3 Output Q16-Q23 Hi-Z Enabled
TABLE 3B. CLOCK SELECT FUNCTION TABLE
Control Input CLK_SEL 0 1 CLK0, nCLK0 Selected De-selected Clock CLK1, nCLK1 De-selected Selected
TABLE 3C. CLOCK INPUTS FUNCTION TABLE
Inputs OE1, OE2, OE3 1 1 1 1 1 CLK 0 1 0 1 Biased; NOTE 1 nCLK 1 0 Biased; NOTE 1 Biased; NOTE 1 0 Outputs Q0 thru Q23 LOW HIGH LOW HIGH HIGH Input to Output Mode Differential to Single Ended Differential to Single Ended Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting
1 Biased; NOTE 1 1 LOW Single Ended to Differential Inver ting NOTE 1: Please refer to the Application Information section on page 13, Figure 8, which discusses wiring the differential input to accept single ended levels.
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REV. A AUGUST 9, 2001
Integrated Circuit Systems, Inc.
ICS8344I
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
4.6V -0.5V to VDD + 0.5V -0.5V to VDDO + 0.5V 47.9C/W (0lfpm) -65C to 150C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol VDD VDDO IDD Parameter Positive Supply Voltage Output Supply Voltage Quiescent Power Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 95 Units V V mA
TABLE 4B. LVCMOS DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol VIH VIL IIH IIL VOH VOL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage Output Low Voltage CLK_SEL, OE1, OE2, OE3 CLK_SEL, OE1, OE2, OE3 OE1, OE2, OE3 CLK_SEL OE1, OE2, OE3 CLK_SEL Test Conditions Minimum 2 -0.3 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465, VIN = 0V VDD = 3.465, VIN = 0V VDD = VDDO = 3.135V IOH = -36mA VDD = VDDO = 3.135V IOL = 36mA -150 -5 2.6 0.6 Typical Maximum 3.8 0.8 5 150 Units V V A A A A V V
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current nCLK0, nCLK1 CLK0, CLK1 nCLK0, nCLK1 CLK0, CLK1 -150 -5 0.15 1.3 VDD - 0.85 Test Conditions Minimum Typical Maximum 5 150 Units A A A A V V
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 VCMR NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
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REV. A AUGUST 9, 2001
Integrated Circuit Systems, Inc.
ICS8344I
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Test Conditions Minimum Typical Maximum Units 100 f 100MHz f 100MHz 2.6 2.4 4.3 4.3 150 275 600 30% to 70% 30% to 70% 300 300 40% f = 66.7MHz f = 66.7MHz 1700 1400 60% 5 4 MHz ns ns ps ps ps ps ps % ns ns
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol Parameter fMAX tpLH tpHL Maximum Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Bank Skew; NOTE 2, 6 Output Skew; NOTE 3, 6 Par t-to-Par t Skew; NOTE 4, 6 Output Rise Time; NOTE 5 Output Fall Time; NOTE 5 Output Duty Cycle Output Enable Time; NOTE 5 Output Disable TIme; NOTE 5
tsk(b) tsk(o) tsk(pp)
tR tF odc tEN tDIS
All parameters measured at 100MHz unless noted otherwise. NOTE 1: Measured from the diffferential input crossing point to VDDO/2. NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A AUGUST 9, 2001
Integrated Circuit Systems, Inc.
ICS8344I
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Test Conditions Minimum 3.135 2.375 Typical 3.3 2.5 Maximum 3.465 2.625 95 Units V V mA
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = -40C TO 85C
Symbol VDD VDDO IDD Parameter Positive Supply Voltage Output Supply Voltage Quiescent Power Supply Current
TABLE 4E. LVCMOS DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = -40C TO 85C
Symbol VIH VIL IIH IIL VOH Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK_SEL, OE1, OE2, OE3 CLK_SEL, OE1, OE2, OE3 OE1, OE2, OE3 CLK_SEL OE1, OE2, OE3 CLK_SEL Test Conditions Minimum 2 -0.3 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465, VIN = 0V VDD = 3.465, VIN = 0 VDD = 3.135V, VDDO = 2.375V IOH = -27mA VDD = 3.135V, VDDO = 2.365V IOL = 27mA -150 -5 2 Typical Maximum 3.8 0.8 5 150 Units V V A A A A V
Output High Voltage
VOL
Output Low Voltage
0.63
V
TABLE 4F. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = -40C TO 85C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current nCLK0, nCLK1 CLK0, CLK1 nCLK0, nCLK1 CLK0, CLK1 -150 -5 0.15 1.3 VDD - 0.85 Test Conditions Minimum Typical Maximum 5 150 Units A A A A V V
Peak-to-Peak Input Voltage
VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
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REV. A AUGUST 9, 2001
Integrated Circuit Systems, Inc.
ICS8344I
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = -40C TO 85C
Symbol Parameter fMAX tpLH tpHL Maximum Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Bank Skew; NOTE 2, 6 Output Skew; NOTE 3, 6 Par t-to-Par t Skew; NOTE 4, 6 Output Rise Time; NOTE 5 Output Fall Time; NOTE 5 Output Duty Cycle Output Enable Time; NOTE 5 Output Disable TIme; NOTE 5 f = 66.7MHz f = 66.7MHz 30% to 70% 30% to 70% 300 300 40% f 100MHz f 100MHz 2.6 2.6 Test Conditions Minimum Typical Maximum Units 100 4.5 4.5 150 275 600 1700 1400 60% 6 6 MHz ns ns ps ps ps ps ps % ns ns
tsk(b) tsk(o) tsk(pp)
tR tF odc tEN tDIS
All parameters measured at 100MHz unless noted otherwise. NOTE 1: Measured from the diffferential input crossing point to VDDO/2. NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A AUGUST 9, 2001
Integrated Circuit Systems, Inc.
ICS8344I
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Test Conditions Minimum 2.375 2.375 Typical 2.5 2.5 Maximum 2.625 2.625 95 Units V V mA
TABLE 4G. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = -40C TO 85C
Symbol VDD VDDO IDD Parameter Positive Supply Voltage Output Supply Voltage Quiescent Power Supply Current
TABLE 4H. LVCMOS DC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = -40C TO 85C
Symbol VIH VIL IIH IIL VOH VOL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage Output Low Voltage CLK_SEL, OE1, OE2, OE3 CLK_SEL, OE1, OE2, OE3 OE1, OE2, OE3 CLK_SEL OE1, OE2, OE3 CLK_SEL Test Conditions Minimum 2 -0.3 VDD = VIN = 2.625V VDD = VIN = 2.625V VDD = 2.625, VIN = 0V VDD = 2.625, VIN = 0V VDD = VDDO = 2.375V IOH = -27mA VDD = VDDO = 2.375V IOL = 27mA -150 -5 2 0.6 Typical Maximum 2.9 0.8 5 150 Units V V A A A A V V
TABLE 4I. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = -40C TO 85C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current nCLK0, nCLK1 CLK0, CLK1 nCLK0, nCLK1 CLK0, CLK1 -150 -5 0.15 1.3 VDD - 0.85 Test Conditions Minimum Typical Maximum 5 150 Units A A A A V V
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 VCMR NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
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REV. A AUGUST 9, 2001
Integrated Circuit Systems, Inc.
ICS8344I
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
TABLE 5C. AC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = -40C TO 85C
Symbol Parameter fMAX tpLH tpHL Maximum Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Bank Skew; NOTE 2, 6 Output Skew; NOTE 3, 6 Par t-to-Par t Skew; NOTE 4, 6 Output Rise Time; NOTE 5 Output Fall Time; NOTE 5 Output Duty Cycle Output Enable Time; NOTE 5 Output Disable TIme; NOTE 5 f = 66.7MHz f = 66.7MHz 30% to 70% 30% to 70% 300 300 40% f 100MHz f 100MHz 2.7 2.7 Test Conditions Minimum Typical Maximum Units 100 4.3 4.3 150 275 600 1700 1400 60% 6 6 MHz ns ns ps ps ps ps ps % ns ns
tsk(b) tsk(o) tsk(pp)
tR tF odc tEN tDIS
All parameters measured at 100MHz unless noted otherwise. NOTE 1: Measured from the diffferential input crossing point to VDDO/2. NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A AUGUST 9, 2001
Integrated Circuit Systems, Inc.
ICS8344I
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
VDD
VDDO
SCOPE LVCMOS
VDD = +1.65V VDDO = +1.65V
Qx
GND = -1.65V
FIGURE 1A - 3.3V OUTPUT LOAD TEST CIRCUIT
VDDO
SCOPE LVCMOS
Qx
VDDO = +1.25V
GND = -1.25V
FIGURE 1B - 2.5V OUTPUT LOAD TEST CIRCUIT
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REV. A AUGUST 9, 2001
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ICS8344I
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
V DD
VDDO
SCOPE LVCMOS
VDD = +2.05V VDDO = +1.25V Qx
GND = -1.25V
FIGURE 1C - 3.3V/2.5V OUTPUT LOAD TEST CIRCUIT
VDD
CLK0, CLK1
V
nCLK0, nCLK1
PP
Cross Points
V
CMR
GND
FIGURE 2 - DIFFERENTIAL INPUT LEVEL
Qx
Qy
tsk(o)
FIGURE 3 - OUTPUT SKEW
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REV. A AUGUST 9, 2001
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ICS8344I
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
PART 1 Qx
PART 2 Qy
tsk(pp)
FIGURE 4 - PART-TO-PART SKEW
70%
70% V
SWING
30% Clock Inputs and Outputs trise tfall
AND
30%
FIGURE 5 - INPUT
OUTPUT RISE
AND
FALL TIME
CLK0, CLK1
nCLK0, nCLK1
V
Q0 - Q23
DDOx
/2
tp
LH
tp
HL
FIGURE 6 - PROPAGATION DELAY
CLK0, CLK1, Q0 - Q23 nCLK0, nCLK1
Pulse Width t t odc = t
PW PERIOD
PERIOD
FIGURE 7 - odc & tPERIOD
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REV. A AUGUST 9, 2001
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ICS8344I
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 8 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD VCC R1 1K R1 1K + V_REF V_REF C1 C1 0.1uF 0.1uF R2 1K R2 1K +
CLK_IN CLK_IN
FIGURE 8 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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REV. A AUGUST 9, 2001
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ICS8344I
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute) 0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8344I is: 1,449
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REV. A AUGUST 9, 2001
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ICS8344I
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
PACKAGE OUTLINE - Y SUFFIX
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BCC SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L q ccc 0.45 0 0.05 1.35 0.17 0.09 9.00 BASIC 7.00 BASIC 5.50 9.00 BASIC 7.00 BASIC 5.50 0.5 BASIC 0.60 0.75 7 0.08 1.40 0.22 MINIMUM NOMINAL 48 1.60 0.15 1.45 0.27 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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REV. A AUGUST 9, 2001
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ICS8344I
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS8344BYI ICS8344BYI-T Marking ICS8344BYI ICS8344BYI Package 48 Lead LQFP 48 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature -40C to 85C -40C to 85C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8344BYI
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