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PD - 9.1497A
PRELIMINARY Logic-Level Gate Drive Advanced Process Technology l Isolated Package l High Voltage Isolation = 2.5KVRMS l Sink to Lead Creepage Dist. = 4.8mm l Fully Avalanche Rated Description
l l
IRLI540N
HEXFET(R) Power MOSFET
D
VDSS = 100V RDS(on) = 0.044
G
ID = 23A
S
Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The TO-220 Fullpak eliminates the need for additional insulating hardware in commercial-industrial applications. The moulding compound used provides a high isolation capability and a low thermal resistance between the tab and external heatsink. This isolation is equivalent to using a 100 micron mica barrier with standard TO-220 product. The Fullpak is mounted to a heatsink using a single clip or by a single screw fixing.
TO-220 FULLPAK
Absolute Maximum Ratings
Parameter
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS EAS IAR EAR dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Mounting torque, 6-32 or M3 screw
Max.
23 16 120 54 0.36 16 310 18 5.4 5.0 -55 to + 175 300 (1.6mm from case ) 10 lbf*in (1.1N*m)
Units
A W W/C V mJ A mJ V/ns C
Thermal Resistance
Parameter
RJC RJA Junction-to-Case Junction-to-Ambient
Typ.
--- ---
Max.
2.8 65
Units
C/W
3/16/98
IRLI540N
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
V(BR)DSS
V(BR)DSS/TJ
Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Drain to Sink Capacitance
RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss C
Max. Units Conditions --- V VGS = 0V, ID = 250A --- V/C Reference to 25C, ID = 1mA 0.044 VGS = 10V, ID = 12A 0.053 VGS = 5.0V, ID = 12A 0.063 VGS = 4.0V, ID = 10A 2.0 V VDS = VGS , ID = 250A --- S VDS = 25V, ID = 18A 25 VDS = 100V, VGS = 0V A 250 VDS = 80V, VGS = 0V, TJ = 150C 100 VGS = 16V nA -100 VGS = -16V 74 ID = 18A 9.4 nC VDS = 80V 38 VGS = 5.0V, See Fig. 6 and 13 --- VDD = 50V --- ID = 18A ns --- RG = 5.0, VGS = 5.0V --- RD = 2.7, See Fig. 10 Between lead, --- 4.5 --- 6mm (0.25in.) nH G from package --- 7.5 --- and center of die contact --- 1800 --- VGS = 0V --- 350 --- VDS = 25V pF --- 170 --- = 1.0MHz, See Fig. 5 --- 12 --- = 1.0MHz
Min. 100 --- --- --- --- 1.0 14 --- --- --- --- --- --- --- --- --- --- ---
Typ. --- 0.11 --- --- --- --- --- --- --- --- --- --- --- --- 11 81 39 62
D
S
Source-Drain Ratings and Characteristics
IS
ISM
VSD trr Q rr ton
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time
Min. Typ. Max. Units
Conditions D MOSFET symbol 23 --- --- showing the A G integral reverse --- --- 120 p-n junction diode. S --- --- 1.3 V TJ = 25C, IS = 18A, VGS = 0V --- 190 290 ns TJ = 25C, IF = 18A --- 1.1 1.7 C di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. 11 ) Starting TJ = 25C, L = 1.9mH RG = 25, IAS = 18A. (See Figure 12) ISD 18A, di/dt 180A/s, VDD V(BR)DSS, TJ 175C
Pulse width 300s; duty cycle 2%. t=60s, =60Hz
Uses IRL540N data and test conditions
IRLI540N
1000
TOP VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V
1000
TOP
ID , Drain-to-Source Current (A)
100
ID , Drain-to-Source Current (A)
VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V
100
10
10
2.5V
2.5V
1 0.1 1
20s PULSE WIDTH T J = 25C
10
A
1 0.1 1
20s PULSE WIDTH T J = 175C
10
100
100
A
V D S , Drain-to-Source Voltage (V)
V D S , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
3.0
R D S ( o n ) , Drain-to-Source On Resistance (Normalized)
I D = 30A
I D , Drain-to-Source Current (A)
2.5
100
2.0
TJ = 25C TJ = 175C
1.5
10
1.0
0.5
1
V D S = 50V 20s PULSE WIDTH
2 4 6 8 10
A
0.0 -60 -40 -20 0 20 40 60 80
V G S = 10V
100 120 140 160 180
A
V G S , Gate-to-Source Voltage (V)
T J , Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
IRLI540N
3000 15
C, Capacitance (pF)
C iss
2000
V G S , Gate-to-Source Voltage (V)
V G S = 0V, f = 1MHz C iss = C gs+ C gd C SHORTED , ds C rss = C gd C oss = C ds+ C gd
I D = 18A V D S = 80V V D S = 50V V D S = 20V
12
9
6
1000
C oss C rss
3
0 1 10 100
A
0 0 20 40
FOR TEST CIRCUIT SEE FIGURE 13
60 80 100
A
V D S , Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
1000
1000
I S D , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED BY RD S ( o n )
100
I D , Drain Current (A)
100 10s
TJ = 175C
T J = 25C
10
100s 10 1ms
1 0.4 0.6 0.8 1.0 1.2 1.4
VG S = 0V
1.6
A
1.8
1 1
T C = 25C T J = 175C Single Pulse
10
10ms
100
1000
A
V S D , Source-to-Drain Voltage (V)
V D S , Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
IRLI540N
25
VDS
20
RD
VGS RG
D.U.T.
+
I D , Drain Current (A)
-VDD
15
5.0V
Pulse Width 1 s Duty Factor 0.1 %
10
Fig 10a. Switching Time Test Circuit
5
VDS 90%
0 25 50 75 100 125 150 175
TC , Case Temperature ( C)
10% VGS
td(on) tr t d(off) tf
Fig 9. Maximum Drain Current Vs. Case Temperature
Fig 10b. Switching Time Waveforms
10
Thermal Response (Z thJC )
D = 0.50 1 0.20 0.10 0.05 0.1 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1 1 10 P DM t1 t2
0.01 0.00001
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
IRLI540N
Single Pulse Avalanche Energy (mJ)
800
TOP BOTTOM
600
1 5V
ID 7.3A 13A 18A
VD S
L
D R IV E R
400
RG
10V
D .U .T IA S tp 0.0 1
+ - VD D
A
200
E AS ,
Fig 12a. Unclamped Inductive Test Circuit
0 25 50 75 100 125 150
A
175
V (B R )D SS tp
Starting T J , Junction Temperature (C)
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
IAS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator Same Type as D.U.T.
50K 12V .2F .3F
QG
5.0 V
QGS VG QGD
VGS
3mA
D.U.T.
+ V - DS
IG
ID
Charge
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
IRLI540N
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
+ VDD
Driver Gate Drive P.W. Period D=
P.W. Period VGS=10V
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
VDD
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS
IRLI540N
Package Outline
TO-220 Fullpak Outline Dimensions are shown in millimeters (inches)
1 0 .6 0 (.4 1 7 ) 1 0 .4 0 (.4 0 9 ) o 3 .4 0 (.1 3 3 ) 3 .1 0 (.1 2 3 ) -A 3 .7 0 (.14 5 ) 3 .2 0 (.12 6 ) 4 .8 0 ( .1 89 ) 4 .6 0 ( .1 81 ) 2 .80 (.1 10 ) 2 .60 (.1 02 ) L E A D A S S IG N M E N T S 1 - G A TE 2 - D R A IN 3 - S O U RC E
7 .1 0 (.2 8 0 ) 6 .7 0 (.2 6 3 )
1 6 .0 0 (.6 3 0 ) 1 5 .8 0 (.6 2 2 )
1 .1 5 (.0 4 5) M IN. 1 2 3
NO T E S : 1 D IME N S IO N ING & T O L E R A N C ING P E R A N S I Y 1 4 .5 M , 1 9 8 2 2 C O N TR O L L ING D IM E N S IO N: IN C H .
3.3 0 (.13 0 ) 3.1 0 (.12 2 ) -B1 3 .7 0 (.5 4 0 ) 1 3 .5 0 (.5 3 0 ) C D
A 1 .4 0 (.0 5 5) 3X 1 .0 5 (.0 4 2) 2 .54 (.1 0 0) 2X 0 .9 0 (.0 3 5 ) 3X 0 .7 0 (.0 2 8 ) 0 .2 5 (.0 1 0) M AM B 3X 0 .4 8 (.0 1 9 ) 0 .4 4 (.0 1 7 )
B
2 .85 (.1 1 2 ) 2 .65 (.1 0 4 )
M IN IM U M C R E E P A G E D IS T A NC E B E T W E E N A -B -C -D = 4.8 0 (.1 89 )
Part Marking Information
TO-220 Fullpak
E X A M P LE : TH IS IS A N IR FI840 G W ITH AS S E M B LY LO T CO DE E 401
A
IN TE R N AT IO NA L RE C TIF IE R LOGO A S S EM BL Y LO T CO DE
P AR T NU M B ER IR F I8 40G
E 4 01 9 24 5
DA T E CO D E (Y YW W ) YY = YE A R W W = W EEK
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331 EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020 IR CANADA: 15 Lincoln Court, Brampton, Ontario L6T 3Z2, Tel: (905) 453 2200 IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590 IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111 IR FAR EAST: 171 (K&H Bldg.) 30-4 Nishi-ikebukuro 3-chome, Toshima-ku, Tokyo Japan Tel: 81 33 983 0086 IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 16907 Tel: 65 221 8371 Data and specifications subject to change without notice. 3/98

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