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19-2100; Rev 0; 8/01
Quad Bus LVDS Driver with Flow-Through Pinout
General Description
The MAX9129 is a quad bus low-voltage differential signaling (BLVDS) driver with flow-through pinout. This device is designed to drive a heavily loaded multipoint bus with controlled transition times (1ns 0% to 100% minimum) for reduced reflections. The MAX9129 accepts four LVTTL/LVCMOS input levels and translates them to output levels of 250mV to 450mV (standard LVDS levels) into a 27 load at speeds up to 200Mbps (100MHz). The power-on reset ensures that all four outputs are disabled and high impedance during power up and power down. The outputs can be set to high impedance by two enable inputs, EN and EN, thus dropping the device to a low-power state of 11mW. The enables are common to all four drivers. The flow-through pinout simplifies PC board layout and reduces crosstalk by keeping the LVTTL/LVCMOS inputs and BLVDS outputs separated. The MAX9129 operates from a single +3.3V supply and is specified for operation from -40C to +85C. It is available in 16-pin QFN and TSSOP packages. Refer to the MAX9121 data sheet for a quad LVDS line receiver with flow-through pinout. o Drive LVDS Levels into a 27 Load o 1ns (0% to 100%) Minimum Transition Time Reduces Reflections o Guaranteed 200Mbps (100MHz) Data Rate o Enable Pins for High-Impedance Output o High-Impedance Outputs when Powered Off o Glitch-Free Power-Up and Power-Down o Hot Swappable o Flow-Through Pinout o Available in Tiny QFN Package (50% Smaller than TSSOP) o Single +3.3V Supply
Features
MAX9129
Ordering Information
PART MAX9129EGE MAX9129EUE TEMP. RANGE -40C to +85C -40C to +85C PIN-PACKAGE 16 QFN 16 TSSOP
Applications
Cell Phone Base Stations Add/Drop Muxes Digital Cross-Connects DSLAMs Network Switches/Routers Backplane Interconnect Clock Distribution
Functional Diagram appears at end of data sheet. Pin Configurations appear at end of data sheet.
Typical Applications Circuit
CARD 1A
MAX9129 MAX9121
CARD 10A
MAX9129 MAX9121
CARD 1B
MAX9129 MAX9121
CARD 2B
MAX9129 MAX9121
BUS A Rt Rt MULTIPOINT FULL-DUPLEX TRANSMIT AND RECEIVE BUS = TERMINATION RESISTOR
BUS B Rt Rt
Rt
________________________________________________________________ Maxim Integrated Products
1
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Quad Bus LVDS Driver with Flow-Through Pinout MAX9129
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +4.0V IN_, EN, EN to GND....................................-0.3V to (VCC + 0.3V) OUT_+, OUT_- to GND..........................................-0.3V to +4.0V Short-Circuit Duration (OUT_+, OUT_-) .....................Continuous Continuous Power Dissipation (TA = +70C) 16-Pin QFN (derate 18.5mW/C above +70C) .........1481mW 16-Pin TSSOP (derate 9.4mW/C above +70C) .........755mW Storage Temperature Range .............................-65C to +150C Maximum Junction Temperature .....................................+150C Operating Temperature Range ...........................-40C to +85C ESD Protection Human Body Model, OUT_+, OUT_- ...............................8kV Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, RL = 27 1%, EN = high, EN = low, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) (Notes 1, 2)
PARAMETER Differential Output Voltage Change in Magnitude of VOD Between Complementary Output States Offset Voltage Change in Magnitude of VOS Between Complementary Output States Output High Voltage Output Low Voltage Differential Output Short-Circuit Current Output Short-Circuit Current Output High-Impedance Current Power-Off Output Current Output Capacitance INPUTS (IN_, EN, EN) High-Level Input Voltage Low-Level Input Voltage Input Current SUPPLY CURRENT Supply Current Disabled Supply Current ICC ICCZ RL = 27, IN_ = VCC or 0 for all channels Disabled 58 3.2 70 5 mA mA VIH VIL IIN IN_, EN, EN = 0 or VCC 2.0 GND -15 VCC 0.8 15 V V A SYMBOL VOD VOD VOS VOS VOH VOL IOSD IOS IOZ IOFF COUT VOD = 0 OUT_+ = 0 at IN_ = VCC or OUT_- = 0 at IN_ = 0 Disabled, OUT_+ = 0 or VCC, OUT_- = 0 or VCC VCC = 0 or open, EN = EN = IN_ = 0, OUT_+ = 0 or 3.6V, OUT_- = 0 or 3.6V Capacitance from OUT_+ or OUT_- to GND -1 -1 4.3 0.90 Figure 1 Figure 1 Figure 1 Figure 1 1.125 CONDITIONS MIN 250 TYP 371 1 1.29 5 1.465 1.085 20 -20 1 1 MAX 450 25 1.375 25 1.6 UNITS mV mV V mV V V mA mA A A pF
BLVDS OUTPUTS (OUT_+, OUT_-)
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Quad Bus LVDS Driver with Flow-Through Pinout
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, RL = 27 1%, CL = 15pF, EN = high, EN = low, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) (Notes 3, 4, 5)
PARAMETER Differential Propagation Delay High to Low Differential Propagation Delay Low to High Differential Pulse Skew (Note 6) Differential Channel-to-Channel Skew (Note 7) Differential Part-to-Part Skew (Note 8) Differential Part-to-Part Skew (Note 9) Rise Time Fall Time Disable Time High to Z Disable Time Low to Z Enable Time Z to High Enable Time Z to Low Maximum Operating Frequency (Note 10) SYMBOL tPHLD tPLHD tSKD1 tSKD2 tSKD3 tSKD4 tTLH tTHL tPHZ tPLZ tPZH tPZL fMAX CONDITIONS Figures 2 and 3 Figures 2 and 3 Figures 2 and 3 Figures 2 and 3 Figures 2 and 3 Figures 2 and 3 Figures 2 and 3 Figures 2 and 3 Figures 4 and 5 Figures 4 and 5 Figures 4 and 5 Figures 4 and 5 Figure 2 100 MAX9129EGE MAX9129EUE MAX9129EGE MAX9129EUE 0.60 0.60 0.60 0.60 1.19 1.09 1.12 1.02 MIN 1.0 1.0 TYP 1.98 1.92 MAX 3.0 3.0 300 450 1.2 2.0 1.55 1.40 1.55 1.40 8 8 10 10 UNITS ns ns ps ps ns ns ns ns ns ns ns ns MHz
MAX9129
Note 1: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are 100% tested at TA = +25C. Note 2: Current into the device is defined as positive, and current out of the device is defined as negative. All voltages are referenced to ground except VOD and VOD. Note 3: AC parameters are guaranteed by design and characterization. Note 4: CL includes probe and jig capacitance. Note 5: Signal generator conditions: VOL = 0, VOH = VCC, f = 100MHz, 50% duty cycle, RO = 50, tR = tF = 1ns (10% to 90%). Note 6: tSKD1 is the magnitude difference of differential propagation delays. tSKD1 = | tPHLD - tPLHD |. Note 7: tSKD2 is the magnitude difference of tPHLD or tPLHD of one channel to the tPHLD or tPLHD of another channel on the same device. Note 8: tSKD3 is the magnitude difference of any differential propagation delays between devices at the same VCC and within 5C of each other. Note 9: tSKD4 is the magnitude difference of any differential propagation delays between devices operating over the rated supply and temperature ranges. Note 10: Signal generator conditions: VOL = 0, VOH = VCC, f = 100MHz, 50% duty cycle, RO = 50, tR = tF = 1ns (10% to 90%). MAX9129 output criteria: duty cycle = 45% to 55%, VOD 250mV, all channels switching.
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Quad Bus LVDS Driver with Flow-Through Pinout MAX9129
Typical Operating Characteristics
(MAX9129EUE (TSSOP package), VCC = +3.3V, RL = 27, CL = 15pF, TA = +25C, unless otherwise noted.) (Note 5)
OUTPUT LOW VOLTAGE vs. SUPPLY VOLTAGE
MAX9129 toc02 MAX9129 toc01
OUTPUT HIGH VOLTAGE vs. SUPPLY VOLTAGE
1.48 1.12
OUTPUT SHORT CURRENT (IOS) vs. SUPPLY VOLTAGE
MAX9129 toc03
-14.12 OUTPUT SHORT CURRENT (mA)
OUTPUT HIGH VOLTAGE (V)
OUTPUT LOW VOLTAGE (V)
1.47
1.10
-14.11
1.46
1.08
-14.10
1.45
1.06
-14.09
1.44 3.0 3.3 SUPPLY VOLTAGE (V) 3.6
1.04 3.0 3.3 SUPPLY VOLTAGE (V) 3.6
-14.08 3.0 3.3 SUPPLY VOLTAGE (V) 3.6
OUTPUT HIGH-IMPEDANCE CURRENT vs. SUPPLY VOLTAGE
MAX9129 toc04
DIFFERENTIAL OUTPUT VOLTAGE vs. SUPPLY VOLTAGE
DIFFERENTIAL OUTPUT VOLTAGE (mV)
MAX9129 toc05
DIFFERENTIAL OUTPUT VOLTAGE vs. LOAD RESISTANCE
MAX9129 toc06
430 OUTPUT HIGH-IMPEDANCE CURRENT (pA) VOUT_ = VCC OR 0 428
372.0
1.750 DIFFERENTIAL OUTPUT VOLTAGE (V) 1.500 1.250 1.000 0.750 0.500 0.250 0
371.5
426
371.0
424
422
370.5
420 3.0 3.3 SUPPLY VOLTAGE (V) 3.6
370.0 3.0 3.3 SUPPLY VOLTAGE (V) 3.6
10
30
50
70
90
110
130
150
LOAD RESISTANCE ()
OUTPUT OFFSET VOLTAGE vs. SUPPLY VOLTAGE
MAX9129 toc07
SUPPLY CURRENT vs. FREQUENCY
MAX9129 toc08
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX9129 toc09
1.305 1.300 OUTPUT OFFSET VOLTAGE (V) 1.295 1.290 1.285 1.280 1.275 1.270 1.265 3.0 3.3 SUPPLY VOLTAGE (V)
65
57.7
63 SUPPLY CURRENT (mA)
57.5 SUPPLY CURRENT (mA)
61
57.3
59
57.1
57
56.9
55 3.6 0 1 100 FREQUENCY (MHz) 10 1000
56.7 3.0 3.3 SUPPLY VOLTAGE (V) 3.6
4
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Quad Bus LVDS Driver with Flow-Through Pinout
Typical Operating Characteristics (continued)
(MAX9129EUE (TSSOP package), VCC = +3.3V, RL = 27, CL = 15pF, TA = +25C, unless otherwise noted.) (Note 5)
SUPPLY CURRENT vs. TEMPERATURE
MAX9129 toc10
MAX9129
DIFFERENTIAL PROPAGAION DELAY vs. SUPPLY VOLTAGE
MAX9129 toc11
DIFFERENTIAL PROPAGATION DELAY vs. TEMPERATURE
DIFFERENTIAL PROPAGATION DELAY (ns)
MAX9129 toc12
60
2.10 DIFFERENTIAL PROPAGATION DELAY (ns) 2.05 tPHLD 2.00 1.95 1.90 1.85 1.80
2.20 2.10 2.00 1.90 1.80 1.70 1.60 tPLHD
59 SUPPLY CURRENT (mA)
tPHLD
58
57
tPLHD
56
55 -40 -15 10 35 60 85 TEMPERATURE (C)
3.0
3.3 SUPPLY VOLTAGE (V)
3.6
-40
-15
10
35
60
85
TEMPERATURE (C)
DIFFERENTIAL SKEW vs. SUPPLY VOLTAGE
MAX9129 toc13
DIFFERENTIAL SKEW vs. TEMPERATURE
MAX9129 toc14
TRANSITION TIME vs. SUPPLY VOLTAGE
20% TO 80% 1.2 TRANSITION TIME (ns) tTLH
MAX9129 toc15
70 60 DIFFERENTIAL SKEW (ps) 50 40 30 20 10 0 3.0 3.3 SUPPLY VOLTAGE (V)
100
1.3
80 DIFFERENTIAL SKEW (ps)
60
1.1
40
1.0 tTHL 0.9
20
0 3.6 -40 -15 10 35 60 85 TEMPERATURE (C)
0.8 3.0 3.3 SUPPLY VOLTAGE (V) 3.6
TRANSITION TIME vs. TEMPERATURE
20% TO 80% 1.200 1.150 TRANSITION TIME (ns) 1.100 1.050 1.000 0.950 0.900 0.850 0.800 -40 -15 10 35 60 85 TEMPERATURE (C) tTHL tTLH
MAX9129 toc16
1.250
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Quad Bus LVDS Driver with Flow-Through Pinout MAX9129
Pin Description
PIN QFN 15 1, 4, 5, 16 2 3 6 7, 10, 11, 14 8, 9, 12, 13 TSSOP 1 2, 3, 6, 7 4 5 8 9, 12, 13, 16 10, 11, 14, 15 NAME FUNCTION LVTTL/LVCMOS Enable Input. The driver is disabled when EN is low. EN is internally pulled down. When EN = high and EN = low or open, the outputs are active. For other combinations of EN and EN, the outputs are disabled and are high impedance. LVTTL/LVCMOS Driver Inputs Power-Supply Input. Bypass VCC to GND with 0.1F and 0.001F ceramic capacitors. Ground LVTTL/LVCMOS Enable Input. The driver is disabled when EN is high. EN is internally pulled down. Inverting BLVDS Driver Outputs Noninverting BLVDS Driver Outputs
EN IN_ VCC GND EN OUT_OUT_+
OUT_+
CL
RL/2 GND RL/2 VOS VOD
S
OUT_ + GENERATOR IN_ RL OUT_ CL
VCC
IN_
VO
50
OUT_-
Figure 1. Driver VOD and VOS Test Circuit
Figure 2. Driver Propagation Delay and Transition Time Test Circuit
VCC IN_ 50% 50% 0 tPLHD OUT_ 0 DIFFERENTIAL OUT_+ 0 VOL 80% 0 VOD 20% tTLH tTHL 80% VOD = (VOUT_+) - (VOUT_-) 0 20% tPHLD VOH
Figure 3. Driver Propagation Delay and Transition Time Waveforms
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Quad Bus LVDS Driver with Flow-Through Pinout MAX9129
CL
Table 1. Input/Output Function Table
ENABLES
OUT_+
INPUTS EN IN_ L H X
OUTPUTS OUT_+ L H Z OUT_ H L Z
EN H
VCC GND GENERATOR 50 EN EN
IN_
RL/2
L or open
+1.2V RL/2 OUT_1/4 MAX9129 CL
All other combinations of EN and EN
Figure 4. Driver High-Impedance Delay Test Circuit
EN WHEN EN = 0 OR OPEN 50% 50%
VCC
0
VCC 50% EN WHEN EN = VCC tPHZ OUT_+ WHEN IN_ = VCC OUT_- WHEN IN_ = 0 50% 50% 1.2V 1.2V 50% OUT_+ WHEN IN_ = 0 OUT_- WHEN IN_ = VCC 50% VOL tPLZ tPZL tPZH VOH 50% 0
Figure 5. Driver High-Impedance Delay Waveform
Detailed Description
The MAX9129 is a 200Mbps quad differential BLVDS driver designed for multipoint, heavily loaded backplane applications. This device accepts LVTTL/LVCMOS input levels and translates them to output levels of 250mV to 450mV into a 27 load. The flow-through pinout simplifies board layout and reduces the potential for crosstalk between single-ended inputs and differential outputs. Transition times are designed to reduce reflections, yet enable high data rates. The MAX9129 can be used in conjunction with standard quad LVDS receivers, such
as the MAX9121, to implement full-duplex multipoint buses more efficiently than with transceivers.
Effect of Capacitive Loading
The characteristic impedance of a differential PC board trace is uniformly reduced when equal capacitive loads are attached at equal intervals (provided the transition time of the signal being driven on the trace is longer than the delay between loads). This kind of loading is typical of multipoint buses where cards are attached at 1in or 0.8in intervals along the length of a backplane.
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Quad Bus LVDS Driver with Flow-Through Pinout MAX9129
The reduction in characteristic impedance is approximated by the following formula: ZDIFF-loaded = ZDIFF-unloaded SQRT [Co / (Co + N CL / L)] where: ZDIFF-unloaded = unloaded differential characteristic impedance Co = unloaded trace capacitance (pF/unit length) CL = value of each capacitive load (pF) N = number of capacitive loads L = trace length For example, if Co = 2.5pF/in, CL = 10pF, N = 18, L = 18in, and ZDIFF-unloaded = 120, the loaded differential impedance is: ZDIFF-loaded = 120 SQRT [2.5pF / (2.5pF + 18 10pF/18in)] ZDIFF-loaded = 54 In this example, capacitive loading reduces the characteristic impedance from 120 to 54. The load seen by a driver located on a card in the middle of the bus is 27 because the driver sees two 54 loads in parallel. A typical LVDS driver (rated for a 100 load) would not develop a large enough differential signal to be reliably detected by an LVDS receiver. Maxim's BLVDS driver is designed and specified to drive a 27 load to differential voltage levels of 250mV to 450mV (which are standard LVDS driver levels). A standard LVDS receiver is able to detect this level of differential signal. Short extensions off the bus, called stubs, contribute to capacitive loading. Keep stubs less than 1in for a good balance between ease of component placement and good signal integrity. The MAX9129 is a current source driver and drives larger differential signal levels into loads higher than 27 and smaller levels into loads less than 27 (see typical operating curves). To keep loading from reducing bus impedance below the rated 27 load, PC board traces can be designed for higher unloaded characteristic impedance. minimum transition time of 1ns (rated 0.6ns from 20% to 80%, or about 1ns 0% to 100%) to reduce reflections while being fast enough for high-speed backplane data transmission.
Power-On Reset
The power-on reset voltage of the MAX9129 is typically 2.25V. When the supply falls below this voltage, the device is disabled and the outputs are in high impedance.
Applications Information
Power-Supply Bypassing
Bypass V CC with high-frequency, surface-mount ceramic 0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to VCC.
Termination
In the example above, the loaded differential impedance of the bus is reduced to 54. Since it can be driven from any card position, the bus must be terminated at each end. A parallel termination of 54 at each end of the bus placed across the traces that make up the differential pair provides a proper termination. The total load seen by the driver is 27. The MAX9129 drives higher differential signal levels into lighter loads. A multidrop bus with the driver at one end and receivers connected at regular intervals along the bus has a lowered impedance due to capacitive loading. Assuming the same impedance calculated in the multidrop example above (54), the multidrop bus can be terminated with a single, parallel-connected 54 resistor at the far end from the driver. Only a single resistor is required because the driver sees one 54 differential trace. The signal swing is larger with a 54 load. In general, parallel terminate each end of the bus with a resistor matching the differential impedance of the bus (taking into account any reduced impedance due to loading).
Board Layout
A four-layer PC board that provides separate power, ground, input, and output signals is recommended. Keep the LVTTL/LVCMOS and BLVDS signals separated to prevent coupling as shown in the suggested layout for the QFN package (not drawn to scale) (Figure 6).
Effect of Transition Time
For transition times (measured from 0% to 100%) shorter than the delay between capacitive loads, the loads are seen as low-impedance discontinuities from which the driven signal is reflected. Reflections add and subtract from the signal being driven and cause decreased noise margin and jitter. The MAX9129 is designed for a
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Quad Bus LVDS Driver with Flow-Through Pinout MAX9129
EN IN1 OUT1OUT1+
GND
IN2 VCC GND IN3
OUT2+ OUT2OUT3OUT3+
IN4 EN
OUT4+ OUT4-
Figure 6. Suggested Layout for QFN Package
Chip Information
TRANSISTOR COUNT: 948 PROCESS: CMOS
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Quad Bus LVDS Driver with Flow-Through Pinout MAX9129
Pin Configurations
TOP VIEW
IN1 16 EN 1 IN1 2 IN2 3 VCC 4 GND 5 IN3 6 IN4 7 EN 8 16 OUT115 OUT1+ 14 OUT2+ IN2 VCC GND IN3 1 2 3 4 5 7 6 8 EN OUT1- OUT1+ 15 14 13
GND
GND
12 11 OUT2+ OUT2OUT3OUT3+
GND
MAX9129
13 OUT212 OUT311 OUT3+ 10 OUT4+ 9 OUT4-
MAX9129
10 9
GND
IN4 EN OUT4- OUT4+
GND
TSSOP
QFN
(4mm x 4mm) (CONTACTS UNDER QFN)
Functional Diagram
OUT1+ IN1 OUT1-
OUT2+ IN2 OUT2-
OUT3+ IN3 OUT3-
OUT4+ IN4 OUT4-
EN
MAX9129
EN
10
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Quad Bus LVDS Driver with Flow-Through Pinout
Package Information
TSSOP,NO PADS.EPS
MAX9129
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Quad Bus LVDS Driver with Flow-Through Pinout MAX9129
Package Information (continued)
12, 16,20, 24L QFN.EPS
12
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Quad Bus LVDS Driver with Flow-Through Pinout
Package Information (continued)
MAX9129
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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