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PRELIMINARY
W229B
Frequency Generator for Integrated Core Logic with 133-MHz FSB
Features
* Maximized EMI suppression using Cypress's Spread Spectrum technology * Low jitter and tightly controlled clock skew * Highly integrated device providing clocks required for CPU, core logic, and SDRAM * Two copies of CPU clock * Thirteen copies of SDRAM clock * Eight copies of PCI clock * One copy of synchronous APIC clock * Three copies of 66-MHz outputs * Two copies of 48-MHz outputs * One copy of selectable 24- or 48-MHz clock * One copy of double strength 14.31818-MHz reference clock * Power-down control * I2CTM interface for turning off unused clocks Table 1. Frequency Selections
FS4 FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU 75.3 95.0 129.0 150.0 150.0 110.0 140.0 144.0 68.3 105.0 138.0 140.0 66.8 100.2 133.6 133.6 157.3 160.0 146.6 122.0 127.0 122.0 117.0 114.0 80.0 78.0 166.0 133.6 66.6 100.0 133.3 133.3 SDRAM 3V66 113.0 75.3 95.0 129.0 113.0 150.0 110.0 140.0 108.0 102.5 105.0 138.0 105.0 100.2 100.2 133.6 100.2 118.0 120.0 110.0 91.5 127.0 122.0 117.0 114.0 120.0 117.0 124.5 133.6 100.0 100.0 133.3 100.0 63.3 86.0 75.3 75.0 73.0 70.0 72.0 68.3 70.0 69.0 70.0 66.8 66.8 66.8 66.8 78.6 80.0 73.3 61.0 84.6 81.3 78.0 76.0 80.0 78.0 83.0 89.0 66.6 66.6 66.6 66.6 PCI 37.6 31.6 43.0 37.6 37.5 36.6 35.0 36.0 34.1 35.0 34.5 35.0 33.4 33.4 33.4 33.4 39.3 40.0 36.6 30.5 42.3 40.6 39.0 38.0 40.0 39.0 41.5 44.5 33.3 33.3 33.3 33.3 APIC 18.8 15.8 21.5 18.8 18.7 18.3 17.5 18.0 17.0 17.5 17.0 17.5 16.7 16.7 16.7 16.7 19.6 20.0 18.3 15.2 21.1 20.3 19.5 19.0 20.0 19.5 20.7 22.2 16.6 16.6 16.6 16.6 SS OFF -0.6% OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF 0.45% 0.45% 0.45% 0.45% OFF OFF OFF -0.6% OFF -0.6% OFF OFF OFF OFF OFF OFF -0.6% -0.6% -0.6% -0.6%
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter: ............. 250 ps APIC, 48-MHz, 3V66, PCI Outputs Cycle-to-Cycle Jitter:................................................... 500 ps CPU, 3V66 Output Skew:............................................ 175 ps SDRAM, APIC, 48-MHz Output Skew:........................ 250 ps PCI Output Skew: ....................................................... 500 ps CPU to SDRAM Skew (@ 133 MHz) ....................... 0.5 ns CPU to SDRAM Skew (@ 100 MHz) ................. 4.5 to 5.5 ns CPU to 3V66 Skew (@ 66 MHz)........................ 7.0 to 8.0 ns 3V66 to PCI Skew (3V66 lead) .......................... 1.5 to 3.5 ns PCI to APIC Skew ..................................................... 0.5 ns
Block Diagram
X1 X2 XTAL OSC
PLL REF FREQ
VDDQ3 REF2X/FS3*
Pin Configuration [1]
GND VDDQ3 REF2X/FS3* X1 X2 VDDQ3 3V66_0 3V66_1 3V66_2 GND PCI0/FS0* PCI1/FS1* PCI2/FS2* GND PCI3 PCI4 VDDQ3 PCI5 PCI6 PCI7 GND 48MHz_0 48MHz_1/FS4* SIO/24_48MHz#* VDDQ3 SDATA GND VDDQ3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDQ2 APIC GND VDDQ2 CPU0 CPU1 GND SDRAM0 SDRAM1 SDRAM2 VDDQ3 GND SDRAM3 SDRAM4 SDRAM5 SDRAM6 VDDQ3 GND SDRAM7 SDRAM8 SDRAM9 SDRAM10 VDDQ3 GND SDRAM11 SDRAM12 PWRDWN# SCLK
VDDQ2
SDATA SCLK
I2C Logic
(FS0:4*)
Divider, Delay, and Phase Control Logic
CPU0:1
2
W229B
APIC VDDQ3
3
3V66_0:2 PCI0/FS0* PCI1/FS1* PCI2/FS2*
PLL 1
5
PCI3:7 SDRAM0:12
PWRDWN#
13
VDDQ3 48MHz_0
PLL2
/2
48MHz_1/FS4* SI0/24_48 MHz#*
Note: 1. Internal pull-down or pull-up resistors present on inputs marked with * or ^, respectively. Design should not rely solely on internal pull-up or pull-down resistor to set I/O pins HIGH or LOW, respectively.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 December 27, 1999, rev. **
PRELIMINARY
I
W229B
Pin Definitions
Pin Name REF2x/FS3 Pin No. 3 Pin Type I/O Pin Description Reference Clock with 2x Drive/Frequency Select 3: 3.3V 14.318-MHz clock output. This pin also serves as the select strap to determine device operating frequency as described in Table 1. Crystal Input: This pin has dual functions. It can be used as an external 14.318MHz crystal connection or as an external reference frequency input. Crystal Output: An input connection for an external 14.318-MHz crystal connection. If using an external reference, this pin must be left unconnected. PCI Clock 0/Frequency Selection 0: 3.3V 33-MHz PCI clock outputs. This pin also serves as the select strap to determine device operating frequency as described in Table 1. PCI Clock 1/Frequency Selection 1: 3.3V 33-MHz PCI clock outputs. This pin also serves as the select strap to determine device operating frequency as described in Table 1. PCI Clock 2/Frequency Selection 2: 3.3V 33-MHz PCI clock outputs. This pin also serves as the select strap to determine device operating frequency as described in Table 1. PCI Clock 3 through 7: 3.3V 33-MHz PCI clock outputs. PCI0:7 can be individually turned off via I2C interface. 66-MHz Clock Output: 3.3V output clocks. The operating frequency is controlled by FS0:4 (see Table 1). 48-MHz Clock Output: 3.3V fixed 48-MHz, non-spread spectrum clock output. 48-MHz Clock Output/Frequency Selection 4: 3.3V fixed 48-MHz, non-spread spectrum clock output. This pin also serves as the select strap to determine device operating frequency as described in Table 1. Clock Output for Super I/O: This is the input clock for a Super I/O (SIO) device. During power up, it also serves as a selection strap. If it is sampled HIGH, the output frequency for SIO is 24 MHz. If the input is sampled LOW, the output is 48 MHz. Power Down Control: LVTTL-compatible input that places the device in powerdown mode when held LOW. CPU Clock Outputs: Clock outputs for the host bus interface. Output frequencies depending on the configuration of FS0:4. Voltage swing is set by VDDQ2. SDRAM Clock Outputs: 3.3V outputs for SDRAM and chipset. The operating frequency is controlled by FS0:4 (see Table 1).
X1 X2 PCI0/FS0*
4 5 11
I I I/O
PCI1/FS1*
12
I/O
PCI2/FS2*
13
I/O
PCI3:7 3V66_0:2 48MHz_0 48MHz_1/ FS4* SIO/ 24_48MHz#* PWRDWN# CPU0:1 SDRAM0:12,
15, 16, 18, 19, 20 7, 8, 9 22 23
O O O I/O
24
I/O
30 52, 51 49, 48, 47, 44, 43, 42, 41, 38, 37, 36, 35, 32, 31 55 26 29 2, 6, 17, 25, 28, 34, 40, 46 53, 56 1, 10, 14, 21, 27, 33, 39, 45, 50, 54
I O
O
APIC SDATA SCLK VDDQ3 VDDQ2 GND
O I/O I P P G
Synchronous APIC Clock Outputs: Clock outputs running synchronous with the PCI clock outputs. Voltage swing set by VDDQ2. Data pin for I2C circuitry. Clock pin for I2C circuitry. 3.3V Power Connection: Power supply for SDRAM output buffers, PCI output buffers, reference output buffers and 48-MHz output buffers. Connect to 3.3V. 2.5V Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to 2.5V or 3.3V. Ground Connections: Connect all ground pins to the common system ground plane.
2
PRELIMINARY
Output Strapping Resistor Series Termination Resistor W229B Power-on Reset Timer Clock Load Output Buffer Output Three-state
Q
W229B
Hold Output Low
D
10 k
Data Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Overview
The W229B is a highly integrated frequency timing generator, supplying all the required clock sources for an Intel(R) architecture platform using graphics integrated core logic.
Functional Description
I/O Pin Operation Pin # 3, 11, 12, 13, 23, and 24 are dual-purpose l/O pins. Upon power-up the pin acts as a logic input. An external 10-k strapping resistor should be used. Figure 1 shows a suggested method for strapping resistor connections. After 2 ms, the pin becomes an output. Assuming the power supply has stabilized by then, the specified output frequency
10 ns 20 ns
is delivered on the pins. If the power supply has not yet reached full value, output frequency initially may be below target but will increase to target once supply voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled. Offsets Among Clock Signal Groups Figure 2, Figure 3, and Figure 4 represent the phase relationship among the different groups of clock outputs from W229B when it is providing a 66-MHz CPU clock, a 100-MHz CPU clock, and a 133 MHz CPU clock, respectively. It should be noted that when CPU clock is operating at 100 MHz, CPU clock output is 180 degrees out of phase with SDRAM clock outputs.
0 ns
30 ns
40 ns
CPU 100 Period
CPU 66-MHz
SDRAM 100 Period
SDRAM 100-MHz 3V66 66-MHz PCI 33-MHz REF 14.318-MHz USB 48-MHz APIC
Hub-PC
Figure 2. Group Offset Waveforms (66-MHz CPU Clock, 100-MHz SDRAM Clock)
3
PRELIMINARY
W229B
0 ns
10 ns
20 ns
30 ns
40 ns
CPU 100 Period
CPU 100-MHz
SDRAM 100 Period
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz REF 14.318-MHz USB 48-MHz APIC
Hub-PC
Figure 3. Group Offset Waveforms (100-MHz CPU Clock/100-MHz SDRAM Clock)
0 ns
10 ns
20 ns
30 ns
40 ns
Cycle Repeats
CPU 133-MHz
SDRAM 100-MHz 3V66 66-MHz PCI 33-MHz APIC 33-MHz REF 14.318-MHz USB 48-MHz DOT 48-MHz
Figure 4. Group Offset Waveforms (133-MHz CPU/100-MHz SDRAM)
4
PRELIMINARY
0 ns 10 ns 20 ns 30 ns 40 ns
W229B
CPU 100-MHz
Cycle Repeat
SDRAM 133-MHz 3V66 66-MHz PCI 33-MHz APIC 33-MHz REF 14.318-MHz USB 48-MHz DOT 48-MHz
Figure 5. Group Offset Waveform (133-MHz CPU/133-MHz SDRAM)
Power Down Control W229B provides one PWRDWN# signal to place the device in low-power mode. In low-power mode, the PLLs are turned off and all clock outputs are driven LOW.
0ns
25ns
50ns
75ns Center
1 VCO Internal CPU 100MHz 3V66 66MHz PCI 33MHz APIC 33MHz PwrDwn SDRAM 100MHz REF 14.318MHz USB 48MHz
2
Figure 6. W229B PWRDWN# Timing Diagram [2, 3, 4, 5]
Notes: 2. Once the PWRDWN# signal is sampled LOW for two consecutive rising edges of CPU, clocks of interest will be held LOW on the next HIGH-to-LOW transition. 3. PWRDWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W229B. 4. The shaded sections on the SDRAM, REF, and USB clocks indicate "don't care" states. 5. Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz.
5
PRELIMINARY
Spread Spectrum Frequency Timing Generator
The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 7. As shown in Figure 7, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is dB = 6.5 + 9*log10(P) + 9*log10(F)
W229B
Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The output clock is modulated with a waveform depicted in Figure 8. This waveform, as discussed in "Spread Spectrum Clock Generation for the Reduction of Radiated Emissions" by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is 0.45% or 0.6% of the selected frequency. Figure 8 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices.
EMI Reduction
SSFTG
Typical Clock
Amplitude (dB)
Amplitude (dB)
Spread Spectrum Enabled
NonSpread Spectrum
Frequency Span (MHz) Center Spread
Frequency Span (MHz) Down Spread
Figure 7. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX.
FREQUENCY
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
MIN.
Figure 8. Typical Modulation Profile
6
100%
PRELIMINARY
1 bit Start bit 7 bits Slave Address 1 R/W 1 Ack 8 bits Command Code 1 Ack
W229B
Byte Count = N
Ack 1 bit
Data Byte 1 8 bits
Ack 1
Data Byte 2 8 bits
Ack 1
...
Data Byte N 8 bits
Ack 1
Stop 1
Figure 9. An Example of a Block Write[6] Serial Data Interface The W229B features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Data Protocol The clock driver serial protocol accepts only block writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. Indexed bytes are not allowed. A block write begins with a slave address and a write condition. After the command code the core logic issues a byte count which describes how many more bytes will follow in the message. If the host had 20 bytes to send, the first byte would be the number 20 (14h), followed by the 20 bytes of data. The byte count may not be 0. A block write command is allowed to transTable 2. Example of Possible Byte Count Value Byte Count Byte MSB 0000 0000 0000 0000 0000 0000 0000 0000 0010 LSB 0000 0001 0010 0011 0100 0101 0110 0111 0000 Not allowed. Must have at least one byte. Data for functional and frequency select register (currently byte 0 in spec) Reads first two bytes of data. (byte 0 then byte 1) Reads first three bytes (byte 0, 1, 2 in order) Reads first four bytes (byte 0, 1, 2, 3 in order) Reads first five bytes (byte 0, 1, 2, 3, 4 in order)[7] Reads first six bytes (byte 0, 1, 2, 3, 4, 5 in order)[7] Reads first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order) Max. byte count supported = 32 Notes fer a maximum of 32 data bytes. The slave receiver address for W229B is 11010010. Figure 9 shows an example of a block write. The command code and the byte count bytes are required as the first two bytes of any transfer. W229B expects a command code of 0000 0000. The byte count byte is the number of additional bytes required for the transfer, not counting the command code and byte count bytes. Additionally, the byte count byte is required to be a minimum of 1 byte and a maximum of 32 bytes to satisfy the above requirement. Table 2 shows an example of a possible byte count value. A transfer is considered valid after the acknowledge bit corresponding to the byte count is read by the controller. The command code and byte count bytes are ignored by the W229B. However, these bytes must be included in the data write sequence to maintain proper byte allocation.
Table 3. Serial Data Interface Control Functions Summary Control Function Output Disable Description Any individual clock output(s) can be disabled. Disabled outputs are actively held LOW. Common Application Unused outputs are disabled to reduce EMI and system power. Examples are clock outputs to unused PCI slots.
(Reserved)
Reserved function for future device revision or pro- No user application. Register bit must be written as 0. duction device testing.
Notes: 6. The acknowledgment bit is returned by the slave/receiver (W229B). 7. Bytes 6 and 7 are not defined for W229B.
7
PRELIMINARY
W229B Serial Configuration Map
1. The serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 0: Control Register (1 = Enable, 0 = Disable)[8] Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 24 22, 23 Name Reserved Reserved Reserved Reserved Reserved SIO/24_48 MHz 48 MHz Reserved Default 0 0 0 0 0 1 1 0 Reserved Reserved Reserved Reserved Reserved (Active/Inactive) (Active/Inactive) Reserved Pin Function
W229B
2. All unused register bits (reserved and N/A) should be written to a "0" level. 3. All register bits labeled "Initialize to 0" must be written to zero during initialization. Failure to do so may result in higher than normal operating current. The controller will read back the written value.
Byte 1: Control Register (1 = Enable, 0 = Disable)[8] Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 38 41 42 43 44 47 48 49 Name SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0 Default 1 1 1 1 1 1 1 1 (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Pin Description
Byte 2: Control Register (1 = Enable, 0 = Disable)[8] Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 20 19 18 16 15 13 12 11 Name PCI7 PCI6 PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 Default 1 1 1 1 1 1 1 1 (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Pin Description
Note: 8. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation.
8
PRELIMINARY
Byte 3: Reserved Register (1 = Enable, 0 = Disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 55 Name Reserved Reserved Reserved Reserved APIC Reserved Reserved Reserved Default 0 0 0 0 1 0 0 0 Reserved Reserved Reserved Reserved (Active/Inactive) Reserved Reserved Reserved Pin Description
W229B
Byte 4: Reserved Register (1 = Enable, 0 = Disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# SEL3 SEL2 SEL1 SEL0 FS(0:4) Override SEL4 Reserved Test Mode Name Default 0 0 0 0 0 0 0 0 See Table 4 See Table 4 See Table 4 See Table 4 0 = Select operating frequency by FS(0:4) strapping 1 = Select operating frequency by SEL(0:4) bit settings See Table 4 Reserved 0 = Normal 1 = Three-stated Pin Function
Byte 5: Reserved Register (1 = Enable, 0 = Disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 9 8 7 31 32 35 36 37 Name 3V66_2 3V66_1 3V66_0 SDRAM12 SDRAM11 SDRAM10 SDRAM9 SDRAM8 Default 1 1 1 1 1 1 1 1 (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Pin Description
Byte 6: Reserved Register (1 = Enable, 0 = Disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Pin Description
9
PRELIMINARY
Table 4. Additional Frequency Selections through Serial Data Interface Data Bytes Input Conditions Data Byte 4, Bit 3 = 1 Bit 2 SEL_4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 7 SEL_3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 6 SEL_2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 5 SEL_1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 4 SEL_0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU 75.3 95.0 129.0 150.0 150.0 110.0 140.0 144.0 68.3 105.0 138.0 140.0 66.8 100.2 133.6 133.6 157.3 160.0 146.6 122.0 127.0 122.0 117.0 114.0 80.0 78.0 166.0 133.6 66.6 100.0 133.3 133.3 SDRAM 113.0 95.0 129.0 113.0 150.0 110.0 140.0 108.0 102.5 105.0 138.0 105.0 100.2 100.2 133.6 100.2 118.0 120.0 110.0 91.5 127.0 122.0 117.0 114.0 120.0 117.0 124.5 133.6 100.0 100.0 133.3 100.0 3V66 75.3 63.3 86.0 75.3 75.0 73.0 70.0 72.0 68.3 70.0 69.0 70.0 66.8 66.8 66.8 66.8 78.6 80.0 73.3 61.0 84.6 81.3 78.0 76.0 80.0 78.0 83.0 89.0 66.6 66.6 66.6 66.6 PCI 37.6 31.6 43.0 37.6 37.5 36.6 35.0 36.0 34.1 35.0 34.5 35.0 33.4 33.4 33.4 33.4 39.3 40.0 36.6 30.5 42.3 40.6 39.0 38.0 40.0 39.0 41.5 44.5 33.3 33.3 33.3 33.3 APIC 18.8 15.8 21.5 18.8 18.7 18.3 17.5 18.0 17.0 17.5 17.0 17.5 16.7 16.7 16.7 16.7 19.6 20.0 18.3 15.2 21.1 20.3 19.5 19.0 20.0 19.5 20.7 22.2 16.6 16.6 16.6 16.6 Output Frequency
W229B
Spread Spectrum OFF -0.6% OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF 0.45% 0.45% 0.45% 0.45% OFF OFF OFF -0.6% OFF -0.6% OFF OFF OFF OFF OFF OFF -0.6% -0.6% -0.6% -0.6%
10
PRELIMINARY
DC Electrical Characteristics
DC parameters must be sustainable under steady state (DC) conditions. Absolute Maximum DC Power Supply Parameter VDDQ3 VDDQ2 TS Description 3.3V Core Supply Voltage 2.5V I/O Supply Voltage Storage Temperature Min. -0.5 -0.5 -65 Max. 4.6 3.6 150
W229B
Unit V V C
Absolute Maximum DC I/O Parameter Vi/o3 Vi/o3 ESD prot. Description 3.3V Core Supply Voltage 2.5V I/O Supply Voltage Input ESD Protection Min. -0.5 -0.5 2000 Max. 4.6 3.6 Unit V V V
DC Operating Requirements Parameter VDD3 VDDQ3 VDDQ2 VDD3 = 3.3V5% Vih3 Vil3 Iil VDDQ2 = 2.5V5% Voh2 Vol2 VDDQ3 = 3.3V5% Voh3 Vol3 VDDQ3 = 3.3V5% Vpoh3 Vpol3 Cin Cxtal Cout Lpin Ta PCI Bus Output High Voltage PCI Bus Output Low Voltage Input Pin Capacitance Xtal Pin Capacitance Output Pin Capacitance Pin Inductance Ambient Temperature No Airflow 0 0 13.5 Ioh=(-1 mA) Iol=(1 mA) 2.4 0.55 5 22.5 6 7 70 V V pF pF pF nH C 3.3V Output High Voltage 3.3V Output Low Voltage Ioh=(-1 mA) Iol=(1 mA) 2.4 0.4 V V 2.5V Output High Voltage 2.5V Output Low Voltage Ioh=(-1 mA) Iol=(1 mA) 2.0 0.4 V V 3.3V Input High Voltage 3.3V Input Low Voltage Input Leakage Current
[9]
Description 3.3V Core Supply Voltage 3.3V I/O Supply Voltage 2.5V I/O Supply Voltage
Condition 3.3V5% 3.3V5% 2.5V5% VDD3 0Min. 3.135 3.135 2.375 2.0 VSS - 0.3 -5
Max. 3.465 3.465 2.625 VDD + 0.3 0.8 +5
Unit V V V V V A
Note: 9. Input Leakage Current does not include inputs with pull-up or pull-down resistors.
11
PRELIMINARY
AC Electrical Characteristics
TA = 0C to +70C, VDDQ3 = 3.3V5%, V DDQ2 = 2.5V5% fXTL = 14.31818 MHz 66.6-MHz Host Parameter TPeriod THIGH TLOW TRISE TFALL TPeriod THIGH TLOW TRISE TFALL TPeriod THIGH TLOW TRISE TFALL TPeriod THIGH TLOW TRISE TFALL TPeriod THIGH TLOW TRISE TFALL tpZL, tpZH tpLZ, tpZH tstable Description Host/CPUCLK Period Host/CPUCLK High Time Host/CPUCLK Low Time Host/CPUCLK Rise Time Host/CPUCLK Fall Time SDRAM CLK Period SDRAM CLK High Time SDRAM CLK Low Time SDRAM CLK Rise Time SDRAM CLK Fall Time APIC 33-MHz CLK Period APIC 33-MHz CLK High Time APIC 33-MHz CLK Low Time APIC CLK Rise Time APIC CLK Fall Time 3V66 CLK Period 3V66 CLK High Time 3V66 CLK Low Time 3V66 CLK Rise Time 3V66 CLK Fall Time PCI CLK Period PCI CLK High Time PCI CLK Low Time PCI CLK Rise Time PCI CLK Fall Time Output Enable Delay (All outputs) Output Disable Delay (All outputs) All Clock Stabilization from Power-Up Min. 15.0 5.2 5.0 0.4 0.4 10.0 3.0 2.8 0.4 0.4 30.0 12.0 12.0 0.4 0.4 15.0 5.25 5.05 0.5 0.5 30.0 12.0 12.0 0.5 0.5 1.0 1.0 Max. 15.5 N/A N/A 1.6 1.6 10.5 N/A N/A 1.6 1.6 N/A N/A N/A 1.6 1.6 16.0 N/A N/A 2.0 2.0 N/A N/A N/A 2.0 2.0 10.0 10.0 3 100-MHz Host Min. 10.0 3.0 2.8 0.4 0.4 10.0 3.0 2.8 0.4 0.4 30.0 12.0 12.0 0.4 0.4 15.0 5.25 5.05 0.5 0.5 30.0 12.0 12.0 0.5 0.5 1.0 1.0 Max. 10.5 N/A N/A 1.6 1.6 10.5 N/A N/A 1.6 1.6 N/A N/A N/A 1.6 1.6 16.0 N/A N/A 2.0 2.0 N/A N/A N/A 2.0 2.0 10.0 10.0 3 133-MHz Host Min. 7.5 1.87 1.67 0.4 0.4 10.0 3.0 2.8 0.4 0.4 30.0 12.0 12.0 0.4 0.4 15.0 5.25 5.05 0.5 0.5 30.0 12.0 12.0 0.5 0.5 1.0 1.0 Max. 8.0 N/A N/A 1.6 1.6 10.5 N/A N/A 1.6 1.6 N/A N/A N/A 1.6 1.6 16.0 N/A N/A 2.0 2.0 N/A N/A N/A 2.0 2.0 10.0 10.0 3 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
W229B
Notes 10 13 14
10 13 14
10 13 14
10, 12 13 14
10, 11 13 14
Notes: 10. Period, jitter, offset, and skew measured on rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks. 11. THIGH is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs. 12. TLOW is measured at 0.4V for all outputs. 13. The time specified is measured from when VDDQ3 achieves its nominal operating level (typical condition VDDQ3 = 3.3V) until the frequency output is stable and operating within specification. 14. TRISE and TFALL are measured as a transition through the threshold region Vol = 0.4V and Voh = 2.0V (1 mA) JEDEC specification.
12
PRELIMINARY
Group Skew and Jitter Limits
Output Group CPU SDRAM APIC 48MHz 3V66 PCI REF Pin-Pin Skew Max. 175 ps 250 ps 250 ps 250 ps 175 ps 500 ps N/A Cycle-Cycle Jitter 250 ps 250 ps 500 ps 500 ps 500 ps 500 ps 1000 ps Duty Cycle 45/55 45/55 45/55 45/55 45/55 45/55 45/55 Nom Vdd 2.5V 3.3V 2.5V 3.3V 3.3V 3.3V 3.3V
W229B
Skew, Jitter Measure Point 1.25V 1.5V 1.25V 1.5V 1.5V 1.5V 1.5V
Output Buffer Clock Output Wave
Test Point
Test Load TPERIOD Duty Cycle THIGH
2.0
2.5V Clocking Interface
1.25 0.4
TLOW TRISE TFALL TPERIOD Duty Cycle THIGH
2.4
3.3V Clocking Interface
1.5 0.4
TLOW TRISE TFALL
Figure 10. Output Buffer
Ordering Information
Ordering Code W229B Package Name H Package Type 56-pin SSOP (300 mils)
I2C is a trademark of Phillips Corporation Intel is a registered trademark of Intel Corporation. Document #: 38-00889
13
PRELIMINARY
Layout Example
+3.3V Supply FB
VDDQ3
W229B
+2.5V Supply FB
VDDQ2
10 F
C4
0.005 F
C3
C1 G V G
10 F
0.005 F
C2 G G G
G
G
G
C2
G
1 2 3 4 5 6 7 8 9
C1
G V G
10 G
G
VDDQ3
5
C5 G
G C6 G
11 12 13 14 G 15 16 17 V G 18 19 20 21 G 22 23 24 25 26 27 G 28 V
C1 & C3 = 10-22 F
VDDQ3 Core
56 55 54 V 53 G 52 51 G 50 49 48 G 47 V 46 G 45 44 43 42 G 41 V 40 G 39 38 37 36 G 35 V 34 G 33 32 31 30 G 29
V G C5 = 47 F
G
G
G
FB = Dale ILB1206 - 300 (300 @ 100 MHz) C2 & C4 = 0.005 F C6 = 0.1 F
W229B
G
G
G = VIA to GND plane layer
V =VIA to respective supply plane layer
Note: Each supply plane or strip should have a ferrite bead and capacitors
14
PRELIMINARY
Package Diagram
56-Pin Shrink Small Outline Package (SSOP, 300 mils)
W229B
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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