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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MC74VHCT4066/D
Advance Information
Quad Analog Switch/ Multiplexer/Demultiplexer
MC74VHCT4066
High-Performance Silicon-Gate CMOS
The MC74VHCT4066 utilizes silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF- channel leakage current. This bilateral switch/multiplexer/demultiplexer controls analog and digital voltages that may vary across the full power-supply range (from VCC to GND). The VHCT4066 is identical in pinout to the metal-gate CMOS MC14066 and the high-speed CMOS HC4066A. Each device has four independent switches. The device has been designed so that the ON resistances (RON) are much more linear over input voltage than RON of metal-gate CMOS analog switches. The ON/OFF control inputs are compatible with standard LSTTL outputs. The input protection circuitry on this device allows overvoltage tolerance on the ON/OFF control inputs, allowing the device to be used as a logic-level translator from 3.0V CMOS logic to 5.0V CMOS Logic or from 1.8V CMOS logic to 3.0V CMOS Logic while operating at the higher-voltage power supply. The MC74VHCT4066 input structure provides protection when voltages up to 7V are applied, regardless of the supply voltage. This allows the MC74VHCT4066 to be used to interface 5V circuits to 3V circuits. * * * * * * * Fast Switching and Propagation Speeds High ON/OFF Output Voltage Ratio Low Crosstalk Between Switches Diode Protection on All Inputs/Outputs Wide Power-Supply Voltage Range (VCC - GND) = 2.0 to 6.0 Volts Analog Input Voltage Range (VCC - GND) = 2.0 to 6.0 Volts Improved Linearity and Lower ON Resistance over Input Voltage than the MC14016 or MC14066 * Low Noise LOGIC DIAGRAM
XA A ON/OFF CONTROL XB B ON/OFF CONTROL XC C ON/OFF CONTROL XD D ON/OFF CONTROL 1 13 4 5 8 6 11 12 10 YD ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD PIN 14 = VCC PIN 7 = GND 9 YC 3 YB ANALOG OUTPUTS/INPUTS 2 YA D SUFFIX 14-LEAD SOIC PACKAGE CASE 751A-03
DT SUFFIX 14-LEAD TSSOP PACKAGE CASE 948G-01 ORDERING INFORMATION MC74VHCTXXXXD MC74VHCTXXXXDT SOIC TSSOP
PIN ASSIGNMENT
XA YA YB XB B ON/OFF CONTROL C ON/OFF CONTROL GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC A ON/OFF CONTROL D ON/OFF CONTROL XD YD YC XC
FUNCTION TABLE
On/Off Control Input L H State of Analog Switch Off On
This document contains information on a new product. Specifications and information herein are subject to change without notice.
10/98
(c) Motorola, Inc. 1998
1
REV 0
MC74VHCT4066
II I II I I I II I I I I I I II I II I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIIIIIII I I II I I I II I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I III I I I I I I II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIII I I I I II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I I IIII I I III I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII I III I I I I I I IIIIIIIIIIIIIIIIIIIIIII III I I III I I III IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII II I I III I IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I
II I I I IIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIII II I I I I I I IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIII IIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS*
Symbol VCC VIS Vin I Parameter Value Unit V V V Positive DC Supply Voltage (Referenced to GND) Analog Input Voltage (Referenced to GND) Digital Input Voltage (Referenced to GND) DC Current Into or Out of Any Pin Power Dissipation in Still Air, - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 -20 500 450 mA PD SOIC Package TSSOP Package mW TstgIIIIIIIIIIIIII - 65 to + 150 Storage Temperature TL Lead Temperature, 1 mm from Case for 10 Seconds 260
_C _C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus.
v
v
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIS Vin TA Parameter Min 2.0 Max 6.0 Unit V V V Positive DC Supply Voltage (Referenced to GND) Analog Input Voltage (Referenced to GND) Digital Input Voltage (Referenced to GND) Static or Dynamic Voltage Across Switch
GND GND --
VCC VCC 100
VIO* tr, tf
mV
Operating Temperature, All Package Types
- 55 0 0
+ 125 100 20
_C
Input Rise and Fall Time, ON/OFF Control Inputs (Figure 10) VCC = 3.3 V 0.3 V VCC = 5.0 V 0.5 V
ns/V
* For voltage drops across the switch greater than 100 mV (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to GND)
VCC V 3.0 4.5 6.0 3.0 4.5 6.0 6.0 6.0
Guaranteed Limit
S bl Symbol VIH
P Parameter
T Test C di i Conditions
- 55 to 25_C 1.2 2.0 2.0
v 85_C v 125_C
1.2 2.0 2.0 1.2 2.0 2.0 0.53 0.8 0.8 0.53 0.8 0.8
Ui Unit V
Minimum High-Level Voltage ON/OFF Control Inputs (Note 1)
Ron = Per Spec
VIL
Maximum Low-Level Voltage ON/OFF Control Inputs (Note 1)
Ron = Per Spec
0.53 0.8 0.8
V
Iin
Maximum Input Leakage Current ON/OFF Control Inputs Maximum Quiescent Supply Current (per Package)
Vin = VCC or GND Vin = VCC or GND VIO = 0 V
0.1 4.0
1.0 40
1.0 160
A A
ICC
1. Specifications are for design target only. Not final specification limits.
MOTOROLA
2
VHC Data - Advanced CMOS Logic DL203 -- Rev 2
MC74VHCT4066
DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND)
VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 3.0 4.5 6.0 6.0
IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIII I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I III I I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I II I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I I I I II I I I II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I II I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I III I I I I I I II I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIII IIIIIIIIIIIIIIIIIIIIIII I II I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIII I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I I
Guaranteed Limit Symbol S bl Ron Parameter P Test C di i T Conditions - 55 to 25_C -- 25 18 15 -- 20 15 10 -- 20 15
v 85_C v 125_C
-- 30 23 20 -- 25 20 15 -- 25 20 -- 35 28 25 -- 30 25 20 -- 30 25
Unit Ui
Maximum "ON" Resistance
Vin = VIH VIS = VCC to GND IS 2.0 mA (Figures 1, 2)
v v
Vin = VIH VIS = VCC or GND (Endpoints) IS 2.0 mA (Figures 1, 2) Vin = VIH VIS = 1/2 (VCC - GND) IS 2.0 mA
Ron
Maximum Difference in "ON" Resistance Between Any Two Channels in the Same Package
v
Ioff
Maximum Off-Channel Leakage Current, Any One Channel
Vin = VIL VIO = VCC or GND Switch Off (Figure 3) Vin = VIH VIS = VCC or GND (Figure 4)
0.1
0.5
1.0
A
Ion
Maximum On-Channel Leakage Current, Any One Channel
6.0
0.1
0.5
1.0
A
At supply voltage (VCC) approaching 2 V the analog switch-on resistance becomes extremely non-linear. Therefore, for low-voltage operation, it is recommended that these devices only be used to control digital signals.
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, ON/OFF Control Inputs: tr = tf = 6 ns)
VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 -- -- --
Guaranteed Limit
Symbol S bl tPLH, tPHL
Parameter P
- 55 to 25_C 4.0 3.0 1.0 1.0 30 20 15 15
v 85_C v 125_C
6.0 5.0 2.0 2.0 35 25 18 18 25 14 10 10 10 8.0 6.0 2.0 2.0 40 30 22 20 30 15 12 12 10
Unit Ui ns
Maximum Propagation Delay, Analog Input to Analog Output (Figures 8 and 9)
tPLZ, tPHZ
Maximum Propagation Delay, ON/OFF Control to Analog Output (Figures 10 and 11)
ns
tPZL, tPZH
Maximum Propagation Delay, ON/OFF Control to Analog Output (Figures 10 and 1 1)
20 12 8.0 8.0 10
ns
C
Maximum Capacitance
ON/OFF Control Input
pF
Control Input = GND Analog I/O Feedthrough
35 1.0
35 1.0
35 1.0
Typical @ 25C, VCC = 5.0 V 15
CPD
Power Dissipation C P Di i i Capacitance (P S i h) (Fi i (Per Switch) (Figure 13)*
pF F
* Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC .
VHC Data - Advanced CMOS Logic DL203 -- Rev 2
3
MOTOROLA
MC74VHCT4066
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
Symbol BW Parameter Test Conditions
II II I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I II I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I III I I I II I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII I II I II II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II I I I III I I I II I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
VCC V 4.5 6.0 Limit* 25_C 150 160 Unit Maximum On-Channel Bandwidth or Minimum Frequency Response (Figure 5) Off-Channel Feedthrough Isolation (Figure 6) fin = 1 MHz Sine Wave Adjust fin Voltage to Obtain 0 dBm at VOS Increase fin Frequency Until dB Meter Reads - 3 dB RL = 50 , CL = 10 pF fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 , CL = 50 pF MHz --
4.5 6.0 4.5 6.0 4.5 6.0 4.5 6.0 4.5 6.0 4.5 6.0
- 50 - 50 - 40 - 40 100 200
dB
fin = 1.0 MHz, RL = 50 , CL = 10 pF
--
Feedthrough Noise, Control to Switch (Figure 7)
Vin 1 MHz Square Wave (tr = tf = 3 ns) Adjust RL at Setup so that IS = 0 A RL = 600 , CL = 50 pF
v
mVPP
RL = 10 k, CL = 10 pF
--
Crosstalk Between Any Two Switches (Figure 12)
fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 , CL = 50 pF
50 100
- 70 - 70 - 80 - 80
dB
fin = 1.0 MHz, RL = 50 , CL = 10 pF
THD
Total Harmonic Distortion (Figure 14)
fin = 1 kHz, RL = 10 k, CL = 50 pF THD = THDMeasured - THDSource VIS = 4.0 VPP sine wave VIS = 5.5 VPP sine wave
%
4.5 6.0
0.10 0.06
* Guaranteed limits not tested. Determined by design and verified by qualification.
MOTOROLA
4
VHC Data - Advanced CMOS Logic DL203 -- Rev 2
MC74VHCT4066
TBD
TBD
Figure 1a. Typical On Resistance, VCC = 2.0 V
Figure 1b. Typical On Resistance, VCC = 3.0 V
PLOTTER
TBD
PROGRAMMABLE POWER SUPPLY - +
MINI COMPUTER
DC ANALYZER
VCC DEVICE UNDER TEST
ANALOG IN
COMMON OUT
GND
Figure 1c. Typical On Resistance, VCC = 4.5 V
Figure 2. On Resistance Test Set-Up
VHC Data - Advanced CMOS Logic DL203 -- Rev 2
5
MOTOROLA
MC74VHCT4066
VCC VCC GND VCC A OFF 14 VCC A GND ON 14 N/C VCC
7
SELECTED CONTROL INPUT
VIL 7
SELECTED CONTROL INPUT
VIH
Figure 3. Maximum Off Channel Leakage Current, Any One Channel, Test Set-Up
Figure 4. Maximum On Channel Leakage Current, Test Set-Up
VCC 14 fin 0.1F ON
VOS fin 0.1F
VIS OFF RL SELECTED CONTROL INPUT 7
VCC 14
VOS
CL*
dB METER
CL*
dB METER
7
SELECTED CONTROL INPUT
VCC
*Includes all probe and jig capacitance.
*Includes all probe and jig capacitance.
Figure 5. Maximum On-Channel Bandwidth Test Set-Up
Figure 6. Off-Channel Feedthrough Isolation, Test Set-Up
VCC/2 14 RL OFF/ON
VCC
VCC/2
RL IS
VOS CL* VCC ANALOG IN tPLH 50% ANALOG OUT 50% GND tPHL
VIH VIL
Vin 1 MHz tr = tf = 3 ns CONTROL
7
SELECTED CONTROL INPUT
*Includes all probe and jig capacitance.
Figure 7. Feedthrough Noise, ON/OFF Control to Analog Out, Test Set-Up
Figure 8. Propagation Delays, Analog In to Analog Out
MOTOROLA
6
VHC Data - Advanced CMOS Logic DL203 -- Rev 2
MC74VHCT4066
VCC 14 ANALOG IN ON CL* 50% ANALOG OUT 50% *Includes all probe and jig capacitance. tPZH tPHZ 90% VOH HIGH IMPEDANCE ANALOG OUT TEST POINT CONTROL 90% 50% 10% tPZL tPLZ tr tf VCC GND HIGH IMPEDANCE 10% VOL
7
SELECTED CONTROL INPUT
VIH
Figure 9. Propagation Delay Test Set-Up
Figure 10. Propagation Delay, ON/OFF Control to Analog Out
VIS VCC RL 14 ON 0.1 F TEST POINT OFF VIH OR VIL RL SELECTED CONTROL INPUT 7 VCC/2 RL CL* RL CL* fin VOS
POSITION 1 WHEN TESTING tPHZ AND tPZH 1 2 VCC 1 2 ON/OFF CL* VIH VIL SELECTED CONTROL INPUT 7 POSITION 2 WHEN TESTING tPLZ AND tPZL VCC 14 1 k
VCC/2
VCC/2
*Includes all probe and jig capacitance.
*Includes all probe and jig capacitance.
Figure 11. Propagation Delay Test Set-Up
Figure 12. Crosstalk Between Any Two Switches, Test Set-Up
VCC A 14 N/C OFF/ON N/C 0.1 F fin ON RL SELECTED CONTROL INPUT VCC/2 7 SELECTED CONTROL INPUT VIH CL* VIS
VCC
VOS TO DISTORTION METER
7 VIH VIL
ON/OFF CONTROL *Includes all probe and jig capacitance.
Figure 13. Power Dissipation Capacitance Test Set-Up
Figure 14. Total Harmonic Distortion, Test Set-Up
VHC Data - Advanced CMOS Logic DL203 -- Rev 2
7
MOTOROLA
MC74VHCT4066
0 - 10 - 20 - 30 dBm - 40 - 50 - 60 - 70 - 80 - 90 1.0 2.0 FREQUENCY (kHz) 3.0 DEVICE SOURCE FUNDAMENTAL FREQUENCY
Figure 15. Plot, Harmonic Distortion
APPLICATION INFORMATION
The ON/OFF Control pins should be at VIH or VIL logic levels, VIH being recognized as logic high and VIL being recognized as a logic low. Unused analog inputs/outputs may be left floating (not connected). However, it is advisable to tie unused analog inputs and outputs to VCC or GND through a low value resistor. This minimizes crosstalk and feedthrough noise that may be picked-up by the unused I/O pins. The maximum analog voltage swings are determined by the supply voltages VCC and GND. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below GND. In the example
below, the difference between VCC and GND is six volts. Therefore, using the configuration in Figure 16, a maximum analog signal of six volts peak-to-peak can be controlled. When voltage transients above VCC and/or below GND are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure 17. These diodes should be small signal, fast turn-on types able to absorb the maximum anticipated current surges during clipping. An alternate method would be to replace the Dx diodes with MOsorbs (Motorola high current surge protectors). MOsorbs are fast turn-on devices ideally suited for precise DC protection with no inherent wear out mechanism.
VCC = 6.0 V + 6.0 V 0V 14 ANALOG I/O ON ANALOG O/I + 6.0 V 0V Dx
VCC 16 ON Dx VIH SELECTED CONTROL INPUT 7
VCC Dx
Dx
VIH
SELECTED CONTROL INPUT 7
OTHER CONTROL INPUTS (VIH OR VIL)
OTHER CONTROL INPUTS (VIH OR VIL)
Figure 16. 6.0 V Application
Figure 17. Transient Suppressor Application
MOTOROLA
8
VHC Data - Advanced CMOS Logic DL203 -- Rev 2
MC74VHCT4066
+3 V +5 V
+3V GND
ANALOG SIGNALS
14
ANALOG SIGNALS
+3V GND
ANALOG SIGNALS
14
ANALOG SIGNALS
VHCT4066 1.8 - 2.5V CIRCUITRY 5 6 14 15 R* = 2 TO 10 k CONTROL INPUTS 7
LSTTL/ NMOS/ ABT/ ALS
VHCT4066 5 6 14 15 CONTROL INPUTS 7
a. Low Voltage Logic Level Shifting Control Figure 18. Low Voltage CMOS Interface
b. Using VHCT4066
CHANNEL 4
1 OF 4 SWITCHES 1 OF 4 SWITCHES COMMON I/O 1 OF 4 SWITCHES 1 OF 4 SWITCHES - INPUT 1 OF 4 SWITCHES + 0.01 F 1 2 34 CONTROL INPUTS LF356 OR EQUIVALENT OUTPUT
CHANNEL 3
CHANNEL 2
CHANNEL 1
Figure 19. 4-Input Multiplexer
Figure 20. Sample/Hold Amplifier
VHC Data - Advanced CMOS Logic DL203 -- Rev 2
9
MOTOROLA
MC74VHCT4066
OUTLINE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F
8
-A-
14
-B-
1 7
P 7 PL
0.25 (0.010)
M
B
M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
G C
R X 45
F
SEATING PLANE
D
14 PL
K
M
M B
S
J
0.25 (0.010)
T
A
S
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.75 8.55 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 7 0 0.228 0.244 0.010 0.019
MOTOROLA
10
VHC Data - Advanced CMOS Logic DL203 -- Rev 2
MC74VHCT4066
OUTLINE DIMENSIONS
DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948G-01 ISSUE O
14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
N
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K K1 J J1
0.15 (0.006) T U
S
SECTION N-N -W-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
VHC Data - Advanced CMOS Logic DL203 -- Rev 2
11
EEE CCC EEE CCC
A -V-
MOTOROLA
MC74VHCT4066
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 Customer Focus Center: 1-800-521-6274 MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, Motorola Fax Back System - US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 - http://sps.motorola.com/mfax/ HOME PAGE: http://motorola.com/sps/ JAPAN: Nippon Motorola Ltd.; SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan. 81-3-5487-8488
MOTOROLA 12
MC74VHCT4066/D VHC Data - Advanced CMOS Logic DL203 -- Rev 2

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