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| SSRX3930 Low Power ISM-Band FM/FSK Receiver IC Description The SSRX3930 is a low power 433/868/915 MHz FM/FSK receiver IC which is suitable for use in the North American 915 MHz and the European 433 and 868 MHz ISM bands. Features Integrated VCO with fixed / 64 prescaler, phase/frequency detector, and reference oscillator forming complete phase-locked loop User selectable FM or FSK output RSSI output with 70 dB dynamic range Receiver enable pin for power saving TQFP-32 package (5mm x 5mm) Applications Wireless mouse Wireless amplifier/ speaker/ earphone/ microphone Wireless car alarm system Block Diagram OSC RXEN IN OSC OUT DO VSS4 VCC2 RES RES Pin Out Diagram 32 VCC1 1 RXIN 2 31 OSC 30 29 28 27 26 25 IF2DEC IF2DEC VCC3 MUTE RSSI FMOUT IF2OUT QUAD VCO PFD / 64 24 QUAD 23 IF2 OUT OUT RES RES VCC2 VSS4 DO OSCOUT OSCIN RXEN 25 26 27 28 29 30 31 32 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 16 15 14 13 12 11 10 9 VSS1 3 LNA OUT 4 VSS2 5 LNA BIAS COMPARATOR/ AUDIO AMP 22 FM IF2IN VSS5 VREFIF IF1OUT IF1DEC IF1DEC IFIN IFIN 21 RSSI 20 MUTE MIXER MIX 6 IN VSS3 7 MIX 8 OUT IFAMP RSSI DEMOD LIMITER 19 VCC3 18 IF2 IF2 1 2 3 4 5 6 7 8 DEC MIXOUT VSS3 MIXIN VSS2 LNAOUT VSS1 RXIN VCC1 17 DEC 9 IFIN 10 IFIN 11 IF1 DEC 12 IF1 DEC 13 14 15 16 VREF VSS5 IF2 IF1 OUT IF IN Rev.2.01 6/26/2003 www.SiliconStandard.com 1 of 7 SSRX3930 Pin Descriptions Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Name VCC1 RXIN VSS1 LNAOUT VSS2 MIXIN VSS3 MIXOUT IFIN IFIN IF1DEC IF1DEC IF1OUT VREFIF VSS5 IF2 IN IF2DEC IF2DEC VCC3 MUTE RSSI FMOUT IF2OUT QUAD RES RES VCC2 VSS4 DO I/O POWER I GND O GND I GND O I I I/O I/O O O GND I I/O I/O POWER I O O O I I/O I/O POWER GND I/O Supply DC bias for RF amplifier RF amplifier input Ground for RF amplifier LNA output Ground for 40dB IF limiting amplifier RF input to RF Mixer Ground for RF Mixer IF output from RF Mixer IF input (required 10nF DC blocking capacitor) Same as pin 9 except non-inverting node amplifier input DC feedback for 40dB limiting amplifier (required 100nF bypass capacitor) See pin 11 IF output from the 40 dB limiting amplifier DC voltage reference for the IF limiting amplifier (required 0.1 F capacitor) Ground for 60dB IF limiting amplifier Inverting input to the 60dB limiting amplifier (required 10nF DC blocking capacitor) DC feedback node for the 60dB limiting amplifier (required 100nF bypass capacitor) See pin 17 Supply DC bias to the 60dB IF limiting amplifier Select FM, FSK, or mute at the FM OUT pin. (to Ground: FSK OUTPUT; floating: FM OUTPUT; to Vcc: muting) Proportional DC voltage (0.5V~2.5V) output Demodulated output IF output from the 60dB limiting strip FM demodulator input (not AC coupled) Supply DC voltage to VCO See pin 25 Supply DC bias to the VCO, prescaler, and PLL Ground shared by the VCO, prescaler, and PLL Output of the charge pump, and input to the VCO Description Rev.2.01 6/26/2003 www.SiliconStandard.com 2 of 7 SSRX3930 Number 30 31 32 Name OSCOUT OSCIN RXEN I/O I/O I/O I Description Connected to the reference oscillator transistor base Connected to the emitter of the reference oscillator transistor Power up or down. (logic high powers up the receiver and PLL; logic low powers down circuit to stand by mode) Absolute Maximum Ratings VSS = 0 V Parameter Supply voltage Operating temperature range Storage temperature range Soldering temperature range Soldering time range Symbol VCC1 VCC2 TOPR TSTG TSLD tSLD Rating VSS - 0.5 to VSS + 5.5 -40 to 85 -40 to 150 255 10 Unit V C C C s Recommended Operating Conditions VSS = 0 V Value Parameter Symbol min. VCC1 Supply voltage range VCC2 VCC3 Operating temperature TA 2.7 2.7 2.7 -10 typ. 3.6 3.6 3.6 25 max. 5.0 5.0 5.0 60 V V V Unit C Rev.2.01 6/26/2003 www.SiliconStandard.com 3 of 7 SSRX3930 Receiver Characteristics (VCC1, VCC2, VCC3 = 2.7 to 5.0 V, VSS = 0 V, RXEN = high, TA = -10 to 60 C unless otherwise noted) Value Parameter Input RF frequency range Psens LO BWIF = 150 KHz, fRF = 915 MHz, SNR = 8 dB Symbol Condition min. 300 typ. max. 1000 MHz Unit Sensitivity -97 dBm LO leakage -55 dBm Electrical Characteristics (VCC1, VCC2, VCC3 = 2.7 to 5.0 V, VSS = 0 V, RXEN = high, TA = -10 to 60 C, fRF = 915 MHz unless otherwise noted) Value Parameter Power supply VCC1 supply voltage VCC2 supply voltage VCC3 supply voltage Total dc current (normal operation) Total dc current (stand-by mode) LNA Power gain Noise figure Input third-order intermodulation intercept point Mixer Conversion power gain Noise figure (SSB) Input third-order intermodulation intercept point VCO Frequency range External varactor 300 1000 MHz GC NFMIX IIP3MIX Matched to 50 7 17 -15.5 dB dB dBm GLNA NFLNA IIP3LNA Matched to 50 17 3.8 -8 dB dB dBm VCC1 VCC2 VCC3 IDC Istandby RXEN = low 2.7 2.7 2.7 3.6 3.6 3.6 10 1 5.0 5.0 5.0 V V V mA A Symbol Condition min. typ. max. Unit Rev.2.01 6/26/2003 www.SiliconStandard.com 4 of 7 SSRX3930 Value Parameter PLL N-divider ratio Reference frequency Charge pump current Lock time fREF ICP lock PLL's lock time set by bandwidth of external loop filter -40 64 17 40 MHz A ms Symbol Condition min. typ. max. Unit 10 IF amplifier Frequency range Input impedance Output impedance Limiter Frequency range Input impedance Output impedance RSSI RSSI dynamic range RSSI dc output range FM/FSK Demodulator Demodulated output level (audio) FSK output duty ratio VOD 40 70 50 60 mVrms % Rload = 51 K 0.5 70 2.5 dB V Zin,IF Zout,IF 0.1 10.7 330 330 25 MHz Zin,IF Zout,IF 0.1 10.7 330 330 25 MHz Rev.2.01 6/26/2003 www.SiliconStandard.com 5 of 7 SSRX3930 Application Circuit (906 MHz) 47N 2.7K Ctrim 100P RXEN 100P *:Alpha smv1233-11 3.3N 10K * 3.9N 10 VCC 47P 10N 2.7P 14.31818MHz 3.9N 32 10N VCC 12N RXIN 22P 47P 31 30 OSC OUT 29 DO 28 27 26 25 RES QUAD IF2 OUT FM OUT RSSI RXEN OSC IN VSS4 VCC2 RES **: 10.7MHz discriminator CDF-107B 15K 1 VCC1 2 RXIN 3 VSS1 8.2N LNA 24 23 22 21 ** 2.2P 10N FMOUT RSSI 10P MUTE 51K VCC 100P 47P 10N 4 OUT 5 VSS2 6 MIX IN MUTE 20 VCC3 19 IF2 DEC IF1 DEC IF1 DEC IF2 DEC VREF IF1 IF2 OUT IF VSS5 IN VCC 10N 47P 10N 7 VSS3 VCC 47P 10uA 10N 18 17 8 OUT IFIN IFIN MIX 10N 9 10N 10 11 12 13 14 15 16 10N 10N 10N 10N LT 10.7MS3 f 0 = 10.7MHz BW = 180KHz Rev.2.01 6/26/2003 www.SiliconStandard.com 6 of 7 SSRX3930 Package and Pin Assignment: TQFP-32 IF2DEC IF2DEC VCC3 MUTE RSSI FMOUT IF2OUT QUAD 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 RES RES VCC2 VSS4 DO OSCOUT OSCIN RXEN 25 26 27 28 29 30 31 32 IF2IN VSS5 VREFIF IF1OUT IF1DEC IF1DEC IFIN IFIN MIXOUT VSS3 MIXIN VSS2 LNAOUT VSS1 RXIN VCC1 Dimensions in mm Symbols min. A A1 A2 b C D1 D E1 E e L L1 1 ccc nom. max. 1.20 0.15 1.05 0.27 0.20 5.10 7.20 5.10 7.20 min. Dimensions in inch nom. max. 0.047 0.006 0.041 0.011 0.008 0.201 0.283 0.201 0.283 -- 0.05 0.95 0.17 0.09 4.90 6.80 4.90 6.80 -- -- 1.00 0.22 -- 0.002 0.037 0.007 0.003 0.193 0.267 0.193 0.267 -- -- 0.039 0.009 -- 5.00 7.00 5.00 7.00 0.50(typ) 0.60 1.00(ref.) 3.5 -- 0.197 0.275 0.197 0.275 0.02(typ) 0.024 0.039(ref.) -- 0.45 -- 0.75 -- 0.018 -- 0.029 -- 0 -- 7 0.008 -- 0 -- 8 0.003 3.5 -- -- -- -- Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. Rev.2.01 6/26/2003 www.SiliconStandard.com 7 of 7 |
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