View ICS843023I_284479.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
ICS843023I
FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
FEATURES
* 1 differential 3.3V LVPECL output * Crystal oscillator interface designed for 25MHz, 18pF parallel resonant crystal * Output frequency range: 245MHz - 320MHz * VCO range: 490MHz - 640MHz * RMS phase jitter @ 250MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.39ps (typical) Phase noise: Offset Noise Power 100Hz ............... -86.3 dBc/Hz 1kHz .............. -114.6 dBc/Hz 10kHz .............. -125.6 dBc/Hz 100kHz ................ -126 dBc/Hz * 3.3V or 2.5V operating supply * -40C to 85C ambient operating temperature * Lead-Free package fully RoHS compliant
GENERAL DESCRIPTION
The ICS843023I is a Gigabit Ethernet Clock Generator and a member of the HiPerClocksTM HiPerClockSTM family of high performance devices from ICS. The ICS843023I uses a 25MHz crystal to synthesize 250MHz. The ICS843023I has excellent phase jitter performance, over the 1.875MHz - 20MHz integration range. The ICS843023I is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space.
ICS
BLOCK DIAGRAM
OE 25MHz XTAL_IN
PIN ASSIGNMENT
VCC XTAL_OUT XTAL_IN VEE 1 2 3 4 8 7 6 5 Q nQ VCC OE
OSC
XTAL_OUT
Phase Detector
VCO
/2 (fixed)
Q nQ
ICS843023I
/20 (fixed)
8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View
843023AGI
www.icst.com/products/hiperclocks.html
1
REV. A JUNE 29, 2005
Integrated Circuit Systems, Inc.
ICS843023I
FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
Type Description Core supply pin. Cr ystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Negative supply pin. Active high output enable. When logic HIGH, the outputs are enabled and active. When logic LOW, the outputs are disabled and the device is in power down mode. LVCMOS/LVTTL interface levels. Differential clock outputs. LVPECL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 6 2, 3 4 5 7, 8 Name VCC XTAL_OUT, XTAL_IN VEE OE nQ, Q Power Input Power Input Output Pullup
Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP Parameter Input Capacitance Input Pullup Resistor Test Conditions Minimum Typical 4 51 Maximum Units pF k
843023AGI
www.icst.com/products/hiperclocks.html
2
REV. A JUNE 29, 2005
Integrated Circuit Systems, Inc.
ICS843023I
FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
4.6V -0.5V to VCC + 0.5V 50mA 100mA 101.7C/W (0 mps) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V5%, TA = -40C TO 85C
Symbol VCC VCCA IEE Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 75 Units V V mA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.5V5%, TA = -40C TO 85C
Symbol VCC VCCA IEE Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Test Conditions Minimum 2.375 2.375 Typical 2. 5 2. 5 Maximum 2.625 2.625 70 Units V V mA
TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 3.3V5% OR 2.5V5%, TA = -40C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current OE OE Test Conditions VCC = 3.3V VCC = 2.5V VCC = 3.3V VCC = 2.5V VCC = VIN = 3.465V or 2.625V VCC = 3.465V or 2.625V, VIN = 0V -150 Minimum 2 1.7 -0.3 -0.3 Typical Maximum VCC + 0.3 VCC + 0.3 0.8 0.7 5 Units V V V V A A
TABLE 3D. LVPECL DC CHARACTERISTICS, VCC = 3.3V5% OR 2.5V5%, TA = -40C TO 85C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.6 Typical Maximum VCC - 0.9 VCC - 1.7 1.0 Units V V V
NOTE 1: Outputs terminated with 50 to VCC - 2V.
www.icst.com/products/hiperclocks.html
3
843023AGI
REV. A JUNE 29, 2005
Integrated Circuit Systems, Inc.
ICS843023I
FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
Test Conditions Minimum 24.5 Typical Fundamental 32 50 7 1 MHz pF mW Maximum Units
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level
TABLE 5A. AC CHARACTERISTICS, VCC = 3.3V5%, TA = -40C TO 85C
Symbol fOUT Parameter Output Frequency RMS Phase Jitter (Random); NOTE 1 Output Rise/Fall Time Test Conditions 250MHz, Integration Range: 1.875MHz - 20MHz 20% to 80% Minimum 245 0.39 300 47 600 53 Typical Maximum 320 Units MHz ps ps %
tjit(O)
tR / tF
odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plot after this section.
TABLE 5B. AC CHARACTERISTICS, VCC = 2.5V5%, TA = -40C TO 85C
Symbol fOUT Parameter Output Frequency RMS Phase Jitter (Random); NOTE 1 Output Rise/Fall Time Test Conditions 250MHz, Integration Range: 1.875MHz - 20MHz 20% to 80% Minimum 245 0.39 300 47 600 53 Typical Maximum 320 Units MHz ps ps %
tjit(O)
tR / tF
odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plot after this section.
843023AGI
www.icst.com/products/hiperclocks.html
4
REV. A JUNE 29, 2005
Integrated Circuit Systems, Inc.
ICS843023I
FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
TYPICAL PHASE NOISE AT 250MHZ (3.3V)
0 -10 -20 -30 -40 -50
Gigabit Ethernet Filter 250MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.39ps (typical)
NOISE POWER dBc Hz
-60 -70 -80 -90 -100
Raw Phase Noise Data
-110 -120 -130 -140 -150
-170 -180 -190 100 1k 10k
-160
Phase Noise Result by adding Gigabit Ethernet Filter to raw data
100k 1M 10M 100M 500M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 250MHZ (2.5V)
0 -20 -30 -40 -50
Gigabit Ethernet Filter 250MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.39ps (typical)
-10
NOISE POWER dBc Hz
-60 -70 -80 -90 -100
Raw Phase Noise Data
-110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k
10k
OFFSET FREQUENCY (HZ)
843023AGI
www.icst.com/products/hiperclocks.html
5
Phase Noise Result by adding Gigabit Ethernet Filter to raw data
100k 1M 10M 100M 500M
REV. A JUNE 29, 2005
Integrated Circuit Systems, Inc.
ICS843023I
FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V 2V
V CC
Qx
SCOPE
VCC
Qx
SCOPE
LVPECL
nQx
LVPECL
nQx
VEE
VEE
-1.3V 0.165V
-0.5V 0.125V
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
Noise Power
80%
Phase Noise Mask
80% VSW I N G
Clock Outputs
20% tR tF
20%
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT RISE/FALL TIME
nQ Q
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
843023AGI
www.icst.com/products/hiperclocks.html
6
REV. A JUNE 29, 2005
Integrated Circuit Systems, Inc.
ICS843023I
FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR APPLICATION INFORMATION
CRYSTAL INPUT INTERFACE
The ICS843023I has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 1 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 22p
Figure 1. CRYSTAL INPUt INTERFACE
TERMINATION
FOR
3.3V LVPECL OUTPUT
drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to
3.3V
Zo = 50 FOUT FIN
125 Zo = 50 FOUT
50 50 VCC - 2V RTT
125
Zo = 50
FIN
Zo = 50 84 84
1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o
FIGURE 2A. LVPECL OUTPUT TERMINATION
843023AGI
FIGURE 2B. LVPECL OUTPUT TERMINATION
REV. A JUNE 29, 2005
www.icst.com/products/hiperclocks.html
7
Integrated Circuit Systems, Inc.
ICS843023I
FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
ground level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C.
TERMINATION
FOR
2.5V LVPECL OUTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5 R3 250
VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
R3 18
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
843023AGI
www.icst.com/products/hiperclocks.html
8
REV. A JUNE 29, 2005
Integrated Circuit Systems, Inc.
ICS843023I
FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843023I. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS843023I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 75mA= 259.87mW Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 259.87mW + 30mW = 289.87mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.290W * 90.5C/W = 111.2C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
8-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W
1
90.5C/W
2.5
89.8C/W
843023AGI
www.icst.com/products/hiperclocks.html
9
REV. A JUNE 29, 2005
Integrated Circuit Systems, Inc.
ICS843023I
FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT RL 50 VCC - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = VOH_MAX = VCC_MAX - 0.9V (V
CCO_MAX
-V
OH_MAX
) = 0.9V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. ))/R ] * (V - (V - 2V))/R ] * (V -V ) = [(2V - (V -V -V )= Pd_H = [(V OH_MAX CC_MAX CC_MAX OH_MAX OH_MAX CC_MAX OH_MAX L CC_MAX L [(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
843023AGI
www.icst.com/products/hiperclocks.html
10
REV. A JUNE 29, 2005
Integrated Circuit Systems, Inc.
ICS843023I
FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
8 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W
1
90.5C/W
2.5
89.8C/W
TRANSISTOR COUNT
The transistor count for ICS843023I is: 2360
843023AGI
www.icst.com/products/hiperclocks.html
11
REV. A JUNE 29, 2005
Integrated Circuit Systems, Inc.
ICS843023I
FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
8 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 2.90 6.40 BASIC 4.50 Millimeters Minimum 8 1.20 0.15 1.05 0.30 0.20 3.10 Maximum
Reference Document: JEDEC Publication 95, MO-153
843023AGI
www.icst.com/products/hiperclocks.html
12
REV. A JUNE 29, 2005
Integrated Circuit Systems, Inc.
ICS843023I
FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
Marking 023AI 023AI TB D TBD Package 8 Lead TSSOP 8 Lead TSSOP 8 Lead "Lead-Free" TSSOP 8 Lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS843023AGI ICS843023AGIT ICS843023AGILF ICS843023AGILFT
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843023AGI
www.icst.com/products/hiperclocks.html
13
REV. A JUNE 29, 2005

▲Up To Search▲

Price & Availability of ICS843023I

	To Download ICS843023I Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .