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IDT74SSTU32864/A 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O
COMMERCIAL TEMPERATURE RANGE
1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O
IDT74SSTU32864/A PRELIMINARY
FEATURES:
* * * * * * * *
1:1 and 1:2 registered buffer 1.8V Operation SSTL_18 style clock and data inputs Differential CLK input Control inputs compatible with LVCMOS levels Flow-through architecture for optimum PCB design Latch-up performance exceeds 100mA ESD >2000V per MIL-STD-883, Method 3015; >200V using machine model (C = 200pF, R = 0) * Available in 96-pin LFBGA package
APPLICATIONS:
* * * *
Ideally suited for DDR2 DIMM registered applications SSTU32864 is optimized for DDR2 Raw Cards B and C R-DIMMs SSTU32864A is optimized for DDR2 Raw Card A R-DIMMs Along with CSPU877, zero delay PLL clock buffer, provides complete solution for DDR2 DIMMs
The SSTU32864/A is a 25-bit 1:1 / 14-bit 1:2 configurable registered buffer designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The SSTU32864/A operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. The C0 input controls the pinout configuration of the 1:2 pinout from the A configuration (when low) to B configuration (when high). The C1 input controls the configuration from the 25-bit 1:1 (when low) to 14-bit 1:2 (when high). This device supports low-power standby operation. When the reset input (RESET) is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is low all registers are reset, and all outputs are forced low. The LVCMOS RESET and Cx inputs must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. In the DDR2 DIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of a reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the SSTU32864/A must ensure that the outputs will remain low, thus ensuring no glitches on the outputs. The device monitors both DCS and CSR inputs and will gate the outputs from changing states when both DCS and CSR inputs are high. If either DCS or CSR input is low, the device will function normally. The RESET input has priority over the DCS control and will force the inputs low. If the DCS control functionality is not desired, then the CSR input can be hardwired to ground, in which case the set-up time requirement for DCS would be the same as for the other D data inputs.
DESCRIPTION:
COMMERCIAL TEMPERATURE RANGE
1
c 2003 Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
AUGUST 2003
DSC-5980/15
IDT74SSTU32864/A 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM (1:2)
RESET
CLK CLK
VREF
DCKE
1D C1 R
QCKEA
QCKEB
DODT
1D C1 R
QODTA
QODTB
DCS
1D C1 R
QCSA
QCSB
CSR
Dx
O
1
1D C1 R
QxA
QxB
TO 10 OTHER CHANNELS
2
IDT74SSTU32864/A 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION (TYPE A)
ZOL Q12B
6
QCKEB
Q2B
Q3B
QODTB
Q5B
Q6B
C0
QCSB
Q8B
Q9B
Q10B
Q11B
Q13B
Q14B
5
QCKEA
Q2A
Q3A
QODTA
Q5A
Q6A
C1
QCSA
ZOH
Q8A
Q9A
Q10A
Q11A
Q12A
Q13A
Q14A
4
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VDD
3
VREF
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VREF
2
NC
NC
NC
NC
NC
NC
RESET
DCS
CSR
NC
NC
NC
NC
NC
NC
NC
1
DCKE
D2
D3
DODT
D5
D6
NC
CLK
CLK
D8
D9
D10
D11
D12
D13
D14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
96-PIN LFBGA 1:2 REGISTER (TYPE A, FRONTSIDE) TOP VIEW
PIN CONFIGURATION (TYPE B)
6
Q1B
Q2B
Q3B
Q4B
Q5B
Q6B
C0
QCSB
ZOL
Q8B
Q9B
Q10B
QODTB
Q12B
Q13B
QCKEB
5
Q1A
Q2A
Q3A
Q4A
Q5A
Q6A
C1
QCSA
ZOH
Q8A
Q9A
Q10A
QODTA
Q12A
Q13A
QCKEA
4
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VDD
3
VREF
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VREF
2
NC
NC
NC
NC
NC
NC
RESET
DCS
CSR
NC
NC
NC
NC
NC
NC
NC
1
D1
D2
D3
D4
D5
D6
NC
CLK
CLK
D8
D9
D10
DODT
D12
D13
DCKE
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
96-PIN LFBGA 1:2 REGISTER (TYPE B, BACKSIDE) TOP VIEW 3
IDT74SSTU32864/A 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM (1:1)
RESET
CLK1 CLK1
VREF
DCKE
1D C1 R QCKE
DODT
1D C1 R QOTD
DCS
1D C1 R QCS
CSR
Dx
O
1
1D C1 R Qx
TO 21 OTHER CHANNELS
4
IDT74SSTU32864/A 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
Q17 Q18
6
NC
Q15
Q16
NC
C0
NC
ZOL
Q19
Q20
Q21
Q22
Q23
Q24
Q25
5
QCKE
Q2
Q3
QODT
Q5
Q6
C1
QCS
ZOH
Q8
Q9
Q10
Q11
Q12
Q13
Q14
4
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VDD
3
VREF
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VREF
2
NC
D15
D16
NC
D17
D18
RESET
DCS
CSR
D19
D20
D21
D22
D23
D24
D25
1
DCKE
D2
D3
DODT
D5
D6
NC
CLK
CLK
D8
D9
D10
D11
D12
D13
D14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
*Rows 3 and 4 are reserved for VDD and GND.
96-PIN LFBGA 1:1 REGISTER TOP VIEW
96 BALL LFBGA PACKAGE ATTRIBUTES
6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
5
IDT74SSTU32864/A 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O
COMMERCIAL TEMPERATURE RANGE
FUNCTION TABLE (EACH FLIP-FLOP) (1)
Inputs RESET H H H H H H H H H H H H L DCS L L L L L L H H H H H H X or Floating CSR L L L H H H L L L H H H X or Floating CLK L or H L or H L or H L or H X or Floating CLK L or H L or H L or H L or H X or Floating Dx, DODT, DCKE L H X L H X L H X L H X X or Floating Qx Outputs L H Q0
(2)
QCSx Output L L Q0
(2)
QODTx, QCKEx Outputs L H Q0(2) L H Q0(2) L H Q0(2) L H Q0(2) L
L H Q0
(2)
L L Q0
(2)
L H Q0(2) Q0(2) Q0 Q0
(2) (2)
H H Q0(2) H H Q0
(2)
L
L
NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW to HIGH = HIGH to LOW 2. Output level before the indicated steady-state conditions were established.
MODE SELECT
C0 0 0 1 1 C1 0 1 0 1 Device Mode 1:1 25-bit to 25-bit 1:2 14-bit to 28-bit, Front (Type A) Reserved 1:2 14-bit to 28-bit, Back (Type B)
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IDT74SSTU32864/A 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS (1)
Symbol VDD VI
(2,3)
Description Supply Voltage Range Input Voltage Range Output Voltage Range Input Clamp Current VI < 0 VI > VDD
Max. -0.5 to 2.5 -0.5 to 2.5 -0.5 to VDD +0.5 50 50 50 100 -65 to +150
Unit V V V mA mA mA mA C
VO(2,3) IIK IOK IO VDD TSTG
Output Clamp Current VO < 0 VO > VDD Continuous Output Current, VO = 0 to VDD Continuous Current through each VDD or GND Storage Temperature Range
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative voltage ratings may be exceeded if the ratings of the I/P and O/P clamp current are observed. 3. This value is limited to 2.5V maximum.
TERMINAL FUNCTIONS (ALL PINS)
Terminal Name GND VDD VREF ZOH(1) ZOL(1) CLK CLK Cx RESET CSR, DCS Dx DODT DCKE Qx QCSx QODTx QCKEx Electrical Characteristics Ground Input 1.8V nominal 0.9V nominal Input Input Differential Input Differential Input LVCMOS Input LVCMOS Input SSTL_18 Input SSTL_18 Input SSTL_18 Input SSTL_18 Input 1.8V CMOS 1.8V CMOS 1.8V CMOS 1.8V CMOS Description Ground Power Supply Voltage Input Reference Voltage Reserved for future use Reserved for future use Positive Master Clock Input Negative Master Clock Input Configuration Control Inputs Asynchronous Reset Input. Resets registers and disables VREF data and clock differential-input receivers. Chip Select Inputs. Disables outputs Dx switching when both inputs are HIGH. Data Input. Clocked in on the crossing of the rising edge of CLK and the falling edge of CLK. The outputs of this register bit will not be suspended by the DCS and CSR controls The outputs of this register bit will not be suspended by the DCS and CSR controls Data Outputs that are suspended by the DCS and CSR controls Data Output that will not be suspended by the DCS and CSR controls Data Output that will not be suspended by the DCS and CSR controls Data Output that will not be suspended by the DCS and CSR controls
NOTE: 1. The signals will be left unconnected.
7
IDT74SSTU32864/A 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O
COMMERCIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, TA = 25C (1,2)
Symbol VDD VREF VTT VI VIH VIL VIH VIL VIH VIL VICR VID IOH IOL TA Parameter Supply Voltage Reference Voltage Termination Voltage Input Voltage AC High-Level Input Voltage AC Low-Level Input Voltage DC High-Level Input Voltage DC Low-Level Input Voltage High-Level Input Voltage Low-Level Input Voltage Common Mode Input Voltage Differential Input Voltage High-Level Output Current Low-Level Output Current Operating Free-Air Temperature Data Inputs Data Inputs Data Inputs Data Inputs RESET, Cx RESET, Cx CLK, CLK CLK, CLK Min. 1.7 0.49 * VDD VREF- 40mV 0 VREF+ 250mV -- VREF+ 125mV -- 0.65 * VDD -- 0.675 600 -- -- 0 Typ. -- 0.5 * VDD VREF -- -- -- -- -- -- -- -- -- -- -- -- Max. 1.9 0.51 * VDD VREF+ 40mV VDD -- VREF- 250mV -- VREF- 125mV -- 0.35 * VDD 1.125 -- TBD TBD 70 C Unit V V V V V V V V V V V mV mA
NOTES: 1. The RESET and Cx inputs of the device must be held at valid levels (not floating) to ensure proper device operation. 2. The differential inputs must not be floating unless RESET is LOW.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, VDD = 1.8V 0.1V
Symbol VOH VOL II IDD IDDD All Inputs Static Standby Static Operating Dynamic Operating (Clock Only) Dynamic Operating (Per Each Data Input) Data Inputs CI CLK and CLK RESET Parameter Test Conditions VDD = 1.7V to 1.9V, IOH = - TBD mA VDD = 1.7V to 1.9V, IOL = TBD mA VI = VDD or GND IO = 0, VDD = 1.9V, RESET = GND IO = 0, VDD = 1.9V, RESET = VDD, VI = VIH (AC) or VIL (AC) IO = 0, VDD = 1.8V, RESET = VDD, VI = VIH (AC) or VIL (AC), CLK and CLK Switching 50% Duty Cycle. IO = 0, VDD = 1.8V, RESET = VDD, VI = VIH (AC) or VIL (AC), CLK and CLK Switching at 50% Duty Cycle. One Data Input Switching at Half Clock Frequency, 50% Duty Cycle. VI = VREF 250mV VICR = 0.9V, VID = 600mV VI = VDD or GND 2.5 2 -- -- -- -- 3.5 3 -- pF 1:2 Mode -- -- -- 1:1 Mode -- -- -- A/Clock MHz/Data Input Min. TBD -- -- -- -- -- Typ. -- -- -- -- -- -- Max. -- TBD 5 100 TBD -- Unit V V A A mA A/Clock MHz
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IDT74SSTU32864/A 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O
COMMERCIAL TEMPERATURE RANGE
TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE
VDD = 1.8V 0.1V Symbol fCLOCK tw tACT(1,2) tINACT(1,3) tSU tH Parameter Clock Frequency Pulse Duration, CLK, CLK HIGH or LOW Differential Inputs Active Time Differential Inputs Inactive Time DCS before CLK, CLK, CSR HIGH Setup Time Hold Time DCS before CLK, CLK, CSR LOW DODT, CSR, Data, and DCKE before CLK, CLK Data, DCS, CSR, DCKE, and DODT after CLK, CLK Min. -- 1 -- -- 0.7 0.5 0.5 0.5 Max. 270 -- TBD TBD -- -- -- -- ns ns Unit MHz ns ns ns
NOTES: 1. This parameter is not production tested. 2. Data and VREF inputs must be low a minimum time of tACT max, after RESET is taken HIGH. 3. Data, VREF, and clock inputs must be held at valid levels (not floating) a minimum time of tINACT max, after RESET is taken LOW.
SWITCHING CHARACTERISTICS OVER RECOMMENDED FREE-AIR OPERATING RANGE (UNLESS OTHERWISE NOTED) (1)
VDD = 1.8V 0.1V Symbol fMAX tPDM(2) tPDMSS(2,4) tRPHL dV/dt_r dV/dt_f dV/dt_(5) Parameter CLK and CLK to Q CLK and CLK to Q (simultaneous switching) RESET to Q Output slew rate from 20% to 80% Output slew rate from 20% to 80% Output slew rate from 20% to 80% Min 270 1.41(3) -- -- 1 1 -- Max. -- 2.15(3) 2.35(3) 3 4 4 1 Unit MHz ns ns ns V/ns V/ns V/ns
NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. 2. Includes 350ps of test load transmission line delay. 3. For reference only. Final values to be determined. 4. This parameter is not production tested. 5. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate).
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IDT74SSTU32864/A 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS (VDD = 1.8V 0.1V)
VDD
DUT
TL = 50 CLK Inputs CLK CLK Test Point RL = 100 Test Point LVCMOS RESET Input tINACT IDD(2) 10% VDD VDD/2 VDD/2 0V tACT 90% Output CLK CLK tPLH VTT VICR Out CL = 30 pF
(1)
RL = 1K TL = 350ps, 50 Test Point RL = 1K
Load Circuit
VICR tPHL VTT
VID
VOH VOL
Voltage and Current Waveforms Inputs Active and Inactive Times
tW Input VICR VICR VID
Voltage Waveforms - Propagation Delay Times
Voltage Waveforms - Pulse Duration
LVCMOS RESET Input
VIH VDD/2 VIL tRPHL VOH
Output CLK CLK tSU Input VREF tH VIH VREF VIL VICR VID
VTT VOL
Voltage Waveforms - Propagation Delay Times
Voltage Waveforms - Setup and Hold Times
NOTES: 1. CL includes probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA 3. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, ZO = 50, input slew rate = 1 V/ns 20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VTT = VREF = VDD/2 6. VIH = VREF + 250mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 7. VIL = VREF - 250mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. VID = 600mV. 9. tPLH and tPHL are the same as tPDM.
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IDT74SSTU32864/A 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS (VDD = 1.8V 0.1V)
VDD
DUT
Out
RL = 50 Test Point
CL = 10 pF
(1)
Load Circuit: High-to-Low Slew-Rate Adjustment
Output 80%
VOH
20% dv_f dt_f VOL
Voltage Waveforms: High-to-Low Slew-Rate Adjustment
DUT
Out CL = 10 pF
(1)
Test Point RL = 50
Load Circuit: Low-to-High Slew-Rate Adjustment
dt_r dv_r 80% VOH
20% Output VOL
Voltage Waveforms: Low-to-High Slew-Rate Adjustment
NOTES: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, ZO = 50, input slew rate = 1 V/ns 20% (unless otherwise specified).
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IDT74SSTU32864/A 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX XX SSTU Family Temp. Range XXX XX Device Type Package
Low Profile, Fine Pitch, Ball Grid Array BF BFG Very Fine Pitch Ball Grid Array, Green 864 1:1 and 1:2 Registered Buffer with 1.8V SSTL I/O 864A 32 74 TBD 0C to +70C
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
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