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19-2576; Rev 0; 10/02
One-to-Five LVPECL/LVCMOS Output Clock and Data Driver
General Description
The MAX9324 low-skew, low-jitter, clock and data driver distributes a differential LVPECL input to four differential LVPECL outputs and one single-ended LVCMOS output. All outputs default to logic low when the differential inputs equal GND or are left open. The MAX9324 operates from 3.0V to 3.6V, making it ideal for 3.3V systems, and consumes only 25mA (max) of supply current. The MAX9324 features low 150ps (max) part-to-part skew, low 15ps output-to-output skew, and low 1.7ps RMS jitter, making the device ideal for clock and data distribution across a backplane or board. CLK_EN and SEOUT_Z control the status of the various outputs. Asserting CLK_EN low configures the differential (Q_, Q_) outputs to a differential low condition and SEOUT to a single-ended logic-low state. CLK_EN operation is synchronous with the CLK_ inputs. A logic high on SEOUT_Z places SEOUT in a high-impedance state. SEOUT_Z is asynchronous with the CLK (CLK) inputs. The MAX9324 is available in space-saving 20-pin TSSOP and ultra-small 20-pin 4mm 4mm thin QFN packages and operates over the extended (-40C to +85C) temperature range. o 1.7psRMS Added Random Jitter o 150ps (max) Part-to-Part Skew o 450ps Propagation Delay o Synchronous Output Enable/Disable o Single-Ended Monitor Output o Outputs Assert Low when CLK, CLK are Open or at GND o 3.0V to 3.6V Supply Voltage Range o -40C to +85C Operating Temperature Range
Features
o 15ps Differential Output-to-Output Skew
MAX9324
Ordering Information
PART MAX9324EUP MAX9324ETP* TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 20 TSSOP 20 Thin QFN-EP**
Applications
Precision Clock Distribution Low-Jitter Data Repeater Data and Clock Driver and Buffer Central-Office Backplane Clock Distribution DSLAM Backplane Base Station ATE
CLK_EN
*Future product--Contact factory for availability. **EP = Exposed paddle.
Functional Diagram and Typical Operating Circuit appear at end of data sheet.
Pin Configurations
GND N.C. Q0 17
TOP VIEW
20
19
18
16 GND 1 20 Q0 19 Q0 18 VCC 17 Q1 CLK_EN 2 N.C. 3 SEOUT 4 GND 5 12 Q2 11 Q2 N.C. 6 SEOUT_Z 7 CLK 8
Q0
SEOUT 1 GND 2 N.C. 3 SEOUT_Z 4 CLK 5
15 VCC 14 Q1
MAX9324
**EXPOSED PADDLE
13 Q1
MAX9324
16 Q1 15 Q2 14 Q2 13 VCC 12 Q3 11 Q3
6 CLK
7 VCC
8 Q3
9 Q3
10 VCC CLK 9 VCC 10
THIN QFN-EP** (4mm x 4mm)
**CONNECT EXPOSED PADDLE TO GND.
TSSOP
________________________________________________________________ Maxim Integrated Products
1
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One-to-Five LVPECL/LVCMOS Output Clock and Data Driver MAX9324
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +4.0V Q_, Q_, CLK, CLK, SEOUT_Z, CLK_EN, SEOUT to GND.......................................-0.3V to (VCC + 0.3V) CLK to CLK ............................................................................3V SEOUT Short to GND .................................................Continuous Continuous Output Current (Q_, Q_) ..................................50mA Surge Output Current (Q_, Q_) .........................................100mA Continuous Power Dissipation (TA = +70C) 20-Pin TSSOP (derate 11mW/C)..............................879.1mW 20-Pin 4mm 4mm Thin QFN (derate 16.9mW/C)..1349.1mW Junction-to-Ambient Thermal Resistance in Still Air 20-Pin TSSOP ............................................................+91C/W 20-Pin 4mm 4mm Thin QFN.................................+59.3C/W Junction-to-Case Thermal Resistance 20-Pin TSSOP ............................................................+20C/W 20-Pin 4mm 4mm Thin QFN......................................+2C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Soldering Temperature (10s) ...........................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, differential outputs terminated with 50 1% to (VCC - 2V), SEOUT_Z = GND, CLK_EN = VCC, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25C.) (Notes 1, 2, and 3)
PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current DIFFERENTIAL INPUT (CLK, CLK) Differential Input High Voltage Differential Input Low Voltage Differential Input Voltage Input Current DIFFERENTIAL OUTPUTS (Q_, Q_) Single-Ended Output High Single-Ended Output Low Differential Output Voltage Output High Voltage Output Low Voltage Output High-Impedance Current Output Short-Circuit Current SUPPLY Supply Current ICC (Note 4) 25 mA SINGLE-ENDED OUTPUT (SEOUT) VOH VOL IOZ IOS IOH = -4mA IOL = 4mA SEOUT_Z = VCC, SEOUT = VCC or GND VCLK = VCC, SEOUT = GND -10 2.4 0.4 +10 75 V V A mA VIHD VILD VIHD - VILD ICLK VOH VOL VOH - VOL VIHD, VILD Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 1.5 0 0.15 -5 VCC - 1.4 VCC - 2.0 0.6 VCC VCC - 0.15 1.5 +150 VCC - 1.0 VCC - 1.7 0.85 V V V A V V V SYMBOL VIH VIL IIH IIL CLK_EN = VCC SEOUT_Z = VCC CLK_EN = GND SEOUT_Z = GND -150 -5 +5 CONDITIONS MIN 2 0 -5 TYP MAX VCC 0.8 +5 150 UNITS V V A A
SINGLE-ENDED INPUTS (CLK_EN, SEOUT_Z)
2
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One-to-Five LVPECL/LVCMOS Output Clock and Data Driver
AC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, differential outputs terminated with 50 1% to (VCC - 2V), fCLK 266MHz, input duty cycle = 50%, input transition time = 125ps (20% to 80%), VIHD = 1.5V to VCC, VILD = GND to (VCC - 0.15V), VIHD - VILD = 0.15V to 1.5V, CLK_EN = VCC, SEOUT_Z = GND, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = 3.3V, VIHD = (VCC - 1V), VILD = (VCC 1.5V), TA = +25C.) (Note 5)
PARAMETER Switching Frequency Propagation Delay Output-to-Output Skew Part-to-Part Skew Output Rise Time Output Fall Time Output Duty Cycle Added Random Jitter Added Deterministic Jitter Added Jitter Single-Ended Output Rise Time Single-Ended Output Fall Time Single-Ended Output Duty Cycle SYMBOL fMAX tPHL, tPLH tSKOO tSKPP tR tF ODC tRJ tDJ tAJ tR tF ODC fCLK = 650MHz (Note 9) 2e23 - 1 PRBS pattern, f = 650Mbps (Note 9) VCC = 3.3V with 25mV superimposed sinusoidal noise at 100kHz (Note 9) CL = 15pF, 20% to 80%, Figure 1 CL = 15pF, 80% to 20%, Figure 1 (Note 10) 40 CONDITIONS VOH - VOL 0.6V, SEOUT_Z = VCC SEOUT_Z = GND, SEOUT CLK, CLK to Q_, Q_, Figure 1 (Note 6) (Note 7) (Note 8) 20% to 80%, Figure 1 80% to 20%, Figure 1 100 100 48 217 207 50 1.7 83 8.5 1.6 1.6 52 MIN 650 125 100 TYP 800 200 450 600 30 150 300 300 52 3 100 12 2 2 60 MAX UNITS MHz ps ps ps ps ps % ps(RMS) ps(P-P) ps(P-P) ns ns %
MAX9324
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8:
Measurements are made with the device in thermal equilibrium. Current into a pin is defined as positive. Current out of a pin is defined as negative. DC parameters are production tested at TA = +25C and guaranteed by design over the full operating temperature range. All pins open except VCC and GND. Guaranteed by design and characterization. Limits are set at 6 sigma. Measured from the differential input signal crosspoint to the differential output signal crosspoint. Measured between the differential outputs of the same part at the differential signal crosspoint for a same-edge transition. Measured between the differential outputs of different parts at the differential signal crosspoint under identical conditions for a same-edge transition. Note 9: Jitter added to the input signal. Note 10: Measured at 50% of VCC.
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One-to-Five LVPECL/LVCMOS Output Clock and Data Driver MAX9324
Typical Operating Characteristics
(VCC = 3.3V, outputs terminated to (VCC - 2V) through 50, SEOUT_Z = VCC, CLK_EN = VCC, TA = +25C.)
SUPPLY CURRENT vs. TEMPERATURE
MAX9324 toc01
DIFFERENTIAL OUTPUT AMPLITUDE (VOH - VOL) vs. FREQUENCY
700 OUTPUT AMPLITUDE (mV) 600 500 400 300 200 100 0 0 200 400 600 800 1000 1200 1400 1600 FREQUENCY (MHz)
MAX9324 toc02
14.0 13.5 SUPPLY CURRENT (mA) 13.0 12.5 12.0 11.5 11.0 10.5 10.0 -40 -15 10 35 60
800
85
TEMPERATURE (C)
DIFFERENTIAL OUTPUT RISE/FALL TIME vs. TEMPERATURE
MAX9324 toc03
DIFFERENTIAL PROPAGATION DELAY vs. TEMPERATURE
DIFFERENTIAL PROPAGATION DELAY (ps) 500 490 480 470 460 450 440 430 420 410 -40 -15 10 35 60 85 tPHL tPLH
MAX9324 toc04
250 DIFFERENTIAL OUTPUT RISE/FALL TIME (ps) 240 230 220 210 200 190 180 170 160 150 -40 -15 10 35 60 tF tR
510
85
TEMPERATURE (C)
TEMPERATURE (C)
4
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One-to-Five LVPECL/LVCMOS Output Clock and Data Driver
Pin Description
PIN TSSOP 1, 5 QFN 2, 18 NAME GND FUNCTION Ground. Provide a low-impedance connection to the ground plane. Synchronous Output Enable. Connect CLK_EN to VCC or leave floating to enable the differential outputs. Connect CLK_EN to GND to disable the differential outputs. When disabled, Q_ asserts low, Q_ asserts high, and SEOUT asserts low. A 51k pullup resistor to VCC allows CLK_EN to be left floating. No Connect. Not internally connected. LVCMOS/LVTTL Clock Output. SEOUT reproduces CLK when SEOUT_Z = GND. SEOUT goes high impedance when SEOUT_Z = VCC. The maximum output frequency of SEOUT is 125MHz. Single-Ended Clock Output Enable/Disable. Connect SEOUT_Z to GND to enable the singleended clock output. Connect SEOUT_Z to VCC to disable the single-ended clock output. A 51k pulldown resistor to GND allows SEOUT_Z to be left floating. Noninverting Differential LVPECL Input. An internal 51k pulldown resistor to GND forces the outputs (Q_, Q_) to differential low and logic low (SEOUT) when CLK and CLK are left open or at GND and the outputs are enabled. Inverting Differential LVPECL Input. An internal 51k pulldown resistor to GND forces the outputs (Q_, Q_) to differential low and logic low (SEOUT) when CLK and CLK are left open or at GND and the outputs are enabled. Positive Supply Voltage. Bypass VCC to GND with three 0.01F and one 0.1F ceramic capacitors. Place the 0.01F capacitors as close to each VCC input as possible (one per VCC input). Connect all VCC inputs together, and bypass to GND with a 0.1F ceramic capacitor. Inverting Differential LVPECL Output. Terminate Q3 to (VCC - 2V) with a 50 1% resistor. Noninverting Differential LVPECL Output. Terminate Q3 to (VCC - 2V) with a 50 1% resistor. Inverting Differential LVPECL Output. Terminate Q2 to (VCC - 2V) with a 50 1% resistor. Noninverting Differential LVPECL Output. Terminate Q2 to (VCC - 2V) with a 50 1% resistor. Inverting Differential LVPECL Output. Terminate Q1 to (VCC - 2V) with a 50 1% resistor. Noninverting Differential LVPECL Output. Terminate Q1 to (VCC - 2V) with a 50 1% resistor. Inverting Differential LVPECL Output. Terminate Q0 to (VCC - 2V) with a 50 1% resistor. Noninverting Differential LVPECL Output. Terminate Q0 to (VCC - 2V) with a 50 1% resistor.
MAX9324
2
19
CLK_EN
3, 6 4
3, 20 1
N.C. SEOUT
7
4
SEOUT_Z
8
5
CLK
9
6
CLK
10, 13, 18 11 12 14 15 16 17 19 20
7, 10, 15 8 9 11 12 13 14 16 17
VCC Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0
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One-to-Five LVPECL/LVCMOS Output Clock and Data Driver MAX9324
Detailed Description
The MAX9324 low-skew, low-jitter, clock and data driver distributes a differential LVPECL input signal to four differential LVPECL outputs and a single-ended LVCMOS output. The differential output drivers operate at frequencies up to 800MHz. When SEOUT_Z = GND, the single-ended LVCMOS output driver operates with frequencies as high as 200MHz. The MAX9324 operates from 3.0V to 3.6V, making the device ideal for 3.3V systems. signal. Terminate CLK and CLK through 50 to (VCC 2V) to minimize input signal reflections. Internal 51k pulldown resistors to GND ensure the outputs default to differential low (Q_, Q_) or logic low (SEOUT) when the CLK inputs are left open.
CLK_EN Input
CLK_EN enables/disables the differential outputs of the MAX9324. Connect CLK_EN to VCC to enable the differential outputs. The (Q_, Q_) outputs are driven to a differential low condition when CLK_EN = GND. Each differential output pair disables following successive rising and falling edges on CLK (falling and rising edges on CLK), after CLK_EN connects to GND. Both a rising and falling edge on CLK are required to complete the enable/disable function (Figure 2).
Data Inputs
Differential LVPECL Inputs
The MAX9324 accepts a differential LVPECL input. Each differential output duplicates the differential input
CLK VIHD
VILD CLK
Q_ VOH VOH - VOL VOL Q_ tPLH tPHL
80% Q_ - Q_ 20% tR tF
80%
20%
80% SEOUT 20% tR tF
80%
20%
Figure 1. MAX9324 Clock Input-to-Output Delay and Rise/Fall Time 6 _______________________________________________________________________________________
One-to-Five LVPECL/LVCMOS Output Clock and Data Driver MAX9324
CLK
CLK
DISABLED CLK_EN
ENABLED
Q_
Q_
SEOUT
HIGH IMPEDANCE
SEOUT_Z
Figure 2. MAX9324 CLK_EN Timing Diagram
SEOUT_Z
SEOUT_Z enables/disables the single-ended LVCMOS output (Table 1). Connect SEOUT_Z to GND to enable the single-ended output. Connect SEOUT_Z to VCC to force the single-ended output to a high-impedance state. SEOUT provides a single-ended monitor for operating frequencies as high as 200MHz.
Applications Information
Output Termination
Terminate both outputs of each differential pair through 50 to (VCC - 2V) or use an equivalent Thevenin termination. Use identical termination on each output for the lowest output-to-output skew. Terminate both outputs when deriving a single-ended signal from a differential output. For example, using Q0 as a single-ended output requires termination for both Q0 and Q0.
Table 1. Control Input Table
INPUTS CLK_EN 0 0 1 1 SEOUT_Z 0 1 0 1 Q0-Q3 Disabled, pulled to logic low Disabled, pulled to logic low Enabled Enabled OUTPUTS
Q Q0-Q3
SEOUT Enabled, logic low Disabled, high impedance Enabled Disabled, high impedance
Disabled, pulled to logic high Disabled, pulled to logic high Enabled Enabled
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One-to-Five LVPECL/LVCMOS Output Clock and Data Driver MAX9324
SEOUT provides a single-ended LVCMOS monitor output. SEOUT operates with a maximum output frequency of 200MHz. Ensure that the output currents do not violate the current limits as specified in the Absolute Maximum Ratings table. Observe the device's total thermal limits under all operating conditions.
Circuit Board Traces
Input and output trace characteristics affect the performance of the MAX9324. Connect each input and output to a 50 characteristic impedance trace to minimize reflections. Avoid discontinuities in differential impedance and maximize common-mode noise immunity by maintaining the distance between differential traces and avoiding sharp corners. Minimize the number of vias to prevent impedance discontinuities. Minimize skew by matching the electrical length of the traces.
Power-Supply Bypassing
Bypass VCC to GND using three 0.01F ceramic capacitors and one 0.1F ceramic capacitor. Place the 0.01F capacitors (one per VCC input) as close to VCC as possible (see the Typical Operating Circuit). Use multiple bypass vias to minimize parasitic inductance.
Chip Information
TRANSISTOR COUNT: 4430 PROCESS: BiCMOS
Functional Diagram
VCC VCC VCC
SEOUT_Z
MAX9324
SEOUT
VCC
Q0 Q0
CLK_EN
D Q CLK Q1 Q1
CLK CLK
Q2 Q2
Q3 Q3
GND
GND
8
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One-to-Five LVPECL/LVCMOS Output Clock and Data Driver
Typical Operating Circuit
3.0V TO 3.6V 0.01F 0.1F 0.01F 0.01F
MAX9324
VCC
VCC
VCC Q0 Q0
ZO = 50
MAX9324
ZO = 50 ZO = 50 50 50 CLK CLK Q1 Q1
ZO = 50 50 ZO = 50 50 LVPECL RECEIVER
VCC - 2V ZO = 50 ZO = 50
Q2 VCC - 2V Q2 ZO = 50 ON CLK_EN OFF OFF SEOUT_Z ON SEOUT Q3 Q3 ZO = 50 LVCMOS/ LVTTL INPUT ZO = 50
GND
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One-to-Five LVPECL/LVCMOS Output Clock and Data Driver MAX9324
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm
21-0139
A
10
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One-to-Five LVPECL/LVCMOS Output Clock and Data Driver
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX9324
PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm
21-0139
A
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One-to-Five LVPECL/LVCMOS Output Clock and Data Driver MAX9324
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
TSSOP4.40mm.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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