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PRELIMINARY PRODUCT INFORMATION
MOS INTEGRATED CIRCUIT
PD789322,789324,789326,789327
8-BIT SINGLE-CHIP MICROCONTROLLER
The PD789322, 789324, 789326, and 789327 are PD789327 Subseries (designed for remote controller with onchip LCD) product in the 78K/0S Series. In addition to an 8-bit CPU, they have on-chip hardware for a remote controller with on-chip LCD, Including a LCD controller/driver, a serial interface, a key return signal detection circuit, and timers with carrier generator that can easily output waveforms for infrared remote control. The PD78F9328, a product with on-chip flash memory which can operate on the same supply voltage as for masked ROM products and various development tools are also under development. Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing.
PD789327, 789467 Subseries User's Manual: To be prepared 78K/0S Series User's Manual Instructions: U11047E
FEATURES
* ROM and RAM size Item Part Number Program memory (ROM) RAM 4 K bytes 8 K bytes 16 K bytes 24 K bytes 512 bytes 256 bytes 24 bytes 52-pin plastic LQFP (10x10 mm) Data Memory Internal High-Speed LCD display RAM Packege
PD789322 PD789324 PD789326 PD789327
* Variable minimum instruction execution time: High speed (0.4 s: @5.0-MHz operation with main system clock), low speed (1.6 s: @5.0-MHz operation with main system clock), and ultra low speed (122 s: @32.768-kHz operation with subsystem clock) * I/O ports: 21 * Serial interface (3-wire serial I/O mode): 1 channel * LCD controller/driver Segment signals: 24 Common signals: 4 * Timer: 4 channels * Supply voltage: VDD = 1.8 to 5.5 V
APPLICATIONS
Remote-control devices, healthcare equipment, etc.
The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. U14673EJ1V0PM00 (1st edition) Date Published March 2000 NS CP(K) Printed in Japan
2000
PD789322,789324,789326,789327
ORDERING INFORMATION
Part Number Package 52-pin plastic LQFP (10x10 mm) 52-pin plastic LQFP (10x10 mm) 52-pin plastic LQFP (10x10 mm) 52-pin plastic LQFP (10x10 mm)
PD789322GB-xxx-8ET PD789324GB-xxx-8ET PD789326GB-xxx-8ET PD789327GB-xxx-8ET
Remark xxx Indicates ROM code suffix.
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Preliminary Product Information U14673EJ1V0PM00
PD789322,789324,789326,789327
78K/0S SERIES LINEUP
The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.
Products under mass production Products under development Y subseries supports SMB.
Small, general-purpose 44 pins 42/44 pins 28 pins
PD789046 PD789026 PD789014
PD789026 with subsystem clock added PD789014 with timer reinforced and ROM and RAM expanded
UART. Low-voltage (1.8-V) operation
Small, general-purpose + A/D 44 pins 44 pins 30 pins 30 pins 30 pins 30 pins 30 pins 30 pins
PD789177 PD789167 PD789156 PD789146 PD789134A PD789124A PD789114A PD789104A
PD789177Y PD789167Y
PD789167 with improved A/D PD789104A with improved timer PD789146 with improved A/D PD789104A with EEPROM added PD789124A with improved A/D RC oscillation model of PD789104A PD789104A with improved A/D PD789026 with A/D and multiplier added
For inverter control 44 pins 78K/0S series 80 pins 80 pins 64 pins 64 pins 64 pins 64 pins 64 pins 64 pins
PD789842
For driving LCD
Internal inverter control circuit and UART
PD789417A PD789407A PD789456 PD789446 PD789436 PD789426 PD789316 PD789306
PD789407A with improved A/D PD789456 with improved I/O PD789446 with improved A/D PD789426 with improved display output PD789426 with improved A/D PD789306 with A/D added RC oscillation model of PD789306
Basic subseries for driving LCD
For driving Dot LCD 144 pins 88 pins
PD789835 PD789830
For ASSP
Segment/common output: 96 pins Segment: 40 pins, common: 16 pins
52 pins 52 pins 44 pins 44 pins 20 pins 20 pins
PD789467 PD789327 PD789800 PD789840 PD789861 PD789860
PD789327 with A/D added For remote controller. Internal LCD controller/driver For PC keyboard. Internal USB function For key pad. Internal POC RC oscillation model of PD789860 For keyless entry. Internal POC and key return circuit
Preliminary Product Information U14673EJ1V0PM00
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PD789322,789324,789326,789327
The major differences between subseries are shown below.
Function Subseries Name Timer 8-bit 1 ch 16-bit 1 ch Watch WDT 1 ch - 2 ch 3 ch - 1 ch 1 ch 1 ch - 8 ch 1 ch - - 4 ch 8 ch - 4 ch - 4 ch 4 ch - 4 ch 3 ch Note 1 ch 1 ch 8 ch - 4 ch - - 1 ch (UART: 1 ch) 30 pins 4.0 V - 20 pins Internal EEPROM RC oscillation version - 22 pins 1 ch (UART: 1 ch) 31 pins 1.8 V - 1 ch VDD MIN Value 1.8 V
ROM Capacity
8-bit A/D -
10-bit A/D -
Serial Interface
I/O
Remark -
Small, PD789046 16 K generalPD789026 4 K-16 K purpose PD789014 2 K-4 K Small, PD789177 16 K-24 K generalPD789167 purpose PD789156 8 K-16 K + A/D
1 ch (UART:1 ch)
34 pins
PD789146 PD789134A 2 K-8 K PD789124A PD789114A PD789104A
For inverter control
PD789842 8 K-16 K
For LCD PD789417A 12 K-24 K driving PD789407A
3 ch
1 ch
1 ch
1 ch 7 ch
7 ch - 6 ch - 6 ch -
1 ch (UART: 1 ch) 43 pins
1.8 V
-
PD789456 12 K-16 K PD789446 PD789436 PD789426 PD789316 8 K to 16K PD789306
For Dot LCD driving ASSP
2 ch
- 6 ch - 6 ch -
30 pins
40 pins
2 ch (UART: 1 ch) 23 pins
RC oscillation version -
PD789835 24 K-60 K PD789830 24 K PD789467 4 K-24 K PD789327 PD789800 8 K PD789840 PD789861 4 K
6 ch 1 ch 2 ch
- 1 ch -
1 ch
1 ch
2 ch -
-
1 ch
27 pins
1.8 V 2.7 V 1.8 V
-
1 ch (UART: 1 ch) 30 pins - 1 ch 2 ch (USB: 1 ch) 1 ch - - 18 pins 21 pins 31 pins 29 pins 14 pins
1 ch
1 ch
1 ch -
Internal LCD -
2 ch
1 ch
-
1 ch
- 4 ch
4.0 V 2.8 V 1.8 V
-
-
RC oscillation version, Internal EEPROM Internal EEPROM
PD789860
Note 10-bit timer: 1 channel
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Preliminary Product Information U14673EJ1V0PM00
PD789322,789324,789326,789327
OVERVIEW OF FUNCTIONS
Item Internal memory ROM High-speed RAM LCD display RAM Main system clock (oscillation frequency) Subsystem clock (oscillation frequency) Minimum instruction execution time
PD789322
4 Kbytes 256 bytes 24 bytes
PD789324
8 Kbytes
PD789326
16 Kbytes 512 bytes
PD789327
24 Kbytes
Ceramic/crystal resonator (1.0 to 5.0 MHz)
Crystal resonator (32.768 kHz) 0.4 s/1.6 s (@5.0-MHz operation with main system clock) 122 s (@32.768-kHz operation with subsystem clock)
General-purpose registers Instruction set
8 bits x 8 registers * 16-bit operations * Bit manipulation (set, reset, test) etc. Total: CMOS I/O: 21 21
I/O ports
Timers
2 channels * 8-bit timer: 1 channel * Watch timer: * Watchdog timer: 1 channel 1 3-wire serial I/O mode: 1 channel * Segment signal outputs: 24 * Common signal outputs: 4 Maskable Non-maskable Internal: 6, External: 2 Internal: 1 * Reset by RESET signal input * Internal reset by watchdog timer * Reset via power-on-clear circuit VDD = 1.8 to 5.5 V TA = -40 to +85C 52-pin plastic LQFP (10x10 mm)
Timer outputs Serial interface LCD controller/driver
Vectored interrupt sources Reset
Supply voltage Operating ambient temperature Package
Preliminary Product Information U14673EJ1V0PM00
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PD789322,789324,789326,789327
CONTENTS
1. PIN CONFIGURATION (TOP VIEW).....................................................................................................8 2. BLOCK DIAGRAM .................................................................................................................................9 3. PIN 3.1 3.2 3.3 4. CPU 4.1 4.2 4.3 FUNCTIONS ..................................................................................................................................10 Port Pins.......................................................................................................................................10 Non-Port Pins...............................................................................................................................11 Pin I/O Circuits and Recommended Connection of Unused Pins ..........................................12 ARCHITECTURE .........................................................................................................................14 Memory Space .............................................................................................................................14 Data Memory Addressing ...........................................................................................................15 Processor Registers....................................................................................................................16
5. PERIPHERAL HARDWARE FUNCTIONS..........................................................................................20 5.1 Ports .............................................................................................................................................20 5.2 Clock Generator...........................................................................................................................26 5.3 8-Bit Timer 30, 40.........................................................................................................................31 5.4 Watch Timer .................................................................................................................................41 5.5 Watchdog Timer ..........................................................................................................................44 5.6 Serial Interface 10........................................................................................................................46 5.7 LCD Controller/Driver..................................................................................................................50 6. INTERRUPT FUNCTION ......................................................................................................................56 6.1 Interrupt Types ............................................................................................................................56 6.2 Interrupt Sources and Configuration ........................................................................................56 6.3 Interrupt Function Control Registers ........................................................................................59 7. STANDBY FUNCTION .........................................................................................................................65 7.1 Standby Function ........................................................................................................................65 7.2 Standby Function Control Register...........................................................................................67 8. RESET FUNCTION...............................................................................................................................68 8.1 Reset Function.............................................................................................................................68 8.2 Power Failure Detection Function .............................................................................................70 9. MASK OPTION ......................................................................................................................................71 10. INSTRUCTION SET OVERVIEW ......................................................................................................72 10.1 Conventions...............................................................................................................................72 10.2 Operations..................................................................................................................................74 11. ELECTRICAL SPECIFICATIONS ......................................................................................................79 12. PACKAGE DRAWING.........................................................................................................................90 6
Preliminary Product Information U14673EJ1V0PM00
PD789322,789324,789326,789327
APPENDIX A. DEVELOPMENT TOOLS ................................................................................................ 91 APPENDIX B. RELATED DOCUMENTS................................................................................................ 93
Preliminary Product Information U14673EJ1V0PM00
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PD789322,789324,789326,789327
1. PIN CONFIGURATION (TOP VIEW)
52-pin plastic LQFP (10x10 mm) x
PD789322GB-xxx-8ET PD789327GB-xxx-8ET
PD789324GB-xxx-8ET
PD789326GB-xxx-8ET
P20/SCK10
P21/SO10
P22/SI10
RESET P60/TO40 P43/KR03 P42/KR02 P41/KR01 P40/KR00 P03 P02 P01 P00 INT/P61 P11 P10
1 2 3 4 5 6 7 8 9
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
P80/S22
XT2
XT1
VLC0
S23
VDD
IC0
VSS
X1
X2
P81/S21 P82/S20 P83/S19 P84/S18 P85/S17 S16 S15 S14 S13 S12 S11 S10 S9
10 11 12
27 13 14 15 16 17 18 19 20 21 21 23 24 25 26
COM0
COM1
COM2
COM3
S0
S7
S1
S2
S3
S4
S5
Caution Connect the IC0 (Internally Connected) pin directly to VSS. COM0 to COM3: Common Output IC0: INT: KR00 to KR03: P00 to P03: P10, P11: P20 to P22: P40 to P43: P60, P61: P80 to P85: TO40: Internally connected Interrupt from Peripherals Key Return Port 0 Port 1 Port 2 Port 4 Port 6 Port 8 Timer Output RESET: S0 to S23: SCK10: SI10: SO10: VDD: VLC0: VSS: X1, X2: XT1, XT2: Reset Segment Output Serial Clock Input/Output Serial Data Input Serial Data Output Power Supply Power Supply for LCD Ground Crystal (Main system clock) Crystal (Sabsystem clock)
8
Preliminary Product Information U14673EJ1V0PM00
S6
S8
PD789322,789324,789326,789327
2. BLOCK DIAGRAM
Port 0 P00 to P03
TO40/P60
8-bit timer 30 Cascaded 16-bit 8-bit timer timer 40
Port 1
P10, P11
Watch timer 78K/0S CPU core Watchdog timer ROM
Port 2
P20 to P22
Port 4
P40 to P43
Port 6
P60, P61
SCK10/P20 SO10/P21 SI10/P22
Serial interface 10 RAM
RAM space for LCD data
Port 8
P80 to P85
S0 to S23 COM0 to COM3 VLC0 LCD controller/driver System control
RESET X1 X2 XT1 XT2
INT/P61 Power-on clear Interrupt control KR00/P40 to KR03/P43
VDD
VSS
IC0
Remark The Internal ROM and RAM capacities differ depending on the product.
Preliminary Product Information U14673EJ1V0PM00
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PD789322,789324,789326,789327
3. PIN FUNCTIONS 3.1 Port Pins
Pin Name P00 to P03 I/O I/O Function Port 0. This is a 4-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, on-chip pull-up resistors can be specified for the whole port using pull-up resistor option register 0 (PU0). Port 1. This is a 2-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, on-chip pull-up resistors can be specified for the whole port using pull-up resistor option register 0 (PU0). Port 2. This is a 3-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, on-chip pull-up resistors can be specified in 1-bit units using pull-up resistor option register 2 (PUB2). Port 4. This is a 4-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, on-chip pull-up resistors can be specified for the whole port using pull-up resistor option register 0 (PU0), or key return mode register 00 (KRM00). Port 6. This is a 2-bit I/O port. Input/output can be specified in 1-bit units. Port 8. This is a 6-bit I/O port. Input/output can be specified in 1-bit units. After Reset Input Alternate Function -
P10, P11
I/O
Input
-
P20 P21 P22
I/O
Input
SCK10 SO10 SI10
P40 to P43
I/O
Input
KR00 to KR03
P60 P61 P80 to P85
I/O
Input
TO40 INT
I/O
Low-level output
S22 to S17
10
Preliminary Product Information U14673EJ1V0PM00
PD789322,789324,789326,789327
3.2 Non-Port Pins
Pin Name INT I/O Input Function External interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. Key return signal detection 8-bit timer 40 output Serial clock input/output of serial interface 10 Serial data input of serial interface 10 Serial data output of serial interface 10 LCD controller/driver segment signal outputs After Reset Input Alternate Function P61
KR00 to KR03 TO40 SCK10 SI10 SO10 S0 to S16 S17 to S22 S23 COM0 to COM3
Input Output I/O Input Output Output
Input Input Input Input Input Low-level output
P40 to P43 P60 P20 P22 P21 - P85 to P80 -
Output - Input - Input - Input - - -
LCD controller/driver common signal outputs
Low-level output - - -
- - - - - - -
VLC0 X1 X2 XT1 XT2 RESET VDD VSS IC0
LCD drive voltage Connecting crystal resonator for main system clock oscillation
Connecting crystal resonator for subsystem clock oscillation
- -
System reset input Positive power supply Ground potential Internally connected. Connect to VSS directly.
Input - - -
- - -
Preliminary Product Information U14673EJ1V0PM00
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PD789322,789324,789326,789327
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The I/O circuit type of each pin and recommended connection of unused pins is shown in Table 3-1. For the input/output circuit configuration of each type, refer to Figure 3-1. Table 3-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins
Pin Name P00 to P03 P10, P11 P20/SCK10 P21/SO10 P22/SI10 P40/KR00 to P43/KR03 P60/TO40 P61/INT 5 8 Input: Independently connect to VSS via a resistor. Output: Leave open. Input: Independently connect to VDD or VSS via a resistor. Output: Leave open. Output Leave open. 8-A 5-A 8-A I/O Circuit Type 5-A I/O I/O Recommend Connection of Unused Pins Input: Independently connect to VDD or VSS via a resistor. Output: Leave open.
P80/S22 to P85/S17
17-G
S0 to S16, S23 COM0 to COM3 VLC0 XT1 XT2 RESET IC0
17-D 18-B -
- Input - Connect to VSS. Leave open. - Connect directly to VSS directly.
2 -
Input -
Figure 3-1. I/O Circuit Type (1/2)
Type 2 Type 5
VDD Data
IN
P-ch IN/OUT
Output disable
Schmitt-triggered input with hysteresis characteristics.
N-ch VSS
Input enable
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Preliminary Product Information U14673EJ1V0PM00
PD789322,789324,789326,789327
Figure 3-1. I/O Circuit Type (2/2)
Type 5-A
VDD Pull-up enable VDD Data P-ch IN/OUT Output disable N-ch VSS
Type 8
P-ch
Data
VDD P-ch IN/OUT Output disable N-ch VSS
Input enable
Type 8-A
VDD
Type 17-D
VLC0 P-ch
Pull-up enable VDD Data P-ch
P-ch
VLC1
P-ch N-ch P-ch
SEG data
IN/OUT
OUT N-ch
Output disable
N-ch VSS
VLC2 N-ch VSS
P-ch N-ch
Type 17-G
VDD Data P-ch IN/OUT Output disable N-ch VSS
Type 18-B
VLC0
P-ch P-ch N-ch P-ch N-ch OUT N-ch P-ch N-ch N-ch P-ch
Input enable VLC0 P-ch VLC1 P-ch N-ch P-ch SEG data N-ch VLC2 N-ch VSS P-ch N-ch
VLC1
COM data VLC2
VSS
Remark VLC1: VLC0 x 2/3, VLC2: VLC0/3
Preliminary Product Information U14673EJ1V0PM00
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PD789322,789324,789326,789327
4. CPU ARCHITECTURE 4.1 Memory Space
The PD789322, 789324, 789326, and 789327 are provided with 64 Kbytes of accessible memory space. Figure 4-1 shows the memory map. Figure 4-1. Memory Map
FFFFH Special function registers 256 x 8 bits FF00H FEFFH Internal high-speed RAM
Note
mmmmH mmmmH-1 Reserved FA18H FA17H Data memory space FA00H F9FFH n n n n H+1 nnnnH LCD display RAM 24 x 8 bits nnnnH Reserved
Program area
Program memory space
Internal ROM
Note
0080H 007FH CALLT table area 0040H 003FH Program area 0014H 0013H
0000H
0000H
Vector table area
Note The internal ROM capacity and internal high-speed RAM capacity depend on the products (see the next table).
Relevant Product Name Internal ROM Last Address nnnnH Internal High-Speed RAM Start Address mmmmH FE00H
PD789322 PD789324 PD789326 PD789327
0FFFH 1FFFH 3FFFH 5FFFH
FD00H
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Preliminary Product Information U14673EJ1V0PM00
PD789322,789324,789326,789327
4.2 Data Memory Addressing
The PD789322, 789324, 789326, and 789327 are provided with a variety of addressing modes to improve the operability of the memory. In the area that incorporates data memory (FD00H to FFFFH) in particular, specific addressing modes that correspond to the particular functions of an area, such as the special function registers (SFRs), are available. Figure 4-2 shows the data memory addressing modes. Figure 4-2. Data Memory Addressing Modes
FFFFH Special function registers (SFRs) 256 x 8 bits FF20H FF1FH FF00H FEFFH Short direct addressing SFR addressing
Internal high-speed RAM
Note
FE20H FE1FH mmmmH mmmmH-1 Reserved FA18H FA17H LCD display RAM 24 x 8 bits FA00H F9FFH Reserved n n n n H+1 nnnnH
Direct addressing Register indirect addressing Based addressing
Internal ROM
Note
0000H
Note The internal ROM capacity and internal high-speed RAM capacity depend on the products (see the next table).
Relevant Product Name Internal ROM Last Address nnnnH Internal High-Speed RAM Start Address mmmmH FE00H
PD789322 PD789324 PD789326 PD789327
0FFFH 1FFFH 3FFFH 5FFFH
FD00H
Preliminary Product Information U14673EJ1V0PM00
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PD789322,789324,789326,789327
4.3 Processor Registers
4.3.1 Control registers (1) Program counter (PC) The PC is a 16-bit register that holds the address information of the next program to be executed. Figure 4-3. Program Counter Configuration
15 PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 0 PC0
(2) Program status word (PSW) The PSW is an 8-bit register that indicates the status of the CPU according to the results of instruction execution. Figure 4-4. Program Status Word Configuration
7 IE Z 0 AC 0 0 1 0 CY
(a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledgement of the CPU. (b) Zero flag (Z) This flag is set (1) if the result of an operation is zero; otherwise it is reset (0). (c) Auxiliary carry flag (AC) AC is set (1) if the result of the operation has a carry from bit 3 or a borrow at bit 3; otherwise it is reset (0). (d) Carry flag (CY) CY is used to indicate whether an overflow or underflow has occurred during the execution of a subtract or add instruction. (3) Stack pointer (SP) The SP is a 16-bit register that holds the start address of the stack area. Only the internal RAM area (FD00H to FEFFH) can be specified as the stack area. Figure 4-5. Stack Pointer Configuration
15 SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 0 SP0
Caution RESET input makes the SP contents undefined, so be sure to initialize the SP before instruction execution.
16
Preliminary Product Information U14673EJ1V0PM00
PD789322,789324,789326,789327
4.3.2 General-purpose registers The PD789322, 789324, 789326, and 789327 have eight 8-bit general-purpose registers (X, A, C, B, E, D, L, and H). These registers can be used either singly as 8-bit registers or in pairs as 16-bit registers (AX, BC, DE, and HL), and can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3). Figure 4-6. General-Purpose Register Configuration (a) Absolute register names
16-bit processing 8-bit processing R7 RP3 R6 R5 RP2 R4 R3 RP1 R2 R1 RP0 R0 15 0 7 0
(b) Functional register names
16-bit processing 8-bit processing H HL L D DE E B BC C A AX X 15 0 7 0
Preliminary Product Information U14673EJ1V0PM00
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PD789322,789324,789326,789327
4.3.3 Special function registers (SFRs) Special function registers are used as peripheral hardware mode registers and control registers, and are mapped in the 256-byte space from FF00H to FFFFH. Note that the bit number of a bit name that is a reserved word in the RA78K0S and defined under the header file "sfrbit.h" in the CC78K0S appears enclosed in a circle in the register formats. Refer to the register formats in 5. PERIPHERAL HARDWARE FUNCTIONS. Table 4-1. Special Function Registers (1/2)
Address Special Function Register (SFR) Name Symbol R/W Bit Unit for Manipulation 1 Bit FF00H FF01H FF02H FF03H FF05H FF08H FF20H FF21H FF22H FF24H FF26H FF28H FF32H FF4AH FF58H FF63H FF64H FF65H FF66H FF67H FF68H FF69H FF6AH FF72H FF74H FFB0H FFB2H Port 0 Port 1 Port 2 port 4 Port 6 Port 8 Port mode register 0 Port mode register 1 Port mode register 2 Port mode register 4 Port mode register 6 Port mode register 8 Pull-up resistor option register B2 Watch timer mode control register Port function register 8 8-bit compare register 30 8-bit timer counter 30 8-bit timer mode control register 30 8-bit compare register 40 8-bit H width compare register 40 8-bit timer counter 40 8-bit timer mode control register 40 Carrier generator output control register 40 Serial operation mode register 10 Transmission/reception shift register 10 LCD display mode register 0 LCD clock control register 0 P0 P1 P2 P4 P6 P8 PM0 PM1 PM2 PM4 PM6 PM8 PUB2 WTM PF8 CR30 TM30 TMC30 CR40 CRH40 TM40 TMC40 TCA40 CSIM10 SIO10 LCDM0 LCDC0 POCF1 R R/W W R/W W R R/W W R/W - - - - - - 8 Bits 16 Bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - 00H
Note
After Reset 00H
FFH
00H
Undefined 00H
Undefined
00H
Undefined 00H
FFDDH Power-on-clear register 1
Note This value is 04H only after a power-on-clear reset.
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PD789322,789324,789326,789327
Table 4-1. Special Function Registers (2/2)
Address Special Function Register (SFR) Name Symbol R/W Bit Unit for Manipulation 1 Bit FFE0H FFE4H Interrupt request flag register 0 Interrupt mask flag register 0 IF0 MK0 INTM0 SCKM CSS KRM00 PU0 WDTM OSTS PCC R/W - - 8 Bits 16 Bits - - - - - - - - - - 04H 02H After Reset 00H FFH 00H
FFECH External interrupt mode register 0 FFF0H FFF2H FFF5H FFF7H FFF9H Subclock oscillation mode register Subclock control register Key return mode register 00 Pull-up resistor option register 0 Watchdog timer mode register
FFFAH Oscillation stabilization time selection register FFFBH Processor clock control register
Preliminary Product Information U14673EJ1V0PM00
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PD789322,789324,789326,789327
5. PERIPHERAL HARDWARE FUNCTIONS 5.1 Ports
5.1.1 Port functions Various kinds of control operations are possible using the ports provided in the PD789322, 789324, 789326, and 789327. These ports are illustrated in Figure 5-1 and their functions are listed in Table 5-1. A number of alternate functions are also provided, except for those ports functioning as digital I/O ports. Refer to 3. PIN FUNCTIONS for details of the alternate function pins. Figure 5-1. Ports
P40 Port 4 P43
P00 Port 0 P03
Port 6
P60 P61
P10 P11
Port 1
P80 Port 8 P85
P20 Port 2 P22
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PD789322,789324,789326,789327
Table 5-1. Port Functions
Port Name Port 0 Pin Name P00 to P03 Function This is an I/O port for which input and output can be specified in 1-bit units. When used as an input port, on-chip pull-up resistors can be specified using pull-up resistor option register 0 (PU0). This is an I/O port for which input and output can be specified in 1-bit units. When used as an input port, on-chip pull-up resistors can be specified using pull-up resistor option register 0 (PU0). This is an I/O port for which input and output can be specified in 1-bit units. When used as an input port, on-chip pull-up resistors can be specified using pull-up resistor option register B2 (PUB2). This is an I/O port for which input and output can be specified in 1-bit units. When used as an input port, on-chip pull-up resistors can be specified using pull-up resistor option register 0 (PU0), or key return mode register 00 (KRM00). This is an I/O port for which input and output can be specified in 1-bit units. This is an I/O port for which input and output can be specified in 1-bit units.
Port 1
P10, P11
Port 2
P20 to P22
Port 4
P40 to P43
Port 6 Port 8
P60, P61 P80 to P85
Preliminary Product Information U14673EJ1V0PM00
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PD789322,789324,789326,789327
5.1.2 Port configuration The ports consist of the following hardware. Table 5-2. Port Configuration
Item Control registers Configuration Port mode registers (PMm: m = 0 to 2, 4, 6, 8) Pull-up resistor option registers (PU0, PUB2) Port function register 8 (PF8) Total: 21 (CMOS I/O: 21) Total: 13 (software control: 13)
Ports Pull-up resistors
Figure 5-2. Basic Configuration of CMOS Port
VDD
WRPUm
PUx P-ch
WRPORTm
Internal bus
WRPORTm Output latch Pmn
Selector
Pmn
WRPMm
PMmn
Caution Figure 5-2 shows the basic configuration of a CMOS I/O port.
This configuration differs
depending on the functions of alternate function pins. Also, an on-chip pull-up resistor can be connected to port 4 by means of a setting in key return mode register 00 (KRM00). Remark PUx: Pmn: RD: WR: Pull-up resistor option register (x = 0, B2) Bit n of port m Port read signal Port write signal
PMmn: Bit n of port mode register m (m = 0 to 2, 4, 6, 8 n = 0 to 5)
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Preliminary Product Information U14673EJ1V0PM00
PD789322,789324,789326,789327
5.1.3 Port function control registers The ports are controlled by the following three types of registers. * Port mode registers (PM0 to PM2, PM4, PM6, PM8) * Pull-up resistor option registers (PU0, PUB2) * Port function register 8 (PF8) (1) Port mode registers (PM0 to PM2, PM4, PM6, PM8) Input and output can be specified in 1-bit units. These registers can be set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to FFH. When using the port pins as their alternate functions, set the port mode register and the output latch as shown in Table 5-3. Caution Because P61 functions alternately as an external interrupt input, when the output level changes after the output mode of the port function is specified, the interrupt request flag will be inadvertently set. Therefore, be sure to preset the interrupt mask flag (PMK0) before using the port in output mode. Figure 5-3. Port Mode Register Format
Symbol PM0 7 1 6 1 5 1 4 1 3 PM03 2 PM02 1 PM01 0 PM00 Address FF20H After reset FFH R/W R/W
PM1
1
1
1
1
1
1
PM11
PM10
FF21H
FFH
R/W
PM2
1
1
1
1
1
PM22
PM21
PM20
FF22H
FFH
R/W
PM4
1
1
1
1
PM43
PM42
PM41
PM40
FF24H
FFH
R/W
PM6
1
1
1
1
1
1
PM61
PM60
FF26H
FFH
R/W
PM8
1
1
PM85
PM84
PM83
PM82
PM81
PM80
FF28H
FFH
R/W
PMmn
Pmn pin input/output mode selection (m = 0 to 2, 4, 6, 8 n = 0 to 5) Output mode (output buffer on) Input mode (output buffer off)
0 1
Preliminary Product Information U14673EJ1V0PM00
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PD789322,789324,789326,789327
Table 5-3. Port Mode Registers and Output Latch Settings When Using Alternate Functions
Pin Name Alternate Function Name P20 SCK10 I/O Input Output P21 P22 P40 to P43 P60 P61 P80 to P85 SO10 SI10 KR00 to KR03 TO40 INT S22 to S17
Note
PMxx
Pxx
1 0 0 1 1 0 1 x
x 1 1 x x 0 x x
Output Input Input Output Input Output
Note When using P80 to P85 pins as S22 to S17, set port function register 8 (PF8) to 3FH. Remark x: Pxx: don't care Port output latch
PMxx: Port mode register
(2) Pull-up resistor option register 0 (PU0) This register sets whether to use on-chip pull-up resistors for ports 0, 1, and 4 on a port by port basis. An onchip pull-up resistor can be used only for those bits set to the input mode of a port for which the use of the onchip pull-up resistor has been specified using PU0. For those bits set to the output mode, on-chip pull-up resistors cannot be used, regardless of the setting of PU0. This also applies to alternate-function pins used as output pins. PU0 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 5-4. Format of Pull-Up Resistor Option Register 0
Symbol PU0 7 0 6 0 5 0 <4> PU04 3 0 2 0 <1> PU01 <0> PU00 Address FFF7H After reset 00H R/W R/W
PU0m
Port m on-chip pull-up resistor selection (m = 0, 1, 4) An on-chip pull-up resistor is not connected An on-chip pull-up resistor is connected
0 1
Caution Always set bits 2, 3, and 5 to 7 to 0.
24
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PD789322,789324,789326,789327
(3) Pull-up resistor option register B2 (PUB2) This register sets whether to use on-chip pull-up resistors for P20 to P22 in bit units. An on-chip pull-up resistor can be used only for those bits set to the input mode of a port for which the use of the on-chip pull-up resistor has been specified using PUB2. For those bits set to the output mode, on-chip pull-up resistors cannot be used, regardless of the setting of PUB2. This also applies to alternate-function pins used as output pins. PUB2 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 5-5. Format of Pull-Up Resistor Option Register B2
Symbol PUB2 7 0 6 0 5 0 4 0 3 0 <2> PUB22 <1> PUB21 <0> PUB20 Address FF32H After reset 00H R/W R/W
PUB2n
P2n on-chip pull-up resistor selection (n = 0 to 2) An on-chip pull-up resistor is not connected An on-chip pull-up resistor is connected
0 1
Caution Always set bits 3 to 7 to 0. (4) Port function register 8 (PF8) This register sets the port function of port 8 in 1-bit units. The pins of port 8 are selected as either LCD segment signal outputs or general-purpose port pins according to the setting of PF8. PF8 can be set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 5-6. Format of Port Function Register 8
Symbol PF8 7 0 6 0 5 PF85 4 PF84 3 PF83 2 PF82 1 PF81 0 PF80 Address FF58H After reset 00H R/W R/W
PF8n 0 1 Operates as a general-purpose port
P8n port function (n = 0 to 5)
Operates as an LCD segment signal output
Preliminary Product Information U14673EJ1V0PM00
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PD789322,789324,789326,789327
5.2 Clock Generator
5.2.1 Clock generator function The clock generator generates the clock pulse to be supplied to the CPU and peripheral hardware. There are two types of system clock oscillators: * Main system clock oscillator (ceramic/crystal resonator) This circuit generates a frequency of 1.0 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction or by means of a processor clock control register (PCC) setting. * Subsystem clock oscillator This circuit generates a frequency of 32.768 kHz. Oscillation can be stopped using the subclock oscillation mode register (SCKM). 5.2.2 Clock generator configuration The clock generator consists of the following hardware. Table 5-4. Clock Generator Configuration
Item Control registers Processor clock control register (PCC) Subclock oscillation mode register (SCKM) Subclock control register (CSS) Main system clock oscillator Subsystem clock oscillator Configuration
Oscillators
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PD789322,789324,789326,789327
Figure 5-7. Clock Generator Block Diagram
Internal bus
FRC SCC
Subclock oscillation mode register (SCKM)
XT1 XT2
Subsystem clock oscillatior
fXT
Watch timer LCD controller/driver
1/2 X1 X2 Main system fX clock oscillator fXT 2
Prescaler fX 22
Clock to peripheral hardware
STOP
MCC PCC1
CLS CSS0 Subclock control register (CSS) Internal bus
Processor clock control register (PCC)
Selector
Standby control circuit
Wait control circuit
CPU clock (fCPU)
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PD789322,789324,789326,789327
5.2.3 Clock generator control registers The clock generator is controlled by the following three registers. * Processor clock control register (PCC) * Subclock oscillation mode register (SCKM) * Subclock control register (CSS) (1) Processor clock control register (PCC) This register is used to select the CPU clock and set the frequency division ratio. PCC is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 02H. Figure 5-8. Format of Processor Clock Control Register
Symbol PCC <7> MCC 6 0 5 0 4 0 3 0 2 0 1 PCC1 0 0 Address FFFBH After reset 02H R/W R/W
MCC 0 1 Operation enabled Operation stopped
Main system clock oscillator operation control
CSS0 0 0 1
PCC1 0 1 x fX fX/2
2
CPU clock (fCPU) selection (0.2 s) (0.8 s)
Note
Minimum instruction execution time: 2fCPU 0.4 s 1.6 s 122 s
fXT/2 (61 s)
Note The CPU clock is selected by a combination of flag settings in the PCC and CSS registers. (Refer to 5.2.3 (3) Subclock control register (CSS).) Cautions 1. Always set bits 0 and 2 to 6 to 0. 2. MCC can be set only when the subsystem clock is selected as the CPU clock. Setting MCC to 1 while the main system clock is operating is invalid. Remarks 1. fX: Main system clock oscillation frequency 2. fXT: Subsystem clock oscillation frequency 3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
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PD789322,789324,789326,789327
(2) Subclock oscillation mode register (SCKM) This register is used to select a feedback resistor for the subsystem clock and control the oscillation of the clock. SCKM is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 5-9. Format of Subclock Oscillation Mode Register
Symbol SCKM 7 0 6 0 5 0 4 0 3 0 2 0 1 FRC <0> SCC Address FFF0H After reset 00H R/W R/W
FRC 0 1 An on-chip feedback resistor is used An on-chip feedback resistor is not used
Feedback resistor selection
SCC 0 1 Operation enabled Operation stopped
Control of subsystem clock oscillator operation
Caution Always set bits 2 to 7 to 0.
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PD789322,789324,789326,789327
(3) Subclock control register (CSS) This register is used to specify whether the main system or subsystem clock oscillator is selected and to indicate the operating status of the CPU clock. CSS is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 5-10. Format of Subclock Control Register
Symbol CSS 7 0 6 0 5 CLS 4 CSS0 3 0 2 0 1 0 0 0 Address FFF2H After reset 00H R/W R/W
Note
CLS 0 1
CPU clock operating status Operating on the output of the (divided) main system clock Operating on the output of the subsystem clock
CSS0 0 1
Selection of main system clock or subsystem clock oscillator Main system clock oscillator (divided) output Subsystem clock oscillator output
Note Bit 5 is read-only. Caution Always set bits 0 to 3, 6, and 7 to 0.
30
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PD789322,789324,789326,789327
5.3 8-Bit Timer 30, 40
5.3.1 Functions of 8-bit timer 30, 40 The 8-bit timer in the PD789322, 789324, 789326, and 789327 have 2 channels (timer 30 and timer 40). The operation modes in the following table are possible by means of mode register settings. Table 5-5. List of Modes
Channel Mode 8-bit timer counter mode (discrete mode) 16-bit timer counter mode (cascade connection mode) Carrier generator mode PWM output mode - Timer 30 Timer 40
(1) 8-bit timer counter mode (discrete mode) The timer can be used for the following functions in this mode. * 8-bit resolution interval timer * 8-bit resolution square wave output (timer 40 only) (2) 16-bit timer counter mode (cascade connection mode) These timers can be used for 16-bit timer operations via a cascade connection. The timer can be used for the following functions in this mode. * 16-bit resolution interval timer * 16-bit resolution square wave output (3) Carrier generator mode In this mode the carrier clock generated by timer 40 is output in the cycle set by timer 30. (4) PWM output mode In this mode, a pulse with an arbitrary duty ratio, which is set by timer 40, is output.
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PD789322,789324,789326,789327
5.3.2 Configuration of 8-bit timer 30, 40 8-bit timers 30 and 40 consist of the following hardware. Table 5-6. Configuration of 8-Bit Timer 30, 40
Item Timer counter Registers Timer outputs Control registers 8 bits x 2 (TM30, TM40) Compare registers: 8 bits x 3 (CR30, CR40, CRH40) 1 (TO40) 8-bit timer mode control register 30 (TMC30) 8-bit timer mode control register 40 (TMC40) Carrier generator output control register 40 (TCA40) Port mode register 6 (PM6) Configuration
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Figure 5-11. Block Diagram of Timer 30
Internal bus 8-bit timer mode control registedr 30 (TMC30) TCE30 TCL301 TCL300 TMD300
Decoder Selector
8-bit compare register 30 (CR30) Match To Figure 5-12 (G) Timer 30 match signal (in carrier generator mode) OVF
Preliminary Product Information U14673EJ1V0PM00
Bit 7 of TM40 (from Figure 5-12 (A)) 8-bit timer counter 30 (TM30) Clear
PD789322,789324,789326,789327
(from Figure 5-12 (B)) Carrier clock (in carrier generator mode) or timer 40 output signal (in other than carrier generator mode) (from Figure 5-12 (C))
Selector
Selector
fX/26 fX/28 Timer 40 interrupt request signal
Internal reset signal
From Figure 5-12 (D) Count operation start signal (for cascade connection)
Selector Cascade connection mode INTTM30
From Figure 5-12 (E) Timer 40 match signal (in cascade connection mode) To Figure 5-12 (F) Timer 30 match signal (in cascade connection mode)
33
Selector
Prescaler
34
8-bit timer mode control register 40 (TMC40) Decoder
Preliminary Product Information U14673EJ1V0PM00
Figure 5-12. Block Diagram of Timer 40
Internal bus
Carrier generator output control register 40 (TCA40) 8-bit H width compare register 40 (CRH40) 8-bit compare register 40 (CR40) RMC40 NRZB40 NRZ40
TCE40 TCL402 TCL401 TCL400 TMD401 TMD400 TOE40
Selector
From Figure 5-11 (G) Timer counter match signal from timer 30 (in carrier generator mode)
Match fX fX/22 fX/2 fX/2
2
F/F
Output control circuitNote
TO40/P60 To Figure 5-11 (C) Carrier clock (in carrier generator mode) or timer 40 output signal (in other than carrier generator mode)
8-bit timer counter 40 (TM40) Clear
Carrier generator mode PWM mode
OVF
fX/23 fX/2
4
PD789322,789324,789326,789327
Reset
Cascade connection mode
To Figure 5-11 (A) Bit 7 of TM40 (in cascade connection mode)
Internal reset signal To Figure 5-11 (D) Count operation start signal to timer 30 (in cascade connection mode) To Figure 5-11 (E) TM40 timer counter match signal (in cascade connection mode) INTTM40 To Figure 5-11 (B) Timer 40 interrupt request signal count clock input signal to TM30
To Figure 5-11 (F) TM30 match signal (in cascade connection mode)
Note Refer to Figure 5-13 for details.
PD789322,789324,789326,789327
Figure 5-13. Block Diagram of Output Control Circuit (Timer 40)
TOE40 RMC40 NRZ40 P60
output latch
PM60
Selector
F/F
TO40/P60 Carrier clock (in carrier generator mode) or timer 40 output signal (in other than carrier generator mode)
Carrier generator mode
(1) 8-bit compare register 30 (CR30) A value specified in CR30 is compared with the count value in 8-bit timer counter 30 (TM30), and if they match, an interrupt request (INTTM30) is generated. CR30 is set using an 8-bit memory manipulation instruction. RESET input makes this register undefined. Caution CR30 cannot be used in carrier generator mode or PWM output mode. (2) 8-bit compare register 40 (CR40) A value specified in CR40 is compared with the count value in 8-bit timer counter 40 (TM40), and if they match, an interrupt request (INTTM40) is generated. and TM40 match simultaneously (INTTM30 is not issued). CR40 is set using an 8-bit memory manipulation instruction. RESET input makes this register undefined. (3) 8-bit H width compare register (CRH40) In carrier generator mode or PWM output mode, a timer output high-level width can be set by writing a value to CRH40. CRH40 is set using an 8-bit memory manipulation instruction. RESET input makes this register undefined. When operating as a 16-bit timer in cascade connection with TM30, an interrupt request (INTTM40) is only generated if both CR30 and TM30, and CR40
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PD789322,789324,789326,789327
(4) 8-bit timer counter 30, 40 (TM30, TM40) This is an 8-bit register for counting the count pulses. TM30 and TM40 can be read with a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to 00H. The conditions under which TM30 and TM40 are cleared to 00H are listed below. (a) Discrete mode (i) TM30 * Upon a reset * When TCE30 (bit 7 of 8-bit timer mode control register 30 (TMC30)) is cleared to 0 * Upon a match between TM30 and CR30 * If the TM30 count value overflows (ii) TM40 * Upon a reset * When TCE40 (bit 7 of 8-bit timer mode control register 40 (TMC40)) is cleared to 0 * Upon a match between TM40 and CR40 * If the TM40 count value overflows (b) Cascade connection mode (TM30 and TM40 cleared to 00H simultaneously) * Upon a reset * When the TCE40 flag is cleared to 0 * Upon a simultaneous match between TM30 and CR30, and TM40 and CR40 * If the TM30 and TM40 count values overflow simultaneously (c) Carrier generator/PWM output mode (TM40 only) * Upon a reset * When the TCE40 flag is cleared to 0 * Upon a match between TM40 and CR40 * Upon a match between TM40 and CRH40 * If the TM40 count value overflows
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Preliminary Product Information U14673EJ1V0PM00
PD789322,789324,789326,789327
5.3.3 8-bit timer 30, 40 control registers 8-bit timers 30 and 40 are controlled by the following 4 registers. * 8-bit timer mode control register 30 (TMC30) * 8-bit timer mode control register 40 (TMC40) * Carrier generator output control register 40 (TCA40) * Port mode register 6 (PM6)
Preliminary Product Information U14673EJ1V0PM00
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PD789322,789324,789326,789327
(1) 8-bit timer mode control register 30 (TMC30) This register is used to control the timer 30 count clock and operation mode settings. TMC30 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 5-14. Format of 8-Bit Timer Mode Control Register 30
Symbol TMC30 <7> TCE30 6 0 5 0 4 TCL301 3 TCL300 2 0 1 TMD300 0 0 Address FF65H After reset 00H R/W R/W
TCE30 0 1
TM30 count control operation TM30 count value cleared and operation stopped Count operation starts
Note 1
TCL301 0 0 1 1
TCL300 0 1 0 1 fX/2
6 8
Timer 30 count clock selection (78.1 kHz) (19.5 kHz)
fX/2
Timer 40 match signal Carrier clock (in carrier generator mode) or timer 40 output signal (in other than carrier generator mode)
TMD300 0 1 0 0
TMD401 0 0 1 1
TMD400 0 1 1 0 Discrete mode
Timer 30, timer 40 operation mode selection
Note 2
Cascade connection mode Carrier generator mode PWM output mode Setting prohibited
Other than above
Notes 1. The TCE30 setting will be ignored in cascade mode because in this case the count operation is controlled by TCE40 (bit 7 of TMC40). 2. The operation mode selection is made using a combination of TMC30 and TMC40 register settings. Caution In cascade connection mode, the timer 40 output signal is forcibly selected for the count clock. Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz
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PD789322,789324,789326,789327
(2) 8-bit timer mode control register 40 (TMC40) This register is used to control the timer 40 count clock and operation mode settings. TMC40 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 5-15. Format of 8-Bit Timer Mode Control Register 40
Symbol TMC40 <7> TCE40 6 0 5 TCL402 4 TCL401 3 TCL400 2 TMD401 1 TMD400 <0> TOE40 Address FF69H After reset 00H R/W R/W
TCE40 0
TM40 count control operation
Note 1
TM40 count value cleared and operation stopped (in cascade connection mode, the count value of TM30 is cleared at the same time) Count operation starts (in cascade connection mode, the count operation of TM30 starts at the same time)
1
TCL402 0 0 0 0 1 1
TCL401 0 0 1 1 0 0
TCL400 0 1 0 1 0 1 fX (5 MHz) fX/2 (1.25 MHz) fX/2 (2.5 MHz) fX/2 (1.25 MHz) fX/2 (625 kHz) fX/2 (313 kHz) Setting prohibited
4 3 2 2
Timer 40 count clock selection
Other than above
TMD300 0 1 0 0
TMD401 0 0 1 1
TMD400 0 1 1 0 Discrete mode
Timer 30, timer 40 operation mode selection
Note 2
Cascade connection mode Carrier generator mode PWM output mode Setting prohibited
Other than above
TOE40 0 1 Output disabled (port mode) Output enabled
Timer output control
Notes 1. The TCE30 setting will be ignored in cascade mode because in this case the count operation is controlled by TCE40 (bit 7 of TMC40). 2. The operation mode selection is made using a combination of TMC30 and TMC40 register settings. Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz
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PD789322,789324,789326,789327
(3) Carrier generator output control register 40 (TCA40) This register is used to set the timer output data in the carrier generator mode. TCA40 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 5-16. Format of Carrier Generator Output Control Register 40
Symbol TCA40 7 0 6 0 5 0 4 0 3 0 <2> RMC40 <1> NRZB40 <0> NRZ40 Address FF6AH After reset 00H R/W W
RMC40 0 1
Remote controller output control When NRZ40 = 1, a carrier pulse is output to the TO40/P60 pin When NRZ40 = 1, a high level is output to the TO40/P60 pin
NRZB40 This bit stores the data that NRZ40 will output next. Data is transferred to NRZ40 upon the generation of a timer 30 match signal.
NRZ40 0 1
No return, zero data A low level is output (the carrier clock is stopped) A carrier pulse is output
Caution TCA40 cannot be set with a 1-bit memory manipulation instruction. Be sure to set it with an 8-bit memory manipulation instruction. (4) Port mode register 6 (PM6) This register is used to set port 6 to input or output in 1-bit units. When the TO40/P60 pin is used as a timer output, set the PM60 and P60 output latches to 0. PM6 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to FFH. Figure 5-17. Format of Port Mode Register 6
Symbol PM6 7 1 6 1 5 1 4 1 3 1 2 1 1 PM61 0 PM60 Address FF26H After reset FFH R/W R/W
PM6n 0 1 Output mode (output buffer on) Input mode (output buffer off)
Input/output mode of pin P6n (n = 0, 1)
40
Preliminary Product Information U14673EJ1V0PM00
PD789322,789324,789326,789327
5.4 Watch Timer
5.4.1 Watch timer functions The watch timer has the following functions. * Watch timer * Interval timer The watch and interval timers can be used at the same time. Figure 5-18 shows a block diagram of the watch timer. Figure 5-18. Watch Timer Block Diagram
Clear
Selector
fX/2
7
fW fW 24
9-bit prescaler fW 25 fW 26 fW 27 fW 28 fW 29
5-bit counter Clear
INTWT
fXT
Selector
INTWTI
WTM7 WTM6 WTM5 WTM4 WTM1 WTM0 Watch timer mode control register (WTM) Internal bus
Preliminary Product Information U14673EJ1V0PM00
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PD789322,789324,789326,789327
(1) Watch timer An interrupt request (INTWT) is generated at 0.5-second intervals using the 4.19-MHz main system clock or 32.768-kHz subsystem clock. Caution When the main system clock is operating at 5.0 MHz, it cannot be used to generate a 0.5-second interval. instead. (2) Interval timer The interval timer is used to generate an interrupt request (INTWTI) at preset intervals. Table 5-7. Interval Time of Interval Timer
Interval Time 2 x 1/fW 2 x 1/fW 2 x 1/fW 2 x 1/fW 2 x 1/fW 2 x 1/fW
9 8 7 6 5 4
In this case, the subsystem clock, which operates at 32.768 kHz, should be used
At fX = 5.0 MHz Operation 409.6 s 819.2 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms
At fX = 4.19 MHz Operation 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms
At fXT = 32.768 kHz Operation 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms
7 Remarks 1. fW: Watch timer clock frequency (fX/2 or fXT)
2. fX: Main system clock oscillation frequency 3. fXT: Subsystem clock oscillation frequency 5.4.2 Watch timer configuration The watch timer consists of the following hardware. Table 5-8. Watch Timer Configuration
Item Counter Prescaler Control register 5 bits x 1 9 bits x 1 Watch timer mode control register (WTM) Configuration
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PD789322,789324,789326,789327
5.4.3 Watch timer control register The following register controls the watch timer. * Watch timer mode control register (WTM) (1) Watch timer mode control register (WTM) This register is used to enable/disable the count clock and operation of the watch timer and set the interval time of the prescaler and operation control of the 5-bit counter. WTM is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 5-19. Format of Watch Timer Mode Control Register
Symbol WTM 7 WTM7 6 WTM6 5 WTM5 4 WTM4 3 0 2 0 <1> WTM1 <0> WTM0 Address FF4AH After reset 00H R/W R/W
WTM7 0 1 fX/2 (39.1 kHz) fXT (32.768 kHz)
7
Watch timer count clock (fW) selection
WTM6 0 0 0 0 1 1
WTM5 0 0 1 1 0 0
WTM4 0 1 0 1 0 1 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW Setting prohibited
9 8 7 6 5 4
Prescaler interval time selection
Other than above
WTM1 0 1 Cleared after operation stopped Start
5-bit counter operation control
WTM0 0 1
Watch timer operation enable Operation stopped (both prescaler and timer cleared) Operation enabled
7 Remarks 1. fW: Watch timer clock frequency (fX/2 or fXT)
2. fX: Main system clock oscillation frequency 3. fXT: Subsystem clock oscillation frequency 4. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
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PD789322,789324,789326,789327
5.5 Watchdog Timer
5.5.1 Watchdog timer functions The watchdog timer has the following functions. (1) Watchdog timer The watchdog timer is used to detect a program runaway. If a runaway is detected, either a non-maskable interrupt or the RESET signal can be generated. (2) Interval timer The interval timer is used to generate interrupts at preset intervals. 5.5.2 Watchdog timer configuration The watchdog timer consists of the following hardware. Table 5-9. Watchdog Timer Configuration
Item Control register Watchdog timer mode register (WDTM) Configuration
Figure 5-20. Watchdog Timer Block Diagram
Internal bus
WDTMK
fX 24
7-bit counter Clear
Control circuit
WDTIF
INTWDT maskable interrupt request RESET INTWDT non-maskable interrupt request
RUN WDTM4 WDTM3 Watchdog timer mode register (WDTM) Internal bus
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PD789322,789324,789326,789327
5.5.3 Watchdog timer control register The watchdog timer is controlled by the following register. * Watchdog timer mode register (WDTM) (1) Watchdog timer mode register (WDTM) This register is used to set the watchdog timer operation mode and whether to enable or disable counting. WDTM is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 5-21. Format of Watchdog Timer Mode Register
Symbol WDTM <7> RUN 6 0 5 0 4 WDTM4 3 WDTM3 2 0 1 0 0 0 Address FFF9H After reset 00H R/W R/W
RUN 0 1 Counting stopped
Watchdog timer operation selection
Note 1
Counter cleared and counting starts
WDTM4 0 0 1 1
WDTM3 0 1 0 1 Operation stopped
Watchdog timer operation mode selection
Note 2
Interval timer mode (when an overflow occurs, a maskable interrupt is generated)
Note 3
Watchdog timer mode 1 (when an overflow occurs, a non-maskable interrupt is generated) Watchdog timer mode 2 (when an overflow occurs, a reset operation is activated)
Notes 1. Once the RUN bit has been set (1), it is impossible to clear it (0) by software. Consequently, once counting begins, it cannot be stopped by any means other than RESET input. 2. Once WDTM3 and WDTM4 have been set (1), it is impossible to clear them (0) by software. 3. The interval timer starts operating as soon as the RUN bit is set to 1. Cautions 1. When the RUN bit is set to 1, and the watchdog timer is cleared, the actual overflow time will be up to 0.8% shorter than the time specified by the watchdog timer clock selection register. 2. To use watchdog timer mode 1 or 2, be sure to set WDTM4 to 1 after confirming that WDTIF (bit 0 of interrupt request flag 0 (IF0)) has been set to 0. If WDTIF is 1, selecting watchdog timer mode 1 or 2 causes a non-maskable interrupt to be generated the instant rewriting ends.
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PD789322,789324,789326,789327
5.6 Serial Interface 10
5.6.1 Functions of serial interface 10 Serial interface 10 has the following two modes. * Operation stopped mode * 3-wire serial I/O mode (1) Operation stopped mode This mode is used to minimize power consumption when serial transfer is not performed. (2) 3-wire serial I/O mode (switchable between MSB-first and LSB-first transmission) This mode is used to transmit 8-bit data, using three lines: a serial clock line (SCK10) and two serial data lines (SI10 and SO10). As 3-wire serial I/O mode supports simultaneous transmission and reception, the time required for data processing can be reduced. In 3-wire serial I/O mode, it is possible to select whether 8-bit data transmission begins with the MSB or LSB, allowing serial interface 10 to be connected to any device regardless of whether that device is designed for MSB-first or LSB-first transmission. 3-wire serial I/O mode is effective for connecting peripheral I/O circuits and display controllers having conventional clock synchronous serial interfaces, such as those of the 75XL, 78K, and 17K Series devices. 5.6.2 Configuration of serial interface 10 Serial interface 10 consists of the following hardware. Table 5-10. Configuration of Serial Interface 10
Item Register Control register Configuration Transmission/reception shift register 10 (SIO10) Serial operation mode register 10 (CSIM10)
(1) Transmission/reception shift register 10 (SIO10) This is an 8-bit register used for parallel/serial data conversion and for serial transmission or reception in synchronization with the serial clock. SIO10 is set using an 8-bit memory manipulation instruction. RESET input makes this register undefined.
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Figure 5-22. Block Diagram of Serial Interface 10
Internal bus Serial operation mode register 10 (CSIM10) CSIE10 TPS101 TPS100 DIR10 CSCK10
SI10/P22
Transmission/reception shift register 10 (SIO10)
Selector
TPS101 TPS100
Selector
Preliminary Product Information U14673EJ1V0PM00
SO10/P21 PM21
PD789322,789324,789326,789327
Serial clock counter
Interrupt request generator
INTCSI10
PM20 SCK10/P20 Clock control circuit F/F
fX/22 fX/23
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PD789322,789324,789326,789327
5.6.3 Control register for serial interface 10 Serial interface 10 is controlled by the following register. * Serial operation mode register 10 (CSIM10) Figure 5-23. Format of Serial Operation Mode Register 10
Symbol CSIM10 <7> CSIE10 6 0 5 TPS101 4 TPS100 3 0 2 DIR10 1 CSCK10 0 0 Address FF72H After reset 00H R/W R/W
CSIE10 0 1 Operation stopped Operation enabled
3-wire serial I/O mode operation control
TPS101 0 0
TPS100 0 1 fX/2 (1.25 MHz) fX/2 (625 kHz) Setting prohibited
3 2
Selection of count clock when internal clock selected
Other than above
DIR10 0 1 MSB LSB
First-bit specification
CSCK10 0 1 External clock pulse input to the SCK10 pin
SIO10 clock selection
Internal clock selected with TPS100, TPS101
Cautions 1. Bits 0, 3 and 6 must be fixed to 0. 2. Be sure to switch to operation mode after stopping the serial transmission/reception operation. Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz.
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PD789322,789324,789326,789327
Table 5-11. Operation Mode Settings for Serial Interface 10 (1) Operation stopped mode
CSIM10 CSIE10 0 DIR10 CSCK10 x x xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 - - P22 P21 P20 PM22 P22 PM21 P21 PM20 P20 First Bit Shift Clock P22/SI10 Pin Function P21/SO10 Pin Function P20/SCK10 Pin Function
Other than above
Setting prohibited
(2) 3-wire serial I/O mode
CSIM10 CSIE10 1 DIR10 CSCK10 0 0 1 1 0 1 1Note 2 xNote 2 0 1 1 0 1 0 x 1 x 1 LSB MSB External clock Internal clock External clock Internal clock Setting prohibited SI10Note 2 SO10 (CMOS output) SCK10 input SCK10 output SCK10 input SCK10 output PM22 P22 PM21 P21 PM20 P20 First Bit Shift Clock P22/SI10 Pin Function P21/SO10 Pin Function P20/SCK10 Pin Function
Other than above
Notes 1. Can be used freely as a port 2. Can be used as P22 (CMOS I/O) only when transmitting Remark x: don't care
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PD789322,789324,789326,789327
5.7 LCD Controller/Driver
5.7.1 LCD controller/driver functions The LCD controller/driver incorporated in the PD789322, 789324, 789326, and 789327 has the following features. (1) Segment and common signals based on the automatic reading of the display data memory can be automatically output (2) Four types of frame frequencies are selectable (3) 24 segment signal outputs (S0 to S23), 4 common signal outputs (COM0 to COM3) (4) Operation with a subsystem clock is possible The maximum number of displayable pixels is shown in Table 5-12 below. Table 5-12. Maximum Number of Display Pixels
Bias Method 1/3 Time Division 4 Common Signals Used COM0 to COM3 Maximum Number of Display Pixels 96 (24 segments x 4 commons)
Note The LCD panel of the figure
consists of 12 rows with 2 segments per row.
5.7.2 LCD controller/driver configuration The LCD controller/driver consists of the following hardware. Table 5-13. Configuration of LCD Controller/Driver
Item Display outputs Segment signals: 24 Common signals: 4 LCD display mode register 0 (LCDM0) LCD clock control register 0 (LCDC0) Port function register 8 (PF8) Configuration
Control registers
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PD789322,789324,789326,789327
The correspondence with the LCD display RAM is shown in Figure 5-24 below. Figure 5-24. Correspondence with LCD Display RAM Address 7 FA17H FA16H FA15H FA14H FA13H FA12H FA11H FA10H FA0FH FA0EH FA0DH FA0CH FA0BH FA0AH FA09H FA08H FA07H FA06H FA05H FA04H FA03H FA02H FA01H FA00H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Common COM3 Remark Bits 4 to 7 are fixed to 0. COM2 COM1 COM0 Bit 3 2 1 0 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 Segment
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Port function register 8 (PF8) 2 2
PF85 PF84 PF83 PF82 PF81 PF80
fX/2 fX/26 fX/27 fXT
Selector
5
fCLK fCLK 26
Prescaker fCLK 27 fCLK 28 fCLK 29 LCD clock fLCD selection circuit Timing controller LCDON0 3210 Selector LCDON0 3210 Selector LCDON0 3210 Selector LCDON0 3210 Selector
Segment driver
LCD drive voltage control circuit RLCD 1 VLC0 3 RLCD 2 VLC0 3 VLC0 RLCD
Common driver
VSS
COM0 COM1 COM2 COM3
S0
.......... S17/P85
....
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Figure 5-25. LCD Controller/Driver Block Diagram
Internal bus LCD clock control register 0 (LCDC0)
LCDC03 LCDC02 LCDC01 LCDC00
LCD display mode register 0 (LCDM0)
Display data memory FA00H 76543210 FA11H FA16H 76543210 . . . 76543210 FA17H 6543210
LCDON0 VAON0 LIPS0
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PD789322,789324,789326,789327
Segment driver
Segment driver
Segment driver
PF85 .....
PF80
..... S22/P80 S23
PD789322,789324,789326,789327
5.7.3 LCD controller/driver control registers The LCD controller/driver is controlled by the following three registers. * LCD display mode register 0 (LCDM0) * LCD clock control register 0 (LCDC0) * Port function register 8 (PF8) (1) LCD display mode register 0 (LCDM0) This register is used to enable/disable operation, and set the operation mode and the supply of power for LCD drive. LCDM0 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 5-26. Format of LCD Display Mode Register 0
Symbol <7> <6> VAON0 5 0 <4> LIPS0 3 0 2 0 1 0 0 0 Address FFB0H After reset 00H R/W R/W
LCDM0 LCDON0
LCDON0 0 1
LCD display enable/disable Display off (all segment outputs are unselected for signal output) Display on
VAON0 0 1
LCD controller/driver operation mode No internal booster (for 2.7- to 5.5-V display) Internal booster enabled (for 1.8- to 5.5-V display)
Note
LIPS0 0 1 Power not supplied for LCD drive Power supplied for LCD drive
Supply of power for LCD drive
Note
Note To reduce power consumption when the LCD display is not being used, set VAON0 and LIPS0 to 0. Cautions 1. Always set bits 0 to 3 and 5 to 0. 2. When manipulating VAON0, observe following procedure. A. When internal booster is stopped after changing to the display off condition from the display on condition 1) Set the display off condition by setting LCDON0 = 0. 2) Set all segment buffers and common buffers to output disabled by setting LIPS0 = 0. 3) Stop the booster by setting VAON0 = 0. B. When the booster is stopped in the display on condition This is prohibited. condition. C. When the display is turned on from the booster-stoped condition 1) Wait about 500 ms after starting the booster by setting VAON0 = 1. 2) Set all segment buffers and common buffers to signal output unselected by setting LIPS0 = 1. 3) Set the display on condition by setting LCDON0 = 1.
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Be sure to stop the booster after changing to the display off
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PD789322,789324,789326,789327
(2) LCD clock control register (LCDC0) This register is used to set the internal and LCD clocks. The frame frequency is determined by the number of LCD clock time divisions. LCDC0 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 5-27. Format of LCD Clock Control Register 0
Symbol LCDC0 7 0 6 0 5 0 4 0 3 LCDC03 2 LCDC02 1 LCDC01 0 LCDC00 Address FFB2H After reset 00H R/W R/W
LCDC03 0 0 1 1
LCDC02 0 1 0 1 fXT fX/2 fX/2 fX/2
5 6 7
Internal clock (fCLK) selection (32.768 kHz) (156.3 kHz) (78.1 kHz) (39.1 kHz)
Note
LCDC01 0 0 1 1
LCDC00 0 1 0 1 fCLK/2 fCLK/2 fCLK/2 fCLK/2
6 7 8 9
LCD clock (fLCD) selection
Note Select fX so that a clock of at least 32 kHz is set for the internal clock fCLK. Remarks 1. fX: Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency 3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz Caution Always set bits 4 to 7 to 0. Examples of the frame frequencies when the internal clock is fXT (32.768 kHz) are shown in Table 5-14 below. Table 5-14. Frame Frequency (Hz)
LCD Clock (fLCD) Time Division 4 fXT/2
9
fXT/2
8
fXT/2
7
fXT/2
6
(64 Hz) 16
(128 Hz) 32
(256 Hz) 64
(512 Hz) 128
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PD789322,789324,789326,789327
(3) Port function register 8 (PF8) This register is used to select whether S17/P85 to S22/P80 are used as LCD segment signal outputs or general-purpose ports. PF8 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 5-28. Format of Port Function Register 8
Symbol PF8 7 0 6 0 5 PF85 4 PF84 3 PF83 2 PF82 1 PF81 0 PF80 Address FF58H After reset 00H R/W R/W
PF8n 0 1 Operates as a general-purpose port
Port function of P8n (n = 0 to 5)
Operates as an LCD segment signal output
Preliminary Product Information U14673EJ1V0PM00
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PD789322,789324,789326,789327
6. INTERRUPT FUNCTION 6.1 Interrupt Types
Two types of interrupts are supported. (1) Non-maskable interrupts Non-maskable interrupt requests are acknowledged unconditionally, i.e. even when interrupts are disabled. These interrupts take precedence over all other interrupts and are not subject to interrupt priority control. A non-maskable interrupt causes the generation of the standby release signal. An interrupt from the watchdog timer is the only non-maskable interrupt source supported in the PD789322, 789324, 789326, and 789327. (2) Maskable interrupts Maskable interrupts are subject to mask control. If two or more maskable interrupts occur simultaneously, the default priority listed in Table 6-1 applies. A maskable interrupt causes the generation of the standby release signal. Maskable interrupts from 2 external and 6 internal sources are supported in the PD789322, 789324, 789326, and 789327.
6.2 Interrupt Sources and Configuration
The PD789322, 789324, 789326, and 789327 support a total of 9 maskable and non-maskable interrupt sources (see Table 6-1).
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Table 6-1. Interrupt Sources
Interrupt Type Default Note 1 Priority - Interrupt Source Name INTWDT Trigger Watchdog timer overflow (with watchdog timer mode 1 selected) Watchdog timer overflow (with interval timer mode selected) Pin input edge detection End of serial interface 10 3-wire SIO transfer reception Watch timer interrupt Generation of 8-bit timer 30 matching signal Generation of 8-bit timer 40 matching signal Key return signal detection Watch timer interval timer interrupt External Internal External Internal 0006H 0008H Internal/ External Vector Table Address Basic Configuration Note 2 Type (A)
Non-maskable
Internal
0004H
Maskable
0
INTWDT
(B)
1 2
INTP0 INTCSI10
(C) (B)
3 4
INTWT INTTM30
000AH 000CH
5
INTTM40
000EH
6 7
INTKR00 INTWTI
0010H 0012H
(C) (B)
Notes 1. Default priority is the priority order when more than one maskable interrupt request is generated at the same time. 0 is the highest priority and 7 is the lowest. 2. Basic configuration types (A), (B), and (C) correspond to (A), (B), and (C) in Figure 6-1. Remark Only one of the two watchdog timer interrupt sources, non-maskable or maskable (internal), can be selected.
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PD789322,789324,789326,789327
Figure 6-1. Basic Configuration of Interrupt Function (A) Internal non-maskable interrupt
Internal bus
Interrupt request
Vector table address generator
Standby release signal
(B) Internal maskable interrupt
Internal bus
MK
IE
Interrupt request
IF
Vector table address generator
Standby release signal
(C) External maskable interrupt
Internal bus
INTM0, KRM00
MK
IE
Interrupt request
Edge detection circuit
IF
Vector table address generator
Standby release signal
INTM0: External interrupt mode register 0 KRM00: Key return mode register 00 IF: IE: MK: Interrupt request flag Interrupt enable flag Interrupt mask flag
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PD789322,789324,789326,789327
6.3 Interrupt Function Control Registers
Interrupts are controlled by the following five registers. * Interrupt request flag register 0 (IF0) * Interrupt mask flag register 0 (MK0) * External interrupt mode register 0 (INTM0) * Program status word (PSW) * Key return mode register 00 (KRM00) Table 6-2 lists the interrupt requests and the corresponding interrupt request and interrupt mask flags. Table 6-2. Interrupt Request Signals and Corresponding Flags
Interrupt Request Signal INTWDT INTP0 INTCSI0 INTWT INTTM30 INTTM40 INTKR00 INTWTI WDTIF PIF0 CSIIF0 WTIF TMIF30 TMIF40 KRIF00 WTIIF Interrupt Request Flag WDTMK PMK0 CSIMK0 WTMK TMMK30 TMMK40 KRMK00 WTIMK Interrupt Mask Flag
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PD789322,789324,789326,789327
(1) Interrupt request flag register 0 (IF0) An interrupt request flag is set (1) when the corresponding interrupt request is generated, or when an instruction is executed. It is cleared (0) when the interrupt request is acknowledged, when the RESET signal is input, or when an instruction is executed. IF0 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 6-2. Format of Interrupt Request Flag Register 0
Symbol IF0 <7> WTIIF <6> KRIF00 <5> TMIF40 <4> TMIF30 <3> WTIF <2> CSIIF0 <1> PIF0 <0> WDTIF Address FFE0H After reset 00H R/W R/W
xxIFx 0 1 No interrupt request signal generated
Interrupt request flag
An interrupt request signal is generated and an interrupt request made
Cautions 1. The WDTIF flag can be read/written only when the watchdog timer is being used as an interval timer. It must be cleared to 0 if the watchdog timer is used in watchdog timer mode 1 or 2. 2. Because P61 functions alternately as an external interrupt, when the output level changes after the output mode of the port function is specified, the interrupt request flag will be inadvertently set. Therefore, be sure to preset the interrupt mask flag (PMK0) before using the port in output mode.
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(2) Interrupt mask flag register 0 (MK0) Interrupt mask flags are used to enable and disable the corresponding maskable interrupts. MK0 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to FFH. Figure 6-3. Format of Interrupt Mask Flag Register 0
Symbol MK0 <7> WTIMK <6> <5> <4> <3> WTMK <2> CSIMK0 <1> PMK0 <0> WDTMK Address FFE4H After reset FFH R/W R/W
KRMK00 TMMK40 TMMK30
xxMK 0 1 Interrupt servicing enabled Interrupt servicing disabled
Interrupt servicing control
Cautions 1. When the watchdog timer is being used in watchdog timer mode 1 or 2, any attempt to read the WDTMK flag results in an undefined value being detected. 2. Because P61 functions alternately as an external interrupt, when the output level changes after the output mode of the port function is specified, the interrupt request flag will be inadvertently set. Therefore, be sure to preset the interrupt mask flag (PMK0) before using the port in output mode.
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PD789322,789324,789326,789327
(3) External interrupt mode register 0 (INTM0) This register is used to specify the valid edge for INTP0. INTM0 is set using an 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 6-4. Format of External Interrupt Mode Register 0
Symbol INTM0 7 0 6 0 5 0 4 0 3 ES01 2 ES00 1 0 0 0 Address FFECH After reset 00H R/W R/W
ES01 0 0 1 1
ES00 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges
INTP0 valid edge selection
Cautions 1. Always set bits 0, 1, and 4 to 7 to 0. 2. Before setting INTM0, set (1) the interrupt mask flag (PMK0) to disable interrupts. To enable interrupts, clear (0) the interrupt request flag (PIF0), then clear (0) the interrupt mask flag (PMK0).
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(4) Program status word (PSW) The program status word is used to hold the instruction execution results and the current status of the interrupt requests. The IE flag, used to enable and disable maskable interrupts, is mapped to the PSW. The PSW can be read and written in 8-bit units, as well as in 1-bit units by using bit manipulation instructions and dedicated instructions (EI and DI). When a vector interrupt is acknowledged, the PSW is automatically saved to the stack, and the IE flag is reset (0). RESET input sets the PSW to 02H. Figure 6-5. Program Status Word Configuration
Symbol PSW 7 IE 6 Z 5 0 4 AC 3 0 2 0 1 1 0 CY After reset 02H
Used in the execution of ordinary instructions IE 0 1 Disabled Enabled Interrupt acknowledgement enable/disable
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PD789322,789324,789326,789327
(5) Key return mode register 00 (KRM00) This register is used to set the pin that is to detect the key return signal (rising edge of port 4). KRM00 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 6-6. Format of Key Return Mode Register 00
Symbol KRM00 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 KRM000 Address FFF5H After reset 00H R/W R/W
KRM000 0 1 Key return signal not detected
Key return signal detection control
Key return signal detected (port 4 falling edge detection)
Cautions 1. Always set bits 1 to 7 to 0. 2. Before setting KRM00, set (1) bit 6 (KRMK00) of MK0 to disable interrupts. To enable interrupts, clear (0) KRMK00 after clearing (0) bit 6 (KRIF00) of IF0. 3. On-chip pull-up resistors are automatically connected in input mode to the pins specified for key return signal detection (P40 to P43). Although these resistors are disconnected when the mode changes to output, key return signal detection continues unchanged. Figure 6-7. Block Diagram of Falling Edge Detection Circuit
Key return mode register 00 (KRM00)
Note
Selector
P40/KR00 P41/KR01 P42/KR02 P43/KR03
Falling edge detection circuit
KRIF00 setting signal
Standby release signal KRMK00
Note For selecting the pin to be used as falling edge input.
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7. STANDBY FUNCTION 7.1 Standby Function
A standby function is incorporated to minimize the system's power consumption. There are two standby modes: HALT and STOP. The HALT and STOP modes are selected using the HALT and STOP instructions. (1) HALT mode In this mode, the CPU operating clock is stopped. The average current consumption can be reduced by intermittent operation combining this mode with the normal operation mode. (2) STOP mode In this mode, main system clock oscillation is stopped. All operations performed with the main system clock are suspended, thus minimizing power consumption. Caution When shifting to STOP mode, execute the STOP instruction after first stopping the operation of the hardware.
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PD789322,789324,789326,789327
Table 7-1. Operation Statuses in HALT Mode
Item HALT Mode Operation Status During Main System Clock Operation Subsystem Clock Operating Main system clock CPU Ports (output latches) 8-bit timer 30, 40 Watch timer Watchdog timer Power-on-clear circuit Key return circuit Serial interface 10 LCD controller/driver External interrupts Can be oscillated Operation stopped Status before HALT mode setting retained Operable Operable Operable Operable Operable Operable Operable Operable
Note 4 Note 5
HALT Mode Operation Status During Subsystem Clock Operation Main System Clock Operating Main System Clock Stopped Oscillation stopped
Subsystem Clock Stopped
Operation stopped Operable
Note 1
Operable Operation stopped
Operable
Note 2
Operable Operable
Notes 1, 4
Note 3 Notes 2, 4
Operable
Note 4
Operable
Notes 1. Operation is enabled when the main system clock is selected 2. Operation is enabled when the subsystem clock is selected 3. Operation is enabled only when an external clock is selected 4. The HALT instruction can be set after display instruction execution 5. Operation is enabled only for a maskable interrupt that is not masked Table 7-2. Operation Statuses in STOP Mode
Item STOP Mode Operation Status During Main System Clock Operation Subsystem Clock Operating Main system clock CPU Ports (output latches) 8-bit timer 30, 40 Watch timer Watchdog timer Power-on-clear circuit Key return circuit Serial interface 10 LCD controller/driver External interrupts Oscillation stopped Operation stopped Status before STOP mode setting retained Operation stopped Operable
Note 1
Subsystem Clock Stopped
Operation stopped
Operation stopped Operable Operable Operable Operable Operable
Note 2 Note 1 Note 3
Operation stopped
Notes 1. Operation is enabled when the subsystem clock is selected. 2. Operation is enabled only when an external clock is selected. 3. Operation is enabled only for a maskable interrupt that is not masked
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7.2 Standby Function Control Register
The oscillation stabilization time selection register (OSTS) is used to control the wait time from the time STOP mode is released by an interrupt request until oscillation stabilizes. OSTS is set using an 8-bit memory manipulation instruction. RESET input sets this register to 04H. Note that the time required for oscillation to stabilize after RESET input or the release of STOP mode by POC will be taken as the time selected by mask option (215/fX, or 217/fX) (refer to 9. MASK OPTION for mask option details) . Figure 7-1. Format of Oscillation Stabilization Time Selection Register
Symbol OSTS 7 0 6 0 5 0 4 0 3 0 2 OSTS2 1 OSTS1 0 OSTS0 Address FFFAH After reset 04H R/W R/W
OSTS2 0 0 1
OSTS1 0 1 0
OSTS0 0 0 0 2 /fX (819 s) 2 /fX (6.55 ms) 2 /fX (26.2 ms) Setting prohibited
17 15 12
Oscillation stabilization time selection
Other than above
Caution
The wait time required after releasing STOP mode does not include the time ("a" in the following figure) required for the clock oscillation to restart after STOP mode is released, regardless of whether STOP mode is released by RESET input or interrupt.
STOP mode release X1 pin voltage waveform a VSS
Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz.
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PD789322,789324,789326,789327
8. RESET FUNCTION 8.1 Reset Function
The PD789322, 789324, 789326, and 789327 can be reset using the following three signals. (1) External reset signal input via RESET pin (2) Internal reset by watchdog timer runaway time detection (3) Internal reset using power-on-clear circuit (POC) The external and internal reset signals are functionally equivalent. When RESET is input, program execution begins from the addresses written at addresses 0000H and 0001H. If a low-level signal is applied to the RESET pin, or if the watchdog timer overflows, a reset occurs, causing each item of the hardware to enter the states listed in Table 8-1. While a reset is being applied, or while the oscillation frequency is stabilizing immediately after the end of a reset sequence, each pin remains in the high-impedance state. If a high-level signal is applied to the RESET pin, the reset sequence is terminated, and program execution begins once the oscillation stabilization time has elapsed. A reset sequence caused by a watchdog timer overflow is terminated automatically and again program execution begins upon the elapse of the oscillation stabilization time. Reset by power-ON clear is cleared if the supply voltage rises beyond a specific level, and the program execution is started after the oscillation stabilization time has elapsed. Cautions 1. To use an external reset sequence, input a low-level signal to the RESET pin for at least 10
s.
2. When a reset is used to release STOP mode, the data of when STOP mode was entered is retained during the reset sequence, except for the port pins, which are in the high-impedance state. 3. The oscillation stabilization time after RESET input or the release of STOP mode by POC can be selected from 2 /fX or 2 /fX by mask option (refer to 9. MASK OPTION). Figure 8-1. Reset Function Block Diagram
15 17
Power-on-clear circuit
VDD
RESET
Reset control circuit
Reset signal
Count clock
Watchdog timer Stop
Overflow
Interrupt function
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Preliminary Product Information U14673EJ1V0PM00
PD789322,789324,789326,789327
Table 8-1. Status of Hardware After Reset
Hardware Program counter (PC)
Note 1
Status After Reset Contents of reset vector table (0000H, 0001H) set Undefined 02H Undefined Undefined 00H FFH 00H 00H 02H 00H 00H 04H 00H Undefined 00H 00H 00H 00H 00H Undefined 00H 00H 00H 00H FFH 00H 00H
Note 3 Note 2 Note 2
Stack pointer (SP) Program status word (PSW) RAM Data memory General-purpose registers Ports (P0 to P2, P4, P6, P8) (output latches) Port mode registers (PM0 to PM2, PM4, PM6, PM8) Port function register 8 (PF8) Pull-up resistor option registers (PU0, PUB2) Processor clock control register (PCC) Subclock oscillation mode register (SCKM) Subclock control register (CSS) Oscillation stabilization time selection register (OSTS) 8-bit timer 30, 40 Timer counters (TM30, TM40) Compare registers (CR30, CR40, CRH40) Mode control registers (TMC30, TMC40) Carrier generator output control register (TCA40) Watch timer Watchdog timer Serial interface 10 Mode control register (WTM) Mode register (WDTM) Serial operation mode register 10 (CSIM10) Transmission/reception shift register 10 (SIO10) LCD controller/driver Display mode register 0 (LCDM0) Clock control register 0 (LCDC0) Power-on-clear circuit Interrupts Power-on-clear register 1 (POCF1) Request flag register 0 (IF0) Mask flag register 0 (MK0) External interrupt mode register 0 (INTM0) Key return mode register 00 (KRM00)
Notes 1. While a reset signal is being input, and during the oscillation stabilization period, only the contents of the PC will be undefined; the remainder of the hardware will be the same state as after reset. 2. In standby mode, RAM enters the hold state after reset. 3. The value is 04H only after a power-on-clear reset.
Preliminary Product Information U14673EJ1V0PM00
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PD789322,789324,789326,789327
8.2 Power Failure Detection Function
When a reset is generated via the power-on-clear circuit, bit 2 (POCOF1) of the power-on-clear register (POCF1) is set (1). This bit is then cleared (0) by an instruction written to POCF1. After a power-on-clear reset (i.e. after program execution has started from address 0000H), a power failure can be detected by detecting POCOF1. Figure 8-2. Format of Power-on-Clear Register 1
Symbol POCF1 7 0 6 0 5 0 4 0 3 0 2 POCOF1 1 0 0 0 Address FFDDH After reset 00H
Note
R/W R/W
POCOF1 0 1
Power-on-clear generation status detection Power-on-clear not generated, or cleared by write operation Power-on-clear reset generated
Note The value is 04H only after a power-on-clear reset.
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Preliminary Product Information U14673EJ1V0PM00
PD789322,789324,789326,789327
9. MASK OPTION
The PD789322, 789324, 789326, and 789327 have the following mask option. * Oscillation stabilization wait time The oscillation stabilization wait time after the release of STOP mode by RESET or POC can be selected. <1> 215/fX <2> 217/fX
Preliminary Product Information U14673EJ1V0PM00
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PD789322,789324,789326,789327
10. INSTRUCTION SET OVERVIEW
The instruction set for the PD789322, 789324, 789326, and 789327 are listed in this section.
10.1 Conventions
10.1.1 Operand formats and descriptions The description made in the operand field of each instruction conforms to the operand format for the instructions listed below (the details conform to the assembly specification). If more than one operand format is listed for an instruction, one is selected. Uppercase letters, #, !, $, and brackets [ ] are used to specify keywords, which must be written exactly as they appear. The meanings of these special characters are as follows: * #: Immediate data specification * $: Relative address specification * !: Absolute address specification * [ ]: Indirect address specification Immediate data should be described using appropriate values or labels. The specification of values and labels must be accompanied by #, !, $, or [ ]. Operand registers, expressed as r or rp in the formats, can be described using both functional names (X, A, C, etc.) and absolute names (R0, R1, R2, and other names listed in Table 5-1 below). Table 10-1. Operand Formats and Descriptions
Format r rp sfr saddr saddrp addr16 addr5 word byte bit Description X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special function register symbol FE20H to FF1FH FE20H to FF1FH Immediate data or label Immediate data or label (even addresses only)
0000H to FFFFH Immediate data or label (only even addresses for 16-bit data transfer instructions) 0040H to 007FH Immediate data or label (even addresses only) 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label
Remark For details concerning special function register symbols, refer to Table 4-1 Registers.
Special Function
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Preliminary Product Information U14673EJ1V0PM00
PD789322,789324,789326,789327
10.1.2 Operation field definitions A: X: B: C: D: E: H: L: AX: BC: DE: HL: PC: SP: PSW: CY: AC: Z: IE: NMIS: (): XH, XL: : : : : jdisp8: A register (8-bit accumulator) X register B register C register D register E register H register L register AX register pair (16-bit accumulator) BC register pair DE register pair HL register pair Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Interrupt request enable flag Flag to indicate that a non-maskable interrupt is being processed Contents of a memory location indicated by a parenthesized address or register name Higher and lower 8 bits of a 16-bit register Logical product (AND) Logical sum (OR) Exclusive OR Inverted data Signed 8-bit data (displacement value)
addr16: 16-bit immediate data or label
10.1.3 Flag operation field definitions (Blank): No change 0: 1: x: R: Clear to 0 Set to 1 Set or clear according to the result Restore to the previous value
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PD789322,789324,789326,789327
10.2 Operations
Mnemonic Operand Byte Clock r byte (saddr) byte sfr byte Ar rA A (saddr) (saddr) A A sfr sfr A A (addr16) (addr16) A PSW byte A PSW PSW A A (DE) (DE) A A (HL) (HL) A A (HL + byte) (HL + byte) A AX Ar A (saddr) A (sfr) A (DE) A (HL) A (HL + byte) rp word AX (saddrp) (saddrp) AX AX rp rp AX AX rp x x x x x x Operation Flag Z AC CY MOV r, #byte saddr , #byte sfr, #byte A, r r, A A, saddr saddr, A A, sfr sfr, A A, !addr16 !addr16, A PSW, #byte A, PSW PSW, A A, [DE] [DE], A A, [HL] [HL], A A, [HL + byte] [HL + byte], A XCH A, X A, r A, saddr A, sfr A, [DE] A, [HL] A, [HL + byte] MOVW rp, #word AX, saddrp saddrp, AX AX, rp rp, AX XCHW AX, rp
Note 3 Note 3 Note 3 Note 2 Note 1 Note 1
3 3 3 2 2 2 2 2 2 3 3 3 2 2 1 1 1 1 2 2 1 2 2 2 1 1 2 3 2 2 1 1 1
6 6 6 4 4 4 4 4 4 8 8 6 4 4 6 6 6 6 6 6 4 6 6 6 8 8 8 6 6 8 4 4 8
Notes 1. Except when r = A. 2. Except when r = A or X. 3. Only when rp = BC, DE, or HL. Remark The instruction clock cycle is based on the CPU clock (fCPU) specified by the processor clock control register (PCC).
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Preliminary Product Information U14673EJ1V0PM00
PD789322,789324,789326,789327
Mnemonic
Operand
Byte
Clock A, CY A + byte
Operation x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
Flag Z AC CY x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
ADD
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte]
2 3 2 2 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 1 2
4 6 4 4 8 6 6 4 6 4 4 8 6 6 4 6 4 4 8 6 6 4 6 4 4 8 6 6 4 6 4 4 8 6 6
(saddr), CY (saddr) + byte A, CY A + r A, CY A + (saddr) A, CY A + (addr16) A, CY A + (HL) A, CY A + (HL + byte) A, CY A + byte + CY (saddr), CY (saddr) + byte + CY A, CY A + r + CY A, CY A + (saddr) + CY A, CY A + (addr16) + CY A, CY A + (HL) + CY A, CY A + (HL + byte) + CY A, CY A - byte (saddr), CY (saddr) - byte A, CY A - r A, CY A - (saddr) A, CY A - (addr16) A, CY A - (HL) A, CY A - (HL + byte) A, CY A - byte - CY (saddr), CY (saddr) - byte - CY A, CY A - r - CY A, CY A - (saddr) - CY A, CY A - (addr16) - CY A, CY A - (HL) - CY A, CY A - (HL + byte) - CY A A byte (saddr) (saddr) byte AAr A A (saddr) A A (addr16) A A (HL) A A (HL + byte)
ADDC
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte]
SUB
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte]
SUBC
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte]
AND
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte]
Remark The instruction clock cycle is based on the CPU clock (fCPU) specified by the processor clock control register (PCC).
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PD789322,789324,789326,789327
Mnemonic
Operand
Byte
Clock A A byte
Operation x x x x x x x x x x x x x x x x x x x x x x x x x x x x
Flag Z AC CY
OR
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte]
2 3 2 2 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 1 2 3 3 3 2 2 2 2 1 1 1 1 1 1
4 6 4 4 8 6 6 4 6 4 4 8 6 6 4 6 4 4 8 6 6 6 6 6 4 4 4 4 4 4 2 2 2 2
(saddr) (saddr) byte AAr A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A A byte (saddr) (saddr) byte AAr A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A - byte (saddr) - byte A-r A - (saddr) A - (addr16) A - (HL) A - (HL + byte) AX, CY AX + word AX, CY AX - word AX - word rr+1 (saddr) (saddr) + 1 rr-1 (saddr) (saddr) - 1 rp rp + 1 rp rp - 1 (CY, A7 A0, Am-1 Am) x 1 (CY, A0 A7, Am+1 Am) x 1 (CY A0, A7 CY, Am-1 Am) x 1 (CY A7, A0 CY, Am+1 Am) x 1
XOR
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte]
CMP
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte]
x x x x x x x x x x x x x x
x x x x x x x x x x
ADDW SUBW CMPW INC
AX, #word AX, #word AX, #word r saddr
DEC
r saddr
INCW DECW ROR ROL RORC ROLC
rp rp A, 1 A, 1 A, 1 A, 1
x x x x
Remark The instruction clock cycle is based on the CPU clock (fCPU) specified by the processor clock control register (PCC).
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Preliminary Product Information U14673EJ1V0PM00
PD789322,789324,789326,789327
Mnemonic
Operand
Byte
Clock (saddr.bit) 1 sfr.bit 1 A.bit 1 PSW bit 1 (HL).bit 1 (saddr.bit) 0 sfr.bit 0 A.bit 0 PSW.bit 0 (HL).bit 0 CY 1 CY 0 CY CY
Operation
Flag Z AC CY
SET1
saddr.bit sfr.bit A.bit PSW.bit [HL].bit
3 3 2 3 2 3 3 2 3 2 1 1 1 3 1
6 6 4 6 10 6 6 4 6 10 2 2 2 6 8
x
x
x
CLR1
saddr.bit sfr.bit A.bit PSW.bit [HL].bit
x
x
x
SET1 CLR1 NOT1 CALL CALLT
CY CY CY !addr16 [addr5]
1 0 x
(SP - 1) (PC + 3)H, (SP - 2) (PC + 3)L, PC addr16, SP SP - 2 (SP - 1) (PC + 1)H, (SP - 2) (PC + 1)L, PCH (00000000, addr5 + 1), PCL (00000000, addr5), SP SP - 2 PCH (SP + 1), PCL (SP), SP SP + 2 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3, NMIS 0 (SP - 1) PSW, SP SP - 1 (SP - 1) rpH, (SP - 2) rpL, SP SP - 2 PSW (SP), SP SP + 1 rpH (SP + 1), rpL (SP), SP SP + 2 SP AX AX SP PC addr16 PC PC + 2 + jdisp8 PCH A, PCL X RRR RRR
RET RETI
1 1
6 8
PUSH
PSW rp
1 1 1 1 2 2 3 2 1
2 4 4 6 8 6 6 6 6
POP
PSW rp
MOVW
SP, AX AX, SP
BR
!addr16 $addr16 AX
Remark The instruction clock cycle is based on the CPU clock (fCPU) specified by the processor clock control register (PCC).
Preliminary Product Information U14673EJ1V0PM00
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PD789322,789324,789326,789327
Mnemonic
Operand
Byte
Clock
Operation PC PC + 2 + jdisp8 if CY = 1 PC PC + 2 + jdisp8 if CY = 0 PC PC + 2 + jdisp8 if Z = 1 PC PC + 2 + jdisp8 if Z = 0 PC PC + 4 + jdisp8 if (saddr.bit) = 1 PC PC + 4 + jdisp8 if sfr.bit = 1 PC PC + 3 + jdisp8 if A.bit = 1 PC PC + 4 + jdisp8 if PSW.bit = 1 PC PC + 4 + jdisp8 if (saddr.bit) = 0 PC PC + 4 + jdisp8 if sfr.bit = 0 PC PC + 3 + jdisp8 if A.bit = 0 PC PC + 4 + disp8 if PSW.bit = 0 B B - 1, then PC PC + 2 + jdisp8 if B 0 C C - 1, then PC PC + 2 + jdisp8 if C 0 (saddr) (saddr) - 1, then PC PC + 3 + jdisp8 if (saddr) 0 No Operation IE 1 (Enable Interrupt) IE 0 (Disable Interrupt) Set HALT Mode Set STOP Mode
Flag Z AC CY
BC BNC BZ BNZ BT
$addr16 $addr16 $addr16 $addr16 saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16
2 2 2 2 4 4 3 4 4 4 3 4 2 2 3 1 3 3 1 1
6 6 6 6 10 10 8 10 10 10 8 10 6 6 8 2 6 6 2 2
BF
saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16
DBNZ
B, $addr16 C, $addr16 saddr, $addr16
NOP EI DI HALT STOP
Remark The instruction clock cycle is based on the CPU clock (fCPU) specified by the processor clock control register (PCC).
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Preliminary Product Information U14673EJ1V0PM00
PD789322,789324,789326,789327
11. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage Symbol VDD VLC0 Input voltage Output voltage VI VO1 P00 to P03, P10, P11, P20 to P22, P40 to P43, P60, P61 COM0 to COM3, S0 to S16, P80/S22 to P85/S17, S23 Pin P60/TO40 Per pin (except P60/TO40) Total for all pins (except P60/TO40) Output current, low IOL Per pin Total for all pins Operating ambient temperature Storage temperature TA Tstg Conditions Ratings -0.3 to +6.5 -0.3 to +6.5 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to VLC0 + 0.3 -30 -10 -30 30 80 -40 to +85 -65 to +150
Note Note
Unit V V V V
VO2
Note
V
Output current, high
IOH
mA mA mA mA mA C C
Note 6.5 V or lower Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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PD789322,789324,789326,789327
Main System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Resonator Ceramic resonator Recommended Circuit
VDD X2 X1
Parameter Oscillation frequency Note 1 (fX)
Conditions
MIN. 1.0
TYP.
MAX. 5.0
Unit MHz
C2
C1
Oscillation After VDD has reached the MIN. Note 2 stabilization time oscillation voltage range Oscillation frequency Note 1 (fX) Oscillation Note 2 stabilization time
X1
4
ms
Crystal resonator
IC
X2
X1
1.0
5.0
MHz
C2
C1
30
ms
External clock
X2
X1 input frequency Note 1 (fX) X1 input high-/lowlevel width (tXH, tXL)
1.0
5.0
MHz
85
500
ns
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
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Preliminary Product Information U14673EJ1V0PM00
PD789322,789324,789326,789327
Subsystem Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Resonator Crystal resonator Recommended Circuit
IC XT1 XT2 R C3 C4
Parameter Oscillation frequency Note 1 (fXT)
Conditions
MIN. 32
TYP. 32.768
MAX. 35
Unit kHz
Oscillation VDD = 4.5 to 5.5 V Note 2 stabilization time XT1 input frequency Note 1 (fXT) XT1 input high-/lowlevel width (tXTH, tXTL) 32
1.2
2 10 35
s
External clock
XT1
XT2
kHz
14.3
15.6
s
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. The time required for oscillation to stabilize after VDD reaches the MIN. oscillation voltage range. Use a resonator to stabilize oscillation during the oscillation wait time. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
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PD789322,789324,789326,789327
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (1/2)
Parameter Output current, low Symbol IOL Per pin Total for all pins Output current, high IOH Per pin (except P60/TO40) P60/TO40 VDD = 3.0 V, VOH = 1.0 V -7 -15 Conditions MIN. TYP. MAX. 10 80 -1 -24 -15 0.7 VDD 0.9 VDD VDD = 2.7 to 5.5 V 0.8 VDD 0.9 VDD VDD - 0.1 VDD - 0.1 VDD = 2.7 to 5.5 V 0 0 VDD = 2.7 to 5.5 V 0 0 0 0 1.8 VDD 5.5 V, IOH = -100 A 1.8 VDD 5.5 V, IOH = -500 A 1.8 VDD 5.5 V, IOH = -400 A 1.8 VDD 5.5 V, IOH = -2 mA P80/S22 to P85/S17 1.8 VDD 5.5 V, IOH = -100 A 1.8 VDD 5.5 V, IOH = -500 A P00 to P03, P10, P11, P20 to P22, P40 to P43, P60, P61 1.8 VDD 5.5 V, IOL = 400 A 1.8 VDD 5.5 V, IOL = 2 mA 1.8 VLC0 5.5 V, IOL = 400 A 1.8 VLC0 5.5 V, IOL = 2 mA VDD - 0.5 VDD - 0.7 VDD - 0.5 VDD - 0.7 VLC0 - 0.5 VLC0 - 0.7 VDD VDD VDD VDD VDD VDD 0.3 VDD 0.1 VDD 0.2 VDD 0.1 VDD 0.1 0.1 Unit mA mA mA mA mA V V V V V V V V V V V V V
Total for all pins (except P60/TO40) Input voltage, high VIH1 P00 to P03, P10, P11, P21, P22, P60 RESET, P20, P40 to P43, P61 X1, X2 XT1, XT2 P00 to P03, P10, P11, P21, P22, P60 RESET, P20, P40 to P43, P61 X1, X2 XT1, XT2 P00 to P03, P10, P11, P20 to P22, P40 to P43, P61 VDD = 2.7 to 5.5 V
VIH2
VIH3 VIH4 Input voltage, low VIL1
VIL2
VIL3 VIL4 Output voltage, high VOH11
VOH12
V
VOH21
P60/TO40
V
VOH22
V
VOH31
V
VOH32
V
Output voltage, low
VOL11
0.5
V
VOL12
0.7
V
VOL21
P80/S22 to P85/S17
0.5
V
VOL22
0.7
V
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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Preliminary Product Information U14673EJ1V0PM00
PD789322,789324,789326,789327
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (2/2)
Parameter Input leakage current, high Symbol ILIH1 VIN = VDD Conditions P00 to P03, P10, P11, P20 to P22, P40 to P43, P60, P61, RESET X1, X2, XT1, XT2 VIN = 0 V P00 to P03, P10, P11, P20 to P22, P40 to P43, P60, P61, RESET X1, X2, XT1, XT2 VOUT = VDD MIN. TYP. MAX. 3 Unit
A
ILIH2 Input leakage current, low ILIL1
20 -3
A A
ILIL2 Output leakage current, high Output leakage current, low Software pull-up resistors
Note 1
-20 3 -3
A A A
k
ILOH
ILOL
VOUT = 0 V
R1
VIN = 0 V
P00 to P03, P10, P11, P20 to P22, P40 to P43 VDD = 5.5 V VDD = 3.3 V VDD = 5.5 V VDD = 3.3 V
Note 2 Note 3
50
100
200
Supply current
IDD1
Ceramic/crystal oscillation IDD2
5.0-MHz crystal oscillation operating mode 5.0-MHz crystal oscillation HALT mode
2.0 0.6 1.1 0.4 25 5 1 1
4.0 1.2 2.2 0.8 55 25 10 5
mA mA mA mA
IDD3
32.768-kHz crystal VDD = 5.5 V Note 4 oscillation HALT mode VDD = 3.3 V STOP mode VDD = 5.5 V VDD = 3.3 V
A A A A
IDD4
Notes 1. Current flowing through ports (including current flowing through on-chip pull-up resistors) is not included. 2. High-speed operation (when the processor clock control register (PCC) is set to 00H). 3. Low-speed operation (when PCC is set to 02H) 4. When the main system clock is stopped. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
Preliminary Product Information U14673EJ1V0PM00
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PD789322,789324,789326,789327
AC Characteristics
(1) Basic operation (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Cycle time (Min. instruction execution time) Interrupt input high-/low-level width Key return pin low-level width RESET low-level width Symbol TCY Conditions VDD = 2.7 to 5.5 V MIN. 0.4 1.6 tINTH, tINTL tKRIL INT 10 TYP. MAX. 8.0 8.0 Unit
s s s s s
KR00 to KR03
10
tRSL
10
TCY vs. VDD (Main System Clock)
60
20 10
Cycle time TCY [ s]
2.0 1.0 0.5 0.4
Guaranteed operation range
0.1 1 2 3 4 5 6 Supply voltage VDD (V)
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(2) Serial interface 10 (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (a) 3-wire serial I/O mode (Internal clock output)
Parameter SCK10 cycle time Symbol tKCY1 VDD = 2.7 to 5.5 V Conditions MIN. 800 3,200 SCK10 high-/low-level width SI10 setup time (to SCK10 ) SI10 hold time (from SCK10 ) SO10 output delay time from SCK10 tKH1, tKL1 tSIK1 VDD = 2.7 to 5.5 V tKCY1/2 - 50 tKCY1/2 - 150 VDD = 2.7 to 5.5 V 150 500 tKSI1 VDD = 2.7 to 5.5 V 400 800 tKSO1 R = 1 k, C = 100 pF
Note
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns
VDD = 2.7 to 5.5 V
0 250
250 1,000
ns ns
Note R and C are the load resistance and load capacitance of the SO10 output line. (b) 3-wire serial I/O mode (External clock input)
Parameter SCK10 cycle time Symbol tKCY2 VDD = 2.7 to 5.5 V Conditions MIN. 900 3,500 SCK10 high-/low-level width SI10 setup time (to SCK10 ) SI10 hold time (from SCK10 ) SO10 output delay time from SCK10 tKH2, tKL2 tSIK2 VDD = 2.7 to 5.5 V 400 1,600 VDD = 2.7 to 5.5 V 100 150 tKSI2 VDD = 2.7 to 5.5 V 400 600 tKSO2 R = 1 k, C = 100 pF
Note
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns
VDD = 2.7 to 5.5 V
0 250
300 1,000
ns ns
Note R and C are the load resistance and load capacitance of the SO10 output line.
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AC Timing Measurement Point (excluding X1, XT1 input)
0.8 VDD 0.2 VDD 0.8 VDD 0.2 VDD
Test points
Clock Timing
1/fX tXL tXH VIH3 (MIN.) VIL3 (MAX.)
X1 input
1/fXT tXTL tXTH VIH4 (MIN.) VIL4 (MAX.)
XT1 input
Interrupt Input Timing
tINTL tINTH
INT
Key Return Input Timing
tKRIL
KR00 to KR03
RESET Input Timing
tRSL
RESET
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PD789322,789324,789326,789327
Serial Transfer Timing 3-wire serial I/O mode:
tKCYn tKLn tKHn
SCK10
tSIKn SI10
tKSIn
Input data
tKSOn
SO10
Output data
Remark n = 1, 2
Preliminary Product Information U14673EJ1V0PM00
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LCD Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter LCD drive voltage Symbol VLC0 VAON0 VAON0 LCD division resistance LCD output voltage differential (common) LCD output voltage differential (segment)
Note 2 Note 2 Note 1 Note 1
Conditions =1 =0
MIN. 1.8 2.7 50
TYP.
MAX. 5.5 5.5
Unit V V k V
RLCD VODC IO = 5 A IO = 1 A 1/3 bias
100
200 0.2 0.2
0
VODS
1/3 bias
0
V
Notes 1. Bit 6 of LCD display mode register 0 (LCDM0) 2. The voltage differential is the difference between the output voltage and the ideal value of the segment and common signal outputs.
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Data retention supply voltage Low voltage detection (POC) voltage Power supply rise time Release signal set time Oscillation stabilization wait time
Note 2
Symbol VDDDR VPOC tPth tSREL tWAIT
Conditions
MIN. 1.8
TYP.
MAX. 3.6
Unit V V ms
Response time: 2 ms VDD: 0 V 1.8 V
Note 1
1.8 0.01 10
1.9
2.0 100
STOP cancelled by RESET Cancelled by RESET Cancelled by interrupt request
s
Note 3 Note 4 s s
Notes 1. The response time is the time until the output is inverted following detection of voltage by POC, or the time until operation stabilizes after the shift from the operation stopped state to the operating state. 2. The oscillation stabilization time is the amount of time the CPU operation is stopped in order to avoid unstable operation at the start of oscillation. Program operation does not start until both the oscillation stabilization time and the time until oscillation starts have elapsed.
15 17 3. 2 /fX or 2 /fX can be selected using the mask option (refer to 9. MASK OPTION). 12 15 17 4. 2 /fX, 2 /fX, or 2 /fX can be selected using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization
time selection register (OSTS) (refer to 7.2 Standby Function Control Register). Remark fX: Main system clock oscillation frequency
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Data Retention Timing
Internal reset operation HALT mode STOP mode Data retention mode Operating mode
VDD
VDDDR STOP instruction execution
tSREL
RESET
tWAIT
HALT mode STOP mode Data retention mode Operating mode
VDD
VDDDR STOP instruction execution
tSREL
Standby release signal (interrupt request) tWAIT
Preliminary Product Information U14673EJ1V0PM00
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PD789322,789324,789326,789327
12. PACKAGE DRAWING
52-PIN PLASTIC LQFP (10x10)
A B
detail of lead end 41 42 28 27 S P C D T
R 52 1 F J G H I
M
L U
14 13 Q
K M
ITEM A B C MILLIMETERS 12.00.2 10.00.2 10.00.2 12.00.2 1.1 1.1 0.320.06 0.13 0.65 (T.P.) 1.00.2 0.5 0.17 +0.03 -0.05 0.10 1.4 0.10.05 3 +4 -3 1.50.1 0.25 0.60.15 S52GB-65-8ET-1
N
S
S
D F G H I J K L M N P Q R S T U
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APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the PD789322, 789324, 789326, and 789327. Language Processing Software
RA78K0S
Notes 1, 2, 3 Notes 1, 2 ,3 Notes 1, 2, 3, 5 Notes 1, 2, 3
Assembler package common to 78K/0S Series C compiler package common to 78K/0S Series Device file for PD789327 Subseries C compiler library source file common to 78K/0S Series
CC78K0S
DF789328
CC78K/0S-L
Flash Memory Writing Tools
Flashpro III Note 4 (Part number: FL-PR3 , PG-FP3) FA-52GB
Notes 4, 5
Dedicated flash memory programmer Adapter for writing to flash memory designed for 52-pin plastic LQFP (GB-8ET type)
Debugging Tools
IE-78K0S-NS In-circuit emulator In-circuit emulator to debug hardware or software when application systems using the 78K/0S Series are developed. The IE-78K0S-NS supports an integrated debugger (ID78K0S-NS). The IE-78K0S-NS is used in combination with an interface adapter for connection to an AC adapter, emulation probe, or host machine. AC adapter to supply power from a 100- to 240-V AC outlet. Interface adapter required when using a PC-9800 Series computer (except notebook type) as the host machine for the IE-78K0S-NS (C bus supported). PC card and interface cable required when a notebook PC is used as the host machine for the IE-78K0S-NS (PCMCIA socket supported). Interface adapter required when using an IBM PC/ATTM or compatible as the host machine for the IE-78K0S-NS (ISA bus supported). Interface adapter required when using a PC incorporating a PCI bus as the host machine for the IE-78K0S-NS.
Note 5
IE-70000-MC-PS-B AC adapter IE-70000-98-IF-C Interface adapter IE-70000-CD-IF-A PC card interface IE-70000-PC-IF-C Interface adapter IE-70000-PCI-IF Interface adapter IE-789328-NS-EM1 Emulation board NP-52GB
Notes 4, 5
Emulation board to emulate the peripheral hardware specific to the device. The IE789328-NS-EM1 is used in combination with the in-circuit emulator. Board to connect an in-circuit emulator to the target system. This board is dedicated for a 52-pin plastic LQFP (GB-8ET type). System simulator common to 78K/0S Series Integrated debugger common to 78K/0S Series Device file for PD789327 Subseries
SM78K0S
Notes 1, 2 Notes 1, 2
ID78K0S-NS DF789328
Notes 1, 2, 5
Notes 1. Based on the PC-9800 series (Japanese WindowsTM) 2. Based on IBM PC/AT or compatibles (Japanese/English Windows) 3. Based on the HP9000 series 700TM (HP-UXTM), SPARCstationTM (SunOSTM, SolarisTM), and NEWSTM (NEWS-OSTM) 4. Manufactured by Naito Densei Machida Mfg. Co, Ltd. (+81-44-822-3813). 5. Under development Remark The RA78K0S, CC78K0S, and SM78K0S are used in combination with the DF789328 device file.
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Real-Time OS
MX78K0S
Notes 1, 2
OS for 78K/0S Series
Notes 1. Based on the PC-9800 series (Japanese Windows) 2. Based on IBM PC/AT or compatibles (Japanese/English Windows)
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APPENDIX B. RELATED DOCUMENTS
Documents Related to Devices
Document Name Document No. Japanese English This document U14411E To be prepared U11047E
PD789322, 789324, 789326, 789327 Preliminary Product Information PD78F9328 Preliminary Product Information PD789327, 789467 Subseries User's Manual
78K/0S Series User's Manual Instructions
U14673J U14411J To be prepared U11047J
Documents Related to Development Tools (User's Manual)
Document Name Document No. Japanese RA78K0S Assembler Package Operation Assembly Language Structured Assembly Language CC78K0S C Compiler Operation Language SM78K0S System Simulator Windows Based SM78K Series System Simulator Reference External Part User Open Interface Specifications Reference U11622J U11599J U11623J U11816J U11817J U11489J U10092J English U11622E U11599E U11623E U11816E U11817E U11489E U10092E
ID78K0S-NS Integrated Debugger Windows Based IE-78K0S-NS In-circuit Emulator IE-789328-NS-EM1 Emulation Board
U12901J U13549J To be prepared
U12901E U13549E To be prepared
Documents Related to Embedded Software (User's Manual)
Document Name Document No. Japanese 78K/0S Series OS MX78K0S Fundamental U12938J English U12938E
Other Documents
Document Name Document No. English SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Guide to Microcontroller-Related Products by Third Parties X13769X C10535J C11531J C10983J C11892J U11416J C10535E C11531E C10983E C11892E - Japanese
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
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NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
EEPROM is a trademark of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation.
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Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
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The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
* The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
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