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PCI 9030 Data Book
PCI 9030 Data Book
Version 1.1
January 2001
Website: http://www.plxtech.com Email: apps@plxtech.com Phone: 408 774-9060 800 759-3735 408 774-2169 Fax:
2001 PLX Technology, Inc. All rights reserved. PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX products. PLX Technology and the PLX logo are registered trademarks and SMARTarget is a trademark of PLX Technology, Inc. Other brands and names are the property of their respective owners. Order Number: 9030-SIL-DB-P1-1.1 Printed in the USA, January 2001
Contents
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xviii 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2. Company and Product Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1. PCI 9030 SMARTarget I/O Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2. SMARTarget Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.3. PCI 9030 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.3.1. High-Performance PCI Target Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.3.2. High Performance CompactPCI Adapter Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.3.2.1. Hot Swap Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.3.3. PMC Adapter Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.4. PCI 9030 SMARTarget Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.4.1. Performance Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.4.2. Flexibility Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.4.3. Additional Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.5. PCI 9030 Data Assignment Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.6. PLX Chip Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.6.1. Pin Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.6.2. Register Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.7. PCI 9030, PCI 9050, and PCI 9052 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-2 1-2 1-2 1-3 1-3 1-3 1-3 1-3 1-4 1-4 1-4 1-5 1-5 1-5 1-5 1-5 1-6
2. PCI and Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1. PCI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1. PCI Bus Interface and Bus Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1.1. PCI Target Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1.2. Wait States--PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1.3. PCI Target Accesses to an 8- or 16-Bit Local Bus Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1.4. PCI Bus Little Endian Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1.1. Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1.2. Basic Bus States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2. Local Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3. Local Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3.1. Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3.2. Address/Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-1 2-1 2-1 2-1 2-1 2-1 2-1 2-2 2-2 2-2 2-2 2-3 2-3
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
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Contents
2.2.3.2.1. LAD[31:0] (Multiplexed Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3.2.2. LD[31:0] (Non-Multiplexed Bus). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3.2.3. LA[27:2] (Non-Multiplexed Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3.3. Control/Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3.3.1. ADS#, ALE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3.3.2. LBE[3:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3.3.3. LW/R# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3.3.4. READY# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3.3.5. WAITo# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3.3.6. LLOCKo# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3.3.7. WR# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3.3.8. RD# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3.3.9. LREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3.3.10. LGNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4. Local Bus Interface and Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4.1. Local Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4.2. Wait State Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4.2.1. Wait States--Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4.3. Burst Mode and Continuous Burst Mode (Bterm "Burst Terminate" Mode) . . . . . . . . . . . . . . . . . . . 2.2.4.3.1. Burst and Bterm Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4.3.2. Burst-4 Lword Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4.3.2.1. Continuous Burst Mode (Bterm "Burst Terminate" Mode) . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4.3.3. Partial Lword Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4.4. Recovery States (Multiplexed Mode Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4.5. Local Bus Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4.6. Local Bus Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.5. Local Bus Big/Little Endian Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.5.1. 32-Bit Local Bus--Big Endian Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.5.2. 16-Bit Local Bus--Big Endian Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.5.3. 8-Bit Local Bus--Big Endian Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-3 2-3 2-3 2-3 2-3 2-3 2-3 2-3 2-4 2-4 2-4 2-4 2-4 2-4 2-4 2-4 2-4 2-5 2-5 2-5 2-6 2-6 2-6 2-6 2-6 2-6 2-7 2-7 2-8 2-8
3. Serial EEPROM Reset and Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2. Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1. PCI Bus RST# Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2. Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3. PCI 9030 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4. Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1. Vendor ID and Device ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1.1. Serial EEPROM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2. Serial EEPROM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2.1. Serial EEPROM Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2.2. Recommended Serial EEPROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5. Internal Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1. PCI Bus Access to Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6. New Capabilities Function Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7. Serial EEPROM and Configuration Initialization Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-1 3-1 3-1 3-1 3-1 3-1 3-1 3-1 3-3 3-6 3-6 3-7 3-7 3-8
4. PCI Target (Direct Slave) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2. Direct Data Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1. PCI Target Operation (PCI Master-to-Local Bus Access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1.1. PCI Target Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1.2. PCI Target Delayed Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1.3. PCI Target Read Ahead Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-1 4-1 4-1 4-2 4-2
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PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Contents
4.2.1.4. PCI Target Delayed Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.1.5. PCI Target Local Bus READY# Timeout Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.1.6. PCI Target Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.1.7. PCI Target PCI-to-Local Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.1.7.1. PCI Target Local Bus Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.1.7.2. PCI Target Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.1.7.3. PCI Target Byte Enables (Multiplexed Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.2.1.7.4. PCI Target Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.2.1.7.5. PCI Target Byte Enables (Non-Multiplexed Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.3. Response to FIFO Full or Empty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.4. Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.4.1. Serial EEPROM and Configuration Initialization Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.4.2. PCI Target, Multiplexed and Non-Multiplexed Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4.4.2.1. PCI Target, Multiplexed Mode Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 4.4.2.2. PCI Target, Non-Multiplexed Mode Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27
5. Local Chip Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2. Chip Select Base Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.3. Procedure for Using Chip Select Base Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
6. PCI and Local Interrupts and General Purpose I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2. Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.1. PCI Interrupts (INTA#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.2. Local Interrupt Input (LINTi[2:1]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.3. Local Power Management Interrupt (LPMINT#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.4. Local Power Management Enumerator Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.5. All Modes PCI SERR# (PCINMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3. General Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6-1 6-1 6-1 6-1 6-1 6-1 6-2
7. PCI Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2. PCI Power Management Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.1. Power Management Data_Select, Data_Scale, and Power Data Utilization . . . . . . . . . . . . . . . . . . . . . . 7.2.2. Reading Hidden Data Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3. System Changes Power Mode Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4. Wake-Up Request Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7-1 7-2 7-3 7-3 7-3
8. CompactPCI Hot Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2. Controlling Connection Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.1. Connection Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.1.1. Board Slot Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.1.2. Board Healthy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.1.3. Platform Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2. Software Connection Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2.1. Ejector Switch and Blue LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2.2. ENUM# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2.3. Hot Swap Control/Status Register (HS_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2.4. Hot Swap Capabilities Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8-1 8-1 8-2 8-2 8-2 8-3 8-3 8-3 8-4 8-4
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
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Contents
9. PCI Vital Product Data (VPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2. VPD Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3. VPD Serial EEPROM Partitioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4. Sequential Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5. Random Access Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9-1 9-1 9-1 9-2
10. Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.1. New Register Definitions Summary (As Compared to the PCI 9050 and PCI 9052) . . . . . . . . . . . . . . . . . 10-1 10.2. Register Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.3. PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.4. Local Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15 10.5. Chip Select Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24 10.6. Runtime Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25
11. Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.1. Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.2. Pinout Common to All Bus Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.3. Multiplexed Local Bus Mode Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11.4. Non-Multiplexed Local Bus Mode Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 11.5. Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11.5.1. IEEE 1149.1 Test Access Port (JTAG Debug Port). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11.5.2. JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11.5.3. JTAG Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
12. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.1. General Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.2. Local Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12.3. Local Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
13. Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
13.1. 176-Pin PQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.2. 180-Pin BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
A. General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A.1. Ordering Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.2. United States and International Representatives, and Distributors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.3. Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index-1
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PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Figures
1-1 PCI 9030 Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-2 Typical PCI Target Adapter Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1-3 High-Performance CompactPCI Adapter Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1-4 Typical PMC Adapter Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1-5 Typical PCMCIA PC Card. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 2-1 Local Bus Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2-2 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2-3 Big/Little Endian--32-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2-4 Big/Little Endian--16-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2-5 Big/Little Endian--8-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 3-1 Local Bus PCI Target Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-2 Serial EEPROM Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3-3 PCI 9030 Internal Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 4-1 PCI Target Delayed Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4-2 PCI Target Read Ahead Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4-3 PCI Target Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4-4 PCI Target Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4-5 Local Bus PCI Target Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 5-1 Chip Select Base Address and Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5-2 Memory Map Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 6-1 Interrupt and Error Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 8-1 Redirection of BD_SEL# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8-2 Board Healthy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8-3 PCI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8-4 Hot Swap Capabilities Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 9-1 VPD Capabilities Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 12-1 PCI 9030 Local Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12-2 PCI 9030 Local Output Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12-3 PCI 9030 ALE Output Delay (Min/Max) to the Local Clock at 60 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 13-1 176-Pin PQFP Package Mechanical Dimensions--Topside and Cross-Section Views . . . . . . . . . . . . . . . . . . . . 13-1 13-2 176-Pin PQFP PCB Layout Suggested Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13-3 176-Pin PQFP Signal and Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13-4 180-Pin BGA Package Mechanical Dimensions--Topside, Underside, and Cross-Section Views . . . . . . . . . . 13-4 13-5 180-Pin BGA PCB Layout Suggested Land Pattern. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 13-6 180-Pin BGA Package Layout--Underside View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 13-7 180-Pin BGA Six-Layer Board Routing Example (Four Routing Layers)--Component Side . . . . . . . . . . . . . . 13-10 13-8 180-Pin BGA Six-Layer Board Routing Example (Four Routing Layers)--First Inside Layer. . . . . . . . . . . . . . 13-10 13-9 180-Pin BGA Six-Layer Board Routing Example (Four Routing Layers)--Second Inside Layer . . . . . . . . . . . 13-10 13-10 180-Pin BGA Six-Layer Board Routing Example (Four Routing Layers)--Solder Side . . . . . . . . . . . . . . . . . 13-10
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PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Tables
1-1 FIFO Depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1-2 PCI 9030 Data Assignment Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1-3 PCI 9030, PCI 9050, and PCI 9052 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 2-1 PCI Target Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-2 PCI Bus Little Endian Byte Lanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-3 READY Data Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2-4 Local Bus Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2-5 Burst and Bterm on the Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2-6 Burst-4 Lword Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2-7 PCI Target Single and Burst Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2-8 Byte Number and Lane Cross-Reference--Multiplexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2-9 Byte Number and Lane Cross-Reference--Non-Multiplexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2-10 Cycle Reference Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2-11 Upper Lword Lane Transfer--32-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2-12 Upper Word Lane Transfer--16-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2-13 Lower Word Lane Transfer--16-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2-14 Upper Byte Lane Transfer-- 8-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2-15 Lower Byte Lane Transfer-- 8-Bit Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 3-1 Serial EEPROM Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-2 Serial EEPROM Register Load Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3-3 New Capabilities Function Support Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 4-1 Response to FIFO Full or Empty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 5-1 Chip Select Base Address Register Signal Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 8-1 Hot Swap Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 10-1 New Registers Definitions Summary (As Compared to the PCI 9050 and PCI 9052) . . . . . . . . . . . . . . . . . . . . . 10-1 10-2 PCI Configuration Register Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10-3 Local Configuration Register Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10-4 Chip Select Register Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10-5 Runtime Register Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 11-1 Pin Type Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11-2 Power and Ground Pins (176-Pin PQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11-3 Power and Ground Pins (180-Pin BGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11-4 Serial EEPROM Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11-5 Test and Debug Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11-6 PCI System Bus Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11-7 Local Bus Mode Independent Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 11-8 Multiplexed Bus Mode Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11-9 Non-Multiplexed Bus Mode Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 11-10 JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11-11 JTAG Infrared Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 12-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12-2 Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12-3 Capacitance (Sample Tested Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12-4 Package Thermal Resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12-5 Electrical Characteristics over Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12-6 AC Electrical Characteristics (Local Inputs) over Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12-7 AC Electrical Characteristics (Local Outputs) over Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
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13-1 176-Pin PQFP Package Mechanical Dimensions (Legend for Figure 13-1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13-2 180-Pin BGA Package Mechanical Dimensions (Legend for Figure 13-4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13-3 180-Pin BGA PCI 9030 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8 13-4 180-Pin BGA Six-Layer Board Routing Example (Four Routing Layers)--Sample Parameters . . . . . . . . . . . . 13-9 A-1 Available Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
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PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Registers
10-1 (PCIIDR; PCI:00h) PCI Configuration ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10-2 (PCICR; PCI:04h) PCI Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10-3 (PCISR; PCI:06h) PCI Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10-4 (PCIREV; PCI:08h) PCI Revision ID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10-5 (PCICCR; PCI:09-0Bh) PCI Class Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10-6 (PCICLSR; PCI:0Ch) PCI Cache Line Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 10-7 (PCILTR; PCI:0Dh) PCI Bus Latency Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 10-8 (PCIHTR; PCI:0Eh) PCI Header Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 10-9 (PCIBISTR; PCI:0Fh) PCI Built-In Self Test (BIST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 10-10 (PCIBAR0; PCI:10h) PCI Base Address Register for Memory Accesses to Local Registers . . . . . . . . . . . . . . . 10-6 10-11 (PCIBAR1; PCI:14h) PCI Base Address Register for I/O Accesses to Local Registers . . . . . . . . . . . . . . . . . . . 10-7 10-12 (PCIBAR2; PCI:18h) PCI Base Address Register for Memory Accesses to Local Address Space 0. . . . . . . . . 10-7 10-13 (PCIBAR3; PCI:1Ch) PCI Base Address Register for Memory Accesses to Local Address Space 1 . . . . . . . . 10-8 10-14 (PCIBAR4; PCI:20h) PCI Base Address Register for Memory Accesses to Local Address Space 2. . . . . . . . . 10-8 10-15 (PCIBAR5; PCI:24h) PCI Base Address Register for Memory Accesses to Local Address Space 3 . . . . . . . . 10-9 10-16 (PCICIS; PCI:28h) PCI Cardbus CIS Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 10-17 (PCISVID; PCI:2Ch) PCI Subsystem Vendor ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 10-18 (PCISID; PCI:2Eh) PCI Subsystem ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 10-19 (PCIERBAR; PCI:30h) PCI Expansion ROM Base. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 10-20 (CAP_PTR; PCI:34h) New Capability Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 10-21 (PCIILR; PCI:3Ch) PCI Interrupt Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 10-22 (PCIIPR; PCI:3Dh) PCI Interrupt Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 10-23 (PCIMGR; PCI:3Eh) PCI Min_Gnt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 10-24 (PCIMLR; PCI:3Fh) PCI Max_Lat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 10-25 (PMCAPID; PCI:40h) Power Management Capability ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 10-26 (PMNEXT; PCI:41h) Power Management Next Capability Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 10-27 (PMC; PCI:42h) Power Management Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 10-28 (PMCSR; PCI:44h) Power Management Control/Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12 10-29 (PMCSR_BSE; PCI:46h) PMCSR Bridge Support Extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12 10-30 (PMDATA; PCI:47h) Power Management Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13 10-31 (HS_CNTL; PCI:48h) Hot Swap Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13 10-32 (HS_NEXT; PCI:49h) Hot Swap Next Capability Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13 10-33 (HS_CSR; PCI:4Ah) Hot Swap Control/Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13 10-34 (PVPDCNTL; PCI:4Ch) PCI Vital Product Data Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 10-35 (PVPD_NEXT; PCI:4Dh) PCI Vital Product Data Next Capability Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 10-36 (PVPDAD; PCI:4Eh) PCI Vital Product Data Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 10-37 (PVPDATA; PCI:50h) PCI VPD Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 10-38 (LAS0RR; 00h) Local Address Space 0 Range Register for PCI-to-Local Bus . . . . . . . . . . . . . . . . . . . . . . . . 10-15 10-39 (LAS1RR; 04h) Local Address Space 1 Range Register for PCI-to-Local Bus . . . . . . . . . . . . . . . . . . . . . . . . 10-15 10-40 (LAS2RR; 08h) Local Address Space 2 Range Register for PCI-to-Local Bus . . . . . . . . . . . . . . . . . . . . . . . . 10-16 10-41 (LAS3RR; 0Ch) Local Address Space 3 Range Register for PCI-to-Local Bus . . . . . . . . . . . . . . . . . . . . . . . . 10-16 10-42 (EROMRR; 10h) Expansion ROM Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17 10-43 (LAS0BA; 14h) Local Address Space 0 Local Base Address (Remap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17 10-44 (LAS1BA; 18h) Local Address Space 1 Local Base Address (Remap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
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Registers
10-45 (LAS2BA; 1Ch) Local Address Space 2 Local Base Address (Remap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18 10-46 (LAS3BA; 20h) Local Address Space 3 Local Base Address (Remap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18 10-47 (EROMBA; 24h) Expansion ROM Local Base Address (Remap). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18 10-48 (LAS0BRD; 28h) Local Address Space 0 Bus Region Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19 10-49 (LAS1BRD; 2Ch) Local Address Space 1 Bus Region Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20 10-50 (LAS2BRD; 30h) Local Address Space 2 Bus Region Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21 10-51 (LAS3BRD; 34h) Local Address Space 3 Bus Region Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22 10-52 (EROMBRD; 38h) Expansion ROM Bus Region Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23 10-53 (CS0BASE; 3Ch) Chip Select 0 Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24 10-54 (CS1BASE; 40h) Chip Select 1 Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24 10-55 (CS2BASE; 44h) Chip Select 2 Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24 10-56 (CS3BASE; 48h) Chip Select 3 Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24 10-57 (INTCSR; 4Ch) Interrupt Control/Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25 10-58 (PROT_AREA; 4Eh) Serial EEPROM Write-Protected Address Boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25 10-59 (CNTRL; 50h) PCI Target Response, Serial EEPROM, and Initialization Control . . . . . . . . . . . . . . . . . . . . . . 10-26 10-60 (GPIOC; 54h) General Purpose I/O Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27 10-61 (PMDATASEL; 70h) Hidden 1 Power Management Data Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-29 10-62 (PMDATASCALE; 74h) Hidden 2 Power Management Data Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-29
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PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Timing Diagrams
3-1 Initialization from Serial EEPROM (2K or 4K Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3-2 PCI Configuration Write to PCI Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3-3 PCI Configuration Read from PCI Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3-4 PCI Memory Write to Local Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3-5 PCI Memory Read from Local Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3-6 Local Level Triggered Interrupt Asserting PCI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3-7 Local Edge Triggered Interrupt Asserting PCI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 4-1 Local Bus Arbitration from the PCI 9030 by Another Local Bus Initiator (LREQ and LGNT) . . . . . . . . . . . . . . . . . . 4-7 4-2 Initialization from Serial EEPROM (2K or 4K Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4-3 PCI Configuration Write to PCI Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4-4 PCI Configuration Read from PCI Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4-5 PCI Memory Write to Local Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4-6 PCI Memory Read from Local Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4-7 Local Level Triggered Interrupt Asserting PCI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4-8 Local Edge Triggered Interrupt Asserting PCI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4-9 PCI Target Burst Write with Delayed Write and SRAM Chip Select Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4-10 PCI Target Burst Write (32-Bit Local Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4-11 PCI Target Burst Write (16-Bit Local Bus), No Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 4-12 PCI Target Burst Write (16-Bit Local Bus), One Data-to-Data Wait State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 4-13 PCI Target Burst Writes (8-Bit Local Bus), One Data-to-Data Wait State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 4-14 PCI Target Single Writes (16-Bit Local Bus). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4-15 PCI Target Single Writes (8-Bit Local Bus). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 4-16 PCI Target Single Writes (8-Bit Local Bus), No Wait States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 4-17 PCI Target Back-to-Back Single Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 4-18 PCI Target Back-to-Back Write Followed by a Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 4-19 PCI Target Back-to-Back Read Followed by a Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 4-20 PCI Target Back-to-Back Reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 4-21 PCI Target Single Write (32-Bit Local Bus), Multiplexed Mode Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 4-22 PCI Target Single Read (32-Bit Local Bus), Multiplexed Mode Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 4-23 PCI Target Burst Write with Bterm Enabled (32-Bit Local Bus), Multiplexed Mode Only . . . . . . . . . . . . . . . . . . . 4-25 4-24 PCI Target Burst Read with Prefetch Enabled (32-Bit Local Bus), Prefetch Counter Set to 8, Multiplexed Mode Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 4-25 PCI Target Single Write (32-Bit Local Bus), Non-Multiplexed Mode Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27 4-26 PCI Target Single Write (16-Bit Local Bus), Non-Multiplexed Mode Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28 4-27 PCI Target Single Write (8-Bit Local Bus), Non-Multiplexed Mode Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28 4-28 PCI Target Single Read (32-Bit Local Bus), Non-Multiplexed Mode Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29 4-29 PCI Target Single Read with One Wait State Using READY# Input (32-Bit Local Bus), Non-Multiplexed Mode Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 4-30 PCI Target Single Read with One Wait State Using Internal Wait State (32-Bit Local Bus), Non-Multiplexed Mode Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 4-31 PCI Target Non-Burst Write (32-Bit Local Bus), Non-Multiplexed Mode Only . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32 4-32 PCI Target Non-Burst Write (8-Bit Local Bus), Non-Multiplexed Mode Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33 4-33 PCI Target Non-Burst Read, Non-Multiplexed Mode Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34 4-34 PCI Target Burst Write with Bterm Enabled (32-Bit Local Bus), Non-Multiplexed Mode Only . . . . . . . . . . . . . . . 4-35 4-35 PCI Target Burst Write with Bterm Disabled (32-Bit Local Bus), Non-Multiplexed Mode Only . . . . . . . . . . . . . . 4-36
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
xv
Timing Diagrams
4-36 PCI Target Burst Read with Prefetch Counter Set to 8 (32-Bit Local Bus), Non-Multiplexed Mode Only. . . . . . . 4-37 4-37 PCI Target Burst Read with Prefetch Counter Set to 5 (32-Bit Local Bus), Non-Multiplexed Mode Only. . . . . . . 4-38 4-38 PCI Target Burst Write (32-Bit Local Bus), Non-Multiplexed Mode Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39 4-39 PCI Target Burst Write (16-Bit Local Bus), Non-Multiplexed Mode Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40 4-40 PCI Target Burst Write with External Wait States (8-Bit Local Bus), Non-Multiplexed Mode Only. . . . . . . . . . . . 4-40 4-41 Delayed Read Transaction PCI Specification v2.2, Non-Multiplexed Mode Only. . . . . . . . . . . . . . . . . . . . . . . . . 4-41 4-42 PCI Target Read No Flush Mode (Read Ahead Mode), Prefetch Enabled, Prefetch Count Disabled, Non-Multiplexed Mode Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42 4-43 Locked PCI Target Read Followed by Write and Release (LLOCKo#), Non-Multiplexed Mode Only . . . . . . . . . 4-43 4-44 PCI Target Write to Local Target in BIGEND Mode, Non-Multiplexed Mode Only . . . . . . . . . . . . . . . . . . . . . . . . 4-44
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PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
PREFACE
The information contained in this document is subject to change without notice. Although an effort has been made to keep the information accurate, there may be misleading or even incorrect statements made herein. The following is a list of additional documentation to provide the reader with more information about the PCI 9030 and related subjects: * PCI Local Bus Specification, Revision 2.2, December 18, 1998 PCI Special Interest Group (PCI SIG) 5440 SW Westgate Drive #217, Portland, OR 97221 USA Tel: 800 433-5177 (domestic only) or 503 693-6232, Fax: 503 693-8344, http://www.pcisig.com * PCI Hot-Plug Specification, Revision 1.0 PCI Special Interest Group (PCI SIG) 5440 SW Westgate Drive #217, Portland, OR 97221 USA Tel: 800 433-5177 (domestic only) or 503 693-6232, Fax: 503 693-8344, http://www.pcisig.com * PCI Bus Power Management Interface Specification, Revision 1.1, December 18, 1998 PCI Special Interest Group (PCI SIG) 5440 SW Westgate Drive #217, Portland, OR 97221 USA Tel: 800 433-5177 (domestic only) or 503 693-6232, Fax: 503 693-8344, http://www.pcisig.com * PICMG 2.1, R1.0, CompactPCI Hot Swap Specification, August 3, 1998 PCI Industrial Computer Manufacturers Group (PICMG) c/o Virtual Inc., 401 Edgewater Place, Suite 500, Wakefield, MA 01880, USA Tel: 781 224-1100, Fax: 781 224-1239, http://www.picmg.org
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
xvii
Revision History
Revision History
Date
3/1999 8/1999 10/1999 10/1999 11/1999 12/1999 4/2000 1/31/2001
Revision
New Release 0.90 0.90 0.91 0.92 0.93 1.0 1.1
Comment
New Release PCI 9030 Preliminary Data Book, Version 0.9. Update. Initial Release Red Book. Update. Update. Initial Release Blue Book. Production Release. Incorporate 1/31/2001 Addendum changes, including past design notes.
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PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
PCI 9030
PCI SMARTargetTM I/O Accelerator
January 2001 Version 1.1 CompactPCI Hot Swap Ready for Adapters and Embedded Systems
1
1.1
INTRODUCTION
FEATURES
* Flexible Local Bus runs up to 60 MHz * 3.3/5V tolerant PCI and Local signaling supports Universal PCI Adapter designs * Flexible Local Bus provides 32-bit Multiplexed or Non-Multiplexed Protocol for 8-, 16-, or 32-bit Peripheral and Memory devices * Serial EEPROM interface * Nine programmable General Purpose I/O (GPIOs) * Five programmable Local Address spaces * Four programmable independent chip selects * Programmable Local Bus wait states * Programmable Local Read prefetch mechanism * Local Bus can run asynchronously to the PCI Bus * Two programmable Local-to-PCI interrupts * Endian Byte Swapping * 3.3V Core, Low-Power CMOS in 176-pin PQFP or 180-pin BGA * Industrial Temp Range operation
* PCI Local Bus Specification v2.2-compliant 32-bit, 33 MHz Bus Target Interface Device enabling PCI Burst Transfers up to 132 MB/s * PCI Bus Power Management Interface Specification v1.1 compliant * PCI Local Bus Specification v2.2 Vital Product Data (VPD) configuration support * Hot Swap Specification, Revision 1.0(R) Hot Swap Ready compliant PICMG 2.1, CompactPCI(R)
* PCI Target Programmable Burst Management * PCI Target Read Ahead mode * PCI Target Delayed Read mode * PCI Target Delayed Write mode * Programmable Interrupt Generator/Controller * Two programmable FIFOs for zero wait state burst operation
32-Bit 60 MHz Local Bus
Local Bus Interface Control Logic
Local Bus Control Logic
Endian Control Logic
Dynamic Data Bus Width Control Logic
Multiplexed/ Non-Multiplexed Control Logic
Serial EEPROM Controller
PCI Configuration Register
Local Non Configuration Register
Read FIFO
Write FIFO
FIFO Control Logic
PCI Bus Interface Control Logic
PCI Bus Control Logic
Hot Swap Control Logic
32-Bit 33 MHz PCI Bus
Figure 1-1. PCI 9030 Internal Block Diagram
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
1-1
Section 1--Introduction
Section 1 Introduction
Company and Product Background
1.2
COMPANY AND PRODUCT BACKGROUND
1.2.2
SMARTarget Technology
PLX Technology, Inc. is the world leader in PCI-to-Local Bus I/O accelerator chips, which are used in a wide variety of PCI applications. Customer applications include PCI add-in boards in PC workstations and servers, embedded PCI communication systems (such as routers and switches), and industrial PCI implementations (such as CompactPCI, PMC, and Passive Backplane PCI). PLX Technology, Inc. is an active member of industrystandard committees, including the PCI SIG, I2O SIG, and PICMG, and maintains active developer technology and cross-marketing partnerships with industry leaders, such as Intel, IBM, Hewlett-Packard, Motorola, WindRiver, and others. Focused on providing complete solutions for PCI implementations, PLX provides design assistance to customers in the form of Reference Design and Software Development kits. Depending upon the application, these kits may include reference boards, API libraries, software debug tools, and sample device drivers, enabling customers to quickly bring new designs to production. New tools, application notes, FAQs, and information updates are frequently being added to the PLX website (http://www.plxtech.com) for customer convenience. PLX's expertise and total solutions for the PCI interface allow customers to focus on adding value in their designs without worrying about the complexities of implementing PCI and CompactPCI.
Many PCI chip and core designs implement only basic PCI Local Bus Specification v2.2 bus interface signaling, leaving the difficult performance and compatibility issues to the designer. The PCI 9030, with SMARTarget Technology, incorporates features which simplify design implementation. These features go far beyond the minimum to provide the highest possible design performance and flexibility. SMARTarget Technology performance features: * PCI v2.2 compliant, 32-bit, 33 MHz Target Interface, enabling PCI Burst Transfers up to 132 MB/s * Up to 60 MHz Local Bus Operation, Enabling Burst Transfers up to 240 MB/s * PCI Target Read Ahead mode * PCI Target Programmable Burst * PCI Target Delayed Write * Posted Memory Writes SMARTarget Technology flexibility features: * Programmable 32-bit Local Bus operates up to 60 MHz * Supports five PCI-to-Local Address spaces * Nine Programmable General Purpose I/Os (GPIOs) * Four Programmable Chip Selects * CompactPCI Hot Swap Ready * Big/Little Endian Byte Conversion * Interrupt Generator/Controller * PCI v2.2 Vital Product Data (VPD) * PCI Bus Power Management Interface Specification v1.1 * 3.3/5V Tolerant PCI Signaling * 3.3V CMOS Device in 176-PQFP or 180-pin BGA * Programmable Read and Write Strobe Timing on the Local Bus
1.2.1
PCI 9030 SMARTarget I/O Accelerator
The PCI 9030, a 32-bit, 33-MHz PCI Bus Target Interface chip with SMARTargetTM Technology, is the most advanced general-purpose PCI Target device available. It offers a complete PCI Local Bus Specification (v2.2) implementation, enabling Burst transfers up to 132 MB/s, and is the industry's first CompactPCI Hot Swap Ready Target device. The PCI 9030 is the perfect solution for migrating legacy designs to PCI while adding new features that enhance next generation Target designs. The PCI 9030 SMARTarget I/O Accelerator brings PLX's industry-leading experience in the PCI design world to the customer in a way that is simple and convenient to use.
1-2
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
1.2.3
PCI 9030 Applications
Memory I/O ENUM# 32-Bit 60 MHz Local Bus I/O LED PCI 9030 SMARTargetTM Device 32-Bit 33 MHz CompactPCI Bus
The PCI 9030 can be used in a wide variety of networking, telecom, imaging, industrial and storage applications. The PCI 9030 simplifies legacy design migration to PCI by providing a convenient off-theshelf solution that enables prototypes to be operational in a short time period.
1.2.3.1
High-Performance PCI Target Interface
Figure 1-3. High-Performance CompactPCI Adapter Card
The PCI 9030's built-in SMARTarget performance features (such as 3.3/5V tolerant I/O buffers and Local Bus operation up to 60 MHz), enable designers to connect a wide variety of memory and I/O devices. With SMARTarget in action, PCI Target Adapter designs have never been simpler to implement. Figure 1-2 illustrates a typical PCI Target adapter card.
1.2.3.2.1 Hot Swap Ready
Hot Swap Ready performance features include: * PCI Local Bus Specification v2.2 * Tolerant of Vcc from early power * Tolerant of asynchronous reset * Tolerant of precharge voltage * Limited I/O pin leakage at precharge voltage * Incorporates the Hot Swap Control/Status register (HS_CSR) * Incorporates an Extended Capability Pointer (ECP) mechanism
Memory
I/O
I/O
32-Bit 60 MHz Local Bus I/O PCI 9030 SMARTarget TM Device I/O
* Incorporates added resources for software control of ENUM#, the ejector switch, and the status LED, which indicates insertion and removal status to the user * Precharge 10K ohm resistor network and BIAS voltage internal to the PCI 9030 * Early power support internal to the PCI 9030
32-Bit 33 MHz System PCI Bus
Figure 1-2. Typical PCI Target Adapter Card
1.2.3.3
PMC Adapter Cards
1.2.3.2
High Performance CompactPCI Adapter Designs
Built upon substantial CompactPCI experience, the PLX PCI 9030 is the industry's first CompactPCI Hot Swap Ready Target device. This allows CompactPCI I/O board designs to be compatible with both traditional CompactPCI and new Hot Swap system designs. Figure 1-3 illustrates a typical CompactPCI adapter card.
In the real estate-conscious world of PMC, PC-MIP, and PCMCIA PC cards, the PCI 9030 offers an attractive packaging option with the dime-size 180-pin BGA. SMARTarget flexibility features, such as GPIOs and Programmable Chip selects, save additional valuable board space. The PCI 9030 enables a whole new generation of mini form factor PCI cards. Figure 1-4 illustrates a typical PMC adapter card and Figure 1-5 illustrates a typical PCMCIA PC card.
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
1-3
Section 1--Introduction
Company and Product Background
Section 1 Introduction
Section 1 Introduction
Company and Product Background
Memory
32-Bit 33 MHz PCI Bus
I/O
32-Bit 60 MHz Local Bus
PCI 9030 TM SMARTarget Device (BGA)
PCI Target Delayed Write Mode. The PCI Target Write data accumulates in the PCI Target Write FIFO to allow uninterrupted burst transactions on the Local Bus. This allows for a higher throughput for conditions in which the PCI Clock frequency is slower than the Local Clock frequency. Posted Memory Writes. A PCI Memory write is posted to the PCI 9030 for later transfer to the Local Bus. This allows for maximum PCI performance and avoids potential deadlock situations.
Figure 1-4. Typical PMC Adapter Card
1.2.4.2
I/O 32-Bit 60 MHz Local Bus
PCI 9030 TM SMARTarget Device (BGA)
Flexibility Features
Programmable Local Bus. Operates up to 60 MHz and supports both Multiplexed and Non-Multiplexed 32-bit address/data protocol, and dynamic Local Bus width control allowing slave accesses to 8-,16- or 32-bit devices. PCI-to-Local Address Spaces. Supports five PCI-toLocal Address spaces. Spaces 0, 1, 2, 3, and the Expansion ROM space all allow a PCI Bus Master to access the Local Memory spaces with individually programmable wait states, bus width, and burst capabilities. GPIOs. The PCI 9030 has nine programmable general purpose I/O pins, which may be used for generic interface purposes. Four Programmable Chip Selects. Eliminates decode logic, which improves performance. CompactPCI Hot Swap Ready. Compliant with PICMG 2.1 R1.0. Big/Little Endian Conversion. Supports automatic on-the-fly Big Endian and Little Endian conversion for all operations and data widths. Interrupt Generator/Controller. Can assert PCI interrupts from external and internal sources. VPD Support. Fully supports the PCI v2.2 Vital Product Data (VPD) extension, including the New Capabilities Structure. Provides an alternate access method for user- or system-defined parameters or configuration data. PCI Power Management. Supports both the D0 and D3hot power states.
Memory
Figure 1-5. Typical PCMCIA PC Card
1.2.4 1.2.4.1
PCI 9030 SMARTarget Features Performance Features
PCI v2.2 Compliant. This 32-bit, 33 MHz Target Interface Chip enables PCI Burst Transfers up to 132 MB/s. Up to 60 MHz Local Bus Operation. Enables burst transfers up to 240 MB/s. PCI Target Read Ahead Mode. Prefetches a programmable amount of data from the Local Bus. This data can then be burst-transferred onto the PCI bus from the PCI 9030 internal PCI Target Read FIFO. The prefetch size can be programmed to match the PCI master burst length or can be used in the PCI Target Read Ahead mode data. This feature also allows for increased bandwidth and reduced read latency. PCI Target Programmable Burst. The PCI 9030 may be programmed for several burst lengths, including unlimited burst. This allows for maximum transfer rates on both the PCI and Local Buses.
1-4
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Two Programmable FIFOs for Zero Wait State Burst Operation. The following table describes the FIFO depth.
Table 1-1. FIFO Depth
FIFO
PCI Target Read PCI Target Write
1.2.5
PCI 9030 Data Assignment Convention
The following table describes the PCI 9030 data assignment convention.
Table 1-2. PCI 9030 Data Assignment Convention
Data Width
1 byte (8 bits)
Length
16 Lwords 32 Lwords
PCI 9030 Convention
Byte Word Lword
3.3/5V Tolerant PCI Signaling. Enables Universal PCI Adapters. 3.3V CMOS Device in 176-pin PQFP or 180-pin
BGA.
2 bytes (16 bits) 4 bytes (32 bits)
1.2.6 Additional Features 1.2.6.1
PLX Chip Compatibility Pin Compatibility
1.2.4.3
5 Volt Tolerant Operation. The PCI 9030 requires a 3.3V supply. It provides 3.3V signaling with 5V I/O tolerance on both the PCI and Local Buses. Serial EEPROM Interface. Contains a serial EEPROM interface that offers the option of loading configuration information from an EEPROM device. Clocks. The Local Bus interface runs from a Local Bus clock, which runs asynchronously to the PCI clock. In addition, the PCI 9030 provides a PCI Buffered clock, which can be used as a Local Bus clock. RST# Timing. Supports response to first configuration accesses after de-assertion of PCI RST# in less than 225 clocks. Subsystem and Subsystem Vendor IDs. Contains Subsystem ID and Subsystem Vendor ID in the PCI Configuration register space, in addition to Device and Vendor IDs. The PCI 9030 also contains a permanent Vendor ID (10B5h) and Device ID (9030h). Silicon Revision ID. Contains the PCI 9030 Silicon Revision ID, which is programmable by way of the serial EEPROM.
The PCI 9030 is not pin compatible with the PCI 9050, PCI 9052, PCI 9054, nor the PCI 9080.
1.2.6.2
Register Compatibility
All registers implemented in the PCI 9050 and 9052 are implemented in the PCI 9030. The PCI 9030 includes many new bit definitions and several new registers. Refer to Table 1-3 for details. The PCI 9030 is not register-compatible with the PCI 9080 nor the PCI 9054.
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
1-5
Section 1--Introduction
Company and Product Background
Section 1 Introduction
Section 1 Introduction
Company and Product Background
1.2.7
PCI 9030, PCI 9050, and PCI 9052 Comparison
The following table compares the PCI 9030, PCI 9050, and PCI 9052.
Table 1-3. PCI 9030, PCI 9050, and PCI 9052 Comparison
Feature
Pin Count and Type Package Size Local Address Spaces PCI Initiator Mode Number of FIFOs FIFO Depth--PCI Target Write FIFO Depth--PCI Target Read LLOCKo# Pin for Lock Cycles WAITo# Pin for Wait State Generation BCLKo (BCLKO) Pin; Buffered PCI Clock ISA Bus Interface
PCI 9030
176 PQFP/180 BGA 27 x 27 mm 5 No 2 32 Lwords (128 bytes) 16 Lwords (64 bytes) Yes Yes Yes No Identical to the PCI 9050 and PCI 9052, except the PCI 9030 contains additional registers related to added functionality Yes Yes Yes Yes Yes Yes Yes Yes Yes 9 Yes 3.3V 3.3V Yes Yes 2K-, 4K-bit devices Reads allowed via VPD function (refer to Section 9) and CNTRL Register Yes Ready
PCI 9050
160 PQFP 31 x 31 mm 5 No 2 16 Lwords (64 bytes) 8 Lwords (32 bytes) Yes Yes Yes No
PCI 9052
160 PQFP 31 x 31 mm 5 No 2 16 Lwords (64 bytes) 8 Lwords (32 bytes) Yes Yes Yes Yes
Register Addresses
--
--
Big Endian ! Little Endian Conversion PCI Target Delayed Read Transactions PCI Target Delayed Write Transactions PCI Target Local Bus READY# Timeout PCI Bus Power Management Interface v1.1 PCI Local Bus Specification v2.2 VPD Support Programmable Prefetch Counter Programmable Wait States Programmable Ready Timeout Programmable GPIOs Additional Device and Vendor ID Registers Core and Local Bus Vcc PCI Bus Vcc 3.3V PCI Bus and Local Bus Signaling 5V Tolerant PCI Bus and Local Bus Signaling Serial EEPROM Support Serial EEPROM Read Control PCI Target Read Ahead Mode CompactPCI Hot Swap Capability
Yes Yes No No No No Yes Yes No 4 Yes 5V 5V No Yes 1K-bit devices Reads allowed via Serial EEPROM Control Register (CNTRL) No Capable
Yes Yes No No No No Yes Yes No 4 Yes 5V 5V No Yes 1K-bit devices Reads allowed via Serial EEPROM Control Register (CNTRL) No Capable
1-6
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
2
2.1 2.1.1
PCI AND LOCAL BUS
2.1.1.3 PCI BUS PCI Bus Interface and Bus Cycles PCI Target Accesses to an 8or 16-Bit Local Bus Device
This section discusses PCI and Local Bus operation.
2.1.1.1
PCI Target Command Codes
2.1.1.4
PCI Bus Little Endian Mode
As a Target, the PCI 9030 allows access to the PCI 9030 internal registers and the Local Bus, using the commands listed in Table 2-1. All Read or Write accesses to the PCI 9030 can be Byte, Word, or Lword (32-bit data). All memory commands are aliased to basic memory commands. All PCI 9030 I/O accesses are decoded to an Lword boundary. Byte enables are used to determine which bytes are read or written. An I/O access with illegal byte enable combinations is terminated with a Target abort.
Table 2-1. PCI Target Command Codes
Command Type
I/O Read I/O Write Memory Read Memory Write Configuration Read Configuration Write
The PCI Bus is a Little Endian bus (that is, the address is invariant and data is Lword-aligned to the lowermost byte lane).
Table 2-2. PCI Bus Little Endian Byte Lanes
Byte Number
0 1 2 3
Byte Lane
AD[7:0] AD[15:8] AD[23:16] AD[31:24]
2.2 2.2.1
LOCAL BUS Introduction
Code (C/BE[3:0]#)
0010 (2h) 0011 (3h) 0110 (6h) 0111 (7h) 1010 (Ah) 1011 (Bh)
2.1.1.2
Wait States--PCI Bus
The PCI Bus Master throttles IRDY# and the PCI Bus Slave throttles TRDY# to assert PCI Bus wait state(s).
The Local Bus provides a data path between the PCI Bus and non-PCI devices, including memory devices and peripherals. The Local Bus is a 32-bit multiplexed or non-multiplexed bus, with bus memory regions that can be programmed for 8-, 16-, or 32-bit widths. The PCI 9030 Local Bus is signal-compatible with popular RISC and Bridge architecture, including the i960Cx, i960Jx, and PPC401 GF. In addition, the Local Bus can directly connect to Texas Instruments DSP devices (such as the TMS320C6202 and TMS320C54x). The PCI 9030 is the Local Bus master. The PCI 9030 can transfer data between the Local Bus, internal registers and FIFOs. Burst lengths are not limited. The width of the bus depends upon the Local Address Space register setting. There are four address spaces and one default space (the expansion ROM that can be used as another address space). Each space contains a set of configuration registers that determine
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
2-1
Section 2--PCI & Local Bus
The PCI 9030 is compliant with PCI Local Bus Specification v2.2. Refer to the specification for specific PCI Bus functions as a PCI Target Interface chip.
Direct PCI access to an 8- or 16-bit Local Bus device results in the PCI Bus Lword being broken into multiple Local Bus transfers. For each 8-bit transfer, byte enables are encoded as in the i960C to provide Local Address bits LA[1:0]. For each 16-bit transfer, byte enables are encoded to provide BLE#, BHE# and LA1.
Section 2 PCI and Local Bus
Local Bus
all Local Bus characteristics when that space is accessed.
From PCI To PCI Config Data_Inbound Config Data_Outbound Configuration Registers Local Arbiter Feature Control From PCI PCI Control Local Control
Local Master Controller
Local/Data Control
From PCI To PCI
Address/Data Data PCI Target FIFOs
Address/Data Data Local Address/ Data Bus LA[27:2] LD/LAD[31:0]
Figure 2-1. Local Bus Block Diagram
2.2.1.1
Transactions
the bus devices to recover. After recovery state, the bus enters the idle state and waits for another access.
Four types of transactions can occur on a Local Bus: * Read * Write * Read Burst * Write Burst A Bus access is a transaction which is bounded by the assertion of ADS# at the beginning and de-assertion of BLAST# at the end. A Bus access consists of an address cycle followed by one or more data transfers. During each clock cycle of an access, the Local Bus is in one of four basic states defined in Section 2.2.1.2, "Basic Bus States." A clock cycle consists of one period of the Local Bus clock.
2.2.2
Local Signals
The key Local Bus control signals shown in most timing diagram examples are as follows: * ADS# or ALE indicates the start of an access * READY#, WAITo#, and BTERM# are used to assert wait states and terminating Burst cycles during Data transfers * LW/R#, direction of Data transfer * BLAST#, BTERM# indicate the end of an access The key data signals are: * LAD address, data bus * LBE# local byte enables, indicating valid byte lanes
2.2.1.2
Basic Bus States
The four basic bus states are idle, address, data/wait, and recovery. Once the Local Bus master owns the Bus and needs to start a bus access, the address state is entered, ADS# or ALE is asserted, and a valid address is presented on the address/data bus. Data is then transferred while in a data/wait state. READY# or WAITo# is used to insert wait states. BLAST# is asserted during the last data/wait state to signify the last transfer of the access. After all data has been transferred, the bus enters the recovery state to allow
2.2.3
* Clock
Local Bus Signals
There are four groups of Local Bus signals: * Address/Data * Control/Status * Arbitration Signal usage varies upon application.
2-2
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Local Bus
Section 2 PCI and Local Bus
2.2.3.1
Clock
2.2.3.3
Control/Status
2.2.3.2 2.2.3.2.1
Address/Data LAD[31:0] (Multiplexed Bus)
2.2.3.3.2
LBE[3:0]#
The LAD[31:0] bus is a 32-bit multiplexed address/ data bus. During an Address phase, LAD[27:2] contains the word address of the transfer.
Note: Dedicated address pins are available.
During an Address phase, the LBE[3:0]# byte enables denote which byte lanes are being used during access of a 32-bit bus. They remain asserted until the end of the data transfer.
During Data phases, LAD[31:0], LAD[15:0], or LAD[7:0] contain transfer data for a 32-, 16-, or 8-bit bus, respectively. If the bus is 8- or 16-bit wide, the data supplied by the PCI 9030 is replicated across the entire 32-bit wide bus.
2.2.3.3.3
LW/R#
2.2.3.2.2
LD[31:0] (Non-Multiplexed Bus)
During an Address phase, LW/R# is driven to a valid state, and signifies direction of the data transfer. Since the PCI 9030 is the Local Bus master, LWR# is driven high when the PCI 9030 is writing data to a Local Bus, and low when it is reading the bus.
2.2.3.3.4
READY#
The LD[31:0] bus is a 32-bit non-multiplexed data bus. During Data phases, LD[31:0], LD[15:0], or LD[7:0] contain transfer data for a 32-, 16-, or 8-bit bus, respectively. If the bus is 8- or 16-bit wide, the data supplied by the PCI 9030 is replicated across the entire 32-bit wide bus.
2.2.3.2.3
LA[27:2] (Non-Multiplexed Bus)
LA[27:2] contains the word address of the transfer.
The READY# input pin has a corresponding Enable bit in the Configuration registers for each Local address space. If READY# is enabled, this indicates that Write data is being accepted or Read data is being provided by the bus slave. If a Bus Slave needs to insert wait states, it can de-assert READY# until it is ready to accept or provide data. If READY# is disabled, then the length of the Local Bus transfer can be determined by internal wait state generators. (Refer to Table 2-3.)
Table 2-3. READY Data Transfers
Master Device Slave Device READY# Input Enable
0 PCI 9030 Address spaces 1 Sampled
READY# Signal
Ignored
Description
READY# is not sampled by the PCI 9030. Data transfers determined by the internal wait state generator. READY# is ignored and the Data transfer takes place after the internal wait state counter expires. READY# is sampled by the PCI 9030. Data transfers are determined by an external device, which asserts READY# to indicate a Data transfer is taking place.
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
2-3
Section 2--PCI & Local Bus
LCLK, the Local Bus clock, operates at frequencies up to 60 MHz, and is asynchronous to the PCI Bus clock. Most Local Bus signals are driven and sampled on the rising edge of LCLK. Setup and hold times, with respect to LCLK, must be observed. (Refer to Section 12.2 for setup and hold timing requirements.)
The control/status signals control the address latches and flow of data across the Local Bus.
2.2.3.3.1
ADS#, ALE
A Local Bus access starts when ADS# (address/data status) is asserted during an address state by the Local Bus Master. ALE is used to strobe the LA/LAD Bus into an external address latch.
Section 2 PCI and Local Bus
Local Bus
2.2.3.3.5
WAITo#
Because the PCI 9030 is the Local Bus Master, WAITo# is an output that provides status of the internal wait state generators. It is asserted while internal wait states are being inserted. READY# as an input is not sampled until WAITo# is de-asserted.
selected through the MODE pin, corresponding to two bus types--Multiplexed and Non-Multiplexed.
Notes: No PCI Initiator capability.
Internal registers are not readable/writable from the Local Bus. The internal registers are accessible from the Host CPU on the PCI Bus or from the serial EEPROM.
2.2.3.3.6
LLOCKo#
Table 2-4. Local Bus Types
MODE Pin
1 0
When the PCI 9030 owns the Local Bus, LLOCKo# is asserted to indicate that an atomic operation for a PCI Target access may require multiple transactions to complete. LLOCKo# is asserted during the Address phase of the first transaction of the atomic operation, and de-asserted one clock after the last transaction of the atomic operation is complete. If enabled, the Local Bus arbiter does not grant the Bus to another Master until the atomic operation is complete.
Mode
Multiplexed Non-Multiplexed
Bus Type
32-bit multiplexed 32-bit non-multiplexed
2.2.4.1
Local Bus Arbitration
2.2.3.3.7
WR#
WR# is a general purpose write output strobe. The timing is controlled by the current Bus Region Descriptor register. The WR# strobe is asserted during the entire data transfer.
2.2.3.3.8
RD#
RD# is a general purpose read output strobe. The timing is controlled by the current Bus Region Descriptor register. The RD# strobe is asserted during the entire data transfer.
The PCI 9030 is the Local Bus Master. When the PCI Bus initiates a new transfer request, the PCI 9030 takes Local Bus control. Another device can gain Local Bus control by asserting LREQ. If the PCI 9030 has no cycles to run, it asserts LGNT, transferring control to the external master. If the PCI 9030 requires the Local Bus before the external master has completed, LGNT is de-asserted (default preempt condition). The PCI 9030 Local Bus Arbiter also allows the LGNT signal to remain active until the external Local Bus Master completes the transfer, although the PCI 9030 has a PCI Target transaction pending (CNTRL[7]; 50h). The arbiter waits for LREQ to de-assert before taking control of the bus.
2.2.4.2 2.2.3.3.9 LREQ
LREQ is asserted by a Local Bus Master to request Local Bus use.
Wait State Control
The following figure illustrates wait state control.
PCI Bus Local Bus
2.2.3.3.10 LGNT
LGNT is asserted by the PCI 9030 to grant control of the Local Bus to a Local Bus Master. When the PCI 9030 requires the Local Bus, it can signal a preempt by de-asserting LGNT, if configured to do so in the Configuration register.
Accessing PCI 9030 from PCI Bus PCI 9030 accessing Local Bus PCI 9030 de-asserts TRDY# when waiting on the Local Bus PCI Bus de-asserts IRDY# for wait states or simply ends the cycle when it's not ready
PCI 9030
PCI 9030 generates wait states with WAITo# (programmable) Local Bus can respond to PCI 9030 requests with READY#
2.2.4
Local Bus Interface and Bus Cycles
Figure 2-2. Wait States
Note: The figure represents a sequence of Bus cycles.
The PCI 9030 is the Local Bus Master. The PCI 9030 interfaces a PCI Host Bus to two Local Bus types, as listed in Table 2-4. It operates in one of two modes,
2-4
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Local Bus
Section 2 PCI and Local Bus
If READY# mode is disabled, the external READY# input signal has no effect on wait states for a Local access. Wait states between Data cycles are asserted internally by a wait state counter. The wait state counter is initialized with its Configuration register value at the start of each data access. If READY# mode is enabled and the internal wait state counter is zero (default value), the READY# input controls the number of additional wait states. If READY# mode is enabled and the internal wait state counter is programmed to a non-zero value, READY# has no effect until the wait state counter reaches 0. When it reaches 0, the READY# input controls the number of additional wait states. If the internal wait state counter is programmed to a non-zero value and BTERM# is enabled, BTERM# input is not sampled until the wait state counter reaches 0.
2.2.4.3.1
Burst and Bterm Modes
As an input, BTERM# is asserted by external logic. It instructs the PCI 9030 to break up a Burst cycle.
Table 2-5. Burst and Bterm on the Local Bus
Mode Burst
0 Single Cycle 0 Burst-4 Lword Continuous Burst 1 1 0
Bterm
0
Result Section 2--PCI & Local Bus
One ADS# per data (default) One ADS# per data One ADS# per four data One ADS# per BTERM# (refer to Section 2.2.4.3.2.1)
1
1
On the Local Bus, BLAST# and BTERM# perform the following: * If the Burst Mode bit is enabled, but the Bterm Mode bit is disabled, the PCI 9030 bursts (up to four Data phases). BLAST# is asserted at the beginning of the fourth Lword Data phase (LA[3:2]=11) and a new ADS# is asserted at the first Lword (LA[3:2]=00) of the next burst. * If BTERM# is enabled and asserted, the PCI 9030 terminates the Burst cycle at the end of the current Data phase without generating BLAST#. The PCI 9030 generates a new burst transfer, starting with a new ADS#, terminating it normally using BLAST#. * The BTERM# input is valid only when the PCI 9030 is performing a PCI Target transaction. * BTERM# is used to indicate a Memory access is crossing a page boundary or requires a new Address cycle. * If the internal wait state counter is programmed to a non-zero value and BTERM# is enabled, the BTERM# input is not sampled until the wait state counter reaches 0. * BTERM# always overrides READY#, even if both signals are asserted. BTERM# executes the ongoing transaction and causes the PCI 9030 to initiate a new Address/Data cycle for Burst transactions.
Note: If the Bterm Mode bit is disabled, the PCI 9030 performs the following: * * * 32-bit Local Bus--Bursts up to four Lwords 16-bit Local Bus--Bursts up to two Lwords 8-bit Local Bus--Bursts up to one Lword
2.2.4.2.1
Wait States--Local Bus
In PCI Target mode, the PCI 9030 as a Local Bus Master inserts internal wait states with the WAITo# signal. The Local Memory Controller can assert external wait states by delaying the READY# signal. The following Internal Wait State bit(s) can be used to program the number of internal wait states between the first address-to-data state (and subsequent data-to-data in Burst mode): * LAS0BRD[10:6, 12:11, 19:15, 21:20], * LAS1BRD1[10:6, 12:11, 19:15, 21:20], * LAS2BRD[10:6, 12:11, 19:15, 21:20], and/or * LAS3BRD[10:6, 12:11, 19:15, 21:20]
2.2.4.3
Burst Mode and Continuous Burst Mode (Bterm "Burst Terminate" Mode)
Note: In the following sections, Bterm refers to the PCI 9030 internal register bit and BTERM# refers to the PCI 9030 external signal.
In every case, it performs four data beats.
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
2-5
Section 2 PCI and Local Bus
Local Bus
2.2.4.3.2
Burst-4 Lword Mode
If the Burst Mode bit is enabled and the Bterm Mode bit is disabled, bursting can start on any Lword boundary and continue up to a 16-byte address boundary. After data up to the boundary is transferred, the PCI 9030 asserts a new Address cycle (ADS#).
Table 2-6. Burst-4 Lword Mode
Bus Width
32 bit 16 bit 8 bit
Burst Start addresses can be any Lword boundary. If the Burst Start address in a PCI Target transfer is not aligned to an Lword boundary, the PCI 9030 first performs a Single cycle. It then starts to burst on the Lword boundary.
2.2.4.4
Recovery States (Multiplexed Mode Only)
Burst
Four Lwords or up to a quad Lword boundary (LA3, LA2 = 11) Four words or up to a quad word boundary (LA2, LA1 = 11) Four bytes or up to a quad byte boundary (LA1, LA0 = 11)
In Multiplexed mode, the PCI 9030 inserts one recovery state between the last Data transfer and the next Address cycle. The recovery state prevents possible bus contention during the completion of a Read cycle. If the PCI 9030 began driving the bus prior to the Slave device providing the Read data, bus contention could occur.
Note: The PCI 9030 does not support the i960J function that uses the READY# input to add recovery states. No additional recovery states are added if the READY# input remains asserted during the last Data cycle.
2.2.4.3.2.1 Continuous Burst Mode (Bterm "Burst Terminate" Mode)
If both the Burst and Bterm Mode bits are enabled, the PCI 9030 can operate beyond the Burst-4 Lword mode. Bterm mode enables the PCI 9030 to perform long bursts to devices that can accept bursts of longer than four Lwords. The PCI 9030 asserts one Address cycle and continues to burst data. If a device requires a new Address cycle (ADS#), it can assert the BTERM# input to cause the PCI 9030 to assert a new Address cycle. The BTERM# input acknowledges the current Data transfer (replacing READY#) and requests that a new Address cycle be asserted (ADS#). The new address is for the next Data transfer. If the Bterm Mode bit is enabled and the BTERM# signal is asserted, the PCI 9030 asserts BLAST# only if its Read FIFO is full, its Write FIFO is empty, or a transfer is complete.
2.2.4.5
Local Bus Read Accesses
For all Single-Cycle Local Bus Read accesses, the PCI 9030 reads only bytes corresponding to byte enables requested by a PCI Initiator. For all Burst Read cycles, the PCI 9030 can be programmed to: * Perform PCI Target Delayed Reads * Perform PCI Target Read Ahead * Generate internal wait states * Enable external wait control (READY# input) * Enable type of Burst mode to perform
2.2.4.6
Local Bus Write Accesses
2.2.4.3.3
Partial Lword Accesses
For Local Bus writes, only bytes specified by a PCI Bus Master are written. For all Burst Write cycles, the PCI 9030 can be programmed to: * Perform PCI Target Delayed Writes * Generate internal wait states * Enable external wait control (READY# input)
Partial Lword accesses are Lword accesses in which not all byte enables are asserted.
Table 2-7. PCI Target Single and Burst Reads
Bus
32-, 16-, or 8-bit Local Bus
PCI Target Single Reads
Passes the byte enables
PCI Target Burst Reads
Ignores the byte enables and all 32-bit data is passed
2-6
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Local Bus
Section 2 PCI and Local Bus
2.2.5
Local Bus Big/Little Endian Mode
For each of the following transfer types, the PCI 9030 Local Bus can be independently programmed to operate in Little Endian or Big Endian mode: * PCI Target accesses to Local Address Space 0 * PCI Target accesses to Local Address Space 1 * PCI Target accesses to Local Address Space 2 * PCI Target accesses to Local Address Space 3 * PCI Target accesses to Expansion ROM
Notes: The PCI Bus is always Little Endian. Only byte lanes are swapped, not individual bits.
The following table lists PCI Target cycle register information.
Table 2-10. Cycle Reference Table
Cycle Register Bits
LAS0BRD[24] Space 0 LAS1BRD[24] Space 1 LAS2BRD[24] Space 2 LAS3BRD[24] Space 3 EROMBRD[24] Expansion ROM
In Big Endian mode, the PCI 9030 transposes data byte lanes. Data is transferred as listed in Table 2-11 through Table 2-15.
The PCI 9030 Local Bus can be programmed to operate in Big or Little Endian mode, as shown in Table 2-8 and Table 2-9.
Table 2-8. Byte Number and Lane Cross-Reference-- Multiplexed Mode
Byte Number Big Endian
3 2 1 0
2.2.5.1
32-Bit Local Bus--Big Endian Mode
Data is Lword aligned to the uppermost byte lane (Address Invariance).
Table 2-11. Upper Lword Lane Transfer-- 32-Bit Local Bus
Burst Order Byte Lane
PCI Byte 0 appears on Local Data [31:24] PCI Byte 1 appears on Local Data [23:16] First Transfer
Little Endian
0 1 2 3
Byte Lane
LAD[7:0] LAD[15:8] LAD[23:16] LAD[31:24]
Table 2-9. Byte Number and Lane Cross-Reference-- Non-Multiplexed Mode
Byte Number Big Endian
3 2 1 0
PCI Byte 2 appears on Local Data [15:8] PCI Byte 3 appears on Local Data [7:0]
Little Endian
0 1 2 3
Byte Lane
31
LD[7:0] LD[15:8] LD[23:16] LD[31:24]
Little Endian BYTE 3 BYTE 2 BYTE 1 BYTE 0
0
31 BYTE 0 BYTE 1 BYTE 2 BYTE 3
0
Big Endian
Figure 2-3. Big/Little Endian--32-Bit Local Bus
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
2-7
Section 2--PCI & Local Bus
PCI Target
Section 2 PCI and Local Bus
Local Bus
2.2.5.2
16-Bit Local Bus--Big Endian Mode
2.2.5.3
8-Bit Local Bus--Big Endian Mode
For a 16-bit Local Bus, the PCI 9030 can be programmed to use upper or lower word lanes.
Table 2-12. Upper Word Lane Transfer-- 16-Bit Local Bus
Burst Order
First Transfer
For an 8-bit Local Bus, the PCI 9030 can be programmed to use upper or lower byte lanes.
Table 2-14. Upper Byte Lane Transfer-- 8-Bit Local Bus
Burst Order
First transfer Second transfer Third transfer Fourth transfer
Byte Lane
Byte 0 appears on Local Data [31:24] Byte 1 appears on Local Data [23:16]
Byte Lane
Byte 0 appears on Local Data [31:24] Byte 1 appears on Local Data [31:24] Byte 2 appears on Local Data [31:24] Byte 3 appears on Local Data [31:24]
Second Transfer
Byte 2 appears on Local Data [31:24] Byte 3 appears on Local Data [23:16]
Table 2-13. Lower Word Lane Transfer-- 16-Bit Local Bus
Burst Order
First Transfer
Table 2-15. Lower Byte Lane Transfer-- 8-Bit Local Bus
Burst Order
First Transfer Second Transfer Third Transfer Fourth Transfer
Byte Lane
Byte 0 appears on Local Data [15:8] Byte 1 appears on Local Data [7:0]
Byte Lane
Byte 0 appears on Local Data [7:0] Byte 1 appears on Local Data [7:0] Byte 2 appears on Local Data [7:0] Byte 3 appears on Local Data [7:0]
Second Transfer
Byte 2 appears on Local Data [15:8] Byte 3 appears on Local Data [7:0]
31 BYTE 3
Little Endian BYTE 2 BYTE 1
First Cycle
31 0 BYTE 0
Third Cycle
Little Endian BYTE 3 BYTE 2 BYTE 1
Second Cycle
0 BYTE 0
First Cycle
15
Second Cycle
0 BYTE 0 BYTE 1 0 Big Endian
7 BYTE 0
0
Fourth Cycle
31 BYTE 0 15 Big Endian BYTE 1
15 16
23 31 24 7 BYTE 0 7 0
16 BYTE 0 7
15 8 BYTE 0 7 0
0
0
0 Big Endian
Figure 2-4. Big/Little Endian--16-Bit Local Bus Figure 2-5. Big/Little Endian--8-Bit Local Bus
2-8
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
3
SERIAL EEPROM RESET AND INITIALIZATION
After a PCI reset and serial EEPROM load, the software determines the amount of required address space by writing all ones (1) to a PCI Base Address register and then reading back the value. The PCI 9030 returns zeroes (0) in the Don't Care Address bits, effectively specifying the address space required, at which time the PCI software maps the Local Address space into the PCI Address space by programming the PCI Base Address register. (Refer to Figure 3-1.)
Functional operation described can be modified through the PCI 9030 programmable internal registers.
3.1
OVERVIEW
The PCI 9030 initialization procedures follow these steps:
1. 2. 3. 4. 5. Power on Reset PCI 9030 initialization Serial EEPROM Internal Register Access
3.4 3.4.1
SERIAL EEPROM Vendor ID and Device ID Registers
3.2.1
PCI Bus RST# Input
* PCIIDR--Contains the normal Device and Vendor IDs. Can be loaded from the serial EEPROM or Local processor(s). * PCISVID--Contains the Subsystem and Subsystem Vendor IDs. Can be loaded from the serial EEPROM.
The PCI Bus RST# input pin is a PCI Host reset. It causes all PCI Bus outputs to float, resets the entire PCI 9030 and causes the Local reset LRESETo# signal to be asserted.
3.4.1.1 3.2.2 Software Reset
A Host on the PCI Bus can set the PCI Adapter Software Reset bit (CNTRL[30]; 50h) to reset the PCI 9030 and assert LRESETo#. The PCI and Local Configuration register contents are not reset as a result. When the Software Reset bit is set (CNTRL[30]=1), the PCI 9030 responds only to Configuration register accesses, and not to Local Bus accesses. The PCI 9030 remains in this reset condition until the PCI Host clears the bit (CNTRL[30]=0).
Serial EEPROM Initialization
During serial EEPROM initialization, the PCI 9030 responds to PCI Target accesses with a Retry.
3.4.2
Serial EEPROM Operation
3.3
PCI 9030 INITIALIZATION
The PCI 9030 Configuration registers can be programmed by an optional serial EEPROM. The serial EEPROM can be reloaded by setting the Reload Configuration Registers bit (CNTRL[29]; 50h). The PCI 9030 retries all PCI cycles until either the blank serial EEPROM is detected or the serial EEPROM configuration is complete.
After reset, the PCI 9030 attempts to read the serial EEPROM to determine its presence. An active start bit set to 0 indicates a serial EEPROM is present. The PCI 9030 supports 93CS56L (2K bit) or 93CS66L (4K bit). (Refer to manufacturer's data sheet for the particular serial EEPROM being used.) The first 33 bits are then checked to verify that the serial EEPROM is programmed. If the first 33 bits are all ones, a blank serial EEPROM is present. For blank serial EEPROM conditions, the PCI 9030 reverts to the default values (refer to Table 3-1). When the Serial EEPROM Valid bit is set to 1 (CNTRL[28]=1), if programmed, real or random data is detected in the serial EEPROM.
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
3-1
Section 3--Serial EEPROM
3.2
RESET OPERATION
The PCI 9030 supports two Vendor ID and Device ID registers:
Section 3 Serial EEPROM Reset and Initialization
Serial EEPROM
PCI Bus Master
Serial EEPROM 1
Initialize Local Direct Access Registers
Range for PCI-to-Local Address Space 0, 1, 2, and 3 Local Base Address (Remap) for PCI-to-Local Address Space 0, 1, 2, and 3 Bus Region Descriptors for PCI-to-Local Accesses
2
Initialize PCI Base Address Registers
Range for PCI-to-Local Expansion ROM Local Base Address (Remap) for PCI-to-Local Expansion ROM Bus Region Descriptors for PCI-to-Local Accesses
Local Bus Hardware Characteristics
PCI Base Address to Local Address Space 0, 1, 2, and 3 PCI Base Address to Local Expansion ROM
3
PCI Bus Access
4 FIFOs
32-Lword Deep Write 16-Lword Deep Read Local Bus Access
PCI Address Space
PCI Base Address Local Base Address
Local Memory
Range
Figure 3-1. Local Bus PCI Target Access
3-2
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Serial EEPROM
Section 3 Serial EEPROM Reset and Initialization
An active start bit set to 1 indicates that a serial EEPROM is not present. For missing serial EEPROM conditions, the PCI 9030 stops the serial EEPROM load and reverts to the default values within 13 serial EEPROM clocks (EESK). The 3.3V serial EEPROM clock is derived from the PCI clock. The PCI 9030 generates the serial EEPROM clock by internally dividing the PCI clock by 132.
3.4.2.1
Serial EEPROM Load
The registers listed in Table 3-2 are loaded from the serial EEPROM after a reset is de-asserted. The serial EEPROM is organized in words (16 bit). The PCI 9030 first loads the Most Significant Word bits (MSW[31:16]), starting from the most significant bit ([31]). The PCI 9030 then loads the Least Significant Word bits (LSW[15:0]), starting again from the most significant bit ([15]). Therefore, the PCI 9030 loads the Device ID, Vendor ID, class code, and so forth. The serial EEPROM values can be programmed using a Data I/O programmer. The values can also be programmed using the PCI 9030 VPD function (refer to Section 9) or through the Serial EEPROM Control register (CNTRL). The CNTRL register allows programming of the serial EEPROM, one bit at a time. To read back the value from the serial EEPROM, the Vital Product Data (VPD) function should be utilized. With full utilization of VPD, the designer can perform reads and writes from/to the serial EEPROM, 32 bits at a time. Values should be programmed in the order listed in Table 3-2. The 68, 16-bit words listed in the table are stored sequentially in the serial EEPROM.
Table 3-1. Serial EEPROM Guidelines
Serial EEPROM
None Programmed Blank
PCI 9030 System Boot Condition
Uses default values (Start bit is 1). Boots with serial EEPROM values (Start bit is 0). Detects a blank device and reverts to default values (Start bit is 0).
The serial EEPROM can be read or written from the PCI Bus. The Serial EEPROM Control Register bits (CNTRL[28:24]) control the PCI 9030 pins that enable reading or writing of serial EEPROM data bits. (Refer to manufacturer's data sheet for the particular serial EEPROM being used.) The serial EEPROM can also be read or written, using the VPD function (refer to Section 9). The PCI 9030 loads 34 Lwords from the serial EEPROM.
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
3-3
Section 3--Serial EEPROM
Section 3 Serial EEPROM Reset and Initialization
Serial EEPROM
Table 3-2. Serial EEPROM Register Load Sequence
Serial EEPROM Offset
00h 02h 04h 06h 08h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 1Eh 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h 36h 38h 3Ah 3Ch 3Eh
Register Offset
PCI 02h PCI 00h PCI 06h PCI 04h PCI 0Ah PCI 08h PCI 2Eh PCI 2Ch PCI 36h PCI 34h PCI 3Eh PCI 3Ch PCI 42h PCI 40h PCI 46h PCI 44h PCI 4Ah PCI 48h PCI 4Eh PCI 4Ch Local 02h Local 00h Local 06h Local 04h Local 0Ah Local 08h Local 0Eh Local 0Ch Local 12h Local 10h Local 16h Local 14h Device ID Vendor ID PCI Status PCI Command Class Code Class Code / Revision Subsystem ID Subsystem Vendor ID
Register Description
Register Bits Affected
PCIIDR[31:16] PCIIDR[15:0] PCISR[15:0] Reserved PCICCR[15:0] PCICCR[7:0] / PCIREV[7:0] PCISID[15:0] PCISVID[15:0] Reserved CAP_PTR[7:0] Reserved PCIIPR[7:0] / PCIILR [7:0] PMC[14:11, 5, 3:0] PMNEXT[7:0] / PMCAPID[7:0] Reserved PMCSR[14:8] Reserved HS_NEXT[7:0] / HS_CNTL[7:0] Reserved PVPD_NEXT[7:0] / PVPDCNTL[7:0] LAS0RR[31:16] LAS0RR[15:0] LAS1RR[31:16] LAS1RR[15:0] LAS2RR[31:16] LAS2RR[15:0] LAS3RR[31:16] LAS3RR[15:0] EROMRR[31:16] EROMRR[15:0] LAS0BA[31:16] LAS0BA[15:0]
MSB New Capability Pointer LSB New Capability Pointer (Maximum Latency and Minimum Grant are not loadable) Interrupt Pin (Interrupt Line Routing is not loadable) MSW of Power Management Capabilities LSW of Power Management Next Capability Pointer / Power Management Capability ID MSW of Power Management Data / PMCSR Bridge Support Extension LSW of Power Management Control/Status MSW of Hot Swap Control/Status LSW of Hot Swap Next Capability Pointer / Hot Swap Control PCI Vital Product Data Address PCI Vital Product Data Next Capability Pointer/ PCI Vital Product Data Control MSW of Range for PCI-to-Local Address Space 0 LSW of Range for PCI-to-Local Address Space 0 MSW of Range for PCI-to-Local Address Space 1 LSW of Range for PCI-to-Local Address Space 1 MSW of Range for PCI-to-Local Address Space 2 LSW of Range for PCI-to-Local Address Space 2 MSW of Range for PCI-to-Local Address Space 3 LSW of Range for PCI-to-Local Address Space 3 MSW of Range for PCI-to-Local Expansion ROM LSW of Range for PCI-to-Local Expansion ROM MSW of Local Base Address (Remap) for PCI-to-Local Address Space 0 LSW of Local Base Address (Remap) for PCI-to-Local Address Space 0
3-4
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Serial EEPROM
Section 3 Serial EEPROM Reset and Initialization
Table 3-2. Serial EEPROM Register Load Sequence (Continued)
Serial EEPROM Offset
40h 42h 44h 46h 48h 4Ah 4Ch 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h 7Ah 7Ch 7Eh
Register Offset
Local 1Ah Local 18h Local 1Eh Local 1Ch Local 22h Local 20h Local 26h Local 24h Local 2Ah Local 28h Local 2Eh Local 2Ch Local 32h Local 30h Local 36h Local 34h Local 3Ah Local 38h Local 3Eh Local 3Ch Local 42h Local 40h Local 46h Local 44h Local 4Ah Local 48h Local 4Eh Local 4Ch Local 52h Local 50h Local 56h Local 54h
Register Description
MSW of Local Base Address (Remap) for PCI-to-Local Address Space 1 LSW of Local Base Address (Remap) for PCI-to-Local Address Space 1 MSW of Local Base Address (Remap) for PCI-to-Local Address Space 2 LSW of Local Base Address (Remap) for PCI-to-Local Address Space 2 MSW of Local Base Address (Remap) for PCI-to-Local Address Space 3 LSW of Local Base Address (Remap) for PCI-to-Local Address Space 3 MSW of Local Base Address (Remap) for PCI-to-Local Expansion ROM LSW of Local Base Address (Remap) for PCI-to-Local Expansion ROM MSW of Bus Region Descriptors for Local Address Space 0 LSW of Bus Region Descriptors for Local Address Space 0 MSW of Bus Region Descriptors for Local Address Space 1 LSW of Bus Region Descriptors for Local Address Space 1 MSW of Bus Region Descriptors for Local Address Space 2 LSW of Bus Region Descriptors for Local Address Space 2 MSW of Bus Region Descriptors for Local Address Space 3 LSW of Bus Region Descriptors for Local Address Space 3 MSW of Bus Region Descriptors for Expansion ROM LSW of Bus Region Descriptors for Expansion ROM MSW of Chip Select (CS) 0 Base and Range LSW of Chip Select (CS) 0 Base and Range MSW of Chip Select (CS) 1 Base and Range LSW of Chip Select (CS) 1 Base and Range MSW of Chip Select (CS) 2 Base and Range LSW of Chip Select (CS) 2 Base and Range MSW of Chip Select (CS) 3 Base and Range LSW of Chip Select (CS) 3 Base and Range Serial EEPROM Write-Protected Address Boundary LSW of Interrupt Control/Status Register MSW of PCI Target Response, Serial EEPROM, and Initialization Control LSW of PCI Target Response, Serial EEPROM, and Initialization Control MSW of General Purpose I/O Control LSW of General Purpose I/O Control
Register Bits Affected
LAS1BA[31:16] LAS1BA[15:0] LAS2BA[31:16] LAS2BA[15:0] LAS3BA[31:16] LAS3BA[15:0] EROMBA[31:16] EROMBA[15:0] LAS0BRD[31:16] LAS0BRD[15:0]
LAS1BRD[15:0] LAS2BRD[31:16] LAS2BRD[15:0] LAS3BRD[31:16] LAS3BRD[15:0] EROMBRD[31:16] EROMBRD[15:0] CS0BASE[31:16] CS0BASE[15:0] CS1BASE[31:16] CS1BASE[15:0] CS2BASE[31:16] CS2BASE[15:0] CS3BASE[31:16] CS3BASE[15:0] PROT_AREA[7:0] INTCSR[15:0] CNTRL[31:16] CNTRL[15:0] GPIOC[31:16] GPIOC[15:0]
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
3-5
Section 3--Serial EEPROM
LAS1BRD[31:16]
Section 3 Serial EEPROM Reset and Initialization
Internal Register Access
Table 3-2. Serial EEPROM Register Load Sequence (Continued)
Serial EEPROM Offset
80h 82h 84h
Register Offset
Local 72h Local 70h Local 76h
Register Description
Register Bits Affected
PMDATA[7:0] hidden, D0 and D3hot Power Dissipated PMDATA[7:0] hidden, D0 and D3hot Power Consumed Reserved PMCSR[14:13] hidden, Bits [7:0] are used as follows: [7:6] D3hot Power Dissipated, [5:4] D0 Power Dissipated, [3:2] D3hot Power Consumed, [1:0] D0 Power Consumed
MSW of Hidden 1 Power Management Data Select (refer to Section 7.2.1) LSW of Hidden 1 Power Management Data Select (refer to Section 7.2.1) MSW of Hidden 2 Power Management Data Scale (refer to Section 7.2.1)
86h
Local 74h
LSW of Hidden 2 Power Management Data Scale (refer to Section 7.2.1)
3.4.2.2
Recommended Serial EEPROMs
3.5
INTERNAL REGISTER ACCESS
The PCI 9030 is designed to use either a 2K-bit (NM93CS56L or compatible) or 4K-bit (NM93CS66L or compatible) device.
Note: The PCI 9030 does not support serial EEPROMs that do not support sequential reads and writes (such as the NM93C56L).
The PCI 9030 provides several internal registers, which allow for maximum flexibility in the bus-interface design and performance. They are accessible from the PCI Bus and include the following registers: * PCI Configuration * Local Configuration * Power Management * Hot Swap * VPD The following figure illustrates how these registers are accessed.
4096
100h
2048 VPD 1536 Empty 992
80h
60h (PROT_AREA register default) 3Eh
PCI Bus Master
Local Bus Master
Load Data
PCI 9030
0
PCI Interrupt
PCI Configuration Registers
0
Figure 3-2. Serial EEPROM Memory Map
Power Management Registers Hot Swap Registers VPD Registers
Figure 3-3. PCI 9030 Internal Register Access
3-6
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Local Interrupt
# of bits
# of words (16-bit data)
Local Configuration Registers
New Capabilities Function Support
Section 3 Serial EEPROM Reset and Initialization
3.5.1
PCI Bus Access to Internal Registers
3.6
NEW CAPABILITIES FUNCTION SUPPORT
The PCI 9030 PCI Configuration registers can be accessed from the PCI Bus with a Configuration Type 0 cycle. All other PCI 9030 internal registers can be accessed by a Memory cycle, with the PCI Bus address that matches the base address specified in PCI Base Address 0 (PCIBAR0[31:4]) for the PCI 9030 MemoryMapped Configuration register. These registers can also be accessed by an I/O cycle, with the PCI Bus address matching the base address specified in PCI Base Address 1 (PCIBAR1[31:2] for the PCI 9030 I/O-Mapped Configuration register. All PCI Read or Write accesses to the PCI 9030 registers can be Byte, Word, or Lword accesses. All PCI Memory accesses to the PCI 9030 registers can be Burst or Non-Burst accesses. The PCI 9030 responds with a PCI disconnect for all Burst I/O accesses (PCIBAR1[31:2]) to the PCI 9030 Internal registers.
The New Capabilities Function Support includes PCI Power Management, Hot Swap, and VPD features, as listed in the following table.
Table 3-3. New Capabilities Function Support Features
New Capability Function
First (Power Management) Second (Hot Swap)
PCI Register Offset Location
40h, which is pointed to, from CAP_PTR [7:0]. 48h, which is pointed to, from PMNEXT[7:0]. 4Ch, which is pointed to, from HS_NEXT[7:0]. Because PVPD_NEXT[7:0] defaults to zero, this indicates that VPD is the last PCI 9030 New Capability Function Support feature.
Third (VPD)
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
3-7
Section 3--Serial EEPROM
Section 3 Serial EEPROM Reset and Initialization
Serial EEPROM and Configuration Initialization Timing Diagrams
3.7
SERIAL EEPROM AND CONFIGURATION INITIALIZATION TIMING DIAGRAMS
0us 10us 20us 30us
EESK LRESETo# EECS EEDI EEDO
1 1 0 A7 A6 A5 A4 A3 A2 A1 A0 0 D15 D14 D13 D12D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 BITS [31:16] CONFIGURATION REGISTER 0 HEX D0
INTERNALLY PULLED UP START BIT 0 INDICATES SERIAL EEPROM PRESENT ----|
EESK EEDO
D15 D14 D13 D12D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BITS [31:16] OF CONFIGURATION REGISTER 8 HEX
BITS [15:0] CONFIGURATION REGISTER 0 HEX
CONTINUES
EESK (continues) EECS EEDO
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 EESK, EEDO, EECS STATUS FROM CONFIGURATION REGISTERS AFTER COMPLETION OF READ
CONTINUES
Timing Diagram 3-1. Initialization from Serial EEPROM (2K or 4K Bit)
3-8
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
0ns
50ns
100ns
150ns
200ns
250ns
CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY#
1
2
3
4
5
6
7
8
ADDR CMD=B
Data BE
Timing Diagram 3-2. PCI Configuration Write to PCI Configuration Register
0ns 50ns 100ns 150ns 200ns 250ns 300n
CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY#
1
2
3
4
5
6
7
8
ADDR CMD=A
Data Read BE
Timing Diagram 3-3. PCI Configuration Read from PCI Configuration Register
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
3-9
Section 3--Serial EEPROM
Section 1--Introduction
Serial EEPROM and Configuration Initialization Timing Diagrams
Section 3 Serial EEPROM Reset and Initialization
Section 3 Serial EEPROM Reset and Initialization
Serial EEPROM and Configuration Initialization Timing Diagrams
0ns
50ns
100ns
150ns
200ns
250ns
CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY#
1
2
3
4
5
6
7
8
ADDR CMD=7
Data BE
Timing Diagram 3-4. PCI Memory Write to Local Configuration Register
0ns
50ns
100ns
150ns
200ns
250ns
CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY#
1
2
3
4
5
6
7
8
ADDR CMD=6 BE
Data Read
Timing Diagram 3-5. PCI Memory Read from Local Configuration Register
3-10
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
0ns
100ns
200ns
300ns
400ns
500
CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY#
ADDR CMD DATA BE
INTA#
Response on the PCI Bus
LCLK LINTi[2:1]
Timing Diagram 3-6. Local Level Triggered Interrupt Asserting PCI Interrupt
0ns
100ns
200ns
300ns
400ns
500
CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY#
Cleared by Configuration Register ADDR CMD DATA BE
INTA#
Response on the PCI Bus
LCLK LINTi[2:1]
Timing Diagram 3-7. Local Edge Triggered Interrupt Asserting PCI Interrupt
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
3-11
Section 3--Serial EEPROM
Section 1--Introduction
Serial EEPROM and Configuration Initialization Timing Diagrams
Section 3 Serial EEPROM Reset and Initialization
4
PCI TARGET (DIRECT SLAVE) OPERATION
For the highest data-transfer rate, the PCI 9030 supports posted writes and can be programmed to prefetch data during a PCI Burst Read. The Prefetch size, when enabled, can be from one to 16 Lwords or until the PCI Bus stops requesting. When the PCI 9030 prefetches, if enabled, it drops the Local Bus read after reaching the prefetch counter. In Continuous Prefetch mode, the PCI 9030 prefetches as long as FIFO space is available and stops prefetching when the PCI Bus terminates the request. If Read prefetching is disabled, the PCI 9030 stops after one Read transfer. In addition to Prefetch mode, the PCI 9030 supports PCI Target Read Ahead mode (refer to Section 4.2.1.3). Each Local space can be programmed to operate in an 8-, 16-, or 32-bit Local Bus width. The PCI 9030 contains an internal wait state generator and external wait state input, READY#. READY# can be disabled or enabled by way of the Internal Configuration registers. With or without wait state(s), the Local Bus, independent of the PCI Bus, can: * Burst as long as data is available (Continuous Burst mode) * Burst four Lwords at a time
Section 4--PCI Target
Functional operation described can be modified through the PCI 9030 programmable internal registers.
4.1
OVERVIEW
PCI Target (Direct Slave) operations originate on the PCI Bus, go through the PCI 9030, and finally access the Local Bus. The PCI 9030 is a PCI Bus Target and a Local Bus Master.
4.2
DIRECT DATA TRANSFER MODE
The PCI 9030 supports PCI Target accesses to Local Memory or I/O Transfer mode.
4.2.1
PCI Target Operation (PCI Master-to-Local Bus Access)
The PCI 9030 supports both Burst Memory-Mapped Transfer accesses and I/O-Mapped, Single-Transfer accesses to the Local Bus from the PCI Bus through a 16-Lword (64-byte) PCI Target Read FIFO and a 32-Lword (128-byte) PCI Target Write FIFO. The PCI Base Address registers are provided to set up the adapter location in the PCI memory and I/O space. In addition, Local Mapping registers allow address translation from the PCI Address Space to the Local Address Space. Five spaces are available: * Space 0 * Space 1 * Space 2 * Space 3 * Expansion ROM space Expansion ROM space is intended to support a bootable ROM device for the Host. For Single-Cycle PCI Target reads, the PCI 9030 reads a single Local Bus Lword or partial Lword. The PCI 9030 disconnects after one transfer for all PCI Target I/O accesses.
* Perform continuous Single cycles
4.2.1.1
PCI Target Lock
The PCI 9030 supports direct PCI-to-Local-Bus Exclusive accesses (locked atomic operations). A PCI-locked operation to the Local Bus results in the entire address Space 0, Space 1, Space 2, Space 3, and Expansion ROM space being locked until they are released by the PCI Bus Master. Locked operations are enabled or disabled with the PCI Target LOCK# Enable bit (CNTRL[23]; 50h) for PCI-to-Local accesses.
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
4-1
Section 4 PCI Target (Direct Slave) Operation
Direct Data Transfer Mode
4.2.1.2
PCI Target Delayed Read Mode
PCI Bus
PCI 9030
PCI Target Read Ahead mode is set in Internal Registers
Local Bus
PCI 9030 prefetches data from Local Bus device
The PCI 9030 can be programmed to perform PCI Target Delayed Reads (CNTRL[14]; 50h) (refer to Figure 4-1). In addition to delayed reads, the PCI 9030 supports the following PCI Local Bus Specification v2.2 functions: * No write while a read is pending (PCI Retry for reads) * Write and flush pending read
PCI Bus
PCI Read request
Read data PCI Bus Master Read returns with "Sequential Address" Prefetched data is stored in the internal FIFO PCI 9030 returns prefetched data immediately from internal FIFO without reading again from the Local Bus
PCI 9030 prefetches more data if FIFO space is available
Read data
PCI 9030
PCI Target Delayed Read Mode bit is set in Internal Registers
Local Bus
PCI 9030 prefetches more data from Local memory
Figure 4-2. PCI Target Read Ahead Mode
Note: The figure represents a sequence of Bus cycles.
PCI Read request PCI 9030 instructs PCI Host to "Retry" Read cycle later PCI Bus is free to perform other cycles during this time PCI Host returns to fetch Read data again Read data is now ready for Host
4.2.1.4
PCI 9030 requests Read data from Local Bus Local memory returns requested data to PCI 9030
PCI Target Delayed Write Mode
Data is stored in 16-Lword Internal FIFO
PCI 9030 returns prefetched data immediately
Figure 4-1. PCI Target Delayed Reads
Note: The figure represents a sequence of Bus cycles.
4.2.1.3
PCI Target Read Ahead Mode
The PCI 9030 supports PCI Target Delayed Write mode transactions, where posted Write data accumulates in the PCI Target Write FIFO before the PCI 9030 requests a Write transaction (ADS# and/or ALE assertion) to be performed on the Local Bus. The PCI Target Delayed Write mode is programmable to delay the ADS# and/or ALE assertion in the amount of Local clocks (CNTRL[11:10]; 50h). This feature is useful for gaining higher throughput during PCI Target Write burst transactions for conditions in which the PCI clock frequency is slower than the Local clock frequency.
The PCI 9030 also supports PCI Target Read Ahead mode (CNTRL[16]; 50h), where prefetched data can be read from the PCI 9030 internal FIFO instead of the Local Bus. The address must be subsequent to the previous address and 32-bit aligned (next address = current address + 4). The PCI Target Read Ahead mode functions can be used with or without the PCI Target Delayed Read mode.
4.2.1.5
PCI Target Local Bus READY# Timeout Mode
The PCI 9030 supports PCI Target Local Bus READY# Timeout mode transactions, where the PCI 9030 asserts an internal READY# signal to recover from stalling the Local and PCI Buses. The PCI Target Local Bus READY# Timeout mode transaction is programmable to select the amount of Local clocks before READY# times out (CNTRL[9:8]; 50h). If a Local Target stalls with a READY# assertion during PCI Target Write transactions, the PCI 9030 empties the Write FIFO by dumping the data into the Local Bus and does not pass an error condition to the PCI Bus Initiator. During PCI Target Read transactions, the PCI 9030 issues a PCI Target Abort
4-2
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Direct Data Transfer Mode
Section 4 PCI Target (Direct Slave) Operation
to the PCI Bus Initiator every time the PCI Target Local Bus READY# Timeout is detected.
Master
FRAME#, C/BE#, AD (addr) IRDY#
Slave
Master
Slave
4.2.1.6
PCI Target Transfer
PCI Bus
A PCI Bus Master addressing the Memory space decoded for the Local Bus initiates transactions. Upon a PCI Read/Write, the PCI 9030 being a Local Bus Master executes a transfer, at which time it reads data into the PCI Target Read FIFO or writes data to the Local Bus. The PCI 9030 is programmable to "disconnect" or "keep" the PCI Bus by generating a wait state(s) and de-asserting TRDY# if the Write FIFO becomes full (CNTRL[22:19]; 50h). For PCI Target writes, the PCI Bus Initiator writes data to the Local Bus. For PCI Target reads, the PCI Bus Initiator reads data from the Local Bus Slave. The PCI 9030 supports on-the-fly Endian conversion for Space 0, Space 1, Space 2, Space 3, and Expansion ROM space. The Local Bus can be Big/ Little Endian by using the programmable internal register configuration.
Note:
Master
FRAME#, C/BE#, AD (addr) IRDY#, AD (data)
PCI 9030
LA, ADS#, LW/R#, BLAST# READY#, LD/LAD TRDY#, AD (data)
Figure 4-4. PCI Target Read
Note: The figures represent a sequence of Bus cycles.
4.2.1.7
PCI Target PCI-to-Local Address Mapping
Five Local Address spaces--Space 0, Space 1, Space 2, Space 3, and Expansion ROM--are accessible from the PCI Bus. Each is defined by a set of three registers: * Local Address Range (LAS0RR, LAS1RR, LAS2RR, LAS3RR, and/or EROMRR)
The PCI Bus is always Little Endian.
Slave Master Slave
* Local Base Address (LAS0BA, LAS1BA, LAS2BA, LAS3BA, and/or EROMBA)
Section 4--PCI Target
* PCI Base Address (PCIBAR2, PCIBAR3, PCIBAR4, PCIBAR5, and/or PCIERBAR)
PCI 9030
LA, ADS#, LW/R# LD/LAD, BLAST# READY#
Local Bus
PCI Bus
DEVSEL#, TRDY#
A fourth register, the Bus Region Descriptor register for PCI-to-Local Accesses (LAS0BRD, LAS1BRD, LAS2BRD, LAS3BRD, and/or EROMBRD), defines the Local Bus characteristics for the PCI Target regions (refer to Figure 4-5). Each PCI-to-Local Address space is defined as part of reset initialization (refer to Section 4.2.1.7.1). These Local Bus characteristics can be modified at any time before actual data transactions.
Figure 4-3. PCI Target Write
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Local Bus
DEVSEL#
4-3
Section 4 PCI Target (Direct Slave) Operation
Direct Data Transfer Mode
4.2.1.7.1 PCI Target Local Bus Initialization
Range--Specifies the PCI Address bits to use for decoding a PCI access to Local Bus space. Each bit corresponds to a PCI Address bit. Bit 31 corresponds to address bit 31. Write 1 to all bits required to be included in decode, and 0 to all others. Remap PCI-to-Local Addresses into a Local Address Space--Bits in this register remap (replace) the PCI Address bits used in decode as the Local Address bits. Local Bus Region Descriptor--Specifies the Local Bus characteristics.
4.2.1.7.2 PCI Target Initialization
After a PCI reset and serial EEPROM load, the software determines the amount of required address space by writing all ones (1) to a PCI Base Address register and then reading back the value. The PCI 9030 returns zeroes (0) in the Don't Care Address bits, effectively specifying the address space required, at which time the PCI software maps the Local Address space into the PCI Address space by programming the PCI Base Address register. (Refer to Figure 4-5.)
PCI Bus Master
Serial EEPROM 1
Initialize Local Direct Access Registers
Range for PCI-to-Local Address Space 0, 1, 2, and 3 Local Base Address (Remap) for PCI-to-Local Address Space 0, 1, 2, and 3 Bus Region Descriptors for PCI-to-Local Accesses
2
Initialize PCI Base Address Registers
Range for PCI-to-Local Expansion ROM Local Base Address (Remap) for PCI-to-Local Expansion ROM Bus Region Descriptors for PCI-to-Local Accesses
Local Bus Hardware Characteristics
PCI Base Address to Local Address Space 0, 1, 2, and 3 PCI Base Address to Local Expansion ROM
3
PCI Bus Access
4 FIFOs
32-Lword Deep Write 16-Lword Deep Read Local Bus Access
PCI Address Space
PCI Base Address Local Base Address
Local Memory
Range
Figure 4-5. Local Bus PCI Target Access
4-4
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Direct Data Transfer Mode
Section 4 PCI Target (Direct Slave) Operation
4.2.1.7.3 PCI Target Byte Enables (Multiplexed Mode)
During a PCI Target transfer, each of five spaces (Space 0, Space 1, Space 2, Space 3, and Expansion ROM space) can be programmed to operate in an 8-, 16-, or 32-bit Local Bus width by encoding the Local Byte Enables (LBE[3:0]#). LBE[3:0]# (PQFP--pins 55, 58-60; BGA--pins M5, P5, M6, N6) are encoded, based on the configured bus width, as follows: 32-Bit Bus--The four-byte enables indicate which of the four bytes are active during a Data cycle: * LBE3# Byte Enable 3--LAD[31:24] * LBE2# Byte Enable 2--LAD[23:16] * LBE1# Byte Enable 1--LAD[15:8] * LBE0# Byte Enable 0--LAD[7:0] 16-Bit Bus--LBE3#, LBE1# and LBE0# are encoded to provide BHE#, LAD1, and BLE#, respectively: * LBE3# Byte High Enable (BHE#)--LAD[15:8] * LBE2# not used * LBE1# Address bit 1 (LAD1) * LBE0# Byte Low Enable (BLE#)--LAD[7:0] 8-Bit Bus--LBE1# and LBE0# are encoded to provide LAD1 and LAD0, respectively: * LBE3# not used * LBE2# not used * LBE1# Address bit 1 (LAD1) * LBE0# Address bit 0 (LAD0)
b. PCI Initialization software writes all ones to the PCI Base Address, then reads it back. * The PCI 9030 returns a value of FFF00000h, at which time the PCI software writes to the PCI Base Address register(s). * PCI Base Address--789XXXXXh (PCI Base Address for Access to the Local Address Space registers, PCIBAR2 and PCIBAR3). For a PCI Direct access to the Local Bus, the PCI 9030 has a 32-Lword (128-byte) Write FIFO and a 16-Lword (64-byte) Read FIFO. The FIFOs enable the Local Bus to operate independent of the PCI Bus. The PCI 9030 can be programmed to return a Retry response or to throttle TRDY# for PCI Bus transactions attempting to write to the PCI 9030 Local Bus when the FIFO is full. For PCI Read transactions from the Local Bus, the PCI 9030 holds off TRDY# while gathering data from the Local Bus. For Read accesses mapped to PCI Memory space, the PCI 9030 prefetches up to 16 Lwords (in Continuous Prefetch mode) from the Local Bus. Unused Read data is flushed from the FIFO. For Read accesses mapped to PCI I/O space, the PCI 9030 does not prefetch Read data. Rather, it breaks each read of a Burst cycle into a Single Address/Data cycle on the Local Bus. The PCI Target Retry Delay Clocks bits (CNTRL[22:19]; 50h) can be used to program the period of time in which the PCI 9030 holds off TRDY#. The PCI 9030 issues a Retry to the PCI Bus Transaction Master when the programmed time period expires. This occurs when the PCI 9030 cannot gain Local Bus control and return TRDY# within the programmed time period or the Local Bus is slowly emptying the Write FIFO, and filling the Read FIFO.
4.2.1.7.4 PCI Target Example
A 1 MB Local Address Space, 12300000h through 123FFFFFh, is accessible from the PCI Bus at PCI addresses 78900000h through 789FFFFFh. a. Local initialization software sets the Range and Local Base Address registers as follows: * Range--FFF00000h (1 MB, decode the upper 12 PCI Address bits) * Local Base Address (Remap)--123XXXXXh, (Local Base Address for PCI-to-Local accesses) [Space Enable bit(s) must be set to be recognized by the PCI Host (LAS0BA[0]=1, LAS1BA[0]=1)]
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
4-5
Section 4--PCI Target
Section 4 PCI Target (Direct Slave) Operation
Response to FIFO Full or Empty
4.2.1.7.5 PCI Target Byte Enables (Non-Multiplexed Mode)
During a PCI Target transfer, each of five spaces (Space 0, Space 1, Space 2, Space 3, and Expansion ROM space) can be programmed to operate in an 8-, 16-, or 32-bit Local Bus width by encoding the Local Byte Enables (LBE[3:0]#). LBE[3:0]# (PQFP--pins 55, 58-60; BGA--pins M5, P5, M6, N6) are encoded, based on the configured bus width, as follows: 32-Bit Bus--The four-byte enables indicate which of the four bytes are active during a Data cycle: * * * * LBE3# Byte Enable 3--LD[31:24] LBE2# Byte Enable 2--LD[23:16] LBE1# Byte Enable 1--LD[15:8] LBE0# Byte Enable 0--LD[7:0]
16-Bit Bus--LBE3#, LBE1# and LBE0# are encoded to provide BHE#, LA1, and BLE#, respectively: * * * * LBE3# Byte High Enable (BHE#)--LD[15:8] LBE2# not used LBE1# Address bit 1 (LA1) LBE0# Byte Low Enable (BLE#)--LD[7:0]
8-Bit Bus--LBE1# and LBE0# are encoded to provide LA1 and LA0, respectively: * * * * LBE3# not used LBE2# not used LBE1# Address bit 1 (LA1) LBE0# Address bit 0 (LA0)
4.3
RESPONSE TO FIFO FULL OR EMPTY
Table 4-1 lists the PCI 9030 response to full or empty FIFOs.
Table 4-1. Response to FIFO Full or Empty
Mode Direction FIFO
Full PCI Target Write PCI-to-Local Empty Full PCI Target Read Local-to-PCI Empty Normal Normal Disconnect or Throttle TRDY#1
PCI Bus
Disconnect or Throttle TRDY#1
Local Bus
De-assert LGNT if Local Bus is busy and wait for LREQ to be de-asserted Normal, assert BLAST# Normal, assert BLAST# Normal
1. Throttle TRDY# depends on the PCI Target Retry Delay Clocks (CNTRL[22:19]).
4-6
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Timing Diagrams
Section 4 PCI Target (Direct Slave) Operation
4.4
TIMING DIAGRAMS
0ns 250ns 500ns
LCLK
Local Bus is requested by another Local Initiator.
LREQ LGNT
De-asserted if PCI 9030 needs to use a Local Bus, else remains high until another Local Initiator is done.
Local Bus
Another Local Initiator Drives Bus
Timing Diagram 4-1. Local Bus Arbitration from the PCI 9030 by Another Local Bus Initiator (LREQ and LGNT)
4.4.1
Serial EEPROM and Configuration Initialization Timing Diagrams
0us 10us 20us 30us
EESK LRESETo# EECS EEDI EEDO
1 1 0 A7 A6 A5 A4 A3 A2 A1 A0 0 D15 D14 D13 D12D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 BITS [31:16] CONFIGURATION REGISTER 0 HEX D0
INTERNALLY PULLED UP START BIT 0 INDICATES SERIAL EEPROM PRESENT ----|
EESK EEDO
D15 D14 D13 D12D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BITS [31:16] OF CONFIGURATION REGISTER 8 HEX
BITS [15:0] CONFIGURATION REGISTER 0 HEX
CONTINUES
EESK (continues) EECS EEDO
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 EESK, EEDO, EECS STATUS FROM CONFIGURATION REGISTERS AFTER COMPLETION OF READ
CONTINUES
Timing Diagram 4-2. Initialization from Serial EEPROM (2K or 4K Bit)
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
4-7
Section 4--PCI Target
Timing Diagrams
Section 4 PCI Target (Direct Slave) Operation
0ns
50ns
100ns
150ns
200ns
250ns
CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY#
1
2
3
4
5
6
7
8
ADDR CMD=B
Data BE
Timing Diagram 4-3. PCI Configuration Write to PCI Configuration Register
0ns
50ns
100ns
150ns
200ns
250ns
300n
CLK FRAME# AD[31:0] C/BE[3:0]# IRDY#
1
2
3
4
5
6
7
8
ADDR CMD=A
Data Read BE
TRDY#
Timing Diagram 4-4. PCI Configuration Read from PCI Configuration Register
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
4-8
Section 4--PCI Target
DEVSEL#
Timing Diagrams
Section 4 PCI Target (Direct Slave) Operation
0ns
50ns
100ns
150ns
200ns
250ns
CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY#
1
2
3
4
5
6
7
8
ADDR CMD=7
Data BE
Timing Diagram 4-5. PCI Memory Write to Local Configuration Register
0ns
50ns
100ns
150ns
200ns
250ns
CLK FRAME# AD[31:0] C/BE[3:0]# IRDY#
1
2
3
4
5
6
7
8
ADDR CMD=6 BE
Data Read
TRDY#
Timing Diagram 4-6. PCI Memory Read from Local Configuration Register
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
4-9
Section 4--PCI Target
DEVSEL#
Section 4 PCI Target (Direct Slave) Operation
Timing Diagrams
0ns
100ns
200ns
300ns
400ns
500n
CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY#
ADDR CMD DATA BE
INTA#
Response on the PCI Bus
LCLK LINTi[2:1]
Timing Diagram 4-7. Local Level Triggered Interrupt Asserting PCI Interrupt
0ns 100ns 200ns 300ns 400ns 500n
CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY#
Cleared by Configuration Register ADDR CMD DATA BE
INTA#
Response on the PCI Bus
LCLK LINTi[2:1]
Timing Diagram 4-8. Local Edge Triggered Interrupt Asserting PCI Interrupt
4-10
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Timing Diagrams
Section 4 PCI Target (Direct Slave) Operation
4.4.2
PCI Target, Multiplexed and Non-Multiplexed Modes
0ns 100ns 200ns 300ns 400ns 500ns
PCLK FRAME# AD[31:0] CBE[3:0]# IRDY# TRDY# DEVSEL# LCLK LREQ LGNT ADS# LA[27:2] LAD/LD[31:0] LBE[3:0]# BLAST# READY# WR# RD# LW/R# CS[1:0]# Note: For Multiplexed mode, use the LAD[31:0] signal for address. For Non-Multiplexed mode, use the LA[27:2] signal for address.
Timing Diagram 4-9. PCI Target Burst Write with Delayed Write and SRAM Chip Select Enabled
AD +4 +8 +C +10 +14 AD D0 D1 D2 D3 D4 D5 BE AD 7 D0 BE D1 D2 D3 D4 D5
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
4-11
Section 4--PCI Target
Section 4 PCI Target (Direct Slave) Operation
Timing Diagrams
0ns
250ns
500ns
PCLK FRAME# AD[31:0] CBE[3:0]# IRDY# TRDY# DEVSEL# LCLK LREQ LGNT ADS# LA[27:2] LAD/LD[31:0] LBE[3:0]# BLAST# READY# WR# RD# LW/R# Note: For Multiplexed mode, use the LAD[31:0] signal for address. For Non-Multiplexed mode, use the LA[27:2] signal for address.
F AD AD D0 0 D1 D2 D3 F AD 7 0 D0 D1 D2 D3
Five Address-to-Data Wait States; One Data-to-Data Wait State; Three Write Strobe Wait States; Two Write Hold Wait States.
Timing Diagram 4-10. PCI Target Burst Write (32-Bit Local Bus)
4-12
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Timing Diagrams
Section 4 PCI Target (Direct Slave) Operation
0ns
100ns
200ns
300ns
400ns
PCLK FRAME# AD[31:0] CBE[3:0]# IRDY# TRDY# DEVSEL# LCLK LREQ LGNT ADS# LA[27:2] LAD/LD[31:0] LBE[3:0]# BLAST# READY# WR# RD# LW/R# Note: For Multiplexed mode, use the LAD[31:0] signal for address. For Non-Multiplexed mode, use the LA[27:2] signal for address.
F
AD 7 0
D0
D1
D2
D3
D4
D5
AD AD 4 6 4 6 4 6 4 6 4 6 4 6
Timing Diagram 4-11. PCI Target Burst Write (16-Bit Local Bus), No Wait States
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
4-13
Section 4--PCI Target
Section 4 PCI Target (Direct Slave) Operation
Timing Diagrams
0ns
250ns
500ns
PCLK FRAME# AD[31:0] CBE[3:0]# IRDY# TRDY# DEVSEL# LCLK LREQ LGNT ADS# LA[27:2] LAD/LD[31:0] LBE[3:0]# BLAST# READY# WR# RD# LW/R# Note: For Multiplexed mode, use the LAD[31:0] signal for address. For Non-Multiplexed mode, use the LA[27:2] signal for address.
F AD AD 4 6 4 6 4 6 4 6 4 6 4 6 AD 7 0 D0 1 2 3 4 5
Timing Diagram 4-12. PCI Target Burst Write (16-Bit Local Bus), One Data-to-Data Wait State
4-14
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Timing Diagrams
Section 4 PCI Target (Direct Slave) Operation
0ns
250ns
500ns
PCLK FRAME# AD[31:0] CBE[3:0]# IRDY# TRDY# DEVSEL# LCLK LREQ LGNT ADS# LA[27:2] LAD/LD[31:0] LBE[3:0]# BLAST# READY# WR# RD# LW/R# Note: For Multiplexed mode, use the LAD[31:0] signal for address. For Non-Multiplexed mode, use the LA[27:2] signal for address.
Timing Diagram 4-13. PCI Target Burst Writes (8-Bit Local Bus), One Data-to-Data Wait State
AD AD C D E F C D E F C D E F AD 7 D0 BE D1 D2
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
4-15
Section 4--PCI Target
Section 4 PCI Target (Direct Slave) Operation
Timing Diagrams
0ns
250ns
500ns
750ns
PCLK FRAME# AD[31:0] CBE[3:0]# IRDY# TRDY# DEVSEL# LCLK LREQ LGNT ADS# LA[27:2] LAD/LD[31:0] LBE[3:0]# BLAST# READY# WR# RD# LW/R# Note: For Multiplexed mode, use the LAD[31:0] signal for address. For Non-Multiplexed mode, use the LA[27:2] signal for address.
F AD AD 4 AD AD 6 AD AD 4 AD AD 6 AD AD 4 AD AD 6 AD AD 4 AD AD 6 AD AD 4 AD AD 6 AD AD 4 AD AD 6 F AD 7 D0 D1 D2 D3 D4 D5 0
Timing Diagram 4-14. PCI Target Single Writes (16-Bit Local Bus)
4-16
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Timing Diagrams
Section 4 PCI Target (Direct Slave) Operation
0ns
250ns
500ns
PCLK FRAME# AD[31:0] CBE[3:0]# IRDY# TRDY# DEVSEL# LCLK LREQ LGNT ADS# LA[27:2] LAD/LD[31:0] LBE[3:0]# BLAST# READY# WR# RD# LW/R# Note: For Multiplexed mode, use the LAD[31:0] signal for address. For Non-Multiplexed mode, use the LA[27:2] signal for address.
AD AD C AD AD D AD AD E AD AD F AD AD C AD AD D AD AD E F AD D0 BE D1
Timing Diagram 4-15. PCI Target Single Writes (8-Bit Local Bus)
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
4-17
Section 4--PCI Target
Section 4 PCI Target (Direct Slave) Operation
Timing Diagrams
0ns
100ns
200ns
300ns
400ns
PCLK FRAME# AD[31:0] CBE[3:0]# IRDY# TRDY# DEVSEL# LCLK LREQ LGNT ADS# LA[27:2] LAD/LD[31:0] LBE[3:0]# BLAST# READY# WR# RD# LW/R# Note: For Multiplexed mode, use the LAD[31:0] signal for address. For Non-Multiplexed mode, use the LA[27:2] signal for address.
AD AD D0 C D E F CD E F C D E F AD
7
D0
D1
D2
Timing Diagram 4-16. PCI Target Single Writes (8-Bit Local Bus), No Wait States
4-18
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Timing Diagrams
Section 4 PCI Target (Direct Slave) Operation
0ns
100ns
200ns
300ns
400ns
PCLK FRAME# AD[31:0] CBE[3:0]# IRDY# TRDY# DEVSEL# LCLK LREQ LGNT ADS# LA[27:2] LAD/LD[31:0] LBE[3:0]# BLAST# READY# LW/R# Note: For Multiplexed mode, use the LAD[31:0] signal for address. For Non-Multiplexed mode, use the LA[27:2] signal for address.
Timing Diagram 4-17. PCI Target Back-to-Back Single Writes
F AD AD D0 0 AD AD D1 0 F AD 7 0 D0 AD 7 0 D1
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
4-19
Section 4--PCI Target
Section 4 PCI Target (Direct Slave) Operation
Timing Diagrams
0ns
250ns
500ns
PCLK FRAME# AD[31:0] CBE[3:0]# IRDY# TRDY# DEVSEL# LCLK LREQ LGNT ADS# LA[27:2] LAD/LD[31:0] LBE[3:0]# BLAST# READY# LW/R# Note: For Multiplexed mode, use the LAD[31:0] signal for address. For Non-Multiplexed mode, use the LA[27:2] signal for address.
Timing Diagram 4-18. PCI Target Back-to-Back Write Followed by a Read
F
AD 7 0
D0
AD 6 0
D0
AD ADD0 0 8
AD ADD0 0 F
4-20
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Timing Diagrams
Section 4 PCI Target (Direct Slave) Operation
0ns
250ns
500ns
750ns
PCLK FRAME# AD[31:0] CBE[3:0]# IRDY# TRDY# DEVSEL# LCLK LREQ LGNT ADS# LA[27:2] LAD/LD[31:0] LBE[3:0]# BLAST# READY# LW/R# Note: For Multiplexed mode, use the LAD[31:0] signal for address. For Non-Multiplexed mode, use the LA[27:2] signal for address.
F AD
AD D0
AD 6 0
D0
AD 7 0
D1
AD
AD D0
0
F
0
F
Timing Diagram 4-19. PCI Target Back-to-Back Read Followed by a Write
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
4-21
Section 4--PCI Target
Section 4 PCI Target (Direct Slave) Operation
Timing Diagrams
0ns
250ns
500ns
750ns
PCLK FRAME# AD[31:0] CBE[3:0]# IRDY# TRDY# DEVSEL# LCLK LREQ LGNT ADS# LA[27:2] LAD/LD[31:0] LBE[3:0]# BLAST# READY# LW/R# Note: For Multiplexed mode, use the LAD[31:0] signal for address. For Non-Multiplexed mode, use the LA[27:2] signal for address.
Timing Diagram 4-20. PCI Target Back-to-Back Reads
F AD
AD 0
AD 6 0
D0
AD 6
D1
AD
AD 0
0
F
0
F
4-22
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Timing Diagrams
Section 4 PCI Target (Direct Slave) Operation
4.4.2.1
PCI Target, Multiplexed Mode Only
0ns
250ns
500ns
CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY#
1
2
3
4
5
6
7
8
ADDR CMD
Data BE
LCLK LREQ LGNT ADS# ALE BLAST# LBE[3:0]# LW/R# LAD[31:0] READY# (input)
A
LBE
Data
Timing Diagram 4-21. PCI Target Single Write (32-Bit Local Bus), Multiplexed Mode Only
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
4-23
Section 4--PCI Target
Section 4 PCI Target (Direct Slave) Operation
Timing Diagrams
0ns
100ns
200ns
300ns
400ns
500ns
CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY#
1
2
3
4
5
6
7
8
14
ADDR CMD BE
Data
LCLK LREQ LGNT ADS# ALE BLAST# LW/R# LBE[3:0]# LAD[31:0] READY# (input)
A LBE Data
Timing Diagram 4-22. PCI Target Single Read (32-Bit Local Bus), Multiplexed Mode Only
4-24
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Timing Diagrams
Section 4 PCI Target (Direct Slave) Operation
0ns
250ns
500ns
LCLK LREQ LGNT ADS# ALE BLAST# LBE[3:0]# LW/R# LAD[31:0] BTERM# (input) READY# (input)
Eight Lword Burst, no wait states, BTERM# (input) enabled, Burst enabled, 32-bit Local Bus. Note: If BTERM# (input) is disabled, a new ADS# cycle starts every quad-Lword boundary. BTERM# (input) replaces READY# (input) when asserted. Section 4--PCI Target
A D0 D1 D2 D3 D4 A+14 D5 D6 D7 DOES NOT CHANGE, UNALIGNED HAS OWN CYCLE WITH ADS#
Timing Diagram 4-23. PCI Target Burst Write with Bterm Enabled (32-Bit Local Bus), Multiplexed Mode Only
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
4-25
Section 4 PCI Target (Direct Slave) Operation
Timing Diagrams
0ns
250ns
500ns
750ns
1000ns
CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY#
ADDR D0 D1 D2 D3 D4 D5 D6 D7
CMD
BE
LCLK LREQ LGNT ADS# ALE BLAST# LAD[31:0] LBE[3:0]# LW/R# READY# (input)
A D0 D1 D2 D3 D4 D5 D6 D7
LBE
Timing Diagram 4-24. PCI Target Burst Read with Prefetch Enabled (32-Bit Local Bus), Prefetch Counter Set to 8, Multiplexed Mode Only
4-26
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Timing Diagrams
Section 4 PCI Target (Direct Slave) Operation
4.4.2.2
PCI Target, Non-Multiplexed Mode Only
0ns
250ns
500ns
CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY#
1
2
3
4
5
6
7
8
ADDR CMD
Data BE
LCLK LREQ LGNT ADS# BLAST# LBE[3:0]# LW/R# LA[27:2] LD[31:0] READY# (input)
ADDR Data
LBE
Timing Diagram 4-25. PCI Target Single Write (32-Bit Local Bus), Non-Multiplexed Mode Only
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
4-27
Section 4--PCI Target
Section 4 PCI Target (Direct Slave) Operation
Timing Diagrams
0ns
100ns
200ns
300ns
LCLK LREQ LGNT ADS# BLAST# LBE[3:0]# LW/R# LA[27:2] LD[15:0] READY# (input)
Timing Diagram 4-26. PCI Target Single Write (16-Bit Local Bus), Non-Multiplexed Mode Only
A D D 0 2
0ns
100ns
200ns
300ns
400ns
LCLK LREQ LGNT ADS# BLAST# LBE[3:0]# LD[7:0]# LW/R# LA[27:2] READY# (input)
Timing Diagram 4-27. PCI Target Single Write (8-Bit Local Bus), Non-Multiplexed Mode Only
A 0 D 1 D 2 D 3 D
4-28
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Timing Diagrams
Section 4 PCI Target (Direct Slave) Operation
0ns
250ns
500ns
CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ADDR CMD BE
DATA
LCLK LREQ LGNT ADS# BLAST# LW/R# LA[27:2] LD[31:0] READY# (input)
Timing Diagram 4-28. PCI Target Single Read (32-Bit Local Bus), Non-Multiplexed Mode Only
ADDR
DATA
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
4-29
Section 4--PCI Target
Section 4 PCI Target (Direct Slave) Operation
Timing Diagrams
0ns
250ns
500ns
CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ADDR CMD BE
DATA
LCLK LREQ LGNT ADS# BLAST# LBE[3:0]# LW/R# LA[27:2] LD[31:0] READY# (input)
ADDR DATA
LBE
Timing Diagram 4-29. PCI Target Single Read with One Wait State Using READY# Input (32-Bit Local Bus), Non-Multiplexed Mode Only
4-30
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Timing Diagrams
Section 4 PCI Target (Direct Slave) Operation
0ns
100ns
200ns
300ns
400ns
500ns
CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ADDR CMD BE
DATA
LCLK LREQ LGNT ADS# BLAST# LBE[3:0]# LW/R# LA[27:2] LD[31:0]
ADDR
LBE
*
DATA
* Note: The PCI 9030 and Local memory will have one wait state without the READY# signal provided.
Timing Diagram 4-30. PCI Target Single Read with One Wait State Using Internal Wait State (32-Bit Local Bus), Non-Multiplexed Mode Only
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
4-31
Section 4--PCI Target
Section 4 PCI Target (Direct Slave) Operation
Timing Diagrams
0ns
250ns
500ns
CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY#
1
2
3
4
5
6
7
8
ADDR CMD
D0 BE
D1
D2
LCLK LREQ LGNT ADS# BLAST# LBE[3:0]# LW/R# LA[27:2] LD[31:0] BTERM# (input) READY# (input)
ADDR D0
LBE
+4
D1
+8
D2
Timing Diagram 4-31. PCI Target Non-Burst Write (32-Bit Local Bus), Non-Multiplexed Mode Only
4-32
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Timing Diagrams
Section 4 PCI Target (Direct Slave) Operation
0ns
100ns
200ns
300ns
400ns
LCLK LREQ LGNT ADS# BLAST# LBE[3:0]# LW/R# LA[27:2] LD[7:0] BTERM# (input) READY# (input)
Timing Diagram 4-32. PCI Target Non-Burst Write (8-Bit Local Bus), Non-Multiplexed Mode Only
D D A D D C D E F
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
4-33
Section 4--PCI Target
Section 4 PCI Target (Direct Slave) Operation
Timing Diagrams
0ns
250ns
500ns
CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY#
1
2
3
4
5
6
7
8
14
ADDR CMD BE
D0
D1
D2
LCLK LREQ LGNT ADS# BLAST# LBE[3:0]# LW/R# LA[27:2] LD[31:0] BTERM# (input) READY# (input) Timing Diagram 4-33. PCI Target Non-Burst Read, Non-Multiplexed Mode Only
ADDR D0 +4 D1 +8 D2
LBE
4-34
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Timing Diagrams
Section 4 PCI Target (Direct Slave) Operation
0ns
250ns
500ns
LCLK LREQ LGNT ADS# BLAST# LBE[3:0]# LW/R# LA[27:2] LD[31:0] BTERM# (input) READY# (input)
A A+4 A+8 A+C A+10 A+14 A+18 A+1C A+20 A+24 A+28 LBE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
Bterm FORCES NEW ADS# -->
Eight Lword Burst, no wait states, Bterm enabled, Burst enabled, 32-bit Local Bus. Note: If Bterm is disabled, a new ADS# cycle starts every quad-Lword boundary.
Timing Diagram 4-34. PCI Target Burst Write with Bterm Enabled (32-Bit Local Bus), Non-Multiplexed Mode Only
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
4-35
Section 4--PCI Target
Section 4 PCI Target (Direct Slave) Operation
Timing Diagrams
0ns
250ns
500ns
LCLK LREQ LGNT ADS# BLAST# LBE[3:0]# LW/R# LA[27:2] LD[31:0] BTERM# (input) READY# (input)
No wait states, Bterm disabled, Burst enabled, 32-bit Local Bus. Unaligned Transfer results in new ADS#. Note: Not all byte enables asserted on a quad boundary LA[3:2]=11 results in a new ADS#.
ADDR D0 A+4 D1 A+8 D2 A+C D3 A+10 D4 A+14 D5 A+18 A+1C D6 D7 A+20 D8 0001 LBE = 0
Timing Diagram 4-35. PCI Target Burst Write with Bterm Disabled (32-Bit Local Bus), Non-Multiplexed Mode Only
4-36
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Timing Diagrams
Section 4 PCI Target (Direct Slave) Operation
0ns
250ns
500ns
CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY#
ADDR CMD BE D0 D1 D2 D3 D4
LCLK LREQ LGNT ADS# BLAST# LBE[3:0]# LW/R# LA[27:2] LD[31:0] READY# (input)
ADDR D0 +4 D1 +8 D2 +12 D3 +16 D4
LBE
+20 +24 +28 D5 D6 D7
Timing Diagram 4-36. PCI Target Burst Read with Prefetch Counter Set to 8 (32-Bit Local Bus), Non-Multiplexed Mode Only
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
4-37
Section 4--PCI Target
Section 4 PCI Target (Direct Slave) Operation
Timing Diagrams
0ns
250ns
500ns
CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY#
ADDR CMD BE D0 D1 D2 D3 D4
LCLK LREQ LGNT ADS# BLAST# LBE[3:0]# LW/R# LA[27:2] LD[31:0] READY# (input)
ADDR D0 +4 D1 +8 D2 +C D3 +10 D4
LBE
Timing Diagram 4-37. PCI Target Burst Read with Prefetch Counter Set to 5 (32-Bit Local Bus), Non-Multiplexed Mode Only
4-38
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Timing Diagrams
Section 4 PCI Target (Direct Slave) Operation
0ns
250ns
500ns
CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY#
1
2
3
4
5
6
7
8
ADDR
DO
D1
D3
D4
CMD
BE
LCLK LREQ LGNT ADS# BLAST# LBE[3:0]# LW/R# LA[27:2] LD[31:0] READY# (input) Five Lwords, one external wait state, Bterm enabled, Burst enabled.
A D0 +4 D1 +8 D2 +C D3 +10 D4
LBE
Timing Diagram 4-38. PCI Target Burst Write (32-Bit Local Bus), Non-Multiplexed Mode Only
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
4-39
Section 4--PCI Target
Section 4 PCI Target (Direct Slave) Operation
Timing Diagrams
0ns
100ns
200ns
300ns
400ns
LCLK LREQ LGNT ADS# BLAST# LBE[3:0]# LW/R# LA[27:2] LD[7:0] BTERM# (input) READY# (input)
D D A D D C D E F
Timing Diagram 4-39. PCI Target Burst Write (16-Bit Local Bus), Non-Multiplexed Mode Only
0ns
100ns
200ns
300ns
400ns
LCLK LREQ LGNT ADS# BLAST# LBE[3:0]# LW/R# LA[27:2] LD[7:0] BTERM# (input) READY# (input) Timing Diagram 4-40. PCI Target Burst Write with External Wait States (8-Bit Local Bus), Non-Multiplexed Mode Only
D D A D D C D E F
4-40
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Timing Diagrams
Section 4 PCI Target (Direct Slave) Operation
CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY#
Retry Retry Write Is Not Allowed During Delayed Read Reads Data Write Retries and Completes A CMD BE A CMD BE A CMD D0 D1 D2 D3 D4 D5 D6 D7 D8 BE ADDR CMD D0
STOP#
Delayed Read Retries
LCLK LREQ LGNT ADS# BLAST# LBE[3:0]# LW/R# LA[27:2] LD[31:0] READY# (input)
Disconnect immediately for a read. Does not effect pending reads when a Write cycle occurs, nor flush the Read FIFO if the PCI Read cycle completes. When a read is pending, force Retry on a write. De-assert TRDY# until space is available in the PCI Target Write FIFO.
ADDR +4 +8 +C +10 +14 +18 +1C +20 +24 +28 +2C +30 +34 +38 +3C D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11D12D13 D14 D15 LBE
Timing Diagram 4-41. Delayed Read Transaction PCI Specification v2.2, Non-Multiplexed Mode Only
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
4-41
Section 4--PCI Target
Section 4 PCI Target (Direct Slave) Operation
Timing Diagrams
0ns
250ns
500ns
750ns
1000ns
CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY#
ADDR D0 D1 Addr D2 D3 D4 D5 D6
CMD
BE
CMD
BE
LCLK LREQ LGNT ADS# BLAST# LBE[3:0]# LW/R# LA[27:2] LD[31:0] READY# (input)
ADDR +4 +8 +C +10 +14 +18 +1C +20 +24 +28 +2C +30 +34 +38 +3C +40 ADDR LBE
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16
D0
Timing Diagram 4-42. PCI Target Read No Flush Mode (Read Ahead Mode), Prefetch Enabled, Prefetch Count Disabled, Non-Multiplexed Mode Only
4-42
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Timing Diagrams
Section 4 PCI Target (Direct Slave) Operation
0ns
250ns
500ns
750ns
CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# LOCK# LCLK LREQ LGNT ADS# BLAST# LBE[3:0]# LW/R# LA[27:2] LD[31:0] READY# (input) LLOCKo#
ADDR +4 +8 +12 +16 +20 +24 +28 +32 D4 D5 D6 D7 D8 W-ADDR W-DATA <-- CAN BE DE-ASSERTED AFTER LAST DATA ADDR R BYTE ENABLES D0 D1 W-A W W-DATA BE
LBE
LBE
D0 D1 D2 D3
DE-ASSERTED AFTER DETECTING PCI UNLOCK --->
Timing Diagram 4-43. Locked PCI Target Read Followed by Write and Release (LLOCKo#), Non-Multiplexed Mode Only
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
4-43
Section 4--PCI Target
Section 4 PCI Target (Direct Slave) Operation
Timing Diagrams
0ns
100ns
200ns
300ns
400ns
500ns
CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY#
1
2
3
4
5
6
7
8
ADDR
Data= AABBCCDD
01234567
CMD
BE
LCLK LREQ LGNT ADS# BLAST# LBE[3:0]# LW/R# LA[27:2] LD[31:0] READY# (input)
ADDR LBE
DDCCBBAA 67452301
Timing Diagram 4-44. PCI Target Write to Local Target in BIGEND Mode, Non-Multiplexed Mode Only
4-44
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
5
5.1
LOCAL CHIP SELECTS
OVERVIEW
Each 28-bit Chip Select Base Address register is programmed as listed in the following table.
Table 5-1. Chip Select Base Address Register Signal Programming
MSB=27
XXXX XXXX XXXX XXXX XXXX XXXX
The PCI 9030 supports four different chip selects. Each chip select is programmable and independent of Address Space. The PCI 9030 includes the ability to directly provide Chip Select control signals to four devices on the PCI 9030 Local Bus. Without this feature, it is necessary to add address-decoding logic for each required Chip Select.
LSB=0
XXXY
5.2
CHIP SELECT BASE ADDRESS REGISTERS
There are four Chip Select Base Address registers. These registers control the four chip select pins on the PCI 9030. For example, Chip Select 0 Base Address Register controls CS0# (PQFP--pin 147; BGA--pin C9), Chip Select 1 Base Address Register controls CS1# (PQFP--pin 148; BGA--pin B9), and so forth. The Chip Select Base Address registers serve three purposes:
1. To enable or disable chip select functions within the PCI 9030. If enabled, the Chip Select signal is active if the address on the address line falls within the address specified by the range and base address. If disabled, the Chip Select signal is not active. To set the range of addresses for which the Chip Select signal(s) are active. To set the base address at which the range starts.
The Y bit (bit 0) enables or disables the chip select signal. X bits are used to determine the range and base address of where the CS# pin is asserted. To program the base and range, the X bits are set as follows: * Device length or range is equal to the first bit set above the Y bit. Determined by setting a bit in the register equal to the exponent in the exponential representation of the range. Bit is counted up, starting at the Y bit, where the Y bit is counted as 1. * Base address is determined by the bit or bits set above the range bit (range multiple). Number uses all bits in register above the range bits.
0
2. 3.
Range--Address at which CS# is asserted
{
Base Address
To program the Chip Select Base Address registers, there are three rules:
1. 2. 3. Range must be a power of 2. Base address must be a multiple of the range. Multiple Chip Select Base Address registers, if used, are programmed to not overlap one another.
FFFFFFFh
Figure 5-1. Chip Select Base Address and Range
Section 5--Chip Selects
5-1
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Section 5 Local Chip Selects
Procedure for Using Chip Select Base Address Registers
5.3
PROCEDURE FOR USING CHIP SELECT BASE ADDRESS REGISTERS
1.
Determine the range in hex and convert the number to a power of 2 (for example, 16K is equivalent to 4000h, or 214 bits). Set the bit in the Chip Select Base Address register to specify the range. Set the 14th bit to 1.
LSB=0 0000 0000 0010 0000 0000 0000
The following procedure describes how to use the Chip Select Base Address registers.
1. Determine the range in hex. Convert this number to a power of 2. Range must be a power of 2 (for example, 21, 22, 23, 216, and so forth). Set a bit in the Chip Select Base Address register to determine the range. Use the range exponent to set the bit in the Chip Select Base Address register. In a binary representation of the Chip Select Base Address register, count left, starting at the Y bit, where Y is one. Only one bit may be set. Determine the base address. It is recommended to use hex numbers for the base address. Base address must be a multiple of the range. Determine the base address multiplier. Divide range into the base address in hex: (base address)/(range)=(base address multiplier) 5. 6. Convert the base address multiplier to binary. Set the base address multiplier bits directly above the range bit in the Chip Select Base Address register.
2.
MSB=27 0000
3. 2. 4.
Determine the base address (for example, 24000h). Determine the base address multiplier. Divide the range into the base address in hex (for example, 24000h/4000h=9h). Convert the base address multiplier to binary (for example, 1001b). Set the base address multiplier bits directly above the range bit in the Chip Select Base Address register.
5. 6.
3.
4.
Base Address Multiplier MSB=27 0000 0000 00 10 01 10
Range LSB=0 0000 0000 0000
Example: A 16K SRAM device is attached to the Local Bus and a chip select is provided. The base address is specified to be 24000h. The following figure illustrates this example.
0
The following is a complete example of setting the Chip Select Base Address register with a range of 4000h, a base address of 24000h, and enabled:
MSB=27 0000 0000 0010 0110 0000 0000 LSB=0 0001
24000h 27FFFh
FFFFFFFh
Figure 5-2. Memory Map Example
5-2
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
6
6.1
PCI AND LOCAL INTERRUPTS AND GENERAL PURPOSE I/O
OVERVIEW 6.2.3 Local Power Management Interrupt (LPMINT#)
There are two local interrupt pins which can trigger PCI interrupt INTA#. Each pin has a global Enable or Disable bit. In addition, each pin is programmable to a different polarity, and can be triggered by an edge or level. Each interrupt has a status bit indicating which interrupt source is active.
The PCI 9030 is a PCI Target device only; therefore, there is no access to the internal registers from the Local Bus. The Local Power Management Interrupt output (LPMINT#) is included to accommodate the PCI Bus Power Management interface to a Local Bus. The PCI 9030 asserts LPMINT# to request a Power State change to the Local Bus when the Power Management Control/Status register (PMCSR[1:0]) changes. The LPMINT# interrupt is synchronous to the Local clock. When asserted, it is a one clock-wide pulse.
6.2
INTERRUPTS
LINTi1 OR LINTi2 INTA#
External glue logic is needed to latch the Power State change and to retain the previous Power State history for further evaluation by the external Local Bus Initiator.
6.2.4
Figure 6-1. Interrupt and Error Sources
Local Power Management Enumerator Set
6.2.1
PCI Interrupts (INTA#)
A PCI 9030 PCI Interrupt (INTA#) can be asserted by Local Interrupt Input 2 or 1 (LINTi[2:1]), which are described in the next section. INTA#, or individual sources of an interrupt, can be enabled or disabled with the PCI 9030 Interrupt Control/Status register (INTCSR). This register also provides the interrupt status of each interrupt source. The PCI 9030 PCI Bus interrupt is a level output. Disabling an interrupt enable bit or clearing the cause(s) of the interrupt can clear an interrupt.
The Local Power Management Enumerator Set Interrupt input (LPMESET) is included to accommodate the PCI Bus Power Management interface to a Local Bus. The external Local Bus Initiator can assert LPMESET to the PCI 9030 Power Management Control/Status register (PMCSR[15]) to set the PME# status and assert the PME# signal to the PCI Bus in case of a Wake-up Request event.
6.2.5
All Modes PCI SERR# (PCINMI)
6.2.2
Local Interrupt Input (LINTi[2:1])
The PCI 9030 asserts an SERR# pulse if parity checking is enabled (PCICR[6]=1) and it detects an address or parity error. The SERR# output can be enabled or disabled with the SERR# Enable bit (PCICR[8]).
The PCI 9030 provides two Local interrupts (LINTi[2:1]). The Local interrupts can be used to generate a PCI interrupt. LINTi[2:1] supports different polarity, edge or level trigger, programmable through the Interrupt Control/Status register (INTCSR; 4Ch).
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
6-1
Section 6--Interrupts, I/O
Section 6 PCI and Local Interrupts and General Purpose I/O
General Purpose I/O
6.3
GENERAL PURPOSE I/O
The PCI 9030 supports nine general purpose input and output pins, multiplexed GPIO0/WAITo#, GPIO1/ LLOCKo#, GPIO2/CS2#, GPIO3/CS3#, GPIO4/LA27, GPIO5/LA26, GPIO6/LA25, and GPIO7/LA24, and GPIO8. The PCI 9030 default condition is the General Purpose Input for GPIO[3:0], with Local Address LA[27:24] for GPIO[7:4], and General Purpose Input for GPIO8. The general purpose input and output pins and functionality can be enabled and selected in the General Purpose I/O Control register (GPIOC[31:0]).
6-2
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
7
7.1
PCI POWER MANAGEMENT
OVERVIEW
* B2--Intermediate power management state. Full power clock frequency stopped, PCI v2.2 compliant (in the low state). PME Event-driven bus activity. Vcc is applied to all devices on the bus; however, the clock is stopped and held in the Low state.
Section 7--Power Mgmt
The PCI Bus Power Management Interface Specification v1.1 provides a standard mechanism for operating systems to control add-in boards for power management. The Specification defines four PCI functional power states--D0, D1, D2, and D3. States D0 and D3 are required, while states D1 and D2 are optional. State D0 represents the highest power consumption and state D3 the least. * D0 (Uninitialized)--Enters this state from PowerOn Reset or from state D3hot or D3cold. Supports PCI Target transactions only. * D0 (Active)--All functions active. * D1--Uses less power than State D0, and more than state D2. Light Sleep State. Not supported by the PCI 9030. * D2--Uses very little power. Supports PCI Configuration cycles to function if clock is running (Memory, I/O, Bus Mastering, and Interrupts are disabled). It also supports the Wake-up Event from function, but not standard PCI interrupts. Not supported by the PCI 9030. * D3hot--Uses lower power than any other state. Supports PCI Configuration cycles to function if clock is running. Supports Wake-up Event from function, but not standard PCI interrupts. When programmed for state D0, an internal soft reset occurs. The PCI Bus drivers must be disabled. PME# context must be retained during this soft reset. * D3cold--No power. Supports Bus reset only. All context is lost in this state. From a power management perspective, the PCI Bus can be characterized at any point in time by one of four power management states--B0, B1, B2, and B3: * B0 (Fully On)--Bus is fully usable with full power and clock frequency, PCI v2.2 compliant. Fully operational bus activity. This is the only Power Management state in which data transactions can occur. * B1--Intermediate power management state. Full power with clock frequency, PCI v2.2 compliant. PME Event driven bus activity. Vcc is applied to all devices on the bus, and no transactions are allowed to occur on the bus.
* B3 (Off)--Power to the bus is switched off. PME Event-driven bus activity.Vcc is removed from all devices on the PCI Bus. All system PCI Buses have an originating device, which can support one or more power states. In most cases, this creates a bridge (such as, a Host-to-PCIBus or a PCI-to-PCI bridge). Function States must be at the same or lower energy state than the bus on which they reside.
7.2
PCI POWER MANAGEMENT FUNCTIONAL DESCRIPTION
The PCI 9030 passes power management information and has no inherent power-saving feature. The PCI 9030 supports D0, D3hot, and D3cold states. The PCI Status register (PCISR) and the New Capability Pointer register (CAP_PTR) indicate whether a new capability (the Power Management function) is available. The New Capability Functions Support bit (PCISR[4]) enables a PCI BIOS to identify a New Capability function support. This bit is executable for writes from the serial EEPROM and reads from the PCI Bus. CAP_PTR provides an offset into PCI Configuration Space, the start location of the first item in a New Capabilities Linked List. The Power Management Capability ID register (PMCAPID) specifies the Power Management Capability ID, 01h, assigned by the PCI SIG. The Power Management Next Capability Pointer register (PMNEXT) points to the first location of the next item in the capabilities linked list. If Power Management is the last item in the list, then this register should be set to 0. The default value for the PCI 9030 is 48h (Hot Swap). For the PCI 9030 to change the power state and assert PME#, the serial EEPROM or PCI Host should set the PME#_En bit (PMCSR[8]=1). The Local Host then determines to which power state the backplane should change by monitoring the Power_State bits (PMCSR[1:0]), by way of the LPMINT# interrupt signal.
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
7-1
Section 7 PCI Power Management
PCI Power Management Functional Description
The PCI 9030 is a PCI Target device only; therefore, there is no access to the internal registers from the Local Bus. The Local Power Management Interrupt output (LPMINT#) is included to accommodate the PCI Power Management interface to a Local Bus. The PCI 9030 asserts LPMINT# to request a Power State change to an external Local Bus Initiator when the Power Management Control/Status register (PMCSR[1:0]) changes. The LPMINT# interrupt is synchronous to the Local clock. When asserted, it is one clock-wide pulse. External Local glue logic is needed to latch the Power State change and to retain the previous Power State history for further evaluation by the external Local Bus Initiator. The PCI 9030 uses the PME#_Support bits (PMC[14:11]) to identify the PME# Support corresponding to a specific power state (PMCSR[1:0]). (PMC[14:11]) are configured by way of the serial EEPROM. The Local Host then sets the PME#_Status bit (PMCSR[15]=1), by way of LPMESET, and the PCI 9030 asserts PME#. To clear the PME#_Status bit, the PCI Host must write a 1 to the PME# Status bit (PMCSR[15]=1). To disable the PME# Interrupt signal, either the PCI Host or serial EEPROM can write a 0 to the PME#_En bit (PMCSR[8]=0). The Local Power Management Enumerator Set Interrupt input (LPMESET) is included to accommodate the PCI Power Management interface to a Local Bus. The external Local Bus Initiator can assert LPMESET to the PCI 9030 Power Management Control/Status register (PMCSR[15]) to set the PME# status and assert the PME# signal in the case of a Wake-up Request event to the PCI Bus. LPMINT# output is asserted every time the power state in the PMCSR register changes. Transition from state 11 (D3hot) to state 00 (D0) causes a soft reset and serial EEPROM reload. During a soft reset, the Local Bus interface is in Reset mode. The PCI 9030 issues LRESETo# and resets the Local Bus and all its Local Internal registers to their default values. In state D3hot, PCI Memory and I/O accesses are disabled, as well as PCI interrupts, and only configuration is allowed.
7.2.1
Power Management Data_Select, Data_Scale, and Power Data Utilization
The Data_Scale bits (PMCSR[14:13]) indicate the scaling factor to use when interpreting the value of the Power Management Data bits (PMDATA[7:0]). The value and meaning of the bits depend upon the data value specified in the Data_Select bits (PMCSR[12:9]). The Data_Scale bit value is unique for each Data_Select bit. For Data_Select values from 8 to 15, the Data_Scale bits always return a zero (PMCSR[14:13]=0). To accommodate the PCI Power Management interface to a local bus, two hidden registers (loadable by the serial EEPROM) are available to store all necessary information for the Power Management Data and Data_Scale register bits--(PMDATASEL; PCI:70h) for PMDATA[7:0] and (PMDATASCALE; PCI:74h) for PMCSR[14:13], respectively. The PCI 9030 supports only D0, D3hot, and D3cold. Power Management States. Therefore, the PMDATA[7:0] register, which provides operating data (such as power consumption and/or heat dissipation), retains only four possible power data combinations:
1. 2. 3. 4. D0 Power Consumed D3 Power Consumed D0 Power Dissipated D3hot Power Dissipated
Each power combination field requires an 8-bit register in which to store the data. The PCI 9030 provides a 32-bit hidden register, PMDATASEL, to store such information. The PMDATASEL register can be written only from the serial EEPROM and read from the PMDATA[7:0] with the corresponding Data_Select value in the Power Management Control/Status register bits (PMCSR [12:9]).
7-2
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
System Changes Power Mode Example
Section 7 PCI Power Management
The PMDATASEL register loading sequence from the serial EEPROM is as follows: * Bits [31:24]--Data Select for D3hot Power Dissipated * Bits [23:16]--Data Select for D0 Power Dissipated * Bits [15:8]--Data Select for D3hot Power Consumed * Bits [7:0]--Data Select for D0 Power Consumed The Data_Scale register bits (PMCSR[14:13]) that provide a scale factor value for the Data_Select value retains four possible scale factors--0, 1, 2, and 3 (refer to PCI Bus Power Management Interface Specification v1.1 for the scale factor derivative values). Each Data_Scale field requires a 2-bit register in which to store the data. The PCI 9030 provides an 8-bit hidden register, PMDATASCALE, to store such information. The PMDATASCALE register can be written only from the serial EEPROM and read from the PMCSR[14:13] with the corresponding Data_Select value in the Power Management Control/ Status register bits (PMCSR [12:9]). The loading sequence of the PMDATASCALE register from the serial EEPROM is as follows: * Bits [7:6]--Data_Scale for D3hot Power Dissipated * Bits [5:4]--Data_Scale for D0 Power Dissipated * Bits [3:2]--Data_Scale for D3hot Power Consumed * Bits [1:0]--Data_Scale for D0 Power Consumed
7.3
SYSTEM CHANGES POWER MODE EXAMPLE
The Host writes to the PCI 9030 PMCSR register to change the power states. The PCI 9030 sends a Local Power Management Interrupt (LPMINT# output) to a Local CPU (LCPU). The LCPU has 200 s to respond to the power management information change (LPMINT#) from the PCI 9030 PMCSR register to implement the power saving function. After the LCPU implements the power saving function, the PCI 9030 disables all PCI Target accesses and PCI Interrupt output (INTA#).
An example of system changes power mode follows:
1. 2.
3.
4.
Notes: In Power Saving mode, all PCI and Local Configuration cycles are granted. The PCI 9030 automatically performs a soft reset to a Local Bus on D3-to-D0 transitions.
7.4
1. 2.
WAKE-UP REQUEST EXAMPLE
The add-in board (with a PCI 9030 chip installed) is in a powered-down state. The Local CPU performs a LPMESET interrupt assertion (PCI 9030 PMCSR[15] register bit) to request a wake-up procedure. As soon as the request is detected, the PCI 9030 drives PME# out to the PCI Bus. The PCI Host accesses the PCI 9030 PMCSR register to disable the PME# output signal and restores the PCI 9030 to the D0 power state. The PCI 9030 completes the power management task by issuing the Local Power Management Interrupt (LPMINT# output) to the Local CPU, indicating that the power mode has changed.
An example of a wake-up request follows:
3.
7.2.2
1.
Reading Hidden Data Example
4. PMCSR[12:9] Data_Select retains a value of 0h. PMCSR[14:13] provides a scale factor for the D0 Power Consumed from the Data_Scale 0 bits (PMDATASCALE[1:0]). PMDATA[7:0] provides the D0 Power Consumed value from the D0 Power Consumed bits (PMDATASEL[7:0]). 5.
An example of reading hidden data follows:
2.
PMCSR[12:9] Data_Select retains a value of 7h. PMCSR[14:13] provides a scale factor for the D3hot Power Dissipated from the Data_Scale 7 bits (PMDATASCALE[7:6]). PMDATA[7:0] provides the D3hot Power Dissipated value, from the D3 Power Dissipated bits (PMDATASEL[31:24]).
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
7-3
Section 7--Power Mgmt
8
COMPACTPCI HOT SWAP
Hot Swap * Incorporates Hot Swap Control/Status register (HS_CSR)--Contained within the configuration space. * Incorporates an Extended Capability Pointer (ECP) mechanism--It is required that Software retain a standard method of determining if a specific function is designed in accordance with the specification. The Capabilities Pointer is located within standard CSR space, using a bit in the PCI Status register (offset 04h). * Incorporates remaining software connection control resources. Provides ENUM#, Hot Swap switch, and the blue LED. Hot Swap-Ready silicon includes all required Friendly functions and adds others from the following list. The PCI 9030 integrated these functions into the PCI silicon, thereby reducing the amount and cost of external circuitry required. * Early Power Support. * Incorporates a 1V BIAS precharge voltage to the PCI I/O pins--All PCI Bus signals are required to be precharged to a 1V BIAS through a 10K ohm resistor during the Hot Swap process. The PCI 9030 provides an internal voltage regulator to supply 1V, with a built-in 10K ohm resistor, to all required PCI I/O buffers. Other PCI signals can be precharged to VIO. The PCI 9030 is a Hot Swap-Ready PCI silicon device. The PCI 9030 incorporates all compliant functions defined by the CompactPCI Hot Swap specification. The PCI 9030 incorporates LEDon#, CPCISW, BD_SEL#, and ENUM#, as well as Hot Swap Capabilities registers--HS_CNTL, HS_NEXT, and HS_CSR.
The PCI 9030 is a CompactPCI Ready-compliant device.
8.1
OVERVIEW
To avoid confusion in the industry, Hot Swap defines three levels of compatibility: * Hot Swap-Capable devices contain the minimum requirements to operate in a Hot Swap environment * Hot Swap-Friendly devices contain additional functions to ease the designer's job * Hot Swap-Ready devices contain all necessary functions for Hot Swap Hot Swap-Capable requirements are mandatory for a device to be used in a Hot Swap environment. These requirements are attributes for which a system user must compensate using external circuitry, as follows: * PCI Local Bus Specification v2.1 compliance * Tolerate Vcc from early power * Tolerate asynchronous reset * Tolerate precharge voltage * I/O Buffers must meet modified V/I requirements * Limited I/O pin leakage at precharge voltage Hot Swap-Friendly silicon includes all required Capable functions and adds others from the following list. The PCI 9030 integrated these functions into the PCI silicon, thereby reducing the amount and cost of required external circuitry.
8.2
CONTROLLING CONNECTION PROCESSES
The following sections are excerpts from the CompactPCI Hot Swap Specification. Refer to the specification for more details.
8.2.1
Connection Control
Hardware Control provides a means for the platform to control the hardware connection process. The signals listed in the following sections must be
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
8-1
Section 8--Hot Swap
Hot Swap is used for many CompactPCI applications. Hot Swap functionality allows the orderly insertion and removal of boards without adversely affecting system operation. This is done for repair of faulty boards or system reconfiguration. Additionally, Hot Swap provides access to Hot Swap services, allowing system reconfiguration and fault recovery to occur with no system down time and minimum operator interaction. Adapter insertion/removal logic control resides on the individual adapters. The PCI 9030 uses four pins--ENUM#, BD_SEL#, LEDon#, and CPCISW--to implement the hardware aspects of Hot Swap functionality. The PCI 9030 uses the Hot Swap Capabilities register to implement the software aspects of Hot Swap.
Section 8 CompactPCI Hot Swap
Controlling Connection Processes
supported on all Hot Swap boards for interoperability. Implementations on different platforms may vary.
implementing this signaling, route these signals radially to a Hot Swap Controller.
Platform | Board HSC Platform | Board VIO
8.2.1.1
Board Slot Control
BD_SEL#, one of the shortest pins from the CompactPCI backplane, is driven low to enable power-on. For systems not implementing hardware control, it is grounded on the backplane. Systems implementing hardware control radially connect BD_SEL# to a Hot Swap Controller (HSC). The controller terminates the signal with a weak pull-down, and can detect board present when the board pull-up overrides the pull-down. HSC can then control the power-on process by driving BD_SEL# low. The PCI 9030 uses the BD_SEL# signal to tri-state all local output buffers during the insertion and extraction process. In addition, the PCI 9030 uses BD_SEL# as a qualifier to dynamically connect 1V and VI/O BIAS precharge resistors to all required PCI I/O buffers. A pull-up resistor must be provided to the BD_SEL# pin or add-in card, where the pull-up resistor is connected to an early power Power Supply, which provides for proper PCI 9030 operation. (Refer to Section 11, "Pin Description," for precharge connections.)
Platform | Board VIO Power Circuitry HSC PRESENT PWR ON BD_SEL# ON Power Circuitry Platform | Board VIO
NC
Power Circuitry
HEALTHY
HLTY
Power Circuitry
No Hardware Control
Hardware Control
Figure 8-2. Board Healthy
8.2.1.3
Platform Reset
Reset (PCI_RST#), as defined by the CompactPCI Specification, is a bus signal on the backplane, driven by the Host. Platforms may implement this signal as a radial signal from the Hot Swap Controller to further control the electrical connection process. Platforms that maintain function of the bus signal, must OR the Host reset signal with the slot-specific signal. Locally, boards must not exit reset until the H1 State is reached (healthy), and they must honor the backplane reset. The Local board reset (Local_PCI_RST#) must be the logical OR of these two conditions. Local_PCI_RST# is connected to the PCI 9030 RST# input pin. During a BIAS voltage precharge and platform reset, in insertion and extraction procedures, all PCI I/O buffers must be in a high-impedance state. The PCI 9030 supports this condition when the Host RST# is asserted (PCI v2.1). To protect the Local board components from early power, the PCI 9030 floats the Local Bus I/Os. The BD_SEL# pin is used to perform the high-impedance condition on the Local Bus. With full contact of the add-in card to the backplane, BD_SEL# is asserted which ensures that the PCI 9030 asserts the LRESETo# signal to complete a Local Board Reset task.
Platform | Board PCI_RST# LOCAL_PCI_RST# HOST HOST Platform | Board PCI_RST#
LOCAL_PCI_RST#
BD_SEL# ON
No Hardware Control
Hardware Control
Figure 8-1. Redirection of BD_SEL#
8.2.1.2
Board Healthy
A second radial signal is used to acknowledge board health. It signals that a board is suitable to be released from reset and allowed onto the PCI Bus. Minimally, this signal must be connected to the board's power controller "power good" status line. Use of HEALTHY# can be expanded for applications requiring additional conditions to be met for the board to be considered healthy. On platforms that do not use Hardware Connection Control, this line is not monitored. Platforms
HEALTHY #
HSC HEALTHY#
No Hardware Control
Hardware Connection Control
Figure 8-3. PCI Reset
8-2
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Controlling Connection Processes
Section 8 CompactPCI Hot Swap
8.2.2
Software Connection Control
Software Connection Control provides a means to control the Software Connection Process. Hot Swap board resources facilitate software Connection Control. Access to these resources occurs by way of the bus, using PCI protocol transfers (in-band). These resources consist of four elements: * ENUM# driven active indicates the need to change the Hot Swap Board state * A switch, tied to the ejector, indicates the intent to remove a board * LED indicates the software connection process status * Control/Status register allows the software to interact with these resources
The PCI 9030 uses an open-drain output pin to sink the external LED. The LED state is driven from the LED Software On/Off Switch bit (HS_CSR[3]). The CPCISW input signal acknowledges the state ejector handle change to identify when a board is inserted or removed. The appropriate status bits are set (HS_CSR[7:6]).
8.2.2.2
ENUM#
ENUM# is provided to notify the Host CPU that a board was recently inserted or is about to be removed. This signal informs the CPU that system configuration changed, at which time the CPU performs necessary maintenance such as installing a device driver upon board insertion, or quiescing a device driver prior to board extraction. ENUM# is an open collector bused signal with a pullup on the Host bus. It may drive an interrupt (preferred) or be polled by the system software at regular intervals. The CompactPCI Hot-Plug System Driver on the system Host manages the ENUM# sensing. Full Hot Swap Boards assert ENUM# until serviced by the Hot-Plug system driver. When a board is inserted into the system and comes out of reset, the PCI 9030 acknowledges the ejector switch state. If this switch is open (ejector handle closed), the PCI 9030 asserts the ENUM# interrupt and sets the ENUM# Status Indicator for Board Insertion bit (HS_CSR[7]). Once the Host CPU installs the proper drivers, it can logically include this board by clearing the interrupt. When a board is about to be removed, the PCI 9030 acknowledges the ejector handle is open, asserts the ENUM# interrupt, and sets the ENUM# Status Indicator for the Board Removal bit (HS_CSR[6]). The Host then logically removes the board and turns on the LED, at which time the board can be removed from the system.
8.2.2.1
Ejector Switch and Blue LED
A microswitch (switch), located in the Hot Swap CompactPCI board card-ejector mechanism, is used to signal impending board removal. This signal asserts ENUM#. The operator normally activates the switch, waits for the LED illumination to indicate it may remove the board, and then removes the board. The PCI 9030 implements separate control logic for the microswitch and blue LED in two different pins (CPCISW and LEDon#, respectively). When the ejector is opened or closed, the switch bounces for a time. The PCI 9030 uses internal debounce circuitry to clean the signal before the remainder of Hot Swap logic acknowledges it. The switch state is sampled six times, at 1 ms intervals, before it is determined to be closed or open. The Blue "Status" LED, located on the front of the Hot Swap CompactPCI board, is illuminated when it is permissible to remove a board. The hardware connection layer provides protection for the system during all insertions and extractions. This LED indicates the system software is in a state that tolerates board extraction. Upon insertion, the LED is automatically illuminated by the hardware until the hardware connection process completes. The LED remains OFF until the software uses it to indicate extraction is once again permitted.
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
8-3
Section 8--Hot Swap
Section 8 CompactPCI Hot Swap
Controlling Connection Processes
8.2.2.3
Hot Swap Control/Status Register (HS_CSR)
Hot Swap ID. Bits [7:0] (HS_CNTL[7:0]; PCI:48h). These bits are set to a default value of 0x06. Next_Cap Pointer. Bits [15:8] (HS_NEXT[7:0]; PCI:49h). These bits either point to the next New Capability structure, or are set to 0 if this is the last capability in the structure. Control. Bits [23:16] (HS_CSR[7:0]; PCI:4Ah). This 8-bit control register is defined in the following table.
Table 8-1. Hot Swap Control
Bit
23 22 21 20
The PCI 9030 supports Hot Swap directly, as a control/status register is provided in Configuration space. This register is accessed through the PCI Extended Capabilities Pointer (ECP) mechanism. The Hot Swap Control/Status register (HS_CSR) provides status read-back for the Hot-Plug System Driver to determine which board is driving ENUM#. This register is also used to control the Hot Swap Status LED on the board front panel, and to de-assert ENUM#.
Description
ENUM# status--Insertion (1 = board is inserted). ENUM# status--Removal (1 = board is being removed). Not used. Not used. LED state (1 = LED on, 0 = LED off). Not used. ENUM# interrupt enable (1 = de-assert, 0 = enable interrupt). Not used.
8.2.2.4
Hot Swap Capabilities Register Bit Definition
24 23 Control 16 15 Next_Cap Pointer 8 7 0
31
19 18 17 16
Reserved
Hot Swap ID
Figure 8-4. Hot Swap Capabilities Register Bit Definition
8-4
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
9
9.1
PCI VITAL PRODUCT DATA (VPD)
OVERVIEW
F. Bit 31 (PVPDAD[15]; PCI:4Eh). This bit sets a flag to indicate when a serial EEPROM data operation is complete. For Write cycles, the four bytes of data are first written into the VPD Data bits, after which the VPD Address is written at the same time the F flag is set to 1. The F flag clears when the serial EEPROM Data transfer completes. For Read cycles, the VPD Address is written at the same time the F flag is cleared to 0. The F flag is set when four bytes of data are read from the serial EEPROM. VPD Data. Bits [31:0] (PVPDATA[31:0]; PCI:50h). The VPDDATA register is not a pure read/write register. The data read from the register depends upon the last Read operation performed in PVPDAD[15]. VPD data is written or read through this register. Leastsignificant byte corresponding to VPD Byte at the address specified by the VPD Address register. Four bytes are always transferred between the register and the serial EEPROM.
31 F 30 16 15 Next_Cap Pointer (0X00) VPD Data 8 7 VPD ID (0x03) 0
The PCI Specification v2.2 Vital Product Data (VPD) function defines a new location and access method. It also defines the Read Only and Read/Write bits. Currently Device ID, Vendor ID, Revision ID, Class Code, Subsystem ID, and Subsystem Vendor ID are required in the Configuration Space Header and for basic device identification and configuration. Although this information allows a device to be configured, it is not sufficient to allow a device to be uniquely identified. With the addition of VPD, optional information is provided that allows a device to be uniquely identified and tracked. These additional bits enable current and/or future support tools and reduces the total cost of ownership of PCs and systems. This provides an alternate access method other than Expansion ROM for VPD. VPD is stored in an external serial EEPROM, which is accessed using the Configuration Space New Capabilities function. The VPD registers--PVPDCNTL, PVPD_NEXT, PVPDAD, and PVPDATA--are not accessible for reads from the Local Bus. The VPD function can be exercised only from the PCI Bus.
VPD Address
9.2
VPD CAPABILITIES REGISTER
Figure 9-1. VPD Capabilities Register Bit Definition
Section 9--VPD
VPD ID. Bits [7:0] (PVPDCNTL[7:0]; PCI:4Ch). The PCI SIG assigned a value of 03h to these bits. The VPD ID is hardcoded. Next_Cap Pointer. Bits [15:8] (PVPD_NEXT[7:0]; PCI:4Dh). These bits either point to the next New Capability structure, or are set to 0 if this is the last capability in the structure. The PCI 9030 defaults to 0x00. This value can be overwritten from the serial EEPROM. VPD Address. Bits [24:16] (PVPAD[14:0]; PCI:4Eh). These bits specify the VPD byte address to be accessed. All accesses are 32-bit wide; bits [17:16] must be 0, with the maximum serial EEPROM size being 4K bits. Bits [30:25] are ignored.
9.3
VPD SERIAL EEPROM PARTITIONING
To support VPD, the serial EEPROM is partitioned into read only and read/write sections.
9.4
SEQUENTIAL READ ONLY
The first 1024 bits, (128 bytes) of the serial EEPROM contain read-only information. The serial EEPROM read-only portion is loaded into the PCI 9030, using a sequential Read command to the serial EEPROM and occurs once after power-on or Hot Swap insertion.
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
9-1
Section 9 PCI Vital Product Data (VPD)
Random Access Read and Write
9.5
RANDOM ACCESS READ AND WRITE
To perform a simple VPD write to the serial EEPROM, the following steps are necessary:
1. Change the write-protected serial EEPROM address in PROT_AREA[6:0], if required. 0x0000000 makes the serial EEPROM writable from the beginning. Write the desired data into the VPDDATA register. Write the destination serial EEPROM address and flag of operation to a value of 1. Probe the flag of operation until it changes to a 0 to ensure the write is complete.
The PCI 9030 has full access to the read/write portion of the serial EEPROM. The serial EEPROM, starting at Lword Boundary for VPD Accesses bits (PROT_AREA[6:0]), designates this portion. This register is loaded upon power-on and can be written with a desired value, starting at location 0. This provides the capability of writing the entire serial EEPROM. Writes to the serial EEPROM are comprised of the following commands: * Write Enable * Write command, followed by the upper 16-bit Write data * Write command, followed by the lower 16-bit Write data * Write Disable
2. 3. 4.
To perform a simple VPD read from the serial EEPROM, the following steps are necessary:
1. 2. Write a destination serial EEPROM address and flag of operation to a value of 0. Probe the flag of operation until it changes to a 1 to ensure the Read data is available. Read back the VPDDATA register to see the requested data.
This is done to ensure against accidental write of the serial EEPROM. Randomly occurring cycles allow VPD information to be written and read at any time.
3.
9-2
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
10
10.1
REGISTERS
NEW REGISTER DEFINITIONS SUMMARY (AS COMPARED TO THE PCI 9050 AND PCI 9052)
Refer to the description column in the following tables for a full explanation.
Table 10-1. New Registers Definitions Summary (As Compared to the PCI 9050 and PCI 9052)
PCI Register Address
34h 40h 44h 48h 4Ch 50h
Local Offset from Base Address
-- -- -- -- -- --
Register
New Capability Pointer Power Management Power Management CompactPCI Hot Swap PCI Vital Product Data PCI Vital Product Data Serial EEPROM Write-Protected Address Boundary PCI Target Response, Serial EEPROM, and Initialization Control General Purpose I/O Control Hidden 1 Power Management Data Select Hidden 2 Power Management Data Scale
Bits
7:0 31:0 31:0 31:0 31:0 31:0 6:0 15:7 5:0 6 7 8 9 11:10 31 26:0 31:27 31:0 7:0 31:8
Description
Provides offset into PCI Configuration space for the location of the first item in the New Capability Linked List. Provides Power Management ID, Power Management Next Capability Pointer, and Power Management Capabilities. Provides Power Management Status, PMCSR Bridge Support Extensions, and Power Management Data. Hot Swap Control, Hot Swap Next Capability Pointer, and Hot Swap Control/Status Register. VPD ID, VPD Next Capability Pointer, and VPD Address Pointer. VPD Data. Serial EEPROM Write-Protected Address Boundary. Reserved. Reserved. PCI Target Write FIFO Full Condition. Local Arbiter LGNT Select Enable. Local Ready Timeout Enable. Local Ready Timeout Select. PCI Target Write Delay Access Select. Disconnect with Flush Read FIFO. GPIO[7:0] Control Select bits. Reserved. Data Select register for Power Consumed and Dissipated. Written only by the serial EEPROM. Data Scale Factor Values for Power Consumed and Dissipated. Written only by the serial EEPROM. Reserved.
--
4Eh
--
50h
--
54h
--
70h
--
74h
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
10-1
Section 10--Registers
Section 10 Registers
Register Address Mapping
10.2
REGISTER ADDRESS MAPPING
Table 10-2. PCI Configuration Register Address Mapping
PCI Configuration Register Address 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch Max_Lat BIST To ensure software compatibility with other versions of the PCI 9030 family and to ensure compatibility with future enhancements, write 0 to all unused bits. 31 30 24 Device ID Status Class Code Header Type PCI Bus Latency Timer (Not supported) 23 16 15 8 7 0 PCI Writable N Y N Y [7:0] Y Y Y Y Y Y N N Y Next_Cap Pointer Reserved Min_Gnt Interrupt Pin Interrupt Line N N Y [7:0] Serial EEPROM Writable Y Y [20] Y N N N N N N N N Y N Y [7:0] N Y [15:8] Y [30:27, 21, 19:16, 15:8] Y [12:8] Y [15:0] Y [15:8] N
Vendor ID Command Revision ID Cache Line Size
PCI Base Address 0; used for Memory-Mapped Configuration Registers (PCIBAR0) PCI Base Address 1; used for I/O-Mapped Configuration Registers (PCIBAR1) PCI Base Address 2; used for Local Address Space 0 (PCIBAR2) PCI Base Address 3; used for Local Address Space 1 (PCIBAR3) PCI Base Address 4; used for Local Address Space 2 (PCIBAR4) PCI Base Address 5; used for Local Address Space 3 (PCIBAR5) Cardbus CIS Pointer (Not supported) Subsystem ID Subsystem Vendor ID PCI Base Address for Local Expansion ROM Reserved
40h
Power Management Capabilities
Next_Cap Pointer
Capability ID
N
44h
Data
PMCSR Bridge Support Extensions Control/Status VPD Address VPD Data
Power Management Control/Status Next_Cap Pointer Next_Cap Pointer Capability ID Capability ID
Y [15, 12:8, 1:0] Y [23:16] Y [31:16] Y
48h 4Ch 50h Note: F
Reserved
Refer to PCI Specification v2.2 for definitions of these registers.
10-2
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Register Address Mapping
Section 10 Registers
Table 10-3. Local Configuration Register Address Mapping
PCI (Offset from Base Address) 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h To ensure software compatibility with other versions of the PCI 9030 family and to ensure compatibility with future enhancements, write 0 to all unused bits. 31 Range for PCI-to-Local Address Space 0 Range for PCI-to-Local Address Space 1 Range for PCI-to-Local Address Space 2 Range for PCI-to-Local Address Space 3 Range for PCI-to-Local Expansion ROM Local Base Address (Remap) for PCI-to-Local Space 0 Local Base Address (Remap) for PCI-to-Local Space 1 Local Base Address (Remap) for PCI-to-Local Space 2 Local Base Address (Remap) for PCI-to-Local Space 3 Local Base Address (Remap) for PCI-to-Local Expansion ROM Local Bus Region Descriptor (Space 0) for PCI-to-Local Accesses Local Bus Region Descriptor (Space 1) for PCI-to-Local Accesses Local Bus Region Descriptor (Space 2) for PCI-to-Local Accesses Local Bus Region Descriptor (Space 3) for PCI-to-Local Accesses Local Bus Region Descriptor (Expansion ROM) for PCI-to-Local Accesses 0 PCI Writable Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Serial EEPROM Writable Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y
Table 10-4. Chip Select Register Address Mapping
PCI (Offset from Base Address) 3Ch 40h 44h 48h To ensure software compatibility with other versions of the PCI 9030 family and to ensure compatibility with future enhancements, write 0 to all unused bits. 31 Local Chip Select 0 Base Address Local Chip Select 1 Base Address Local Chip Select 2 Base Address Local Chip Select 3 Base Address 0 PCI Writable Y Y Y Y Serial EEPROM Writable Y Y Y Y
Table 10-5. Runtime Register Address Mapping
PCI (Offset from Base Address) 4Ch 50h 54h 70h 74h Reserved To ensure software compatibility with other versions of the PCI 9030 family and to ensure compatibility with future enhancements, write 0 to all unused bits. 31 28 27 24 23 16 Serial EEPROM Write-Protected Address Boundary 15 Interrupt Control/Status 0 PCI Writable Y [31:8] Y Y N N Serial EEPROM Writable Y Y Y Y Y
Reserved
PCI Target Response, Serial EEPROM Control, and Initialization Control General Purpose I/O Control Hidden 1 Register for Power Management Data Select, Power Consumed and Dissipated Values Hidden 2 Register for Power Management Data Scale, Power Consumed and Dissipated Values
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
10-3
Section 10--Registers
Section 10 Registers
PCI Configuration Registers
10.3
PCI CONFIGURATION REGISTERS
All registers may be written to or read from in Byte, Word, or Lword accesses.
Register 10-1. (PCIIDR; PCI:00h) PCI Configuration ID
Bit
15:0 31:16
Description
Vendor ID. Identifies manufacturer of device. Defaults to the PCI SIG-issued Vendor ID of PLX (10B5h) if blank or if no serial EEPROM is present. Device ID. Identifies particular device. Defaults to PLX part number for PCI interface chip (9030h) if blank or no serial EEPROM is present.
Read
Yes Yes
Write
Serial EEPROM Serial EEPROM
Value after Reset
10B5h 9030h
Register 10-2. (PCICR; PCI:04h) PCI Command
Bit
0
Description
I/O Space. Writing a 1 allows the device to respond to I/O space accesses. Writing a 0 disables the device from responding to I/O space accesses. Memory Space. Writing a 1 allows the device to respond to Memory Space accesses. Writing a 0 disables the device from responding to Memory Space accesses. Master Enable. Not supported. Special Cycle. Not supported. Memory Write and Invalidate Enable. Not supported. VGA Palette Snoop. Not supported. Parity Error Response. Writing a 0 indicates parity error is ignored and the operation continues. Writing a 1 indicates parity checking is enabled. Wait Cycle Control. Controls whether a device does address/data stepping. Writing a 0 indicates the device never does stepping. Writing a 1 indicates the device always does stepping. Note: Hardcoded to 0. SERR# Enable. Writing a 1 enables SERR# driver. Writing a 0 disables SERR# driver. Fast Back-to-Back Enable. Indicates what type of fast back-to-back transfers a Master can perform on the bus. Writing a 1 indicates fast back-to-back transfers can occur to any agent on the bus. Writing a 0 indicates fast back-toback transfers can only occur to the same agent as in the previous cycle. Note: Hardcoded to 0. Reserved.
Read
Yes
Write
Yes
Value after Reset
0
1 2 3 4 5 6
Yes Yes Yes Yes Yes Yes
Yes No No No No Yes
0 0 0 0 0 0
7
Yes
No
0
8
Yes
Yes
0
9
Yes
No
0
15:10
Yes
No
0h
10-4
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
PCI Configuration Registers
Section 10 Registers
Register 10-3. (PCISR; PCI:06h) PCI Status
Bit
3:0 Reserved. New Capability Functions Support. Writing a 1 supports New Capabilities Functions. If enabled, the first New Capability Function ID is located at PCI Configuration offset [40h]. Can only be written from the serial EEPROM. Read-only from the PCI Bus. Reserved. Fast Back-to-Back Capable. Writing a 1 indicates an adapter can accept fast back-to-back transactions. Note: 8 10:9 Hardcoded to 1. Yes Yes No No 0 01
Description
Read
Yes
Write
No Serial EEPROM No No
Value after Reset
0h
4
Yes
1
6:5 7
Yes Yes
0 1
Master Data Parity Error Detected. Not supported. DEVSEL# Timing. Indicates timing for DEVSEL# assertion. Writing a 01 sets this bit to medium. Note: Hardcoded to 01. Target Abort. When set to 1, indicates the PCI 9030 signaled a Target Abort. Writing a 1 clears this bit to 0. Received Target Abort. When set to 1, indicates the PCI 9030 received a Target Abort signal. Not supported. Received Master Abort. When set to 1, indicates the PCI 9030 received a Master abort signal. Not supported. Signaled System Error. When set to 1, indicates the PCI 9030 reported a system error on SERR#. Writing a 1 clears this bit to 0. Detected Parity Error. When set to 1, indicates the PCI 9030 detected a PCI Bus parity error, even if parity error handling is disabled (the Parity Error Response bit in the Command register is clear). One of three conditions can cause this bit to be set when the PCI 9030 detects a parity error: 1) During PCI Address phase; 2) When it was the Target of a write; 3) When performing Master Read operation. Writing a 1 clears this bit to 0.
11 12 13 14
Yes Yes Yes Yes
Yes/Clr No No Yes/Clr
0 0 0 0
15
Yes
Yes/Clr
0
Register 10-4. (PCIREV; PCI:08h) PCI Revision ID
Bit
7:0
Description
Revision ID. PCI 9030 Silicon revision.
Read
Yes
Write
Serial EEPROM
Value after Reset
Current Rev #
Register 10-5. (PCICCR; PCI:09-0Bh) PCI Class Code
Section 10--Registers Bit
7:0 15:8 23:16
Description
Register Level Programming Interface. None defined. Subclass Code (Other Bridge Device). Base Class Code (Bridge Device).
Read
Yes Yes Yes
Write
Serial EEPROM Serial EEPROM Serial EEPROM
Value after Reset
0h 80h 06h
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
10-5
Section 10 Registers
PCI Configuration Registers
Register 10-6. (PCICLSR; PCI:0Ch) PCI Cache Line Size
Bit
7:0
Description
System Cache Line Size. Specified in units of 32-bit words (8 or 16 Lwords). Can be written and read; however, the value has no effect on chip operation.
Read
Yes
Write
Yes
Value after Reset
0h
Register 10-7. (PCILTR; PCI:0Dh) PCI Bus Latency Timer
Bit
7:0
Description
PCI Bus Latency Timer. Not supported.
Read
Yes
Write
No
Value after Reset
0h
Register 10-8. (PCIHTR; PCI:0Eh) PCI Header Type
Bit
6:0
Description
Configuration Layout Type. Specifies layout of bits 10h through 3Fh in configuration space. Only one encoding, 0h, is defined. All other encodings are reserved. Header Type. Writing a 1 indicates multiple functions. Writing a 0 indicates single function.
Read
Yes
Write
No
Value after Reset
0h
7
Yes
No
0
Register 10-9. (PCIBISTR; PCI:0Fh) PCI Built-In Self Test (BIST)
Bit
7:0
Description
Built-In Test. Value of 0 indicates device passed its test. Not supported.
Read
Yes
Write
No
Value after Reset
0h
Register 10-10. (PCIBAR0; PCI:10h) PCI Base Address Register for Memory Accesses to Local Registers
Bit Description
Memory Space Indicator. Writing a 0 indicates the register maps into Memory space. Writing a 1 indicates the register maps into I/O space. Note: Hardcoded to 0. Location of Register. Values: 00--Locate anywhere in 32-bit Memory Address space 01--Locate below 1-MB Memory Address space 10--Locate anywhere in 64-bit Memory Address space 11--Reserved Note: 3 Hardcoded to 00. Yes No 0 Prefetchable. Writing a 1 indicates there are no side effects on reads. Does not affect the PCI 9030 operation. Note: 6:4 31:7 Hardcoded to 0. Yes Yes No Yes 0h 0h Memory Base Address. Memory base address for access to Local registers (requires 128 bytes). Note: Hardcoded to 0h. Memory Base Address. Memory base address for access to Local registers.
Read
Write
Value after Reset
0
0
Yes
No
2:1
Yes
No
00
10-6
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
PCI Configuration Registers
Section 10 Registers
Register 10-11. (PCIBAR1; PCI:14h) PCI Base Address Register for I/O Accesses to Local Registers
Bit Description
Memory Space Indicator. Writing a 0 indicates the register maps into Memory space. Writing a 1 indicates the register maps into I/O space. Note: 1 6:2 31:7 Hardcoded to 1. Yes Yes Yes No No Yes 0 0h 0h Reserved. I/O Base Address. Base Address for I/O access to Local registers (requires 128 bytes). Note: Hardcoded to 0h. I/O Base Address. Base Address for I/O access to Local registers.
Read
Write
Value after Reset
1
0
Yes
No
Register 10-12. (PCIBAR2; PCI:18h) PCI Base Address Register for Memory Accesses to Local Address Space 0
Bit
0
Description
Memory Space Indicator. Writing a 0 indicates the register maps into Memory space. Writing a 1 indicates the register maps into I/O space. (Specified in the LAS0RR register.) Location of Register (If Memory Space). Values: 00--Locate anywhere in 32-bit Memory Address space 01--Locate below 1-MB Memory Address space 10--Locate anywhere in 64-bit Memory Address space 11--Reserved (Specified in the LAS0RR register.) If I/O Space, bit 1 is always 0 and bit 2 is included in the base address. Prefetchable (If Memory Space). Writing a 1 indicates there are no side effects on reads. Reflects value of LAS0RR[3] and provides only status to the system. Does not affect PCI 9030 operation. The associated Bus Region Descriptor register controls prefetching functions of this address space. (Specified in the LAS0RR register.) If I/O Space, bit 3 is included in the base address. Memory Base Address. Memory base address for access to Local Address Space 0. PCIBAR2 can be enabled or disabled by setting or clearing the Space 0 Enable bit (LAS0BA[0]). PCIBAR2 can be enabled or disabled by setting or clearing LAS0BA[0].
Read
Yes
Write
No
Value after Reset
0
Mem: No Yes I/O: bit 1 no, bit 2 yes 00
2:1
3
Yes
Mem: No I/O: Yes
0
31:4 Note:
Yes
Yes
0h
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
10-7
Section 10--Registers
Section 10 Registers
PCI Configuration Registers
Register 10-13. (PCIBAR3; PCI:1Ch) PCI Base Address Register for Memory Accesses to Local Address Space 1
Bit
0
Description
Memory Space Indicator. Writing a 0 indicates the register maps into Memory space. Writing a 1 indicates the register maps into I/O space. (Specified in the LAS1RR register.) Location of Register. Values: 00--Locate anywhere in 32-bit Memory Address space 01--Locate below 1-MB Memory Address space 10--Locate anywhere in 64-bit Memory Address space 11--Reserved (Specified in the LAS1RR register.) If I/O Space, bit 1 is always 0 and bit 2 is included in the base address. Prefetchable (If Memory Space). Writing a 1 indicates there are no side effects on reads. Reflects value of LAS1RR[3] and provides only status to the system. Does not affect PCI 9030 operation. The associated Bus Region Descriptor register controls prefetching functions of this address space. (Specified in the LAS1RR register.) If I/O Space, bit 3 is included in base address. Memory Base Address. Memory base address for access to Local Address Space 1. PCIBAR3 can be enabled or disabled by setting or clearing the Space 1 Enable bit (LAS1BA[0]). PCIBAR3 can be enabled or disabled by setting or clearing LAS1BA[0].
Read
Yes
Write
No
Value after Reset
0
Mem: No Yes I/O: Bit 1 No, Bit 2 Yes 00
2:1
3
Yes
Mem: No I/O: Yes
0
31:4 Note:
Yes
Yes
0h
Register 10-14. (PCIBAR4; PCI:20h) PCI Base Address Register for Memory Accesses to Local Address Space 2
Bit
0
Description
Memory Space Indicator. Writing a 0 indicates the register maps into Memory space. Writing a 1 indicates the register maps into I/O space. (Specified in the LAS2RR register.) Location of Register. Values: 00--Locate anywhere in 32-bit Memory Address space 01--Locate below 1-MB Memory Address space 10--Locate anywhere in 64-bit Memory Address space 11--Reserved (Specified in the LAS2RR register.) If I/O Space, bit 1 is always 0 and bit 2 is included in the base address. Prefetchable (If Memory Space). Writing a 1 indicates there are no side effects on reads. Reflects value of LAS2RR[3] and provides only status to the system. Does not affect the PCI 9030 operation. The associated Bus Region Descriptor register controls prefetching functions of this address space. (Specified in the LAS2RR register.) If I/O Space, bit 3 is included in base address. Memory Base Address. Memory base address for access to Local Address Space 2. PCIBAR4 can be enabled or disabled by setting or clearing the Space 2 Enable bit (LAS2BA[0]). PCIBAR4 can be enabled or disabled by setting or clearing LAS2BA[0].
Read
Yes
Write
No
Value after Reset
0
Mem: No Yes I/O: Bit 1 No, Bit 2 Yes 00
2:1
3
Yes
Mem: No I/O: Yes
0
31:4 Note:
Yes
Yes
0h
10-8
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
PCI Configuration Registers
Section 10 Registers
Register 10-15. (PCIBAR5; PCI:24h) PCI Base Address Register for Memory Accesses to Local Address Space 3
Bit
0
Description
Memory Space Indicator. Writing a 0 indicates the register maps into Memory space. Writing a 1 indicates the register maps into I/O space. (Specified in the LAS3RR register.) Location of Register. Values: 00--Locate anywhere in 32-bit Memory Address space 01--Locate below 1-MB Memory Address space 10--Locate anywhere in 64-bit Memory Address space 11--Reserved (Specified in the LAS3RR register.) If I/O Space, bit 1 is always 0 and bit 2 is included in the base address. Prefetchable (If Memory Space). Writing a 1 indicates there are no side effects on reads. Reflects value of LAS3RR[3] and provides only status to the system. Does not affect the PCI 9030 operation. The associated Bus Region Descriptor register controls prefetching functions of this address space. (Specified in the LAS3RR register.) If I/O Space, bit 3 is included in base address. Memory Base Address. Memory base address for access to Local Address Space 3. PCIBAR5 can be enabled or disabled by setting or clearing the Space 3 Enable bit (LAS3BA[0]). PCIBAR5 can be enabled or disabled by setting or clearing LAS3BA[0].
Read
Yes
Write
No
Value after Reset
0
Mem: No Yes I/O: Bit 1 No, Bit 2 Yes 00
2:1
3
Yes
Mem: No I/O: Yes
0
31:4 Note:
Yes
Yes
0h
Register 10-16. (PCICIS; PCI:28h) PCI Cardbus CIS Pointer
Bit
31:0
Description
Cardbus Information Structure Pointer for PCMCIA. Not supported.
Read
Yes
Write
No
Value after Reset
0h
Register 10-17. (PCISVID; PCI:2Ch) PCI Subsystem Vendor ID
Bit
15:0
Description
Subsystem Vendor ID (Unique Add-in Board Vendor ID).
Read
Yes
Write
Serial EEPROM
Value after Reset
0h
Register 10-18. (PCISID; PCI:2Eh) PCI Subsystem ID
Bit
15:0
Description
Subsystem ID (Unique Add-in Board Device ID).
Read
Yes
Write
Serial EEPROM
Value after Reset
0h
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
10-9
Section 10--Registers
Section 10 Registers
PCI Configuration Registers
Register 10-19. (PCIERBAR; PCI:30h) PCI Expansion ROM Base
Bit Description
Address Decode Enable. Writing a 1 indicates a device accepts accesses to the Expansion ROM space. Writing a 0 indicates a device does not accept accesses to Expansion ROM space. Should be set to 0 if there is no Expansion ROM. Works in conjunction with EROMRR[0]. Reserved. Expansion ROM Base Address (upper 21 bits).
Read
Write
Value after Reset
0
0
Yes
Yes
10:1 31:11
Yes Yes
No Yes
0h 0h
Register 10-20. (CAP_PTR; PCI:34h) New Capability Pointer
Bit
7:0 31:8
Description
New Capability Pointer. Provides an offset into PCI Configuration Space for location of the first item in the New Capabilities Linked List. Reserved.
Read
Yes Yes
Write
Serial EEPROM No
Value after Reset
40h 0h
Register 10-21. (PCIILR; PCI:3Ch) PCI Interrupt Line
Bit
7:0
Description
Interrupt Line Routing Value. Value indicates which input of the system interrupt controller(s) is connected to each device interrupt line.
Read
Yes
Write
Yes
Value after Reset
0h
Register 10-22. (PCIIPR; PCI:3Dh) PCI Interrupt Pin
Bit Description
Interrupt Pin Register. Indicates which interrupt pin the device uses. The following values are decoded (the PCI 9030 supports only INTA#): 0 = No Interrupt Pin 1 = INTA# 2 = INTB# 3 = INTC# 4 = INTD#
Read
Write
Value after Reset
7:0
Yes
Serial EEPROM
1h
Register 10-23. (PCIMGR; PCI:3Eh) PCI Min_Gnt
Bit
7:0
Description
Min_Gnt. Specifies how long a Burst period device needs, assuming a clock rate of 33 MHz. Value is a multiple of 1/4 s increments. Not Supported.
Read
Yes
Write
No
Value after Reset
0h
10-10
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
PCI Configuration Registers
Section 10 Registers
Register 10-24. (PCIMLR; PCI:3Fh) PCI Max_Lat
Bit
7:0
Description
Max_Lat. Specifies how often the device must gain access to the PCI Bus. Value is a multiple of 1/4 s increments. Not Supported.
Read
Yes
Write
No
Value after Reset
0h
Register 10-25. (PMCAPID; PCI:40h) Power Management Capability ID
Bit
7:0
Description
Power Management Capability ID.
Read
Yes
Write
No
Value after Reset
1h
Register 10-26. (PMNEXT; PCI:41h) Power Management Next Capability Pointer
Bit
7:0
Description
Next_Cap Pointer. Points to the first location of the next item in the capabilities linked list. If power management is the last item in the list, set this register to 0.
Read
Yes
Write
Serial EEPROM
Value after Reset
48h
Register 10-27. (PMC; PCI:42h) Power Management Capabilities
Bit
2:0
Description
Version. Writing a 1 indicates this function complies with PCI Bus Power Management Interface Specification v1.1. PCI Clock Required for PME# Signal. When set to 1, indicates a function relies on PCI clock presence for PME# operation. The PCI 9030 does not require the PCI clock for PME#, so this bit should set to 0. Auxiliary Power Source. Because the PCI 9030 does not support PME# while in a D3cold state, this bit is always set to 0. Not supported. DSI. When set to 1, the PCI 9030 requires special initialization following a transition to a D0 uninitialized state before a generic class device driver is able to use it. Reserved. D1_Support. When set to 1, the PCI 9030 supports the D1 power state. Not supported. D2_Support. When set to 1, the PCI 9030 supports the D2 power state. Not supported. PME#_Support. Indicates power states in which the PCI 9030 may assert PME#. Value Description XXX1 PME# can be asserted from D0 1XXX PME# can be asserted from D3hot Reserved.
Read
Yes
Write
Serial EEPROM Serial EEPROM No Serial EEPROM No No No
Value after Reset
001
3
Yes
0
4
Yes
0
5 8:6 9 10
Yes Yes Yes Yes
0 000 0 0
14:11
Yes
Serial EEPROM
9h
15
Yes
No
0
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
10-11
Section 10--Registers
Section 10 Registers
PCI Configuration Registers
Register 10-28. (PMCSR; PCI:44h) Power Management Control/Status
Bit Description
Power State. Determines or changes the current power state. Value State 00 D0 11 D3hot Transition from a D3hot state to a D0 state causes a soft reset. Should only be initiated from the PCI Bus because the Local Bus interface is reset during a soft reset. In a D3hot state, PCI Memory and I/O accesses are disabled, as well as PCI interrupts, and only configuration is allowed. Reserved. PME#_En. Writing a 1 enables PME# to be asserted. Data_Select. Selects which data to report through the Data register and Data_Scale bits. Data_Scale. Indicates the scaling factor to use when interpreting the Data register value. Value and meaning of this bit depends on the data value selected by the Data_Select bit. When the Local CPU initializes the Data_Scale values, it must use the Data_Select bit to determine which Data_Scale value it is writing. For Power Consumed and Power Dissipated data, the following scale factors are used. Unit values are in watts. Value Scale 0 Unknown 1 0.1x 2 0.01x 3 0.001x Note: Information regarding hidden register use is provided in Section 7.2.1. PME#_Status. Indicates PME# is being driven if the PME#_En bit is set (PMCSR[8]=1). Writing a 1 from the Local Bus sets this bit; writing a 1 from the PCI Bus clears this bit to 0. Depending on the current power state, set only if the appropriate PME#_Support bit(s) is set (PMC[15:11]=1). Local Interrupt/Set, PCI/Clr
Read
Write
Value after Reset
1:0
Yes
Yes
00
7:2 8 12:9
Yes Yes Yes
No Yes/ Serial EEPROM Yes/ Serial EEPROM
0h 0 0h
14:13
Yes
Serial EEPROM by way of PMDATASCALE
00
15
Yes
0
Register 10-29. (PMCSR_BSE; PCI:46h) PMCSR Bridge Support Extensions
Bit
7:0 Reserved.
Description
Read
Yes
Write
No
Value after Reset
0h
10-12
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
PCI Configuration Registers
Section 10 Registers
Register 10-30. (PMDATA; PCI:47h) Power Management Data
Bit Description
Power Management Data. Provides operating data, such as power consumed or heat dissipation. Data returned is selected by the Data_Select bit(s) (PMCSR[12:9]) and scaled by the Data_Scale bit(s) (PMCSR[14:13]). Data_Select Description 0 D0 Power Consumed 1 Reserved 2 Reserved 3 D3 Power Consumed 4 D0 Power Dissipated 5 Reserved 6 Reserved 7 D3hot Power Dissipated Note: Information regarding hidden register use is provided in Section 7.2.1.
Read
Write
Value after Reset
7:0
Yes
Serial EEPROM by way of PMDATASEL
0h
Register 10-31. (HS_CNTL; PCI:48h) Hot Swap Control
Bit
7:0 Hot Swap ID.
Description
Read
Yes
Write
Serial EEPROM
Value after Reset
06h
Register 10-32. (HS_NEXT; PCI:49h) Hot Swap Next Capability Pointer
Bit
7:0
Description
Next_Cap Pointer. Points to the first location of the next item in the capabilities linked list. If Hot Swap is the last item in the list, this register should be set to zero.
Read
Yes
Write
Serial EEPROM
Value after Reset
4Ch
Register 10-33. (HS_CSR; PCI:4Ah) Hot Swap Control/Status
Bit
0 1 2 3 5:4 6 Reserved. ENUM# Interrupt Mask. Writing a 0 enables the interrupt. Writing a 1 masks the interrupt. Reserved. LED Software On/Off Switch. Writing a 1 turns on the LED. Writing a 0 turns off the LED. Reserved. ENUM# Status Indicator for Board Removal. Value of 1 reports the ENUM# assertion for removal process. Writing a 1 clears the ENUM# Interrupt and Status bit. ENUM# Status Indicator for Board Insertion. Value of 1 reports the ENUM# assertion for the insertion process. Writing a 1 clears the ENUM# Interrupt and Status bit. Reserved.
Description
Read
Yes Yes Yes Yes Yes Yes
Write
No PCI No PCI No PCI/Clr
Value after Reset
0 0 0 0 00 0
7 15:8
Yes Yes
PCI/Clr No
0 0h
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
10-13
Section 10--Registers
Section 10 Registers
PCI Configuration Registers
Register 10-34. (PVPDCNTL; PCI:4Ch) PCI Vital Product Data Control
Bit
7:0
Description
VPD ID. Capability ID = 03h for VPD.
Read
PCI
Write
No
Value after Reset
03h
Register 10-35. (PVPD_NEXT; PCI:4Dh) PCI Vital Product Data Next Capability Pointer
Bit
7:0
Description
Next_Cap Pointer. Points to first location of next item in the capabilities linked list. VPD is the last item in the New Capabilities Linked List. This register is set to 0h.
Read
PCI
Write
Serial EEPROM
Value after Reset
0h
Register 10-36. (PVPDAD; PCI:4Eh) PCI Vital Product Data Address
Bit
14:0
Description
VPD Address. Byte address of the VPD address to be accessed. Supports 2K- or 4K-bit serial EEPROM. F. Flag used to indicate when the transfer of data between PVPDATA and the storage component is complete. Writing a 0 along with the VPD address causes a read of VPD information into PVPDATA. The hardware sets this bit to 1 when the VPD Data transfer is complete. Writing a 1 along with the VPD address causes a write of VPD information from PVPDATA into a storage component. The hardware sets this bit to 0 after the Write operation is complete.
Read
PCI
Write
Yes
Value after Reset
0h
15
PCI
Yes
0
Register 10-37. (PVPDATA; PCI:50h) PCI VPD Data
Bit
31:0 VPD Data Register.
Description
Read
PCI
Write
Yes
Value after Reset
0h
10-14
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Local Configuration Registers
Section 10 Registers
10.4
LOCAL CONFIGURATION REGISTERS
Value after Reset
0
Register 10-38. (LAS0RR; 00h) Local Address Space 0 Range Register for PCI-to-Local Bus
Bit
0
Description
Memory Space Indicator. Writing a 0 indicates Local Address Space 0 maps into PCI Memory space. Writing a 1 indicates address Space 0 maps into PCI I/O space. When mapped into Memory space, encoding is as follows: 2/1 Meaning 00 Locate anywhere in 32-bit PCI Address space 01 Locate below 1 MB in PCI Address space 10 Locate anywhere in 64-bit PCI Address space 11 Reserved When mapped into I/O space, bit 1 must be set to 0. Bit 2 is included with bits [27:3] to indicate the decoding range. When mapped into Memory space, writing a 1 indicates reads are prefetchable (does not affect the PCI 9030 operation, but is used for system status). When mapped into I/O space, it is included with bits [27:2] to indicate the decoding range. Specifies which PCI Address bits to use for decoding a PCI access to Local Bus Space 0. Each bit corresponds to a PCI Address bit. Bit 27 corresponds to address bit 27. Write 1 to all bits that are to be included in decode and 0 to all others (used in conjunction with PCIBAR2). Default is 1 MB. Notes: Range (not Range register) must be power of 2. "Range register value" is inverse of range. User should limit all I/O spaces to 256 bytes per "PCI Specification v2.2."
Read
Yes
Write
Yes
2:1
Yes
Yes
00
3
Yes
Yes
0
27:4
Yes
Yes
FF0000h
31:28
Reserved. (PCI address bits [31:28] are always included in decoding.)
Yes
No
0h
Register 10-39. (LAS1RR; 04h) Local Address Space 1 Range Register for PCI-to-Local Bus
Bit
0
Description
Memory Space Indicator. Writing a 0 indicates Local Address Space 1 maps into PCI Memory space. Writing a 1 indicates address Space 1 maps into PCI I/O space. When mapped into Memory space, encoding is as follows: 2/1 Meaning 00 Locate anywhere in 32-bit PCI Address space 01 Locate below 1 MB in PCI Address space 10 Locate anywhere in 64-bit PCI Address space 11 Reserved When mapped into I/O space, bit 1 must be set to 0. Bit 2 is included with bits [27:3] to indicate the decoding range. When mapped into Memory space, writing a 1 indicates reads are prefetchable (does not affect the PCI 9030 operation, but is used for system status). When mapped into I/O space, it is included with bits [27:2] to indicate the decoding range. Specifies which PCI Address bits to use for decoding a PCI access to Local Bus Space 1. Each bit corresponds to a PCI Address bit. Bit 27 corresponds to address bit 27. Write 1 to all bits that are to be included in decode and 0 to all others (used in conjunction with PCIBAR3). Notes: Range (not Range register) must be power of 2. "Range register value" is inverse of range. User should limit all I/O spaces to 256 bytes per "PCI Specification v2.2."
Read
Yes
Write
Yes
Value after Reset
0
2:1
Yes
Yes
00
3
Yes
Yes
0
27:4
Yes
Yes
000000h
31:28
Reserved. (PCI address bits [31:28] are always included in decoding.)
Yes
No
0h
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
10-15
Section 10--Registers
Section 10 Registers
Local Configuration Registers
Register 10-40. (LAS2RR; 08h) Local Address Space 2 Range Register for PCI-to-Local Bus
Bit
0
Description
Memory Space Indicator. Writing a 0 indicates Local Address Space 2 maps into PCI Memory space. Writing a 1 indicates address Space 2 maps into PCI I/O space. When mapped into Memory space, encoding is as follows: Meaning 2/1 00 Locate anywhere in 32-bit PCI Address space 01 Locate below 1 MB in PCI Address space 10 Locate anywhere in 64-bit PCI Address space 11 Reserved When mapped into I/O space, bit 1 must be set to 0. Bit 2 is included with bits [27:3] to indicate the decoding range. When mapped into Memory space, writing a 1 indicates reads are prefetchable (does not affect the PCI 9030 operation, but is used for system status). When mapped into I/O space, it is included with bits [27:2] to indicate the decoding range. Specifies which PCI Address bits to use for decoding a PCI access to Local Bus Space 2. Each bit corresponds to a PCI Address bit. Bit 27 corresponds to address bit 27. Write 1 to all bits that are to be included in decode and 0 to all others (used in conjunction with PCIBAR4). Notes: Range (not Range register) must be power of 2. "Range register value" is inverse of range. User should limit all I/O spaces to 256 bytes per "PCI Specification v2.2."
Read
Yes
Write
Yes
Value after Reset
0
2:1
Yes
Yes
00
3
Yes
Yes
0
27:4
Yes
Yes
000000h
31:28
Reserved. (PCI address bits [31:28] are always included in decoding.)
Yes
No
0h
Register 10-41. (LAS3RR; 0Ch) Local Address Space 3 Range Register for PCI-to-Local Bus
Bit
0
Description
Memory Space Indicator. Writing a 0 indicates Local Address Space 3 maps into PCI Memory space. Writing a 1 indicates address Space 3 maps into PCI I/O space. When mapped into Memory space, encoding is as follows: 2/1 Meaning 00 Locate anywhere in 32-bit PCI Address space 01 Locate below 1 MB in PCI Address space 10 Locate anywhere in 64-bit PCI Address space 11 Reserved When mapped into I/O space, bit 1 must be set to 0. Bit 2 is included with bits [27:3] to indicate the decoding range. When mapped into Memory space, writing a 1 indicates reads are prefetchable (does not affect the PCI 9030 operation, but is used for system status). When mapped into I/O space, it is included with bits [27:2] to indicate the decoding range. Specifies which PCI Address bits to use for decoding a PCI access to Local Bus Space 3. Each bit corresponds to a PCI Address bit. Bit 27 corresponds to address bit 27. Write 1 to all bits that are to be included in decode and 0 to all others (used in conjunction with PCIBAR5). Notes: Range (not Range register) must be power of 2. "Range register value" is inverse of range. User should limit all I/O spaces to 256 bytes per "PCI Specification v2.2."
Read
Yes
Write
Yes
Value after Reset
0
2:1
Yes
Yes
00
3
Yes
Yes
0
27:4
Yes
Yes
000000h
31:28
Reserved. (PCI address bits [31:28] are always included in decoding.)
Yes
No
0h
10-16
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Local Configuration Registers
Section 10 Registers
Register 10-42. (EROMRR; 10h) Expansion ROM Range
Bit
0 10:1
Description
Address Decode Enable. Bit 0 can only be enabled from the serial EEPROM. To disable, set PCI Expansion ROM Address Decode Enable bit to 0 (PCIERBAR[0]=0; 30h). Reserved. Specifies which PCI Address bits to use for decoding a PCI-to-Local Bus Expansion ROM. Each bit corresponds to a PCI Address bit. Bit 31 corresponds to address bit 31. Write 1 to all bits that are to be included in decode and 0 to all others (used in conjunction with PCIERBAR). Default is 64 KB. Note: Range (not Range register) must be power of 2. "Range register value" is inverse of range.
Read
Yes Yes
Write
Serial EEPROM Only No
Value after Reset
0 0h
27:11
Yes
Yes
1111111111110 0000
31:28
Reserved. (PCI address bits [31:28] are always included in decoding.)
Yes
Yes
1111
Register 10-43. (LAS0BA; 14h) Local Address Space 0 Local Base Address (Remap)
Bit
0 1 3:2
Description
Space 0 Enable. Writing a 1 enables decoding of PCI addresses for PCI Target access to Local Bus Space 0. Writing a 0 disables decoding. Reserved. If Local Bus Space 0 is mapped into Memory space, bits are not used. When mapped into I/O space, included with bits [27:4] for remapping. Remap PCI Address to Local Address Space 0 into Local Address Space. Bits in this register remap (replace) PCI Address bits used in decode as Local Address bits. Note: Remap Address value must be a Range multiple (not the Range register). Reserved. (Local address bits [31:28] do not exist in the PCI 9030.)
Read
Yes Yes Yes
Write
Yes No Yes
Value after Reset
1 0 00
27:4
Yes
Yes
0h
31:28
Yes
No
0h
Register 10-44. (LAS1BA; 18h) Local Address Space 1 Local Base Address (Remap)
Bit
0 1 3:2
Description
Space 1 Enable. Writing a 1 enables decoding of PCI addresses for PCI Target access to Local Bus Space 1. Writing a 0 disables decoding. PCIBAR3 can be enabled or disabled by setting or clearing this bit. Reserved. If Local Bus Space 1 is mapped into Memory space, bits are not used. When mapped into I/O space, included with bits [27:4] for remapping. Remap PCI Address to Local Address Space 1 into Local Address Space. Bits in this register remap (replace) PCI Address bits used in decode as Local Address bits. Note: Remap Address value must be a Range multiple (not the Range register). Reserved. (Local address bits [31:28] do not exist in the PCI 9030.)
Read
Yes Yes Yes
Write
Yes No Yes
Value after Reset
0 0 00
31:28
Yes
No
0h
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
10-17
Section 10--Registers
27:4
Yes
Yes
0h
Section 10 Registers
Local Configuration Registers
Register 10-45. (LAS2BA; 1Ch) Local Address Space 2 Local Base Address (Remap)
Bit
0 1 3:2
Description
Space 2 Enable. Writing a 1 enables decoding of PCI addresses for PCI Target access to Local Bus Space 2. Writing a 0 disables decoding. PCIBAR4 can be enabled or disabled by setting or clearing this bit. Reserved. If Local Bus Space 2 is mapped into Memory space, bits are not used. When mapped into I/O space, included with bits [27:4] for remapping. Remap PCI Address to Local Address Space 2 into Local Address Space. Bits in this register remap (replace) PCI Address bits used in decode as Local Address bits. Note: Remap Address value must be a Range multiple (not the Range register). Reserved. (Local address bits [31:28] do not exist in the PCI 9030.)
Read
Yes Yes Yes
Write
Yes No Yes
Value after Reset
0 0 00
27:4
Yes
Yes
0h
31:28
Yes
No
0h
Register 10-46. (LAS3BA; 20h) Local Address Space 3 Local Base Address (Remap)
Bit
0 1 3:2
Description
Space 3 Enable. Writing a 1 enables decoding of PCI addresses for PCI Target access to Local Bus Space 3. Writing a 0 disables decoding. PCIBAR5 can be enabled or disabled by setting or clearing this bit. Reserved. If Local Bus Space 3 is mapped into Memory space, bits are not used. When mapped into I/O space, included with bits [27:4] for remapping. Remap PCI Address to Local Address Space 3 into Local Address Space. Bits in this register remap (replace) PCI Address bits used in decode as Local Address bits. Note: Remap Address value must be a Range multiple (not the Range register). Reserved. (Local address bits [31:28] do not exist in the PCI 9030.)
Read
Yes Yes Yes
Write
Yes No Yes
Value after Reset
0 0 00
27:4
Yes
Yes
0h
31:28
Yes
No
0h
Register 10-47. (EROMBA; 24h) Expansion ROM Local Base Address (Remap)
Bit
10:0 Reserved. Remap PCI Expansion ROM Space into Local Address Space. Bits in this register remap (replace) the PCI Address bits used in decode as Local Address bits. Note: 31:28 Remap Address value must be a Range multiple (not the Range register). Yes No 0h Reserved. (Local address bits [31:28] do not exist in the PCI 9030.)
Description
Read
Yes
Write
No
Value after Reset
0h 0000000100000 0000
27:11
Yes
Yes
10-18
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Local Configuration Registers
Section 10 Registers
Register 10-48. (LAS0BRD; 28h) Local Address Space 0 Bus Region Descriptor
Bit
0 1
Description
Memory Space 0 Burst Enable. Writing a 1 enables bursting. Writing a 0 disables bursting. Bursting occurs only if Prefetch Count is not equal to 00. Memory Space 0 READY# Input Enable. Writing a 1 enables READY# input. Writing a 0 disables READY# input. Memory Space 0 BTERM# Input Enable. Writing a 1 enables BTERM# input. Writing a 0 disables BTERM# input. For more information, refer to Section 2.2.4.3. Prefetch Count. Number of Lwords to prefetch during Memory Read cycle. Used only if bit 5 is high (prefetch count enabled). Values: 00 = Do not prefetch. Only read bytes specified by C/BE lines. 01 = Prefetch four Lwords if bit 5 is set. 10 = Prefetch eight Lwords if bit 5 is set. 11 = Prefetch 16 Lwords if bit 5 is set. Prefetch Counter Enable. When set to 1 and Memory prefetching is enabled, the PCI 9030 prefetches up to the number of Lwords specified in prefetch count. When set to 0, the PCI 9030 ignores the count and continues prefetching until it is terminated by the PCI Bus. NRAD Wait States. Number of Read Address-to-Data wait states (0-31). NRDD Wait States. Number of Read Data-to-Data wait states (0-3). NXDA Wait States. Number of Read/Write Data-to-Address wait states (0-3). NWAD Wait States. Number of Write Address-to-Data wait states (0-31). NWDD Wait States. Number of Write Data-to-Data wait states (0-3). Memory Space 0 Local Bus Width. Writing a 00 indicates an 8-bit bus width. Writing a 01 indicates a 16-bit bus width. Writing a 10 indicates a 32-bit bus width. Note: Setting of 11 is reserved. Byte Ordering. Value of 1 indicates Big Endian. Value of 0 indicates Little Endian. Big Endian Byte Lane Mode. Writing a 1 specifies that in any Endian mode, use byte lanes [31:16] for a 16-bit Local Bus and byte lanes [31:24] for an 8-bit Local Bus. Writing a 0 specifies that in any Endian mode, use byte lanes [15:0] for a 16-bit Local Bus and byte lanes [7:0] for an 8-bit Local Bus. Read Strobe Delay. Number of clocks from beginning of cycle until RD strobe is asserted (0-3). Value must be NRAD for RD# to be asserted. Write Strobe Delay. Number of clocks from beginning of cycle until WR strobe is asserted (0-3). Value must be NWAD for WR# to be asserted. Write Cycle Hold. Number of clocks from WR# de-assertion until end of cycle (0-3).
Read
Yes Yes
Write
Yes Yes
Value after Reset
0 0
2
Yes
Yes
0
4:3
Yes
Yes
00
5
Yes
Yes
0
10:6 12:11 14:13 19:15 21:20
Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes
0h 00 00 0h 00
23:22
Yes
Yes
10
24
Yes
Yes
0
25
Yes
Yes
0
27:26 29:28 31:30
Yes Yes Yes
Yes Yes Yes
00 00 00
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
10-19
Section 10--Registers
Section 10 Registers
Local Configuration Registers
Register 10-49. (LAS1BRD; 2Ch) Local Address Space 1 Bus Region Descriptor
Bit
0 1
Description
Memory Space 1 Burst Enable. Writing a 1 enables bursting. Writing a 0 disables bursting. Bursting occurs only if Prefetch Count is not equal to 00. Memory Space 1 READY# Input Enable. Writing a 1 enables READY# input. Writing a 0 disables READY# input. Memory Space 1 BTERM# Input Enable. Writing a 1 enables BTERM# input. Writing a 0 disables BTERM# input. For more information, refer to Section 2.2.4.3. Prefetch Count. Number of Lwords to prefetch during Memory Read cycle. Used only if bit 5 is high (prefetch count enabled). Values: 00 = Do not prefetch. Only read bytes specified by C/BE lines. 01 = Prefetch four Lwords if bit 5 is set. 10 = Prefetch eight Lwords if bit 5 is set. 11 = Prefetch 16 Lwords if bit 5 is set. Prefetch Counter Enable. When set to 1 and Memory prefetching is enabled, the PCI 9030 prefetches up to the number of Lwords specified in prefetch count. When set to 0, the PCI 9030 ignores the count and continues prefetching until it is terminated by the PCI Bus. NRAD Wait States. Number of Read Address-to-Data wait states (0-31). NRDD Wait States. Number of Read Data-to-Data wait states (0-3). NXDA Wait States. Number of Read/Write Data-to-Address wait states (0-3). NWAD Wait States. Number of Write Address-to-Data wait states (0-31). NWDD Wait States. Number of Write Data-to-Data wait states (0-3). Memory Space 1 Local Bus Width. Writing a 00 indicates an 8-bit bus width. Writing a 01 indicates a 16-bit bus width. Writing a 10 indicates a 32-bit bus width. Note: Setting of 11 is reserved. Byte Ordering. Value of 1 indicates Big Endian. Value of 0 indicates Little Endian. Big Endian Byte Lane Mode. Writing a 1 specifies that in any Endian mode, use byte lanes [31:16] for a 16-bit Local Bus and byte lanes [31:24] for an 8-bit Local Bus. Writing a 0 specifies that in any Endian mode, use byte lanes [15:0] for a 16-bit Local Bus and byte lanes [7:0] for an 8-bit Local Bus. Read Strobe Delay. Number of clocks from beginning of cycle until RD strobe is asserted (0-3). Value must be NRAD for RD# to be asserted. Write Strobe Delay. Number of clocks from beginning of cycle until WR strobe is asserted (0-3). Value must be NWAD for WR# to be asserted. Write Cycle Hold. Number of clocks from WR# de-assertion until end of cycle (0-3).
Read
Yes Yes
Write
Yes Yes
Value after Reset
0 0
2
Yes
Yes
0
4:3
Yes
Yes
00
5
Yes
Yes
0
10:6 12:11 14:13 19:15 21:20
Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes
0h 00 00 0h 00
23:22
Yes
Yes
10
24
Yes
Yes
0
25
Yes
Yes
0
27:26 29:28 31:30
Yes Yes Yes
Yes Yes Yes
00 00 00
10-20
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Local Configuration Registers
Section 10 Registers
Register 10-50. (LAS2BRD; 30h) Local Address Space 2 Bus Region Descriptor
Bit
0 1
Description
Memory Space 2 Burst Enable. Writing a 1 enables bursting. Writing a 0 disables bursting. Bursting occurs only if Prefetch Count is not equal to 00. Memory Space 2 READY# Input Enable. Writing a 1 enables READY# input. Writing a 0 disables READY# input. Memory Space 2 BTERM# Input Enable. Writing a 1 enables BTERM# input. Writing a 0 disables BTERM# input. For more information, refer to Section 2.2.4.3. Prefetch Count. Number of Lwords to prefetch during Memory Read cycle. Used only if bit 5 is high (prefetch count enabled). Values: 00 = Do not prefetch. Only read bytes specified by C/BE lines. 01 = Prefetch four Lwords if bit 5 is set. 10 = Prefetch eight Lwords if bit 5 is set. 11 = Prefetch 16 Lwords if bit 5 is set. Prefetch Counter Enable. When set to 1 and Memory prefetching is enabled, the PCI 9030 prefetches up to the number of Lwords specified in prefetch count. When set to 0, the PCI 9030 ignores the count and continues prefetching until it is terminated by the PCI Bus. NRAD Wait States. Number of Read Address-to-Data wait states (0-31). NRDD Wait States. Number of Read Data-to-Data wait states (0-3). NXDA Wait States. Number of Read/Write Data-to-Address wait states (0-3). NWAD Wait States. Number of Write Address-to-Data wait states (0-31). NWDD Wait States. Number of Write Data-to-Data wait states (0-3). Memory Space 2 Local Bus Width. Writing a 00 indicates an 8-bit bus width. Writing a 01 indicates a 16-bit bus width. Writing a 10 indicates a 32-bit bus width. Note: Setting of 11 is reserved. Byte Ordering. Value of 1 indicates Big Endian. Value of 0 indicates Little Endian. Big Endian Byte Lane Mode. Writing a 1 specifies that in any Endian mode, use byte lanes [31:16] for a 16-bit Local Bus and byte lanes [31:24] for an 8-bit Local Bus. Writing a 0 specifies that in any Endian mode, use byte lanes [15:0] for a 16-bit Local Bus and byte lanes [7:0] for an 8-bit Local Bus. Read Strobe Delay. Number of clocks from beginning of cycle until RD strobe is asserted (0-3). Value must be NRAD for RD# to be asserted. Write Strobe Delay. Number of clocks from beginning of cycle until WR strobe is asserted (0-3). Value must be NWAD for WR# to be asserted. Write Cycle Hold. Number of clocks from WR# de-assertion until end of cycle (0-3).
Read
Yes Yes
Write
Yes Yes
Value after Reset
0 0
2
Yes
Yes
0
4:3
Yes
Yes
00
5
Yes
Yes
0
10:6 12:11 14:13 19:15 21:20
Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes
0h 00 00 0h 00
23:22
Yes
Yes
10
24
Yes
Yes
0
25
Yes
Yes
0
27:26 29:28 31:30
Yes Yes Yes
Yes Yes Yes
00 00 00
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
10-21
Section 10--Registers
Section 10 Registers
Local Configuration Registers
Register 10-51. (LAS3BRD; 34h) Local Address Space 3 Bus Region Descriptor
Bit
0 1
Description
Memory Space 3 Burst Enable. Writing a 1 enables bursting. Writing a 0 disables bursting. Bursting occurs only if Prefetch Count is not equal to 00. Memory Space 3 READY# Input Enable. Writing a 1 enables READY# input. Writing a 0 disables READY# input. Memory Space 3 BTERM# Input Enable. Writing a 1 enables BTERM# input. Writing a 0 disables BTERM# input. For more information, refer to Section 2.2.4.3. Prefetch Count. Number of Lwords to prefetch during Memory Read cycle. Used only if bit 5 is high (prefetch count enabled). Values: 00 = Do not prefetch. Only read bytes specified by C/BE lines. 01 = Prefetch four Lwords if bit 5 is set. 10 = Prefetch eight Lwords if bit 5 is set. 11 = Prefetch 16 Lwords if bit 5 is set. Prefetch Counter Enable. When set to 1 and Memory prefetching is enabled, the PCI 9030 prefetches up to the number of Lwords specified in prefetch count. When set to 0, the PCI 9030 ignores the count and continues prefetching until it is terminated by the PCI Bus. NRAD Wait States. Number of Read Address-to-Data wait states (0-31). NRDD Wait States. Number of Read Data-to-Data wait states (0-3). NXDA Wait States. Number of Read/Write Data-to-Address wait states (0-3). NWAD Wait States. Number of Write Address-to-Data wait states (0-31). NWDD Wait States. Number of Write Data-to-Data wait states (0-3). Memory Space 3 Local Bus Width. Writing a 00 indicates an 8-bit bus width. Writing a 01 indicates a 16-bit bus width. Writing a 10 indicates a 32-bit bus width. Note: Setting of 11 is reserved. Byte Ordering. Value of 1 indicates Big Endian. Value of 0 indicates Little Endian. Big Endian Byte Lane Mode. Writing a 1 specifies that in any Endian mode, use byte lanes [31:16] for a 16-bit Local Bus and byte lanes [31:24] for an 8-bit Local Bus. Writing a 0 specifies that in any Endian mode, use byte lanes [15:0] for a 16-bit Local Bus and byte lanes [7:0] for an 8-bit Local Bus. Read Strobe Delay. Number of clocks from beginning of cycle until RD strobe is asserted (0-3). Value must be NRAD for RD# to be asserted. Write Strobe Delay. Number of clocks from beginning of cycle until WR strobe is asserted (0-3). Value must be NWAD for WR# to be asserted. Write Cycle Hold. Number of clocks from WR# de-assertion until end of cycle (0-3).
Read
Yes Yes
Write
Yes Yes
Value after Reset
0 0
2
Yes
Yes
0
4:3
Yes
Yes
00
5
Yes
Yes
0
10:6 12:11 14:13 19:15 21:20
Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes
0h 00 00 0h 00
23:22
Yes
Yes
10
24
Yes
Yes
0
25
Yes
Yes
0
27:26 29:28 31:30
Yes Yes Yes
Yes Yes Yes
00 00 00
10-22
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Local Configuration Registers
Section 10 Registers
Register 10-52. (EROMBRD; 38h) Expansion ROM Bus Region Descriptor
Bit
0 1
Description
Expansion ROM Burst Enable. Writing a 1 enables bursting. Writing a 0 disables bursting. Bursting occurs only if Prefetch Count is not equal to 00. Expansion ROM Space READY# Input Enable. Writing a 1 enables READY# input. Writing a 0 disables READY# input. Expansion ROM Space BTERM# Input Enable. Writing a 1 enables BTERM# input. Writing a 0 disables BTERM# input. For more information, refer to Section 2.2.4.3. Prefetch Count. Number of Lwords to prefetch during Memory Read cycle. Used only if bit 5 is high (prefetch count enabled). Values: 00 = Do not prefetch. Only read bytes specified by C/BE lines. 01 = Prefetch four Lwords if bit 5 is set. 10 = Prefetch eight Lwords if bit 5 is set. 11 = Prefetch 16 Lwords if bit 5 is set. Prefetch Counter Enable. When set to 1 and Memory prefetching is enabled, the PCI 9030 prefetches up to the number of Lwords specified in prefetch count. When set to 0, the PCI 9030 ignores the count and continues prefetching until it is terminated by the PCI Bus. NRAD Wait States. Number of Read Address-to-Data wait states (0-31). NRDD Wait States. Number of Read Data-to-Data wait states (0-3). NXDA Wait States. Number of Read/Write Data-to-Address wait states (0-3). NWAD Wait States. Number of Write Address-to-Data wait states (0-31). NWDD Wait States. Number of Write Data-to-Data wait states (0-3). Expansion ROM Space Local Bus Width. Writing a 00 indicates an 8-bit bus width. Writing a 01 indicates a 16-bit bus width. Writing a 10 indicates a 32-bit bus width. Note: Setting of 11 is reserved. Byte Ordering. Value of 1 indicates Big Endian. Value of 0 indicates Little Endian. Big Endian Byte Lane Mode. Writing a 1 specifies that in any Endian mode, use byte lanes [31:16] for a 16-bit Local Bus and byte lanes [31:24] for an 8-bit Local Bus. Writing a 0 specifies that in any Endian mode, use byte lanes [15:0] for a 16-bit Local Bus and byte lanes [7:0] for an 8-bit Local Bus. Read Strobe Delay. Number of clocks from beginning of cycle until RD strobe is asserted (0-3). Value must be NRAD for RD# to be asserted. Write Strobe Delay. Number of clocks from beginning of cycle until WR strobe is asserted (0-3). Value must be NWAD for WR# to be asserted. Write Cycle Hold. Number of clocks from WR# de-assertion until end of cycle (0-3).
Read
Yes Yes
Write
Yes Yes
Value after Reset
0 0
2
Yes
Yes
0
4:3
Yes
Yes
00
5
Yes
Yes
0
10:6 12:11 14:13 19:15 21:20
Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes
0h 00 00 0h 00
23:22
Yes
Yes
00
24
Yes
Yes
0
25
Yes
Yes
0
27:26 29:28 31:30
Yes Yes Yes
Yes Yes Yes
00 00 00
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
10-23
Section 10--Registers
Section 10 Registers
Chip Select Registers
10.5
CHIP SELECT REGISTERS
Value after Reset
0
Register 10-53. (CS0BASE; 3Ch) Chip Select 0 Base Address
Bit
0
Description
Chip Select 0 Enable. Value of 1 indicates enabled. Value of 0 indicates disabled. Local Base Address of Chip Select 0. Write zeroes in the least significant bits to define the range for Chip Select 0. Starting from bit 1 and scanning toward bit 27, the first "1" found defines size. The remaining most significant bits, excluding the first "1" found, define base address. Reserved.
Read
Yes
Write
Yes
27:1
Yes
Yes
0h
31:28
Yes
No
0h
Register 10-54. (CS1BASE; 40h) Chip Select 1 Base Address
Bit
0
Description
Chip Select 1 Enable. Value of 1 indicates enabled. Value of 0 indicates disabled. Local Base Address of Chip Select 1. Write zeroes in the least significant bits to define the range for Chip Select 1. Starting from bit 1 and scanning toward bit 27, the first "1" found defines size. The remaining most significant bits, excluding the first "1" found, define base address. Reserved.
Read
Yes
Write
Yes
Value after Reset
0
27:1
Yes
Yes
0h
31:28
Yes
No
0h
Register 10-55. (CS2BASE; 44h) Chip Select 2 Base Address
Bit
0
Description
Chip Select 2 Enable. Value of 1 indicates enabled. Value of 0 indicates disabled. Local Base Address of Chip Select 2. Write zeroes in the least significant bits to define the range for Chip Select 2. Starting from bit 1 and scanning toward bit 27, the first "1" found defines size. The remaining most significant bits, excluding the first "1" found, define the base address. Reserved.
Read
Yes
Write
Yes
Value after Reset
0
27:1
Yes
Yes
0h
31:28
Yes
No
0h
Register 10-56. (CS3BASE; 48h) Chip Select 3 Base Address
Bit
0
Description
Chip Select 3 Enable. Value of 1 indicates enabled. Value of 0 indicates disabled. Local Base Address of Chip Select 3. Write zeroes in the least significant bits to define the range for Chip Select 3. Starting from bit 1 and scanning toward bit 27, the first "1" found defines size. The remaining most significant bits, excluding the first "1" found, define base address. Reserved.
Read
Yes
Write
Yes
Value after Reset
0
27:1
Yes
Yes
0h
31:28
Yes
No
0h
10-24
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Runtime Registers
Section 10 Registers
10.6
RUNTIME REGISTERS
Value after Reset
0 0 0 0 0 0 0 0 0
Register 10-57. (INTCSR; 4Ch) Interrupt Control/Status
Bit
0 1 2 3 4 5 6 7 8
Description
Local Interrupt 1 Enable. Value of 1 indicates enabled. Value of 0 indicates disabled. Local Interrupt 1 Polarity. Value of 1 indicates active high. Value of 0 indicates Active low. Local Interrupt 1 Status. Value of 1 indicates interrupt active. Value of 0 indicates Interrupt not active. Local Interrupt 2 Enable. Value of 1 indicates enabled. Value of 0 indicates disabled. Local Interrupt 2 Polarity. Value of 1 indicates active high. Value of 0 indicates Active low. Local Interrupt 2 Status. Value of 1 indicates interrupt active. Value of 0 indicates Interrupt not active. PCI Interrupt Enable. Value of 1 enables PCI interrupt. Software Interrupt. Value of 1 generates interrupt. Local Interrupt 1 Select Enable. Value of 1 indicates enabled edge triggerable interrupt. Value of 0 indicates enabled level triggerable interrupt. Note: Operates only in High Polarity mode. Local Interrupt 2 Select Enable. Value of 2 indicates enabled edge triggerable interrupt. Value of 0 indicates enabled level triggerable interrupt. Note: Operates only in High Polarity mode. Local Edge Triggerable Interrupt Clear. Writing 1 to this bit clears Interrupt 1. Local Edge Triggerable Interrupt Clear. Writing 1 to this bit clears Interrupt 2. Reserved.
Read
Yes Yes Yes Yes Yes Yes Yes Yes Yes
Write
Yes Yes No Yes Yes No Yes Yes Yes
9 10 11 15:12
Yes Yes Yes Yes
Yes Yes Yes No
0 0 0 0h
Register 10-58. (PROT_AREA; 4Eh) Serial EEPROM Write-Protected Address Boundary
Bit Description
Serial EEPROM. Serial EEPROM starting at Lword boundary (48 Lwords = 192 bytes) for VPD accesses. Serial EEPROM addresses below this boundary are read-only. Note: Anything below the programmed address may contain the PCI 9030 Configuration data. 15:7 Reserved. Yes No 0h
Read
Write
Value after Reset
6:0
Yes
Yes
0110000
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
10-25
Section 10--Registers
Section 10 Registers
Runtime Registers
Register 10-59. (CNTRL; 50h) PCI Target Response, Serial EEPROM, and Initialization Control
Bit
5:0 Reserved. PCI Target Write FIFO Full Condition. Value of 1 guarantees that when the PCI Target Write FIFO is full with PCI Target Write data, there is always one location remaining empty for the PCI Target Read address to be accepted by the PCI 9030. Value of 0 Retries all PCI Target Read accesses when the PCI Target Write FIFO is full with PCI Target Write data. Local Arbiter LGNT Signal Select Enable. Value of 1 selects LGNT to remain active until LREQ is de-asserted, although the PCI 9030 has a PCI Target transaction pending. Value of 0 selects LGNT to be de-asserted as soon as the PCI 9030 detects a PCI Target transaction pending and waits for LREQ to be de-asserted (Preempt condition). READY# Timeout Enable. Value of 1 enables READY# timeout enable. READY# Timeout Select. Values: 1 = 64 clocks 0 = 32 clocks PCI Target Write Delay. Delay in LCLKs of ADS# from valid address. Values: 00 = 0 LCLKs 10 = 8 LCLKs 01 = 4 LCLKs 11 = 16 LCLKs PCI Configuration Base Address Register (PCIBAR) Enables. Values: 00 = PCIBAR0 (Memory) and PCIBAR1 (I/O) enabled. 01 = PCIBAR0 (Memory) only. 10 = PCIBAR1 (I/O) only. 11 = PCIBAR0 (Memory) and PCIBAR1 (I/O) enabled. Delayed Read Mode. When set to 1, the PCI 9030 operates in Delayed Transaction mode for PCI Target reads. The PCI 9030 issues a Retry to the PCI Host and prefetches Read data. PCI Read with Write Flush Mode. Writing a 1 submits a request to flush a pending Read cycle if a Write cycle is detected. Writing a 0 submits a request to not effect pending reads when a Write cycle occurs (PCI Specification v2.2-compatible). PCI Read No Flush Mode. Writing a 1 submits a request to not flush the Read FIFO if the PCI Read cycle completes (Read Ahead mode). Writing a 0 submits a request to flush the Read FIFO if a PCI Read cycle completes. PCI Read No Write Mode. Writing a 1 forces a Retry on writes if a read is pending. Writing a 0 allows writes to occur while a read is pending. PCI Target Write Mode. Writing a 1 indicates the PCI 9030 should disconnect when the PCI Target Write FIFO is full. Writing a 0 indicates the PCI 9030 should de-assert TRDY# when the PCI Target Write FIFO is full. PCI Target Retry Delay Clocks. Contains the value (multiplied by 8) of the number of PCI Bus clocks after receiving a PCI-to-Local Read or Write access and not successfully completing a transfer. Only valid for read cycles if bit 14 is low. Only valid for write cycles if bit 17 is low. PCI Target LOCK# Enable. Writing a 1 enables the PCI Target locked sequences. Writing a 0 disables PCI Target locked sequences. Serial EEPROM Clock for Local or PCI Bus Reads or Writes to Serial EEPROM. Toggling this bit generates a serial EEPROM clock. (Refer to manufacturer's data sheet for the particular serial EEPROM being used.) Serial EEPROM Chip Select. For Local or PCI Bus reads or writes to the serial EEPROM, setting this bit to 1 provides serial EEPROM chip select. Write Bit to Serial EEPROM. For writes, this output bit is the input to serial EEPROM. Clocked into the serial EEPROM by serial EEPROM clock.
Description
Read
Yes
Write
No
Value after Reset
0h
6
Yes
Yes
0
7
Yes
Yes
0
8 9
Yes Yes
Yes Yes
0 0
11:10
Yes
Yes
00
13:12
Yes
Yes
00
14
Yes
Yes
0
15
Yes
Yes
0
16
Yes
Yes
0
17
Yes
Yes
0
18
Yes
Yes
0
22:19
Yes
Yes
Fh
23
Yes
Yes
0
24
Yes
Yes
0
25 26
Yes Yes
Yes Yes
0 0
10-26
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Runtime Registers
Section 10 Registers
Register 10-59. (CNTRL; 50h) PCI Target Response, Serial EEPROM, and Initialization Control (Continued)
Bit
27 28 29
Description
Read Serial EEPROM Data Bit. For reads, this input bit is the output of serial EEPROM. Clocked out of the serial EEPROM by serial EEPROM clock. Serial EEPROM Valid. Value of 1 indicates a blank or programmed serial EEPROM is present. Reload Configuration Registers. When set to 0, writing a value of 1 causes the PCI 9030 to reload Local Configuration registers from serial EEPROM. PCI Adapter Software Reset. Value of 1 resets the PCI 9030 and issues a reset to the Local Bus. PCI and Local Configuration register contents do not reset. Disconnect with Flush Read FIFO. Value of 1 causes a disconnect with flushing of the Read FIFO in Delayed Read mode (bit 14). Value of 0 causes a disconnect without flushing the Read FIFO (as a Retry).
Read
Yes Yes Yes
Write
No No Yes
Value after Reset
-- 0 0
30
Yes
Yes
0
31
Yes
Yes
0
Register 10-60. (GPIOC; 54h) General Purpose I/O Control
Bit
0 1
Description
GPIO0 or WAITo# Pin Select. Selects the function of GPIO0/WAITo# pin. Value of 1 indicates pin is WAITo#. Value of 0 indicates pin is GPIO0. GPIO0 Direction. Value of 0 indicates Input. Value of 1 indicates output. Always an output if WAITo# function is selected. GPIO0 Data. If programmed as output, writing a value of 1 causes corresponding pin to go high. If programmed as input, reading provides state of corresponding pin. GPIO1 or LLOCKo# Pin Select. Selects the function of GPIO1/LLOCKo# pin. Value of 1 indicates pin is LLOCKo#. Value of 0 indicates pin is GPIO1. GPIO1 Direction. Value of 0 indicates Input. Value of 1 indicates output. Always an output if LLOCK function is selected. GPIO1 Data. If programmed as output, writing a value of 1 causes corresponding pin to go high. If programmed as input, reading provides state of corresponding pin. GPIO2 or CS2# Pin Select. Selects the function of GPIO2/CS2# pin. Value of 1 indicates pin is CS2#. Value of 0 indicates pin is GPIO2. GPIO2 Direction. Value of 0 indicates Input. Value of 1 indicates output. Always an output if CS2 function is selected. GPIO2 Data. If programmed as output, writing a value of 1 causes corresponding pin to go high. If programmed as input, reading provides state of corresponding pin. GPIO3 or CS3# Pin Select. Selects the function of GPIO3/CS3# pin. Value of 1 indicates pin is CS3#. Value of 0 indicates pin is GPIO3. GPIO3 Direction. Value of 0 indicates Input. Value of 1 indicates output. Always an output if CS3 function is selected. GPIO3 Data. If programmed as output, writing a value of 1 causes corresponding pin to go high. If programmed as input, reading provides state of corresponding pin. GPIO4 or LA27 Pin Select. Selects the function of GPIO4/LA27 pin. Value of 1 indicates LA27. Value of 0 indicates GPIO4. GPIO4 Direction. Value of 0 indicates input. Value of 1 indicates output. Always an output if LA27 is selected.
Read
Yes Yes
Write
Yes Yes
Value after Reset
0 0
2
Yes
Yes
0
3 4
Yes Yes
Yes Yes
0 0
5
Yes
Yes
0
6 7
Yes Yes
Yes Yes
0 0
8
Yes
Yes
0
9 10
Yes Yes
Yes Yes
0 0
11
Yes
Yes
0
12 13
Yes Yes
Yes Yes
1 0
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
10-27
Section 10--Registers
Section 10 Registers
Runtime Registers
Register 10-60. (GPIOC; 54h) General Purpose I/O Control (Continued)
Bit
14
Description
GPIO4 Data. If programmed as output, writing a value of 1 causes corresponding pin to go high. If programmed as input, reading provides state of corresponding pin. GPIO5 or LA26 Pin Select. Selects the function of GPIO5/LA26 pin. Value of 1 indicates LA26. Value of 0 indicates GPIO5. GPIO5 Direction. Value of 0 indicates input. Value of 1 indicates output. Always an output if LA26 is selected. GPIO5 Data. If programmed as output, writing a value of 1 causes corresponding pin to go high. If programmed as input, reading provides state of corresponding pin. GPIO6 or LA25 Pin Select. Selects the function of GPIO6/LA25 pin. Value of 1 indicates LA25. Value of 0 indicates GPIO6. GPIO6 Direction. Value of 0 indicates input. Value of 1 indicates output. Always an output if LA25 is selected. GPIO6 Data. If programmed as output, writing a value of 1 causes corresponding pin to go high. If programmed as input, reading provides state of corresponding pin. GPIO7 or LA24 Pin Select. Selects the function of GPIO7/LA24 pin. Value of 1 indicates LA24. Value of 0 indicates GPIO7. GPIO7 Direction. Value of 0 indicates input. Value of 1 indicates output. Always an output if LA24 is selected. GPIO7 Data. If programmed as output, writing a value of 1 causes corresponding pin to go high. If programmed as input, reading provides state of corresponding pin. Reserved. GPIO8 Direction. Value of 0 indicates input. Value of 1 indicates output. GPIO8 Data. If programmed as output, writing a value of 1 causes corresponding pin to go high. If programmed as input, reading provides state of corresponding pin. Reserved.
Read
Yes
Write
Yes
Value after Reset
0
15 16
Yes Yes
Yes Yes
1 0
17
Yes
Yes
0
18 19
Yes Yes
Yes Yes
1 0
20
Yes
Yes
0
21 22
Yes Yes
Yes Yes
1 0
23 24 25 26 31:27
Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes
0 0 0 0 0h
Note: GPIO pins configured as outputs are driven only when the PCI 9030 owns the Local Bus. When another local master owns the bus (LGNT asserted), GPIO pins configured as outputs are floated. Refer to the PCI 9030 Design Notes for additional information.
10-28
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Runtime Registers
Section 10 Registers
Register 10-62. (PMDATASCALE; 74h) Hidden 2 Power Management Data Scale
Bit
1:0 3:2 5:4 7:6 31:8
Description
Data_Scale 0. Provides the D0 Power Consumed scaling factor read in PMDATA[7:0]. Value read in PMCSR[14:13] when Data_Select = 0. Data_Scale 3. Provides the D3 Power Consumed scaling factor read in PMDATA[7:0]. Value read in PMCSR[14:13] when Data_Select = 3. Data_Scale 4. Provides the D0 Power Dissipated scaling factor read in PMDATA[7:0]. Value read in PMCSR[14:13] when Data_Select = 4. Data_Scale 7. Provides the D3 Power Dissipated scaling factor read in PMDATA[7:0]. Value read in PMCSR[14:13] when Data_Select = 7. Reserved.
Read
Refer to Note Refer to Note Refer to Note Refer to Note Refer to Note
Write
Serial EEPROM Serial EEPROM Serial EEPROM Serial EEPROM Serial EEPROM
Value after Reset
00 00 00 00 0h
Note: This register can be read only two bits at a time, through PMCSR[14:13]. The two bits of PMDATASCALE returned in PMCSR[14:13] are selected by PMCSR[12:9].
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
10-29
Section 10--Registers
11
11.1
PIN DESCRIPTION
PIN SUMMARY
The following table lists abbreviations used in this section to represent various pin types.
Table 11-1. Pin Type Abbreviations
Abbreviation DTS I I/O O OC STS TP TS Pin Type Driven tri-state pin, driven high for one-half CLK before float Input pin only Input and output pin Output pin only Open collector pin Sustained tri-state pin, driven high for one CLK before float Totem pole pin Tri-state pin
Tables in this section describe each PCI 9030 pin. Table 11-2 through Table 11-7 provide pin information common to all Local Bus modes of operation: * Power and Ground * Serial EEPROM Interface * Test and Debug * PCI System Bus Interface * PCI Mode Independent Interface * Local Bus Mode Independent Interface Pins in Table 11-8 and Table 11-9 correspond to the PCI 9030 Local Bus modes--Multiplexed and Non-Multiplexed: * Multiplexed Bus Mode Interface Pin Description (32-bit address/32-bit data) * Non-Multiplexed Bus Mode Interface Pin Description (32-bit address/32-bit data) For a visual of the chip pinout, refer to Section 13, "Physical Specifications." No internal pull-up or pull-down resistors are present in the PCI 9030. For the EEDO pin only, an external pull-up resistor is required. The pull-up resistor must be pulled to Early Power Vcc in CompactPCI Hot Swap platforms and normal Vcc in regular PCI platforms. A missing pull-up resistor for the EEDO signal may intermittently bring the PCI 9030 to a quiescent state. Recommended resistor values are 1k to 4.7k. TRST# should be pulled low during PCI RST# assertion. If JTAG is not used, it is recommended that TRST# always be pulled low, using a 5.6k ohm resistor to ground, to put JTAG functionality into the reset state and enable normal chip logic operation.
As a Local Bus Master, the PCI 9030 drives all its outputs to the inactive state after the transaction is complete. If an External Master is present, the PCI 9030 tri-states all outputs when LGNT is asserted by the PCI 9030.
Note: A "#" in the pin name indicates active low.
Note for PCI pins: DO NOT pull up or down on any pins unless the PCI 9030 is being used in an embedded design. Refer to PCI Local Bus Specification, v2.2.
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
11-1
Section 11--Pin Description
Section 11 Pin Description
Pinout Common to All Bus Modes
11.2
PINOUT COMMON TO ALL BUS MODES
Table 11-2. Power and Ground Pins (176-Pin PQFP)
Symbol Signal Name Total Pins 11 Pin Type I PQFP Pin Number 1, 14, 32, 45, 56, 70, 85, 100, 117, 133, 162 53 13, 31, 44, 57, 66, 78, 88, 101, 113, 122, 132, 146, 163, 176 Function 3.3 V power supply pins for core and I/O buffers. Liberal .01 to .1 F decoupling capacitors should be placed near the PCI 9030. System voltage select, 3.3 or 5V, from the PCI Bus.
VDD
Power (+3.3V)
VI/O
Voltage Input/Output
1
I
VSS
Ground
14
I
Ground pins.
Total
26
Note: The die contains 224 pads. Power and Grounds are double bounded in the PQFP packages to meet proper drive strength of the buffers.
Table 11-3. Power and Ground Pins (180-Pin BGA)
Signal Name Spare Power (+3.3V) Total Die Pads -- 34 Total Pins 4 11 Pin Type -- I BGA Pin Number A1, A14, P1, P14 B2, B6, B13, E1, F11, J5, K13, M8, N2, N5, P12 L5 A2, A10, B14, C6, E13, F5, G13, J3, J10, K6, L7, N1, N10, P13
Symbol NC VDD
Function Applicable only to 180-Pin BGA. Unused. 3.3 V power supply pins for core and I/O buffers. Liberal .01 to .1 F decoupling capacitors should be placed near the PCI 9030. System voltage select, 3.3 or 5V, from the PCI Bus.
VI/O VSS
Voltage Input/Output Ground
1 39
1 14
I I
Ground pins.
Total
74
30
11-2
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Pinout Common to All Bus Modes
Table 11-4. Serial EEPROM Interface Pins
Symbol EECS Signal Name Serial EEPROM Chip Select Serial EEPROM Data In Serial EEPROM Data Out Serial Data Clock Total Pins 1 Pin Type O TP 6 mA O TP 6 mA I O TP 6 mA PQFP Pin Number 158 BGA Pin Number C7 Function Serial EEPROM chip select.
EEDI
1
161
D6
Write data to serial EEPROM.
EEDO
1
159
E7
Read data from serial EEPROM.
EESK Total
1 4
160
A7
Serial EEPROM clock pin.
Note: The serial EEPROM interface operates at core voltage (+3.3V). The PCI 9030 requires serial EEPROM use that can operate up to 250 kHz.
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
11-3
Section 11--Pin Description
Section 11 Pin Description
Section 11 Pin Description
Pinout Common to All Bus Modes
Table 11-5. Test and Debug Pins
CompactPCI Hot Swap BIAS Precharge Voltage PQFP Pin Number BGA Pin Number
Symbol
Signal Name
Total Pins
Pin Type
Function
TCK
Test Clock Input
1
I
1V
165
A6
Clock source for the PCI 9030 test access port (TAP). The maximum clock rate into the TCK pin is LCLK rate or less than one-half of the LCLK rate. Used to input serial data into the TAP. When the TAP enables this pin, it is sampled on the rising edge of TCK and the data is input to the selected TAP Shift register. Note: No internal pull-up.
TDI
Test Data In
1
I
1V
168
A5
TDO
Test Data Output
1
O TS PCI
1V
167
C5
Used to transmit data from the PCI 9030 TAP. Data from the selected TAP Shift registers is shifted out on TDO. CompactPCI Hot Swap Systems: Should be pulled high externally. The pull-up resistor needs to be connected to early power. Non-Hot Swap and other Systems: Should be pulled low externally. In combination with EEDO: Used as a IDDQ test enable pin. When pulled high, all outputs except LEDon# are placed in tri-state, and PCI Hot Swap precharge resistors are active. When pulled low, all outputs remain in normal operation and PCI Hot Swap precharge resistors are not active. Sampled by TAP on the rising edge of TCK. The TAP state machine uses the TMS pin to determine the mode in which the TAP operates. Note: Not used to select JTAG operation. Reset used by JTAG testers. TRST# should be pulled low during PCI RST# assertion. If JTAG is not used, it is recommended that TRST# always be pulled low, using a 5.6k ohm resistor to ground, to put JTAG functionality into the reset state and enable normal chip logic operation.
BD_SEL#/ TEST
Board Select/ Test Pin
1
I
No Connect
112
G11
TMS
Test Mode Select
1
I
1V
166
B5
TRST#
Test Reset
1
I
1V
164
E6
Total
6
11-4
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Pinout Common to All Bus Modes
Table 11-6. PCI System Bus Interface Pins
CompactPCI Hot Swap BIAS Precharge Voltage
Symbol
Signal Name
Total Pins
Pin Type
PQFP Pin Number
BGA Pin Number
Function
AD[31:0]
Address and Data
32
I/O TS PCI
1V
173-175, 2-6, 9-12, 15-18, 30, 33-39, 41-43, 46-50
A3, D4, B3, C3, C2, B1, C1, D3, E4, D1, E3, E2, F3, F2, F4, F1, J2, J1, K2, K3, K1, K4, L2, L3, M1, L4, M2, M3, N3, P2, P3, M4
All multiplexed on the same PCI pins. The Bus transaction consists of an Address phase, followed by one or more Data phases. The PCI 9030 supports both Read and Write bursts.
C/BE[3:0]#
Bus Command and Byte Enables
4
I
1V
7, 19, 29, 40
D2, G5, J4, L1
All multiplexed on the same PCI pins. During the Transaction Address phase, defines the bus command. During the Data phase, used as byte enables. Refer to the PCI Local Bus Specification v2.2 for further details. When actively driven, indicates the driving device decoded its address as Target of current access. Interrupt output set when an adapter using the PCI 9030 was recently inserted or ready to be removed from a PCI slot. Driven by the current Master to indicate the beginning and duration of an access. FRAME# is asserted to indicate the bus transaction is beginning. While FRAME# is asserted, Data transfers continue. When FRAME# is de-asserted, the transaction is in the final Data phase. Used as a chip select during Configuration Read and Write transactions. PCI Interrupt request. Indicates initiating agent (Bus Master) ability to complete the current transaction Data phase. Indicates an atomic operation that may require multiple transactions to complete.
DEVSEL#
Device Select
1
O STS PCI O OC PCI
1V
23
G1
ENUM#
Enumeration
1
VI/O
51
N4
FRAME#
Cycle Frame
1
I
1V
20
G2
IDSEL
Initialization Device Select Interrupt A
1
I O OC PCI I
1V
8
E5
INTA#
1
VI/O
170
B4
IRDY#
Initiator Ready
1
1V
21
G3
LOCK#
Lock
1
I
1V
25
H2
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
11-5
Section 11--Pin Description
Section 11 Pin Description
Section 11 Pin Description
Pinout Common to All Bus Modes
Table 11-6. PCI System Bus Interface Pins (Continued)
CompactPCI Hot Swap BIAS Precharge Voltage
Symbol
Signal Name
Total Pins
Pin Type
PQFP Pin Number
BGA Pin Number
Function
PAR
Parity
1
I/O TS PCI
1V
28
H1
Even parity across AD[31:0] and C/ BE[3:0]#. All PCI agents require parity generation. PAR is stable and valid one clock after the Address phase. For Data phases, PAR is stable and valid one clock after either IRDY# is asserted on a Write transaction or TRDY# is asserted on a Read transaction. Once PAR is valid, it remains valid until one clock after current Data phase completes. Provides timing for all transactions on the PCI Bus and is an input to every PCI device. The PCI 9030 operates up to 33 MHz. Reports data parity errors during all PCI transactions, except during a special cycle. Wake-up event interrupt. Used to bring PCI-specific registers, sequencers, and signals to a default state. Reports address parity errors, data parity errors on the Special Cycle command, or any other system error where the result is catastrophic. Indicates the current Target is requesting that the Master stop the current transaction. Indicates the Target agent (selected device) ability to complete the current Data phase transaction.
PCLK
Clock
1
I
No Connection
172
A4
PERR#
Parity Error Power Management Event Reset
1
O STS PCI O OC PCI I
1V
26
H3
PME#
1
VI/O
169
D5
RST#
1
VI/O
171
C4
SERR#
System Error
1
O OC PCI O STS PCI O STS PCI
1V
27
H5
STOP#
Stop
1
1V
24
H4
TRDY#
Target Ready
1
1V
22
G4
Total
51
11-6
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Pinout Common to All Bus Modes
Table 11-7. Local Bus Mode Independent Interface Pins
Symbol BCLKo Signal Name BCLK Out CompactPCI Switch Chip Selects Total Pins 1 Pin Type O TP 12 mA I O TS 12 mA I/O TS 12 mA PQFP Pin Number 71 BGA Pin Number K8 Function Provides a buffered version PCI clock for optional use by the Local Bus. Not in phase with the PCI clock. CompactPCI board latch status input. General purpose chip selects. The base and range of each is programmable by Configuration registers. Can be programmed to a configurable general purpose I/O pin, GPIO0, or Local Bus WAIT out pin. WAITo# is asserted when wait states are caused by the internal wait state generator. Serves as an output to provide ready-out status. Can be programmed to a configurable general purpose I/O pin, GPIO1, or Local Bus LLOCK out pin, LLOCKo#. LLOCKo# indicates an atomic operation that may require multiple transactions to complete and can be used by the Local Bus to lock resources. Can be programmed to a configurable general purpose I/O pin, GPIO2, or as Chip Select 2 output pin, CS2#. Can be programmed to a configurable general purpose I/O pin, GPIO3, or as Chip Select 3 output pin, CS3#.
CPCISW
1
54
P4
CS[1:0]#
2
148, 147
B9, C9
GPIO0/ WAITo#
General Purpose I/O 0 or WAIT Out
1
154
D8
GPIO1/ LLOCKo#
General Purpose I/O 1 or LLOCK Out
1
I/O TS 12 mA
155
A8
GPIO2/ CS2#
General Purpose I/O 2 or Chip Select 2 Out General Purpose I/O 3 or Chip Select 3 Out General Purpose I/O 8 Local Bus Clock
1
I/O TS 12 mA I/O TS 12 mA I/O TS 12 mA I O OC 24 mA O TP 12 mA
156
D7
GPIO3/ CS3#
1
157
B7
GPIO8
1
94
L12
Configurable general purpose I/O pin. Local clock, up to 60 MHz, and may be asynchronous to PCI clock. Hot Swap board indicator LED. Asserted by PCI 9030 to grant control of the Local Bus to a Local Bus Master. When the PCI 9030 requires the Local Bus, it can optionally signal a preempt by de-asserting LGNT. When asserted, causes a PCI interrupt. Polarity is determined by INTCSR configuration register. When asserted, causes a PCI interrupt. Polarity is determined by INTCSR configuration register.
LCLK
1
145
E9
LEDon#
LED On
1
52
K5
LGNT
Local Bus Grant
1
150
A9
LINTi1 LINTi2
Local Interrupt Input 1 Local Interrupt Input 2
1 1
I I
152 153
B8 C8
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
11-7
Section 11--Pin Description
Section 11 Pin Description
Section 11 Pin Description
Pinout Common to All Bus Modes
Table 11-7. Local Bus Mode Independent Interface Pins (Continued)
Symbol Signal Name Total Pins Pin Type PQFP Pin Number BGA Pin Number Function As an input, the Local Initiator can issue LPMESET to the PCI 9030 in the case of a Power Management Wake-Up event. LPMESET must be asserted to the PCI 9030 no less than one Local Clock pulse. The PCI 9030 latches the LPMESET assertion, sets the PME# status bit (PMCSR[15]), and asserts PME# to the PCI Bus, if enabled. Could be used for Local Power Management Events. The PCI 9030 drives the interrupt to the external Master to request a Power State Change. Asserted by a Local Bus Master to request Local Bus use. Asserted when the PCI 9030 chip is reset. Can be used to drive Local processor RESET# input. Selects the PCI 9030 Bus Operation mode: Bus Mode Mode 1 Multiplexed 0 Non-Multiplexed
LPMESET
Local Power Management Event Set
1
I
103
J12
LPMINT#
Local Power Management Interrupt Local Bus Request Local Bus Reset Out
1
O TP 12 mA
126
D13
LREQ
1
I O TP 12 mA
151
E8
LRESETo#
1
149
D9
MODE
Bus Mode
1
I
76
K9
Total
19
11-8
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Multiplexed Local Bus Mode Pinout
11.3
MULTIPLEXED LOCAL BUS MODE PINOUT
Signal Name Address Strobe Total Pins 1 Pin Type O TS 12 mA O TS 12 mA O TS 12 mA PQFP Pin Number 138 BGA Pin Number C11
Table 11-8. Multiplexed Bus Mode Interface Pins
Symbol ADS# Function Indicates a valid address and start of a new Bus access. Asserted for the first clock of a Bus access. Asserted during the Address phase and de-asserted before the Data phase. Driven by the current Local Bus Master to indicate the last transfer in a Bus access. If the Bterm Mode bit is disabled through the PCI 9030 Configuration registers, the PCI 9030 also bursts up to four Lwords. If enabled, the PCI 9030 continues to burst until BTERM# input is asserted or the burst is complete. BTERM# is a Ready input that breaks up a Burst cycle and causes another Address cycle to occur. Used in conjunction with the PCI 9030 programmable wait state generator. Can be programmed to a configurable general purpose I/O pin, GPIO4, or as Address Bus output pin, LA27. Can be programmed to a configurable general purpose I/O pin, GPIO5, or as Address Bus output pin, LA26. Can be programmed to a configurable general purpose I/O pin, GPIO6, or as Address Bus output pin, LA25. Can be programmed to a configurable general purpose I/O pin, GPIO7, or as Address Bus output pin, LA24.
ALE
Address Latch Enable
1
75
M9
BLAST#
Burst Last
1
139
B11
BTERM#
Burst Terminate
1
I
144
B10
GPIO4/ LA27 GPIO5/ LA26 GPIO6/ LA25 GPIO7/ LA24
General Purpose I/O 4 or Address Bus General Purpose I/O 5 or Address Bus General Purpose I/O 6 or Address Bus General Purpose I/O 7 or Address Bus
1
I/O TS 12 mA I/O TS 12 mA I/O TS 12 mA I/O TS 12 mA
137
A12
1
136
A13
1
135
B12
1
134
C12 C13, D11, C14, D14, D12, E11, E14, E12, F14, F10, F12, F13, G14, G10, G12, H14, H11, H12, H13, H10, J14, J11 L6, P6, K7, N7, M7, P7, L8, N8, P8, L9, N9, P9, M10, P10, L10, N11, M11, P11, L11, N12, N13, M12, M13, N14, M14, L13, K10, K11, L14, K12, K14, J13
LA[23:2]
Address Bus
22
O TS 12 mA
131-127, 125-123, 121-118, 116-114, 111-105
Carries the upper 22 bits of the 28-bit physical Address Bus. During bursts, LA[23:2] increment to indicate successive Data cycles.
LAD[31:0]
Address/ Data Bus
32
I/O TS 12 mA
61-65, 6769, 72-74, 77, 79-84, 86-87, 8993, 95-99, 102, 104
During an Address phase, the bus carries the upper 26 bits of 28-bit physical Address Bus [27:2]. During a Data phase, the bus carries 32 bits of data. 8 bit = LAD[7:0] 16 bit = LAD[15:0] 32 bit = LAD[31:0] During an ADS# assertion, carries the Local Address Bus (LA[27:2]).
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
11-9
Section 11--Pin Description
Section 11 Pin Description
Section 11 Pin Description
Multiplexed Local Bus Mode Pinout
Table 11-8. Multiplexed Bus Mode Interface Pins (Continued)
Symbol Signal Name Total Pins Pin Type PQFP Pin Number BGA Pin Number Function Encoded, based on the bus-width configuration: 32-Bit Bus Four byte enables indicate which of the four bytes are active during a data cycle: LBE3# Byte Enable 3 = LAD[31:24] LBE2# Byte Enable 2 = LAD[23:16] LBE1# Byte Enable 1 = LAD[15:8] LBE0# Byte Enable 0 = LAD[7:0] 16-Bit Bus LBE3# Byte High Enable (BHE#) = LAD[15:8] LBE2# Unused LBE1# Address bit 1 (LA1) LBE0# Byte Low Enable (BLE#) = LAD[7:0] 8-Bit Bus LBE3# Unused LBE2# Unused LBE1# Address bit 1 (LA1) LBE0# Address bit 0 (LA0) Asserted low for reads and high for writes. General purpose read strobe. The timing is controlled by current Bus Region Descriptor register. Local ready input indicates Read data on the bus is valid or a Write Data transfer is complete. Used in conjunction with the PCI 9030 programmable wait state generator. General purpose write strobe. Timing is controlled by the current Bus Region Descriptor register.
LBE[3:0]#
Byte Enables
4
O TS 12 mA
55, 58-60
M5, P5, M6, N6
LW/R#
Write/Read
1
O TS 12 mA O TS 12 mA
142
A11
RD#
Read Strobe
1
141
D10
READY#
Local Ready Input
1
I
143
C10
WR# Total
Write Strobe
1 70
O TS 12 mA
140
E10
11-10
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Non-Multiplexed Local Bus Mode Pinout
11.4
NON-MULTIPLEXED LOCAL BUS MODE PINOUT
Signal Name Address Strobe Total Pins 1 Pin Type O TS 12 mA O TS 12 mA O TS 12 mA PQFP Pin Number 138 BGA Pin Number C11
Table 11-9. Non-Multiplexed Bus Mode Interface Pins
Symbol ADS# Function Indicates a valid address and start of a new Bus access. Asserted for the first clock of a Bus access. Asserted during the Address phase and de-asserted before the Data phase. Driven by the current Local Bus Master to indicate the last transfer in a Bus access. If the Bterm Mode bit is disabled through the PCI 9030 Configuration registers, the PCI 9030 also bursts up to four Lwords. If enabled, the PCI 9030 continues to burst until BTERM# input is asserted or the burst is complete. BTERM# is a Ready input that breaks up a Burst cycle and causes another Address cycle to occur. Used in conjunction with the PCI 9030 programmable wait state generator. Can be programmed to a configurable general purpose I/O pin, GPIO4, or as Address Bus output pin, LA27. Can be programmed to a configurable general purpose I/O pin, GPIO5, or as Address Bus output pin, LA26. Can be programmed to a configurable general purpose I/O pin, GPIO6, or as Address Bus output pin, LA25. Can be programmed to a configurable general purpose I/O pin, GPIO7, or as Address Bus output pin, LA24.
ALE
Address Latch Enable
1
75
M9
BLAST#
Burst Last
1
139
B11
BTERM#
Burst Terminate
1
I
144
B10
GPIO4/ LA27 GPIO5/ LA26 GPIO6/ LA25 GPIO7/ LA24
General Purpose I/O 4 or Address Bus General Purpose I/O 5 or Address Bus General Purpose I/O 6 or Address Bus General Purpose I/O 7 or Address Bus
1
I/O TS 12 mA I/O TS 12 mA I/O TS 12 mA I/O TS 12 mA
137
A12
1
136
A13
1
135
B12
1
134
C12 C13, D11, C14, D14, D12, E11, E14, E12, F14, F10, F12, F13, G14, G10, G12, H14, H11, H12, H13, H10, J14, J11
LA[23:2]
Address Bus
22
O TS 12 mA
131-127, 125-123, 121-118, 116-114, 111-105
Carries the upper 22 bits of the 28-bit physical Address Bus. During bursts, LA[23:2] increment to indicate successive Data cycles.
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
11-11
Section 11--Pin Description
Section 11 Pin Description
Section 11 Pin Description
Non-Multiplexed Local Bus Mode Pinout
Table 11-9. Non-Multiplexed Bus Mode Interface Pins (Continued)
Symbol Signal Name Total Pins Pin Type PQFP Pin Number BGA Pin Number Function Encoded, based on the bus-width configuration: 32-Bit Bus Four byte enables indicate which of the four bytes are active during a data cycle: LBE3# Byte Enable 3 = LD[31:24] LBE2# Byte Enable 2 = LD[23:16] LBE1# Byte Enable 1 = LD[15:8] LBE0# Byte Enable 0 = LD[7:0] 16-Bit Bus LBE3# Byte High Enable (BHE#) = LD[15:8] LBE2# Unused LBE1# Address bit 1 (LA1) LBE0# Byte Low Enable (BLE#) = LD[7:0] 8-Bit Bus LBE3# Unused LBE2# Unused LBE1# Address bit 1 (LA1) LBE0# Address bit 0 (LA0) Carries 8-, 16-, or 32-bit data quantities, depending upon a Target bus-width configuration: 8 bit = LD[7:0] 16 bit = LD[15:0] 32 bit = LD[31:0]
LBE[3:0]#
Byte Enables
4
O TS 12 mA
55, 58-60
M5, P5, M6, N6
LD[31:0]
Data Bus
32
I/O TS 12 mA
61-65, 6769, 72-74, 77, 79-84, 86-87, 8993, 95-99, 102, 104
L6, P6, K7, N7, M7, P7, L8, N8, P8, L9, N9, P9, M10, P10, L10, N11, M11, P11, L11, N12, N13, M12, M13, N14, M14, L13, K10, K11, L14, K12, K14, J13 A11
LW/R#
Write/Read
1
O TS 12 mA O TS 12 mA
142
Asserted low for reads and high for writes. General purpose read strobe. The timing is controlled by current Bus Region Descriptor register. Local ready input indicates Read data on the bus is valid or a Write Data transfer is complete. Used in conjunction with the PCI 9030 programmable wait state generator. General purpose write strobe. Timing is controlled by the current Bus Region Descriptor register.
RD#
Read Strobe
1
141
D10
READY#
Local Ready Input
1
I
143
C10
WR# Total
Write Strobe
1 70
O TS 12 mA
140
E10
11-12
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Debug Interface
11.5
DEBUG INTERFACE
Table 11-11. JTAG Infrared Outputs
Instruction
Extest Sample/Preload Bypass
The PCI 9030 provides a JTAG Boundary Scan interface which can be utilized to debug a pin's connectivity to the board.
IR Output
0001 0101 1101
Comments
IEEE 1149.1 standard IEEE 1149.1 standard IEEE 1149.1 standard
11.5.1 IEEE 1149.1 Test Access Port (JTAG Debug Port)
The IEEE 1149.1 Test Access Port (TAP), commonly called the JTAG (Joint Test Action Group) debug port, is an architectural standard described in IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary Scan Architecture. The standard describes a method for accessing internal chip facilities using a four- or five-signal interface. The JTAG debug port, originally designed to support scan-based board testing, is enhanced to support the attachment of debug tools. The enhancements, which comply with the IEEE 1149.1 specifications for vendorspecific extensions, are compatible with standard JTAG hardware for boundary-scan system testing. * JTAG Signals--JTAG debug port implements the four required JTAG signals, TCLK, TMS, TDI, TDO, and the optional TRST# signal. * JTAG Clock Requirements--The TCLK signal frequency can range from DC to one-half of the internal chip clock frequency. * JTAG Reset Requirements--JTAG debug port logic is reset at the same time as a system reset. Upon receiving TRST#, the JTAG TAP controller returns to the Test-Logic Reset state.
11.5.3 JTAG Boundary Scan
Boundary Scan Description Language (BSDL), IEEE 1149.1b-1994, is a supplement to IEEE 1149.1-1990 and IEEE 1149.1a-1993 Standard Test Access Port and Boundary-Scan Architecture. BSDL, a subset of the IEEE 1076-1993 Standard VHSIC Hardware Description Language (VHDL), allows a rigorous description of testability features in components which comply with the standard. It is used by automated test pattern generation tools for package interconnect tests and electronic design automation (EDA) tools for synthesized test logic and verification. BSDL supports robust extensions that can be used for internal test generation and to write software for hardware debug and diagnostics. The primary components of BSDL include the logical port description, physical pin map, instruction set, and boundary register description. The logical port description assigns symbolic names to the pins of a chip. Each pin has a logical type of in, out, inout, buffer, or linkage that defines the logical direction of signal flow. The physical pin map correlates the logical ports of the chip to the physical pins of a specific package. A BSDL description can have several physical pin maps; each map is given a unique name. Instruction set statements describe the bit patterns that must be shifted into the Instruction Register to place the chip in the various test modes defined by the standard. Instruction set statements also support descriptions of instructions that are unique to the chip. The boundary register description lists each cell or shift stage of the Boundary Register. Each cell has a unique number; the cell numbered 0 is the closest to the Test Data Out (TDO) pin and the cell with the highest number is closest to the Test Data In (TDI) pin. Each cell contains additional information, including: cell type, logical port associated with the cell, logical function of the cell, safe value, control cell number, disable value, and result value.
11.5.2 JTAG Instructions
The JTAG debug port provides the standard extest, sample/preload, and bypass instructions. Invalid instructions behave as the bypass instruction. There are three private instructions. The following tables list the JTAG instructions and infrared (IR) outputs. Table 11-10. JTAG Instructions
Instruction
Extest Sample/Preload Bypass
Input Code
0000 0100 1111
Comments
IEEE 1149.1 standard IEEE 1149.1 standard IEEE 1149.1 standard
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
11-13
Section 11--Pin Description
Section 11 Pin Description
12
12.1
ELECTRICAL SPECIFICATIONS
GENERAL ELECTRICAL SPECIFICATIONS
Table 12-1. Absolute Maximum Ratings
Specification
Storage Temperature Ambient Temperature with Power Applied Supply Voltage to Ground Input Voltage (VIN) Output Voltage (VOUT) Maximum Package Power Dissipation 176-Pin PQFP 180-Pin BGA Note: Package Power Dissipation derived with assumption that 1.0m/s air flow is available. 1W 0.5W -55 to +125 C -40 to +85 C -0.5 to +4.6V VSS -0.5 to 11.0V VSS -0.5V to VDD +0.5
Maximum Rating Section 12--Electrical Specs Input Voltage (VIN) Min
VSS
Table 12-2. Operating Ranges
Ambient Temperature
-40 to +85 C
Supply Voltage (VDD)
3.0 to 3.6V
Max
11.0V
Table 12-3. Capacitance (Sample Tested Only)
Parameter
CIN COUT
Test Conditions
VIN = 0V VOUT = 0V
Pin Type
Input Output
Value Typical
4 6
Maximum
6 10
Units
pF pF
The following table lists the package thermal resistance (j-a).
Table 12-4. Package Thermal Resistance
Air Flow Package Type
176-Pin PQFP 180-Pin BGA
0m/s
65 (C/W) 48 (C/W)
1m/s
45 34
2m/s
35 26
3m/s
30 22
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
12-1
Section 12 Electrical Specifications
General Electrical Specifications
Table 12-5. Electrical Characteristics over Operating Range
Parameter
VOH1 VOL1 VIH VIL VOH3 VOL3 VIH3 VIL3 IIL
Description
Output High Voltage Output Low Voltage Input High Level Input Low Level PCI 3.3V Output High Voltage PCI 3.3V Output Low Voltage PCI 3.3V Input High Level PCI 3.3V Input Low Level Input Leakage Current DC Current Per Pin During Pre-Charge Tri-State Output Leakage Current Power Supply Current3 Quiescent Power Supply Current
Test Conditions
VDD = Min VIN = VIH or VIL -- -- VDD = Min VIN = VIH or VIL -- -- -- IOH = -12.0 mA IOL = 12 mA -- -- IOH = -500 A IOL = 1500 A -- --
Min
2.4 -- 2.0 -0.5 0.9 VDD -- 0.5 VDD -0.5 -10
Max
-- 0.4 11.0 0.8 -- 0.1 VDD VDD +0.5 0.3 VDD +10
Units
V V V V V V V V A
VSS VIN VDD, VDD = Max
ILPC2
VP = 0.8 to 1.2V
--
1.0
mA A
IOZ
VDD = Max VDD=3.6V, PCLK = 33 MHz, LCLK = 60 MHz 80 outputs switching simultaneously VCC = Max VIN = GND or VCC
-10
+10
ICC ICCL ICCH ICCZ Notes:
1 2
--
150
mA
--
50
A
Except in the case of EESK, EEDI, EECS, and LPMINT# pins.
ILPC is the DC current flowing from VDD to Ground during precharge, as both PMOS and NMOS devices remain on during precharge. It is not the leakage current flowing into or out of the pin under precharge. Maximum value based upon I/O simultaneously switching outputs.
3
12-2
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Local Inputs
Section 12 Electrical Specifications
12.2
LOCAL INPUTS
Local Clock
H O LD
T
Inputs
SETUP
Valid
Figure 12-1. PCI 9030 Local Input Setup and Hold Waveform
Table 12-6. AC Electrical Characteristics (Local Inputs) over Operating Range
Signals (Synchronous Inputs) CL = 50 pF, Vcc = 3.0V, Ta = 85 C
BTERM# LAD[31:0] (Data) LD[31:0] LPMESET LREQ READY#
Bus Mode
All Multiplexed Non-Multiplexed All All All
TSETUP (ns) (WORST CASE)
7.0 5.0 5.0 5.0 5.0 7.0
THOLD (ns) (WORST CASE)
1 1 1 1 1 1
Input Clocks
Local Clock Input Frequency PCI Clock Input Frequency Note: These values are provided as an example and are only representative of general performance characteristics of the PLX PCI devices.
Bus Mode
All All
Min
0 0
Max
60 MHz 33 MHz
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
12-3
Section 12--Electrical Specs
T
Section 12 Electrical Specifications
Local Outputs
12.3
LOCAL OUTPUTS
Local Clock
T VA L ID (MAX)
T V A L ID (MIN)
Outputs
Valid
Figure 12-2. PCI 9030 Local Output Delay Table 12-7. AC Electrical Characteristics (Local Outputs) over Operating Range
Signals (Synchronous Outputs) CL = 50 pF, Vcc = 3.0V, Ta = 85 C
ADS# BLAST# CS0# CS1# CS2# CS3# LA[27:2] LAD[31:0] (Data) LBE[3:0]# LD[31:0] LGNT LLOCKo# LPMINT# LW/R# RD# WAITo# WR# Notes: All TVALID (Min) values are greater than 5 ns.
Bus Mode
All All All All All All All Multiplexed All Non-Multiplexed All All All All All All All
Output TVALID (Max)
10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 11.0 10.0 10.0 10.0 10.0 10.0 10.0
Timing derating for loading is 35 PS/PF. These values are provided as an example and are only representative of general performance characteristics of PLX PCI devices.
12-4
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Local Outputs
Section 12 Electrical Specifications
1.5V Local Clock
10.7 ns/3.8 ns
1.5V
ALE
16.9 ns/11.5 ns 7.0 ns/10.0 ns
Address Bus
Figure 12-3. PCI 9030 ALE Output Delay (Min/Max) to the Local Clock at 60 MHz
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
12-5
Section 12--Electrical Specs
13
13.1
PHYSICAL SPECIFICATIONS
176-PIN PQFP
HD
For 176 PQFP, JC = 5 C/watt
132
D
89
133
88
Index
176 45
1
e Topside View
b
44
AMAX
A2
R1 R C L2 L1 L
3
Cross-Section View
Figure 13-1. 176-Pin PQFP Package Mechanical Dimensions--Topside and Cross-Section Views Table 13-1. 176-Pin PQFP Package Mechanical Dimensions (Legend for Figure 13-1)
Lead Type STD (QFP18-176 Pin STD) Symbol
E D A A1 A2 e b C L L1 L2 HE HD 2 3 R R1
Dimensions in Millimeters Min.
23.9 23.9 -- -- 2.6 -- 0.15 0.1 0 0.3 -- -- 25.6 25.6 -- -- -- --
Nom.
24 24 -- 0.1 2.7 0.5 0.2 0.15 -- 0.5 1 0.5 26 26 15 15 0.2 0.2
Max.
24.1 24.1 3 -- 2.8 -- 0.3 0.2 10 0.7 -- -- 26.4 26.4 -- -- -- --
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
13-1
Section 13--Physical Specs
2
A1
HE
E
Section 13 Physical Specifications
176-Pin PQFP
0.30 mm (0.012 in)
Metal Pad 1.00 mm (0.040 in) Solder Mask Keepout Area Fiducial 2.54 mm (0.100 in)
1.50 mm (0.060 in)
B = 27.18 mm (1.070 in)
Fiducial
P = 0.50 mm (0.020 in) A = 27.18 mm (1.070 in)
Note: Leave 0.002 inch solder mask clearance around pads.
Figure 13-2. 176-Pin PQFP PCB Layout Suggested Land Pattern
13-2
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
176-Pin PQFP
Section 13 Physical Specifications
Non-Multiplexed
Multiplexed
(outer column)
(inner column)
VDD GPIO7/LA24 GPIO6/LA25 GPIO5/LA26 GPIO4/LA27 ADS# BLAST# WR# RD# LW/R# READY# BTERM# LCLK VSS CS0# CS1# LRESETo# LGNT LREQ LINTi1 LINTi2 GPIO0/WAITo# GPIO1/LLOCKo# GPIO2/CS2# GPIO3/CS3# EECS EEDO EESK EEDI VDD VSS TRST# TCK TMS TDO TDI PME# INTA# RST# PCLK AD31 AD30 AD29 VSS
VDD GPIO7/LA24 GPIO6/LA25 GPIO5/LA26 GPIO4/LA27 ADS# BLAST# WR# RD# LW/R# READY# BTERM# LCLK VSS CS0# CS1# LRESETo# LGNT LREQ LINTi1 LINTi2 GPIO0/WAITo# GPIO1/LLOCKo# GPIO2/CS2# GPIO3/CS3# EECS EEDO EESK EEDI VDD VSS TRST# TCK TMS TDO TDI PME# INTA# RST# PCLK AD31 AD30 AD29 VSS
133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
VSS LA23 LA22 LA21 LA20 LA19 LPMINT# LA18 LA17 LA16 VSS LA15 LA14 LA13 LA12 VDD LA11 LA10 LA9 VSS BD_SEL#/TEST LA8 LA7 LA6 LA5 LA4 LA3 LA2 LD0 LPMESET LD1 VSS VDD LD2 LD3 LD4 LD5 LD6 GPIO8 LD7 LD8 LD9 LD10 LD11
VSS LA23 LA22 LA21 LA20 LA19 LPMINT# LA18 LA17 LA16 VSS LA15 LA14 LA13 LA12 VDD LA11 LA10 LA9 VSS BD_SEL#/TEST LA8 LA7 LA6 LA5 LA4 LA3 LA2 LAD0 LPMESET LAD1 VSS VDD LAD2 LAD3 LAD4 LAD5 LAD6 GPIO8 LAD7 LAD8 LAD9 LAD10 LAD11
PCI 9030
VSS LD12 LD13 VDD LD14 LD15 LD16 LD17 LD18 LD19 VSS LD20 MODE ALE LD21 LD22 LD23 BCLKo VDD LD24 LD25 LD26 VSS LD27 LD28 LD29 LD30 LD31 LBE0# LBE1# LBE2# VSS VDD LBE3# CPCISW VI/O LEDon# ENUM# AD0 AD1 AD2 AD3 AD4 VDD
VSS LAD12 LAD13 VDD LAD14 LAD15 LAD16 LAD17 LAD18 LAD19 VSS LAD20 MODE ALE LAD21 LAD22 LAD23 BCLKo VDD LAD24 LAD25 LAD26 VSS LAD27 LAD28 LAD29 LAD30 LAD31 LBE0# LBE1# LBE2# VSS VDD LBE3# CPCISW VI/O LEDon# ENUM# AD0 AD1 AD2 AD3 AD4 VDD
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
VDD AD28 AD27 AD26 AD25 AD24 C/BE3# IDSEL AD23 AD22 AD21 AD20 VSS VDD AD19 AD18 AD17 AD16 C/BE2# FRAME# IRDY# TRDY# DEVSEL# STOP# LOCK# PERR# SERR# PAR C/BE1# AD15 VSS VDD AD14 AD13 AD12 AD11 AD10 AD9 AD8 C/BE0# AD7 AD6 AD5 VSS
VDD AD28 AD27 AD26 AD25 AD24 C/BE3# IDSEL AD23 AD22 AD21 AD20 VSS VDD AD19 AD18 AD17 AD16 C/BE2# FRAME# IRDY# TRDY# DEVSEL# STOP# LOCK# PERR# SERR# PAR C/BE1# AD15 VSS VDD AD14 AD13 AD12 AD11 AD10 AD9 AD8 C/BE0# AD7 AD6 AD5 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Figure 13-3. 176-Pin PQFP Signal and Pinout
13-3
Section 13--Physical Specs
Section 13 Physical Specifications
180-Pin BGA
13.2
180-PIN BGA
D
Topside View
e
SD
ZD
P N M L K J H G F E D C B A
SE
ob
oxM
Underside View
e
1 2 3 4 5 6 7 8 9 10 1112 13 14 Cross-Section View
S
ZE
yS
Figure 13-4. 180-Pin BGA Package Mechanical Dimensions--Topside, Underside, and Cross-Section Views
13-4
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
A1
D
A
180-Pin BGA
Section 13 Physical Specifications
Table 13-2. 180-Pin BGA Package Mechanical Dimensions (Legend for Figure 13-4)
Dimensions (in Millimeters) Symbol
D E A A1 e ob x y SD SE ZD ZE
Min.
11.85 11.85 -- 0.30 -- 0.40 -- -- -- -- -- --
Nom.
12.0 12.0 -- 0.35 0.80 0.45 -- -- 0.40 0.40 0.80 0.80
Max.
12.3 12.3 1.20 0.45 -- 0.55 0.08 0.10 -- -- -- --
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
13-5
Section 13--Physical Specs
Section 13 Physical Specifications
180-Pin BGA
Topside View
Pin A1 Designator (Silkscreen) Pin A1
Copper Crop Lines (Allows for visual inspection of whether the BGA is centered on the pads)
0.8 mm (0.031 in)
13 mm (0.512 in)
0.25 mm (0.010 in)
1.27 mm (0.050 in)
13 mm (0.512 in)
Detail of Each Pad and Breakout
0.508 mm (0.020 in) Via Pad Diameter
0.15 mm (0.006 in) FHS
Solder Mask
0.35 mm (0.0138 in) Diameter Land
Creating a solder mask clearance using the Via pad is not recommended.
Solder Mask Keepout 0.05-0.07 mm (0.002-0.003 in)
Figure 13-5. 180-Pin BGA PCB Layout Suggested Land Pattern
13-6
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
180-Pin BGA
Section 13 Physical Specifications
G=GND
P N M L K J H G F E D C B A P1 N1 M1 L1 K1 J1 H1 G1 F1 E1 D1 C1 B1 A1 P2 N2 M2 L2 K2 J2 H2 G2 F2 E2 D2 C2 B2 A2 P3 N3 M3 L3 K3 J3 H3 G3 F3 E3 D3 C3 B3 A3 P4 N4 M4 L4 K4 J4 H4 G4 F4 E4 D4 C4 B4 A4 P5 N5 M5 L5 K5 J5 H5 G5 F5 E5 D5 C5 B5 A5 E6 D6 C6 B6 A6 E7 D7 C7 B7 A7 E8 D8 C8 B8 A8 E9 D9 C9 B9 A9 P6 N6 M6 L6 K6 P7 N7 M7 L7 K7 P8 N8 M8 L8 K8 P9 N9 M9 L9 K9 P10 N10 M10 L10 K10 J10 H10 G10 F10 E10 D10 C10 B10 A10 P11 N11 M11 L11 K11 J11 H11 G11 F11 E11 D11 C11 B11 A11 P12 N12 M12 L12 K12 J12 H12 G12 F12 E12 D12 C12 B12 A12 P13 N13 M13 L13 K13 J13 H13 G13 F13 E13 D13 C13 B13 A13 P14 N14 M14 L14 K14 J14 H14 G14 F14 E14 D14 C14 B14 A14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
4 Spare, Not Connected Pins
Figure 13-6. 180-Pin BGA Package Layout--Underside View
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
13-7
Section 13--Physical Specs
Section 13 Physical Specifications
180-Pin BGA
Note:
The following abbreviations apply in Table 13-3: NC = Not Connected M = Multiplexed Mode NM = Non-Multiplexed Mode
Table 13-3. 180-Pin BGA PCI 9030 Pinout
Pin #
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 B2 B3 B4
Symbol
NC VSS AD31 PCLK TDI TCK EESK GPIO1/LLOCKo# LGNT VSS LW/R# GPIO4/LA27 GPIO5/LA26 NC AD26 VDD AD29 INTA#
Bus Mode
All All All All All All All All All All All All All All All All All All
Pin #
C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 D1 D2 D3 D4 D5 D6
Symbol
AD28 RST# TDO VSS EECS LINTi2 CS0# READY# ADS# GPIO7/LA24 LA23 LA21 AD22 C/BE3# AD24 AD30 PME# EEDI
Bus Mode
All All All All All All All All All All All All All All All All All All
Pin #
E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 F1 F2 F3 F4 F5 F10 F11 F12
Symbol
IDSEL TRST# EEDO LREQ LCLK WR# LA18 LA16 VSS LA17 AD16 AD18 AD19 AD17 VSS LA14 VDD LA13
Bus Mode
All All All All All All All All All All All All All All All All All All
Pin #
H1 H2 H3 H4 H5 H10 H11 H12 H13 H14 J1 J2 J3 J4 J5 J10 J11 J12
Symbol
PAR LOCK# PERR# STOP# SERR# LA4 LA7 LA6 LA5 LA8 AD14 AD15 VSS C/BE1# VDD VSS LA2 LPMESET LAD0 LD0 LA3 AD11 AD13 AD12 AD10 LEDon# VSS LAD29 LD29 BCLKo MODE LAD5 LD5
Bus Mode
All All All All All All All All All All All All All All All All All All M NM All All All All All All All M NM All All M NM
B5
TMS
All
D7
GPIO2/CS2#
All
F13
LA12
All
J13
B6 B7 B8 B9 B10 B11 B12
VDD GPIO3/CS3# LINTi1 CS1# BTERM# BLAST# GPIO6/LA25
All All All All All All All
D8 D9 D10 D11 D12 D13 D14
GPIO0/WAITo# LRESETo# RD# LA22 LA19 LPMINT# LA20
All All All All All All All
F14 G1 G2 G3 G4 G5 G10
LA15 DEVSEL# FRAME# IRDY# TRDY# C/BE2# LA10
All All All All All All All
J14 K1 K2 K3 K4 K5 K6
B13
VDD
All
E1
VDD
All
G11
BD_SEL#/TEST
All
K7
B14 C1
VSS AD25
All All
E2 E3
AD20 AD21
All All
G12 G13
LA9 VSS
All All
K8 K9
C2
AD27
All
E4
AD23
All
G14
LA11
All
K10
13-8
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
180-Pin BGA
Section 13 Physical Specifications
Table 13-3. 180-Pin BGA PCI 9030 Pinout (Continued)
Pin # Symbol
LAD4 LD4 LAD2 LD2
Bus Mode
M NM M NM
Pin #
Symbol
GPIO8
Bus Mode
Pin #
Symbol
LAD9 LD9 LAD7 LD7
Bus Mode
M NM M NM
Pin #
Symbol
LAD8 LD8
Bus Mode
M NM
K11
L12
All
M13
N14
K12
L13
LAD6 LD6 LAD3 LD3
M NM M NM
M14
P1
NC
All
K13
VDD
All
L14
N1
VSS
All
P2
AD2
All
K14
LAD1 LD1 C/BE0# AD9
M NM All All
M1
AD7 AD5 AD4
All
N2
VDD
All
P3
AD1
All
L1 L2
M2 M3
All All
N3 N4
AD3 ENUM#
All All
P4 P5
CPCISW LBE2# LAD30 LD30 LAD26 LD26 LAD23 LD23 LAD20 LD20 LAD18 LD18 LAD14 LD14
All All M NM M NM M NM M NM M NM M NM
L3
AD8
All
M4
AD0
All
N5
VDD
All
P6
L4
AD6
All
M5
LBE3#
All
N6
LBE0#
All
P7
L5
VI/O
All
M6
LBE1#
All
N7
LAD28 LD28 LAD24 LD24 LAD21 LD21
M NM M NM M NM
P8
L6
LAD31 LD31
M NM
M7
LAD27 LD27
M NM
N8
P9
L7
VSS
All
M8
VDD
All
N9
P10
L8
LAD25 LD25 LAD22 LD22 LAD17 LD17 LAD13 LD13
M NM M NM M NM M NM
M9
ALE
All
N10
VSS
All
P11
L9
M10
LAD19 LD19 LAD15 LD15 LAD10 LD10
M NM M NM M NM
N11
LAD16 LD16 LAD12 LD12 LAD11 LD11
M NM M NM M NM
P12
VDD
All
L10
M11
N12
P13
VSS
All
L11
M12
N13
P14
NC
All
Table 13-4. 180-Pin BGA Six-Layer Board Routing Example (Four Routing Layers)--Sample Parameters
Via size Other Parameters Routing Layer Parameters
Component Side First Inside Layer Second Inside Layer Solder Side
Via size mm
Land Pad Side Solder Mask Opening Trace Width Drill Size for the Via Hole Side for the Via
0.350 0.549 0.127 0.254 0.152
mm
0.509 0.634 0.634 0.634
inches
0.0200 0.0250 0.0250 0.0250
inches
0.0138 0.0216 0.0050 0.0100 0.0060
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
13-9
Section 13--Physical Specs
Section 13 Physical Specifications
180-Pin BGA
Via Solder Trace Solder Pad
Figure 13-9. 180-Pin BGA Six-Layer Board Routing Example (Four Routing Layers)-- Second Inside Layer
Figure 13-7. 180-Pin BGA Six-Layer Board Routing Example (Four Routing Layers)--Component Side
Figure 13-10. 180-Pin BGA Six-Layer Board Routing Example (Four Routing Layers)--Solder Side
Figure 13-8. 180-Pin BGA Six-Layer Board Routing Example (Four Routing Layers)--First Inside Layer
13-10
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
A
A.1
GENERAL INFORMATION ORDERING INSTRUCTIONS
A.2 UNITED STATES AND INTERNATIONAL REPRESENTATIVES, AND DISTRIBUTORS
The PCI 9030 is a 32-bit, 33-MHz PCI Bus Target Interface Device featuring advanced SMARTarget technology, which includes a programmable Target interface. The PCI 9030 offers 3.3V, 5V tolerant PCI and Local signaling, supports Universal PCI Adapter designs, 3.3V core, low-power CMOS offered in two package options--176-pin PQFP and 180-pin (ball) BGA. The device is designed to operate at Industrial Temperature range.
Table A-1. Available Packages
Package
176-pin PQFP 180-pin BGA
A list of PLX Technology, Inc., representatives and distributors can be found at http://www.plxtech.com.
A.3
TECHNICAL SUPPORT
PLX Technology, Inc., technical support information is listed at http://www.plxtech.com; or call 408 774-9060 or 800 759-3735.
Ordering Part Number
PCI 9030-AA60PI PCI 9030-AA60BI
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
A-1
Appendix A--General Info
Index
A
abort master 10-5 PCI Target 2-1, 10-5 absolute maximum ratings 12-1 AC electrical characteristics 12-3, 12-4 accesses address decode enable 10-10 burst 1-4, 2-3, 2-6, 4-1, 4-5 burst memory-mapped 1-4 Bus master 10-4 byte 2-1, 10-4 configuration 1-5, 3-1, 3-7, 7-2, 10-12 debug interface 11-13 decode 4-4, 10-15 disabled 7-2, 7-3, 10-12 during software reset 3-1 Hot Swap 8-1, 8-3, 8-4 I/O 1-4, 2-1, 3-7, 4-1, 4-5, 10-7, 10-12 I/O space 10-4 internal register 3-6-3-7 Local 2-5 Local Bus 4-5 Big/Little Endian 2-7 read 2-6 write 2-6 locked atomic operations 4-1 Lword 2-1, 10-4 Max_Lat 10-11 memory 2-5 memory base address 10-6 memory space 10-4 other than VPD expansion ROM 1-4 partial Lword 2-6 PCI 10-16, 10-26 PCI Master 4-1 PCI Target 2-1, 3-1, 3-2, 4-1, 4-3, 4-4, 4-5, 10-17, 10-18 PCI, decode 10-15 PCIBAR0 10-6 PCIBAR1 10-7 PCIBAR2 10-7 PCIBAR3 10-8 PCIBAR4 10-8 PCIBAR5 10-9 PCI-to-Local 1-4, 10-3 read 2-6, 4-5 remote 1-3 RST# timing 1-5 single I/O-mapped 1-4 slave 1-1, 1-4 VPD 9-1, 10-14, 10-25 wake-up request example 7-3 word 2-1, 10-4 write 2-6 accesses, burst 2-3 AD[31:0] 11-5 adapter card CompactPCI, high-performance 1-3 PMC, typical 1-4 address address-to-data 2-5 Base Address 1 3-7 base registers 4-1 bits for decoding 4-4 boundary 2-6 burst start 2-6 CS0BASE 10-24 CS1BASE 10-24 CS2BASE 10-24 CS3BASE 10-24 cycle 2-5, 2-6, 4-5 data 1-1, 1-4 decode 4-4, 10-17, 10-18 decode enable 10-10, 10-17 decoding circuitry 5-1 detected 6-1 EROMBA 10-18 invariance 2-1, 2-7 LAS0BA 10-17 LAS0BRD 10-19 LAS0RR 10-15 LAS1BA 10-17 LAS1BRD 10-20 LAS1RR 10-15 LAS2BA 10-18 LAS2BRD 10-21 LAS2RR 10-16 LAS3BA 10-18 LAS3BRD 10-22 LAS3RR 10-16 local bits 2-1 local bus initialization 4-4 local chip selects 5-1-5-2
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Index-1
Index
Address/Data to burst
local space 0 2-7 local space 1 2-7 local space 2 2-7 local space 3 2-7 local spaces 1-1, 1-6 mapping 4-3 multiple independent spaces 1-2 Multiplexed Bus mode 11-1 Multiplexed Bus mode interface 11-9 Non-Multiplexed Bus mode 11-1 Non-Multiplexed Bus mode interface 11-11 PCI command 10-4 PCI status 10-5 PCI system bus interface pins 11-5 PCI Target byte enables 4-6 PCI Target example 4-5 PCI Target initialization 4-4 PCI VPD (PVPDAD) 10-14 PCIBAR enable 10-26 PCIBAR0 10-6 PCIBAR1 10-7 PCIBAR2 10-7 PCIBAR3 10-8 PCIBAR4 10-8 PCIBAR5 10-9 PCI-to-Local spaces 1-4 pointer 10-1 PROT_AREA 10-25 random read and write 9-2 Read Ahead mode 4-2 register 1-6 register mapping 10-2-10-3 serial EEPROM register 10-1 serial EEPROM register load sequence 3-4-3-6 translation 4-1 VPD 9-1 Address/Data 2-3 LA[27:2] 2-3 LAD[31:0] 2-3 LD[31:0] 2-3 ADS# 11-9, 11-11 ALE 11-9, 11-11 arbitration, Local Bus 2-2, 2-4 timing diagrams 4-7 architecture boundary scan 11-13 bridge 2-1 RISC 2-1 atomic operations LLOCKo# 11-7 LOCK# 11-5 locked 4-1
B
back-to-back fast capable 10-5 fast enable 10-4 timing diagrams 4-19-4-22 BCLKo 11-7 BD_SEL# 8-1 BD_SEL#/TEST 11-4 BIAS, precharge voltage 1-3, 8-1, 8-2 bus interface pins 11-5-11-6 test and debut pins 11-4 Big Endian See Endian, Big BIOS, PCI 7-1 BLAST# 11-9, 11-11 block diagrams internal 1-1 Local Bus 2-2 board routing BGA 13-9-13-10 bridge architecture 2-1 BTERM# 2-5, 11-9, 11-11 burst access 1-4, 2-6, 4-1, 4-5 continuous mode 2-5, 2-6 during 11-9, 11-11 expansion ROM enable 10-23 last 11-9, 11-11 memory space enable 10-19, 10-20, 10-21, 10-22 memory-mapped 1-4 Min_Gnt 10-10 mode 2-5 order 2-7, 2-8
Index-2
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
burst access to CompactPCI
PCI read 4-1 read and write 11-5 read cycles 2-6 SMARTarget programmable 1-2 terminate 11-9, 11-11 timing diagrams 4-12-4-15, 4-25, 4-26, 4-32, 4-33, 4-34, 4-35, 4-36, 4-37, 4-38, 4-39, 4-40 write cycles 2-6 timing diagrams 4-11-4-15 zero wait state 1-1, 1-5 burst access 2-3 Burst mode, internal wait state programming 2-5 Burst-4 Lword mode 2-5, 2-6 bus modes See Multiplexed mode and Non-Multiplexed mode bus region descriptors 3-2, 3-5, 4-3, 4-4, 10-3 register 2-4, 10-7, 10-8, 10-9, 10-19, 10-20, 10-21, 10-22, 10-23, 11-10, 11-12 byte conversion, Big/Little Endian 1-2, 1-4 byte enables 2-1, 2-6 C/BE[3:0]# 11-5 PCI Target, Multiplexed mode 4-5 PCI Target, Non-Multiplexed mode 4-6 byte swapping, Big/Little Endian 1-1 LSW 3-5 procedure to use base address registers 5-2 serial EEPROM 10-26, 11-3 SMARTarget 1-2 chip select registers address mapping 10-3 CS0BASE 10-24 CS1BASE 10-24 CS2BASE 10-24 CS3BASE 10-24 clocks 7-1, 11-6 buffered PCI 1-6 Bus access 11-9, 11-11 EESK 3-3, 11-3 EROMBRD 10-23 input 12-3 LAS0BRD 10-19 LAS1BRD 10-20 LAS2BRD 10-21 LAS3BRD 10-22 LCLK 11-7 Local 1-5, 11-7, 12-5 PCI 1-5, 3-3, 10-11, 11-7 PCI Target 10-26 PCI Target retry delay 4-5 PCIMGR 10-10 PCLK 11-6 RST# 1-5 serial EEPROM 3-3, 10-26 serial EEPROM clock pin 11-3 command codes, PCI Target 2-1 CompactPCI adapter card, high-performance 1-3 high performance adapter designs 1-3 Hot Swap 8-1-8-4 applications 8-1 blue LED 8-3 board healthy 8-2 board slot control 8-2 capabilities register bit definition 8-4 capable 1-6, 8-1 compliant 1-1 control bits 8-4 Control/Status register (HS_CSR) 8-4 controlling connection processes 8-1 ejector switch 8-3 ENUM# 8-3 friendly 8-1 hardware connection control 8-1
C
C/BE[3:0]# 2-1, 11-5 cache line size, PCI 10-6 CAP_PTR 10-10 capacitance 12-1 chip select 1-1, 1-4 base address and range 5-1 base address registers 5-1-5-2 CNTRL 10-26 CS[1:0]# 11-7 CS0BASE 10-24 CS1BASE 10-24 CS2BASE 10-24 CS3BASE 10-24 general purpose 11-7 GPIO2/CS2# 11-7 GPIO3/CS3# 11-7 IDSEL 11-5 initialization device 11-5 local 5-1-5-2, 10-3
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Index-3
Index
CompactPCI Specification to decode
ID 8-4 levels of compatibility 8-1 Next_Cap Pointer 8-4 platform reset 8-2 ready 1-4, 8-1 register 10-1 See Also Hot Swap software connection control 8-3 implementing 1-2 industrial PCI implementations 1-2 CompactPCI Specification xvii configuration accesses 1-5, 3-1, 3-7, 7-2, 10-12 Big/Little Endian 4-3 BTERM# 11-9, 11-11 bus-width 11-10, 11-12 command type 2-1 control/status register 8-4 CS[1:0]# 11-7 Hot Swap 8-1, 8-4 I/O-mapped register 3-7 IDSEL 11-5 INTCSR 11-7 LINTi1 11-7 LINTi2 11-7 load information 1-5 local registers 3-1, 3-6 memory-mapped register 3-7 new capabilities 9-1 new capability linked list 10-1 PCI cycles 7-1 PCI registers 3-6, 3-7 power management 7-2 read and write 11-5 register space 1-5 registers 3-1, 4-1, 11-7, 11-9, 11-11 serial EEPROM 3-1 software reset 3-1 space 8-4, 9-1, 10-1 subsystem ID and subsystem vendor ID 1-5 system reconfiguration 8-1, 8-3 Target bus-width 11-12 timing diagrams 3-9, 3-10, 4-8, 4-9, 4-10 type 0 cycle 3-7 VPD 1-1, 9-1 wait state counter 2-4-2-5 configuration initialization timing diagrams 3-8-3-11, 4-7-4-10 Continuous Burst mode 2-5 2-5-2-6 Control/Status 2-3-2-4 ADS# 2-3 ALE 2-3 LBE[3:0]# 2-3 LLOCK# 2-4 LW/R# 2-3 READY# 2-3 WAIT# 2-4 controller programmable interrupt 1-1, 1-2, 1-4 conversion Big/Little Endian 1-6, 4-3 Big/Little Endian byte 1-2, 1-4 on-the-fly 1-5, 4-3 counter, prefetch 1-6, 4-1 register bits 10-19, 10-20, 10-21, 10-22, 10-23 timing diagrams, settings in 4-26, 4-37, 4-38 counter, wait state 2-4-2-5 CPCISW 8-1, 11-7 CPU host 2-4, 8-3 local 7-3, 10-12 CS[1:0]# 11-7 CS0BASE 10-24 CS1BASE 10-24 CS2BASE 10-24 CS3BASE 10-24
D
data assignment convention 1-5 deadlock, avoided with PMW 1-4 debug interface JTAG test access port 11-13 test access method 11-13 pins 11-4 port 11-13 decode accesses 4-4 address 4-4, 10-17, 10-18 address enable 10-10 memory 10-15, 10-16
Index-4
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Delayed Read mode to Endian, Little
Delayed Read mode CNTRL 10-26 PCI Target 1-1, 4-2 read accesses, PCI Target 2-6 transaction timing diagram 4-41 delayed read transactions 1-6 Delayed Write mode, PCI Target 1-1 timing diagrams 4-11 transactions 1-6 descriptors, bus region 2-4, 3-5, 4-3, 4-4, 10-3, 10-7, 10-8, 10-9, 10-19, 10-20, 10-21, 10-22, 10-23, 11-10, 11-12 device ID 3-1, 3-4, 9-1, 10-4 DEVSEL# 11-5 Direct Slave See PCI Target disconnect delayed read transaction 4-41 Flush Read FIFO 10-27 PCI 3-7 PCI Target I/O accesses, after transfer for all 4-1 PCI Target Write mode 10-26 DSP devices, Local Bus can connect to 2-1 local inputs 12-3 local output delay 12-4 local outputs 12-4 embedded design 11-1 systems 1-1, 1-2 Endian, Big 2-7-2-8 16-bit Local Bus 2-8 lower word lane transfer 2-8 upper word lane transfer 2-8 32-bit Local Bus 2-7 upper Lword lane transfer 2-7 8-bit Local Bus 2-8 lower byte lane transfer 2-8 upper byte lane transfer 2-8 Byte Lane mode in EROMBRD 10-23 LAS0BRD 10-19 LAS1BRD 10-20 LAS2BRD 10-21 LAS3BRD 10-22 byte number and lane cross-reference 2-7 byte ordering in EROMBRD 10-23 LAS0BRD 10-19 LAS1BRD 10-20 LAS2BRD 10-21 LAS3BRD 10-22 byte swapping 1-1 conversion 1-2, 1-4, 1-6, 4-3 cycle reference table 2-7 Local Bus accesses 2-7 on-the-fly conversion 1-5, 4-3 Program mode 2-7 Endian, Little 2-7-2-8 Byte Lane mode in EROMBRD 10-23 LAS0BRD 10-19 LAS1BRD 10-20 LAS2BRD 10-21 LAS3BRD 10-22 byte number and lane cross-reference 2-7 byte ordering in EROMBRD 10-23 LAS0BRD 10-19 LAS1BRD 10-20 LAS2BRD 10-21 LAS3BRD 10-22
E
EECS 11-3 EEDI 11-3 EEDO 11-3 EESK 11-3 electrical characteristics, over operating range 12-2 electrical specifications 12-1-12-5 AC characteristics 12-3, 12-4 ALE output delay 12-5 capacitance 12-1 general 12-1-12-2 absolute maximum ratings 12-1 operating ranges 12-1 over operating range 12-2 thermal resistance, packages 12-1
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Index-5
Index
ENUM# to Hot Swap
byte swapping 1-1 conversion 1-2, 1-4, 1-6, 4-3 cycle reference table 2-7 Local Bus accesses 2-7 on-the-fly conversion 1-5, 4-3 PCI Bus 2-1 Program mode 2-7 ENUM# 8-1, 8-3, 10-13, 11-5 EROMBA 10-18 EROMBRD 10-23 EROMRR 10-17 expansion ROM space 1-4, 2-7, 3-4, 4-1, 4-3, 4-6, 10-2, 10-3, 10-10 access, address decode enable 10-10 BTERM# Input enable 10-23 Local Address 4-1 Local Bus width 10-23 on-the-fly Endian conversion 1-5 PCI Target Byte enables (Multiplexed mode) 4-5 PCI Target Byte enables (Non-Multiplexed mode) 4-6 PCI Target lock 4-1 PCI Target transfer 4-3 READY# Input enable 10-23 remap 10-18
G
general purpose I/O 6-1-6-2, 11-7 control register (GPIOC) 6-2, 10-27-10-28 See Also GPIO-related entries generator programmable interrupt 1-1, 1-2, 1-4 programmable wait state 4-1, 11-7, 11-9, 11-10, 11-11, 11-12 GPIO programmable general purpose I/O 1-1, 1-4 See Also general purpose I/O SMARTarget 1-2 GPIO0/WAITo# 11-7 GPIO1/LLOCKo# 11-7 GPIO2/CS2# 11-7 GPIO3/CS3# 11-7 GPIO4/LA27 11-9 LA[27:24] 11-11 GPIO5/LA26 11-9, 11-11 GPIO6/LA25 11-9, 11-11 GPIO7/LA24 11-9, 11-11 GPIO8 11-7 GPIOC register 6-2, 10-27-10-28
F
F., sets a flag 9-1 FIFOs CNTRL, in 10-26, 10-27 Continuous Burst mode 2-6 depth 1-5 enable high-performance bursting 1-4 number of 1-6 PCI Target example 4-5 operation 4-1 Read Ahead mode 4-2 transfer 4-3 programmable 1-1, 1-5 response to 4-6 FRAME# 11-5
H
hidden registers 3-5, 3-6, 7-2, 7-3, 10-1, 10-3, 10-12, 10-13, 10-29 hold and setup waveform, local input 12-3 hold waveform figure 12-3 Hot Plug 1-1 specification xvii system driver 8-3, 8-4 Hot Swap 8-1-8-4 Control 10-13 Control/Status 10-13
Index-6
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Hot Swap Ready to interrupt
HS_CNTL 10-13 HS_CSR 8-4, 10-13 HS_NEXT 10-13 ID 10-13 next capability (Next_Cap) pointer 10-13 resources 8-3 See Also CompactPCI Hot Swap Hot Swap Ready CompactPCI 1-2 compliant with PICMG 2.1 1-1, 1-4 target device 1-3 HS_CNTL 10-13 HS_CSR 8-4, 10-13 HS_NEXT 10-13 new capability function 10-5 power management 10-1 power management capability 7-1, 10-11 revision 9-1, 10-2, 10-5 silicon revision 1-5 subsystem 1-5, 3-1, 9-1, 10-2, 10-9 subsystem vendor 1-5, 3-1, 9-1, 10-2, 10-9 vendor 1-5, 1-6, 3-1, 9-1, 10-2, 10-4 VPD 9-1, 10-1, 10-14 IDSEL 11-5 IEEE 1149.1 specifications, architectural standard 11-13 industrial PCI implementations 1-2 temp range operation 1-1 initialization 3-1 control 10-3 from serial EEPROM (2K or 4K) timing diagram 3-8, 4-7 IDSEL 11-5 PCI Target example 4-5 PCI Target initialization 4-4 PCI Target local bus 4-4 PMC 10-11 reset 4-3 serial EEPROM 3-1-3-11 initialization control (CNTRL) 10-26-10-27 input, general purpose 6-2 INTA# 6-1, 11-5 INTCSR 10-25 interface chip, target 1-4 internal block diagram 1-1 internal wait states 2-5, 2-6, 4-1, 4-31, 11-7 interrupt control/status 10-3, 10-25 controller 1-1, 1-2, 1-4 disabled 7-1, 10-12 ENUM# driven 8-3 interrupt 8-3, 8-4 interrupt mask 10-13 error sources 6-1 generator 1-1, 1-2, 1-4 INTA# 6-1 line 10-2, 10-10 local edge triggered 3-11, 4-10 input (LINTi[2:1]) 6-1
I
I/O accelerator 1-2 access 2-1, 4-1, 4-5, 10-7, 10-12 access internal registers 3-7 base address 10-7 buffers 11-2 Data I/O for programming serial EEPROM values 3-3 disabled 7-1, 7-2 general purpose 6-1-6-2, 11-7 general purpose I/O control register (GPIOC) 10-27- 10-28 Hot Swap requirement 8-1 initialization control (CNTRL) 10-26-10-27 input/output pin 11-1 insertion and extraction, during 8-2 mapped accesses 1-4 mapped configuration registers 10-2 outputs 12-2 pin type 11-5, 11-8, 11-9, 11-12 read 2-1 SMARTarget 1-2 space access 10-4, 10-6, 10-7, 10-8, 10-9, 10-15, 10-16, 10-17, 10-18 tolerance 1-5 write 2-1 ID capability 10-2 class code 9-1 configuration 10-4 device 1-5, 1-6, 3-1, 9-1, 10-2, 10-4 Hot Swap 8-4, 10-13 network 1-5
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Index-7
Index
IRDY# to Local Address
level triggered 3-11, 4-10 LINTi1 6-1, 11-7 LINTi2 6-1, 11-7 LPMINT# output 7-3 power management (LPMINT#) 6-1, 11-8 Local-to-PCI 1-1 LSW 3-5 output set by ENUM# 11-5 PCI Power Management Functional Description 7-1-7-3 PCI and Local 6-1-6-2 PCI SERR# (PCINMI) all modes 6-1 pin 3-4, 10-2, 10-10 request 11-5 wake-up event 11-6 IRDY# 11-5 ISA bus interface 1-6 LAS3BRD 10-22 LAS3RR 10-16 latency timer, PCI, not supported 10-2, 10-6 layers, routing BGA 13-9-13-10 LBE[3:0]# 11-10, 11-12 LCLK 11-7 LD[31:0] 11-12 LEDon# 8-1, 11-7 LGNT 11-7 LINTi1 interrupt input, LINT[2:1] 11-7 LINTi2 11-7 Little Endian See Endian, Little Local Address Big/Little Endian mode 2-7 bits LA[1:0] 2-1 EROMBA 10-18 increment 11-9, 11-11 LAS0BA 10-17 LAS0BRD 10-19 LAS0RR 10-15 LAS1BA 10-17 LAS1BRD 10-20 LAS1RR 10-15 LAS2BA 10-18 LAS2BRD 10-21 LAS2RR 10-16 LAS3BA 10-18 LAS3BRD 10-22 LAS3RR 10-16 mapping 4-3 PCI Target example 4-5 PCIBAR2 10-7 PCIBAR3 10-8 PCIBAR4 10-8 PCIBAR5 10-9 PCI-to-Local spaces 1-4 spaces 1-1, 1-6, 4-1, 10-2, 10-3
J
JTAG boundary scan interface 11-13 instructions 11-13
L
LA[23:2] 11-9, 11-11 LA[27:24] 11-9 LAD[31:0] 11-9 LAS0BA 10-17 LAS0BRD 10-19 LAS0RR 10-15 LAS1BA 10-17 LAS1BRD 10-20 LAS1RR 10-15 LAS2BA 10-18 LAS2BRD 10-21 LAS2RR 10-16 LAS3BA 10-18
Index-8
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Local Bus to map
Local Bus 2-1-2-8 accesses 2-1 arbitration 2-4 Big/Little Endian Mode 2-7-2-8 Burst and Bterm modes 2-5 characteristics 4-3 configuration registers 10-3 control 4-5 cycles 2-4-2-6 I/Os 8-2 independent interface pins 11-7 interface 2-4-2-6 internal register access 3-6 introduction 2-1-2-2 local signals 2-2 memory map example 5-2 PCI Target access 3-2, 4-4 PCI Target operation 4-1 PCI Target READY# Timeout 1-6 PCISR 10-5 PCI-to-Local 1-2 pin information 11-1 PMCSR 10-12 power management 7-1 programmable 1-4 read accesses 2-6 Read Ahead mode 1-4, 4-2 response to FIFO 4-6 serial EEPROM 3-3 signaling 1-5, 1-6 signals 2-2 soft reset 7-2 timing diagrams 4-12-4-18, 4-23-4-33, 4-35-4-40 VPD 9-1 width 4-6 width control 1-2 write accesses 2-6 Local Bus block diagram 2-2 Local Bus region descriptor 2-4, 4-4, 10-3, 10-19, 10-20, 10-21, 10-22, 10-23, 11-10, 11-12 register 10-19, 10-20, 10-21, 10-22, 10-23 local chip selects See chip select local clocks, internal 1-5 Local configuration registers 10-15-10-23 address mapping 10-3 EROMBA 10-18 EROMBRD 10-23 EROMRR 10-17 LAS0BRD 10-19 LAS0RR 10-15 LAS1BA 10-17 LAS1BRD 10-20 LAS1RR 10-15 LAS2BA 10-18 LAS2BRD 10-21 LAS2RR 10-16 LAS3BA 10-18 LAS3BRD 10-22 LAS3RR 10-16 PROT_AREA 10-25 local input setup figure 12-3 local power management enumerator set 6-1 local signal output delay 12-4 Local Signals LW/R# 2-2 lock atomic operations 4-1, 11-7 CNTRL 10-26 cycles 1-6 LLOCKo# 11-7 LOCK# 4-1, 10-26, 11-5 PCI Target 4-1 LOCK# 11-5 LPMESET 11-8 LPMINT# 6-1 11-8 LREQ 11-8 LRESETo# 11-8 LW/R# 11-10, 11-12
M
map I/O-mapped configuration register 3-7 memory 5-2 memory example 5-2 memory-mapped configuration register 3-7 PCI software 3-1, 4-4 PCI Target 1-4 read accesses 4-5 remap local base address 4-5 remap PCI-to-Local addresses 4-4 remap serial EEPROM register load sequence 3-4
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Index-9
Index
mapping to Non-Multiplexed Bus
See Also mapping and remap serial EEPROM memory 3-6 mapping EROMBA 10-18 LAS0BA 10-17 LAS1BA 10-17 LAS2BA 10-18 LAS3BA 10-18 local registers 4-1 register address 10-2-10-3 maximum rating 12-1 memory accesses 2-5, 3-7, 10-6, 10-7, 10-8, 10-9 address spaces 10-7, 10-8, 10-9, 10-15, 10-16 base address 10-6, 10-7, 10-8, 10-9 BTERM# 2-5 burst memory-mapped 1-4 commands aliased to basic 2-1 cycle 3-7 decode 10-15, 10-16 disabled 7-1 local controller 2-5 local spaces 1-4 location of registers 10-6, 10-7, 10-8, 10-9 map example 5-2 mapped configuration registers 10-2 mapping 10-15, 10-16, 10-17, 10-18 PCI 7-2, 10-12 PCI Target transfer 4-3 PCIBAR enabled 10-26 PCIBAR0 10-6 PCIBAR2 10-7 PCIBAR3 10-8 PCIBAR4 10-8 PCIBAR5 10-9 posted writes (PMW) 1-4 prefetchable 10-7, 10-8, 10-9 prefetching 10-19, 10-21, 10-22, 10-23 read 2-1 read accesses 4-5 read cycle 10-19, 10-20, 10-21, 10-22, 10-23 remap 10-17, 10-18 serial EEPROM map 3-6 space 0 10-19 space 1 10-20 space 2 10-21 space 3 10-22 space access 10-4 space indicator 10-6, 10-7, 10-8, 10-9, 10-15, 10-16 spaces 10-15, 10-16, 10-17, 10-18 timing diagram 3-10, 4-9, 4-10 write 2-1 write and invalidate 10-4, 10-6 write transfers 10-6 BGA board routing 13-9-13-10 routing layers 13-9-13-10 low-power CMOS 1-1 ordering instructions A-1 package layout 13-7 package mechanical dimensions 13-4-13-5 PCB layout suggested land pattern 13-6 pinout 13-8-13-9 routing, board 13-9-13-10 MODE 11-8 modes, bus See Multiplexed mode and Non-Multiplexed mode Multiplexed Bus LAD[31:0] 2-3 Multiplexed mode Bus mode interface 11-9 Bus mode, in 11-8 byte number and lane cross-reference 2-7 feature 1-1 interface pin 11-1, 11-5 Local Bus direct interface 1-5 Local Bus interface and Bus cycles 2-4 Local Bus types 2-4 PCI Target timing diagrams 4-11-4-22 programmable Local Bus 1-4 recovery states 2-6 Multiplexed mode only timing diagrams 4-23-4-26
N
new capabilities functions support 10-5 linked list 7-1 Next_Cap Pointer 8-4 Pointer (CAP_PTR) 7-1, 10-1, 10-10 structure 3-7, 8-4, 9-1 support bit 7-1 VPD 9-1 Non-Multiplexed Bus LA[27:2] 2-3 LD[31:0] 2-3
Index-10
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Non-Multiplexed mode to PCI configuration registers
Non-Multiplexed mode Big/Little Endian byte number and lane cross-reference 2-7 Bus mode interface 11-11 Bus mode, in 11-8 feature 1-1 interface pin 11-1 Local Bus direct interface 1-5 Local Bus interface and Bus cycles 2-4 Local Bus types 2-4 PCI Target timing diagrams 4-11-4-22 programmable Local Bus modes 1-4 Non-Multiplexed mode only PCI Target timing diagrams 4-27-4-44 PCI Bus Power Management Interface Specification xvii, 7-1 PCI Target lock 4-1 PCI Target operation 4-1 PCI Target transfer 4-3 PCISR 10-5 region 3-2, 4-3, 4-4, 10-3, 10-7, 10-8, 10-9 response to FIFO 4-6 soft reset 7-1, 7-2 software reset 3-1 system bus interface pins 11-5-11-6 transactions 4-5 Vcc 1-6 VPD 9-1 wait states 2-1 PCI Bus Latency Timer, not supported 10-2, 10-6 PCI Bus Power Management Interface Specification xvii PCI Bus state internal block diagram 1-1 wait state control 2-4 PCI configuration registers 10-4-10-14 address mapping 10-2 CAP_PTR 10-10 HS_CNTL 10-13 HS_CSR 10-13 HS_NEXT 10-13 PCIBAR0 10-6 PCIBAR1 10-7 PCIBAR2 10-7 PCIBAR3 10-8 PCIBAR4 10-8 PCIBAR5 10-9 PCIBISTR 10-6 PCICCR 10-5 PCICIS 10-9 PCICLSR 10-6 PCICR 10-4 PCIERBAR 10-10 PCIHTR 10-6 PCIIDR 10-4 PCIILR 10-10 PCIIPR 10-10 PCILTR 10-6 PCIMGR 10-10 PCIMLR 10-11 PCIREV 10-5 PCISID 10-9 PCISR 10-5
O
180-pin BGA See BGA 176-pin PQFP See PQFP on-the-fly Big/Little Endian conversion 1-5, 4-3 expansion ROM space 1-5 operating ranges 12-1 output, general purpose 6-2
P
package mechanical dimensions BGA 13-4-13-5 PQFP 13-1 PAR 11-6 PCB layout suggested land pattern BGA 13-6 PQFP 13-2 PCI 9030 compared with PCI 9050 and 9052 1-6 compatibility with other PLX chips 1-5 SMARTarget features 1-4-1-5 PCI applications 1-3-1-4 PCI Bus 2-1 1-1, 1-4, 2-7, 10-2, 11-8, 12-3, 12-4 access to internal registers 3-7 board healthy 8-2 CNTRL 10-26 cycles 2-1 GPIOC 6-2 Hot Swap Ready target device 1-2 input RST# 3-1 interface 2-1 Little Endian mode 2-1 local address spaces 4-3, 4-5
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Index-11
Index
PCI Delayed Read mode to PCIREV
PCISVID 10-9 PMC 10-11 PMCAPID 10-11 PMCSR 10-12 PMCSR_BSE 10-12 PMDATA 10-13 PMNEXT 10-11 PVPD_NEXT 10-14 PVPDAD 10-14 PVPDATA 10-14 PVPDCNTL 10-14 PCI Delayed Read mode 4-2, 10-26 timing diagram 4-41 PCI Hot-Plug Specification, Revision 1.0 xvii PCI Industrial Computer Manufacturers Group xvii PCI Initiator, not supported 2-4 PCI Local Bus Specification, Revision 2.2 xvii PCI Special Interest Group xvii, 1-2 PCI specification 1-4 PCI Target abort 2-1, 10-5 accesses to 8- or 16-bit Local Bus 2-1 Big Endian/Little Endian cycle reference table 2-7 BTERM# input 2-5 bursting 1-4 command codes 2-1 Delayed Read mode 1-1 Delayed Write mode 1-1 description 1-2 Direct Data Transfer mode 4-1-4-4 FIFOs depth 1-5, 1-6 interface chip 1-4 Local Bus Big Endian/Little Endian mode accesses 2-7 Local Bus READY# Timeout 1-6 partial Lword accesses 2-6 PCI-to-Local address 4-3 power management 7-1 Power mode example 7-3 programmable burst management 1-1 Read Ahead mode 1-1 response 10-3 response (CNTRL) 10-26-10-27 response to FIFO full or empty 4-6 serial EEPROM initialization, during 3-1 SMARTarget delayed write 1-2 SMARTarget Technology 1-2 space 0 enable in LAS0BA 10-17 space 1 enable in LAS1BA 10-17 space 2 enable in LAS2BA 10-18 space 3 enable in LAS3BA 10-18 transactions 1-4 wait states Local Bus 2-5 PCI Target Operation 4-1-4-44 PCIBAR0 10-6 PCIBAR1 10-7 PCIBAR2 10-7 PCIBAR3 10-8 PCIBAR4 10-8 PCIBAR5 10-9 PCIBISTR 10-6 PCICCR 10-5 PCICIS 10-9 PCICLSR 10-6 PCICR 10-4 PCIERBAR 10-10 PCIHIDR 3-1 PCIHTR 10-6 PCIIDR 3-1, 10-4 PCIILR 10-10 PCIIPR 10-10 PCILTR 10-6 PCIMGR 10-10 PCIMLR 10-11 PCIREV 10-5
Index-12
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
PCISID to pins, PCI System Bus Interface
PCISID 10-9 PCISR 10-5 PCISVID 3-1, 10-9 PCLK 11-6 PCMCIA PC Card, typical 1-4 performance features 1-4 PERR# 11-6 physical specs 13-1-13-10 BGA 13-4-13-10 PQFP 13-1-13-3 PICMG 1-2 PICMG 2.1,CompactPCI Hot Swap Specification, Revision 1.0 xvii pinout BGA 13-8-13-9 PQFP 13-3 pins debug 11-4 Local Bus mode independent interface 11-7 Multiplexed Bus mode interface 11-9 Non-Multiplexed Bus mode interface 11-11 PCI system bus interface 11-5-11-6 power and ground 11-2 serial EEPROM 11-3 test 11-4 pins, Hot Swap BD_SEL# 8-1 CPCISW 8-1 ENUM# 8-1 LEDon# 8-1 pins, Local Bus Mode Independent Interface BCLKo 11-7 CPCISW 11-7 GPIO0/WAITo# 11-7 GPIO1/LLOCKo# 11-7 GPIO2/CS2# 11-7 GPIO3/CS3# 11-7 GPIO8 11-7 LCLK 11-7 LEDon# 11-7 LGNT 11-7 LINTi1 11-7 LINTi2 11-7 LPMESET 11-8 LPMINT# 11-8 LREQ 11-8 LRESETo# 11-8 MODE 11-8 pins, Multiplexed Bus Mode Interface ADS# 11-9 ALE 11-9 BLAST# 11-9 BTERM# 11-9 GPIO4/LA27 11-9 GPIO5/LA26 11-9 GPIO6/LA25 11-9 GPIO7/LA24 11-9 LA[23:2] 11-9 LAD[31:0] 11-9 LBE[3:0]# 11-10 LW/R# 11-10 RD# 11-10 READY# 11-10 WR# 11-10 pins, Non-Multiplexed Bus Mode Interface ADS# 11-11 ALE 11-11 BLAST# 11-11 BTERM# 11-11 GPIO4/LA27 11-11 GPIO5/LA26 11-11 GPIO6/LA25 11-11 GPIO7/LA24 11-11 LA[23:2] 11-11 LBE[3:0]# 11-12 LD[31:0] 11-12 LW/R# 11-12 RD# 11-12 READY# 11-12 WR# 11-12 pins, PCI Mode Independent Interface CS[1:0]# 11-7 LGNT 11-7 pins, PCI System Bus Interface AD[31:0] 11-5 C/BE[3:0]# 11-5 DEVSEL# 11-5 ENUM# 11-5 FRAME# 11-5 IDSEL 11-5 INTA# 11-5 IRDY# 11-5 LOCK# 11-5 PAR 11-6
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Index-13
Index
pins, Power and Ground (BGA) to prefetch
PCLK 11-6 PERR# 11-6 PME# 11-6 RST# 11-6 SERR# 11-6 STOP# 11-6 TRDY# 11-6 V I/O 11-2 pins, Power and Ground (BGA) VDD 11-2 VSS 11-2 pins, Power and Ground (PQFP) VDD 11-2 VSS 11-2 pins, Serial EEPROM Interface EECS 11-3 EEDI 11-3 EEDO 11-3 EESK 11-3 pins, Test and Debug BD_SEL#/TEST 11-4 TCK 11-4 TDI 11-4 TDO 11-4 TMS 11-4 TRST# 11-4 platform, reset 8-2 PLX Technology, Inc. company background 1-2 product ordering instructions A-1 representatives and distributors A-1 technical support A-1 PMC 10-11 PMC adapter card, typical 1-4 PMCAPID 10-11 PMCSR 10-12 PMCSR_BSE 10-12 PMDATA 10-13 PMDATASCALE (Hidden 2) 10-29 PMDATASEL (Hidden 1) 10-29 PME# 11-6 PMNEXT 10-11 power management 7-1-7-3 capabilities 10-2, 10-11 capability ID register 10-11 control/status 10-12 data 10-1, 10-13 data scale 10-29 data select 10-29 enumerator set 6-1 features 1-4 functional description 7-1-7-3 hidden 1 register 10-1, 10-3 hidden 2 register 10-1, 10-3 ID 10-1 local interrupt 6-1 new capability function 3-7 next capability pointer 10-11 PCI specification 1-1, 1-4, 1-6, 10-11 pins 11-6, 11-8 Power mode example 7-3 registers 3-4, 3-6, 10-1, 10-2, 10-3, 10-11-10-12, 10-13, 10-29 specification compliant 1-1 status 10-1 system changes 7-3 wake-up request example 7-3 PQFP Local Bus types 2-4 low-power CMOS 1-1 ordering instructions A-1 package mechanical dimensions 13-1 PCB layout suggested land pattern 13-2 pinout and signal 13-3 signal and pinout 13-3 precharge 1-3, 8-1, 8-2, 12-2 precharge voltage, BIAS 1-3, 8-1, 8-2 bus interface pins 11-5-11-6 test and debug pins 11-4 preempt condition 2-4, 11-7 preempt default condition 2-4 prefetch CNTRL 10-26 EROMBRD 10-23 LAS0BRD 10-19 LAS0RR 10-15 LAS1BRD 10-20 LAS1RR 10-15 LAS2BRD 10-21 LAS2RR 10-16
Index-14
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
prefetch counter to register, addresses
LAS3BRD 10-22 LAS3RR 10-16 mechanism 1-1 PCI Target access 4-1 PCI Target example 4-5 PCI Target read 1-2 PCI Target Read Ahead mode 4-2 PCIBAR0 10-6 PCIBAR2 10-7 PCIBAR3 10-8 PCIBAR4 10-8 PCIBAR5 10-9 prefetch counter prefetch size 4-1 programmable 1-6 timing diagrams, settings in 4-26, 4-37, 4-38 PROT_AREA 10-25 PVPD_NEXT 10-14 PVPDAD 10-14 PVPDATA 10-14 PVPDCNTL 10-14 PCI Target timing diagrams 4-24, 4-26, 4-29, 4-30, 4-31, 4-34, 4-37, 4-38, 4-42, 4-43 PCI Target transfer 4-3 prefetching disabled 4-1 programmable strobe timing on local bus 1-2 random read and write 9-2 Read Ahead mode 1-4, 4-1, 4-2 registers 10-4-10-29 sequential read only 9-1 serial EEPROM accidental 9-2 control 1-6, 3-3 operation 3-1 sequential reads and writes 3-6 transfer 4-1 VPD 9-1 data 9-1 random read and write 9-2 registers 9-1 sequential read only 9-1 serial EEPROM partitioning 9-1 write PCI power management 7-1 Read Ahead mode CNTRL, in 10-26 PCI Target 1-1, 4-2 PCI Target Read No Flush mode timing diagram 4-42 Prefetch mode, in addition to 4-1 read accesses 2-6 SMARTarget Technology 1-2 supported by PCI 9030 1-4 READY# 11-10, 11-12 Bus mode 12-3 EROMBRD 10-23 function 11-10, 11-12 input 2-6 LA32BRD 10-22 LAS0BRD 10-19 LAS1BRD 10-20 LAS2BRD 10-21 recovery states 2-6 serial EEPROM initialization 3-1 Thold 12-3 timeout logic, SMARTarget 1-2 timing diagram 4-30 Tsetup 12-3 wait states 2-5, 4-1 reconfiguration, system See configuration register, addresses 1-6, 10-2-10-3
R
ranges, operating 12-1, 12-2 RD# 11-10, 11-12 read accesses 2-1, 2-6, 3-7, 4-5 configuration command 2-1 configuration timing diagram 3-9, 4-9 delayed 1-6 Delayed mode 4-2 delayed timing diagram 4-41 FIFOs 1-4, 1-6, 2-6, 4-1, 4-5 I/O command 2-1 Local Bus accesses 2-6 local prefetch mechanism 1-1 memory command 2-1 memory timing diagram 3-10, 4-10 PCI burst 4-1 PCI Configuration timing diagram 4-8 PCI initialization 4-4 PCI Memory timing diagram 4-9 PCI Power mode example 7-3 PCI Target 1-5, 1-6, 4-1, 4-2, 4-3, 4-6 PCI Target command codes 2-1 PCI Target prefetching 1-2
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Index-15
Index
registers to serial EEPROM
registers CAP_PTR 10-10 CS0BASE 10-24 CS1BASE 10-24 CS2BASE 10-24 CS3BASE 10-24 EROMBA 10-18 EROMBRD 10-23 EROMRR 10-17 GPIOC 6-2, 10-27-10-28 HS_CNTL 10-13 HS_CSR 10-13 HS_NEXT 10-13 INTCSR 10-25 LAS0BA 10-17 LAS0BRD 10-19 LAS0RR 10-15 LAS1BA 10-17 LAS1BRD 10-20 LAS1RR 10-15 LAS2BA 10-18 LAS2BRD 10-21 LAS2RR 10-16 LAS3BA 10-18 LAS3BRD 10-22 LAS3RR 10-16 PCIBAR0 10-6 PCIBAR1 10-7 PCIBAR2 10-7 PCIBAR3 10-8 PCIBAR4 10-8 PCIBAR5 10-9 PCIBISTR 10-6 PCICCR 10-5 PCICIS 10-9 PCICLSR 10-6 PCICR 10-4 PCIERBAR 10-10 PCIHIDR 3-1 PCIHTR 10-6 PCIIDR 3-1, 10-4 PCIILR 10-10 PCIIPR 10-10 PCILTR 10-6 PCIMGR 10-10 PCIMLR 10-11 PCIREV 10-5 PCISID 10-9 PCISR 10-5 PCISVID 3-1, 10-9 PMC 10-11 PMCAPID 10-11 PMCSR 10-12 PMCSR_BSE 10-12 PMDATA 10-13 PMDATASCALE 10-29 PMDATASEL 10-29 PMNEXT 10-11 PROT_AREA 10-25 PVPD_NEXT 10-14 PVPDAD 10-14 PVPDATA 10-14 PVPDCNTL 10-14 registers, hidden (PMDATASEL, PMDATASCALE) 7-2-7-3, 10-29 registers, new definitions summary 10-1 remap local base address 4-5 PCI-to-Local addresses 4-4 See Also map and mapping serial EEPROM register load sequence 3-4 reset initialization 4-3 platform 8-2 serial EEPROM 3-1-3-11 soft 7-1, 7-2 software 3-1 Revision ID 10-5 RISC architecture 2-1 routing, board BGA 13-9-13-10 RST# 11-6 Runtime registers 10-25-10-29 address mapping 10-3 CNTRL 10-26-10-27 GPIOC 10-27-10-28 INTCSR 10-25 PMDATASCALE 10-29 PMDATASEL 10-29 PROT_AREA 10-25
S
serial EEPROM accidental write to 9-2 address decode enable 10-17 base class code 10-5 CNTRL register 10-26-10-27 control 10-3 device ID 10-4 device ID and vendor ID registers 3-1
Index-16
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
SERR# to STOP#
hot swap ID 10-13 initialization 3-1 interface 1-1, 1-5 interface pins 11-1, 11-3 internal registers access 2-4, 3-6 interrupt pin register 10-10 load 3-3-3-6 memory map 3-6 new capabilities function support 3-7, 10-5 Next_Cap pointer 10-13 operation 3-1 PCI Bus access to internal registers 3-7 PROT_AREA 10-25 random read and write 9-2 read control 1-6 read or write 3-3 read-only portion 9-1 recommended 3-6 register level programming interface 10-5 register load sequence 3-4-3-6 reset and initialization 3-1-3-11 revision ID 10-5 simple VPD read to 9-2 simple VPD write to 9-2 software reset 3-1 subclass code 10-5 subsystem ID 10-9 subsystem vendor ID 10-9 support 1-6 timing diagrams 3-8-3-11, 4-7-4-10 vendor ID 10-4 vendor ID and device ID registers 3-1 VPD address 10-14 VPD stored in 9-1 write-protected address boundary 10-3, 10-25 Write-Protected Address Boundary register (PROT_AREA) 10-1 writes to 9-2 SERR# 11-6 setup and hold waveform, local input 12-3 signal name Local Bus mode independent interface pins 11-7 Multiplexed Bus mode interface 11-9 Non-Multiplexed Bus mode interface 11-11 PCI system bus interface pins 11-5-11-6 power and ground pins 11-2 serial EEPROM interface pins 11-3 signal specs BGA 13-8-13-9 PQFP 13-3 signaling Local Bus 1-5, 1-6 PCI Bus 1-6 support 1-1 signals synchronous inputs 12-3 synchronous outputs 12-4 silicon revision ID 1-5 Single Cycle mode 2-5 single writes, timing diagrams 4-16-4-18 SMARTarget Technology 1-2 chip select 1-2 features 1-4 I/O Accelerator 1-2 multiple independent programmable address spaces 1-2 PCI Target delayed write 1-2 programmable burst 1-2 programmable GPIOs 1-2 Read Ahead mode 1-2 READY# timeout logic 1-2 See Also PCI Target width control 1-2 soft reset 7-1, 7-2 software connection control 8-3 PCI 3-1, 4-4 reset 3-1 space 0 1-4, 2-7, 3-4, 4-1, 4-3, 4-5, 4-6, 10-2, 10-3, 10-7, 10-15, 10-17, 10-19 space 1 1-4, 2-7, 3-4, 4-1, 4-3, 4-5, 4-6, 10-2, 10-3, 10-8, 10-15, 10-17, 10-20 space 2 1-4, 2-7, 3-4, 4-1, 4-3, 4-5, 4-6, 10-2, 10-3, 10-8, 10-16, 10-18, 10-21 space 3 3-4 1-4, 2-7, 4-1, 4-3, 4-5, 4-6, 10-2, 10-3, 10-9, 10-16, 10-18, 10-22 specifications See electrical specifications, physical specs or signal specs SRAM chip enabled, timing diagram 4-11 states, four basic address 2-2 data/wait 2-2 idle 2-2 recovery 2-2 STOP# 11-6
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Index-17
Index
strobe timing, programmable read and write to write
strobe timing, programmable read and write 1-2 subsystem ID 3-1, 10-9 subsystem vendor ID 3-1, 10-9 system reconfiguration See configuration data register 10-14 function 3-3 ID 10-14 internal register access 3-6 last item in capabilities linked list 10-14 new capabilities function support feature 3-7 Next_Cap pointer 10-14 PCI register 10-1 random read and write 9-2 sequential read only 9-1 serial EEPROM accesses 10-25 values programmed with 3-3 VPD partitioning 9-1 support in 9030 1-4, 1-6 Write-Protected Address Boundary register (PROT_AREA) 10-1 voltage, precharge in BIAS 8-1, 8-2 bus interface pins 11-5-11-6 Hot Swap Ready 1-3 test and debug pins 11-4 VPD See Vital Product Data VSS 11-2
T
target interface chip 1-4 TCK 11-4 TDI 11-4 TDO 11-4 test pins 11-4 thermal resistance 12-1 timing diagrams 4-7-4-44 configuration initialization 3-8-3-11, 4-7-4-10 PCI Target, Multiplexed mode 4-11-4-22 PCI Target, Non-Multiplexed mode 4-11-4-22 PCI Target, Non-Multiplexed mode only 4-27-4-44 serial EEPROM 3-8-3-11, 4-7-4-10 timing, strobe programmable read and write 1-2 TMS 11-4 transfer, unaligned diagram 1-1 timing diagram 4-36 TRDY# 11-6 TRST# 11-4 type 0 cycle 3-7
W
wait state control 2-4-2-5 counter configuration 2-4-2-5 cycle control 10-4 generation 1-6, 2-6, 4-1, 4-3, 11-9, 11-10, 11-11, 11-12 internal programming 2-5 Local Bus 1-1, 2-5 NRAD 10-19, 10-20, 10-21, 10-22, 10-23 NRDD 10-19, 10-20, 10-21, 10-22, 10-23 NWAD 10-19, 10-20, 10-21, 10-22, 10-23 NWDD 10-19, 10-20, 10-21, 10-22, 10-23 NXDA 10-19, 10-20, 10-21, 10-22, 10-23 PCI Bus 2-1 PCI Target burst write timing diagram 4-40 PCI Target single read timing diagrams 4-30, 4-31 WAITo# 11-7 zero 1-1, 1-5 width control, SMARTarget 1-2 WR# 11-10, 11-12 write accesses 2-1, 3-7
U
unaligned transfer 1-1, 4-36
V
V I/O 11-2 VDD 11-2, 12-1, 12-2 vendor ID 1-5, 3-1, 3-4, 9-1, 10-4 Vital Product Data (VPD) 9-1-9-2 address 10-2, 10-14 capabilities register 9-1 configuration support 1-1 data 10-2
Index-18
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
zero wait state to zero wait state
configuration command 2-1 configuration timing diagram 3-9, 4-9 cycles 9-1 delayed transactions 1-6 FIFOs 1-4, 1-6, 2-6, 4-1 flush pending 4-2 I/O command 2-1 Local Bus accesses 2-6 memory command 2-1 memory timing diagram 3-10, 4-10 PCI Configuration timing diagram 4-8 PCI Memory timing diagram 4-9 PCI power management 7-1 PCI Power mode example 7-3 PCI Target 1-5, 1-6, 4-6 PCI Target command codes 2-1 PCI Target timing diagrams 4-23, 4-25, 4-27, 4-28, 4-32, 4-33, 4-35, 4-36, 4-39, 4-40, 4-43, 4-44 PCI Target transfer 4-3 posted memory (PMW) 1-4 random read and write 9-2 registers 10-4-10-29 serial EEPROM 9-2 accidental 9-2 control 3-3 operation 3-1 sequential reads and writes 3-6 strobe timing local bus, programmable 1-2 VPD 9-1 data 9-1 random read and write 9-2 serial EEPROM partitioning 9-1 simple 9-2 wake-up request example 7-3
Z
zero wait state 1-1, 1-5
PCI 9030 Data Book Version 1.1 (c) 2001 PLX Technology, Inc. All rights reserved.
Index-19
Index

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