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MITSUBISHI DIGITAL ASSP MITSUBISHI DIGITAL ASSP
M66221SP/FP M66221SP/FP
256256 x 9-BIT MAIL-BOX x 9-BIT MAIL-BOX
DESCRIPTION
The M66221 is a mail box that incorporates a complete CMOS shared memory cell of 256 x 9-bit configuration using high-performance silicon gate CMOS process technology, and is equipped with two access ports of A and B. Access ports A and B are equipped with independent addresses CS, WE and OE control pins and I/O pins to allow independent and asynchronous read/write operations from/to shared memory individually. This product also incorporates a port adjustment arbitration function in address contention from both ports.
PIN CONFIGURATION (Top view)
CHIP SELECT INPUT CSA 1 WRITE ENABLE INPUT WEA 2 NOT READY Not Ready A 3 OUTPUT OUTPUT ENABLE INPUT OEA 4
48 VCC 47 CSB CHIP SELECT INPUT 46 WEB WRITE ENABLE INPUT 45 Not Ready B NOT READY OUTPUT 44 OEB OUTPUT ENABLE INPUT 43 NC 42 A0B 41 A1B 40 A2B 39 A3B B PORT ADDRESS 38 A4B INPUT 37 A5B 36 A6B 35 A7B 34 NC 33 I/O8B 32 I/O7B 31 I/O6B 30 I/O5B B PORT 29 I/O4B DATA I/O 28 I/O3B 27 I/O2B 26 I/O1B 25 I/O0B
NC A PORT ADDRESS INPUT
5
A0A 6 A1A 7 A2A 8 A3A 9 A4A 10 A5A 11 A6A 12 A7A 13 NC 14
FEATURES
* * * * * * * * * * Memory configuration of 256 x 9 bits High-speed access, address access time 40ns (typ.) Complete asynchronous accessibility from ports A and B Completely static operation Built-in port arbitration function Low power dissipation CMOS design 5V single power supply Not Ready output pin is provided (open drain output) TTL direct-coupled I/O 3-state output for I/O pins.
M66221SP
APPLICATION
Inter-MPU data transfer memory, buffer memory for image processing system.
I/O0A 15 I/O1A 16 I/O2A 17 I/O3A 18 A PORT DATA I/O I/O4A 19 I/O5A 20 I/O6A 21 I/O7A 22 I/O8A 23 GND 24
FUNCTION
The M66221 is a mail box most suitable for inter-MPU data transfer which is used in a multiport mode. Provision of two pairs of addresses and data buses in its shared memory cell of 256 x 9 bit configuration allows independent and asynchronous read/write operations from/to two access ports of A and B individually. This allows access to shared memory as simple RAM when viewing from one MPU. The concurrent accessibility to shared memory from two MPUs provides remarkable improvement of a multiport mode processor system in throughput. The arbitration function incorporated in the chip decides the first-in port to assign a higher priority to the access from one MPU, even if two MPUs contend for selection of the same address in shared memory from ports A and B. A Not Ready signal "L" is output to the last-in port and invalidates any access from the other MPU. As a write operation to memory, one of addresses A0 to A7 is specified. The CS signal is set to "L" to place one of I/O pins in the input mode. Also, the WE signal is set to "L". Data at the I/O pin is thus written into memory. As a read operation, the WE signal is set to "H". Both CS signal and OE signal are set to "L" to place one of I/O pins in the output mode. One of addresses A0 to A7 is specified. Data at the specified address is output to the I/O pin. When the CS signal is set to "H", the chip enters a non-select state which inhibits a read and write operation. At this time, the output is placed in the floating state (high impedance state), thus allowing OR tie with another chip. When the OE signal is set to "H", the output enters the floating state. In the I/O bus mode, setting the OE signal to "H" at a write time avoids contention of I/O bus data. When the CS signal is set to Vcc, the output enters the full stand-by state to minimize supply current (See Tables 1 and 2).
Outline 48P4B
CHIP SELECT INPUT CSA 1 WRITE ENABLE INPUT WEA 2 NOT READY Not Ready A 3 OUTPUT OUTPUT ENABLE INPUT OEA 4
52
VCC 51 CSB CHIP SELECT INPUT 50 WEB WRITE ENABLE INPUT 49 Not Ready B NOT READY OUTPUT 48 OEB OUTPUT ENABLE INPUT 47 46 NC NC
NC NC A PORT ADDRESS INPUT
5 6
A0A 7 A1A 8 A2A 9 A3A 10 A4A 11 A5A 12 A6A 13 A7A 14 NC NC 15 16
45 A0B 44 A1B 43 A2B 42 A3B B PORT ADDRESS 41 A4B INPUT 40 A5B 39 A6B 38 A7B 37 36 NC NC
M66221FP
I/O0A 17 I/O1A 18 I/O2A 19 I/O3A 20 A PORT DATA I/O I/O4A 21 I/O5A 22 I/O6A 23 I/O7A 24 I/O8A 25 GND 26
35 I/O8B 34 I/O7B 33 I/O6B 32 I/O5B B PORT 31 I/O4B DATA I/O 30 I/O3B I/O2B 29 28 I/O1B 27 I/O0B NC: No Connection
Outline 52P2G-A
1
MITSUBISHI DIGITAL ASSP
M66221SP/FP
256 x 9-BIT MAIL-BOX
BLOCK DIAGRAM
VCC NOT READY OUTPUT Not Ready A WRITE ENABLE WEA INPUT CHIP SELECT CSA INPUT OUTPUT ENABLE OEA INPUT I/O0A I/O1A I/O2A I/O3A A PORT I/O4A DATA I/O I/O5A I/O6A I/O7A I/O8A A0A A1A A2A A PORT A3A ADDRESS A4A INPUT A5A A6A A7A NOT READY Not Ready B OUTPUT WRITE ENABLE WEB INPUT CHIP SELECT CSB INPUT OUTPUT ENABLE INPUT I/O0B I/O1B I/O2B I/O3B B PORT I/O4B DATA I/O I/O5B I/O6B I/O7B I/O8B OEB A0A OEA 9 I/O BUFFER I/O BUFFER WEA A7A
~
CONTROL CIRCUIT
ARBITRATION CIRCUIT
CONTROL CIRCUIT
A0B A7B WEB OEB 9
~
8
ROW/COLUMN DECODER
MEMORY ARRAY OF 256-WORDx9-BIT CONFIGURATION
ROW/COLUMN 8 DECODER
A0B A1B A2B A3B B PORT ADDRESS A4B INPUT A5B A6B A7B
GND
Table 1 Mode Settings of Ports (A0A ~ A7A A0B ~ A7B) A port input CSA H x L L x x WEA x x L H x x OEA x x x L x x CSB x H x x L L B port input WEB x x x x L H OEB x x x x x L Flag Not Ready A H H H H H H Not Ready B H H H H H H Operation A port is set to the non-select mode. B port is set to the non-select mode. A port is set to the write mode for memory. A port is set to the read mode for memory. B port is set to the write mode for memory. B port is set to the read mode for memory.
Table 2 Basic Functions of Ports CS H L L L WE x L H H OE x x L H Mode Non-select Write Read I/O pin High impedance DIN DOUT High impedance ICC Stand-by Operation Operation Operation
Note 1: x indicates "L" or "H". (Irrelevant) "H" = High level, "L" = Low level
2
MITSUBISHI DIGITAL ASSP
M66221SP/FP
256 x 9-BIT MAIL-BOX
FUNCTIONAL DESCRIPTION Arbitration Function
The M66221 has asynchronous accessibility from two independent ports to shared memory, thus remarkably improving the throughput of the entire processor system used in the multiport mode. On the other hand, this accessibility causes a problem of contending for selecting the same address in shared memory during the addressing from both ports. If the same address is contentionally selected, the following four basic operations are possible depending on an access mode set from both ports: (1) A port .......... Read B port .......... Read (2) A port .......... Read B port .......... Write (3) A port .......... Write B port .......... Read (4) A port .......... Write B port .......... Write In this case, when both ports are operating in the read mode as given in (1), correct data is read to both ports and the contents of memory are not destroyed. There is no special problem. If the other port is in the read mode while one port is operating in the write mode as given in (2) or (3), however, data is written correctly but the data read from the other port in the read mode may change during the same cycle.
This comes into question. When both ports are operating in the write mode as given in (4), reverse data is written into each port and the contents of memory may become uncertain. Consequently, no result will be guaranteed. The M66221 incorporated an arbitration function circuit to solve such problems when contentionally selecting an address from both ports. The arbitration function decides which of A and B ports determines an address first, and unconditionally assigns access priority to the first-in port (At this time, the Not Ready signal holds "H"). As for the last-in port operation, the function inhibits any write to that port from MPU at the same time when "L" is output to the Not Ready output pin at the port regardless of a read or write operation during the period of address matching of both ports. If the address of the first-in port changes after that and both ports do not have the same address, the Not Ready output is reset to "H" and the access in the stopped state is accepted from the last-in port. If the same address is selected by an address input from both ports simultaneously, a decision by the arbitration function on the chip also affords access only from one port, and outputs "L" to the Not Ready output for the other port invalidate any access from MPU. Tables 3 and 4 give the relationship between the port arbitration function and port access.
3
MITSUBISHI DIGITAL ASSP
M66221SP/FP
256 x 9-BIT MAIL-BOX
Arbitration Function and Port Access
Contention No. 1 (Address control) Table 3 gives the port access states and the Not Ready signal output states if the same address is selected in shared memory by an address Table 3 Contention Processing by Address Input Address setting when selecting same address First-in A port First-in B port First-in A port First-in B port First-in A port First-in B port First-in A port First-in B port Simultaneous A and B ports Mode setting Read Read Read Read Write Write Write Write A port Access , , , , , x , x Arbitration Resolved Not Ready A H L H L H L H L Mode setting Read Read Write Write Read Read Write Write B port Access , , x , , , x , Arbitration Resolved input set from A and B ports with CSA = CSB = "L".
CSA = CSB = "L" Not Ready B L H L H L H L H
Contention No. 2 (CS control) Table 4 gives the port access states and the Not Ready signal output states when setting the CS inputs from A and B ports valid, and Table 4 Contention Processing by CS Input CS input set when selecting same address First-in A port First-in B port First-in A port First-in B port First-in A port First-in B port First-in A port First-in B port Simultaneous A and B ports
Note 2: "H" = High level, "L" = Low level
selecting the same address in shared memory with A0A to A7A=A0B to A7B. A0A ~ A7A = A0B ~ A7B
Mode setting Read Read Read Read Write Write Write Write
A port Access , , , , , x , x Arbitration Resolved
Not Ready A H L H L H L H L
Mode setting Read Read Write Write Read Read Write Write
B port Access , , x , , , x , Arbitration Resolved
Not Ready B L H L H L H L H
4
MITSUBISHI DIGITAL ASSP
M66221SP/FP
256 x 9-BIT MAIL-BOX
ABSOLUTE MAXIMUM RATINGS (Ta = 0 ~ 70C, unless otherwise noted)
Symbol VCC VI VO Pd Tstg Parameter Supply voltage Input voltage Output voltage Maximum power dissipation Storage temperature range Conditions When defining GND pin as a reference. Ta = 25C Ratings -0.3 ~ +7.0 -0.3 ~ VCC + 0.3 0 ~ VCC 800 -65 ~ 150 Unit V V V mW C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC GND VI Topr Parameter Supply voltage Ground Input voltage Operating temperature range Min. 4.5 0 0 Limits Typ. 5.0 0 Max. 5.5 VCC 70 Unit V V V C
ELECTRICAL CHARACTERISTICS (Ta = 0 ~ 70C, Vcc=5V10%, unless otherwise noted)
Symbol VIH VIL VOH VOL VOL IIH IIL IOZH IOZL Parameter "H" input voltage "L" input voltage "H" output voltage (I/O) "L" output voltage (I/O) Open drain "L" output voltage (Not Ready) "H" input current "L" input current Off state "H" output current Off state "L" output current Test conditions Min. 2.2 -0.3 2.4 Limits Typ. Max. VCC+0.3 0.8 0.5 0.5 10.0 -10.0 10.0 -10.0 Unit V V V V V A A A A
IOH = -2mA IOL = 4mA IOL = 8mA VI = VCC VI = GND CS = VIH or OE = VIH VO = VCC CS = VIH or OE = VIH VO = GND CS < 0.2V, Another input VIN > VCC - 0.2V or VIN < 0.2V, Output pin open CSA, CSB = VIH CSA or CSB = VIH IOUT = 0mA (Active port output pin open) CSA, CSB > VCC - 0.2V Another input VIN > VCC - 0.2V or VIN < 0.2V CSA or CSB > VCC - 0.2V Another input VIN > VCC - 0.2V or VIN < 0.2V, IOUT = 0mA (Active port output pin open)
ICC ISB1 ISB2
Static current dissipation (active) Two-port stand-by One-port stand-by Stand-by current
60 5 60
mA mA mA
ISB3
Two-port full stand-by
0.1
mA
ISB4
One-port full stand-by
30
mA
CI CO
Input capacitance Output capacitance in off state
10 15
pF pF
Notes 3: The direction in which current flows into the IC is defined as positive (no sign). 4: The above typical values are standard values for VCC = 5V and Ta = 25C.
5
MITSUBISHI DIGITAL ASSP
M66221SP/FP
256 x 9-BIT MAIL-BOX
SWITCHING CHARACTERISTICS (Ta = 0 ~ 70C, Vcc = 5V10%, unless otherwise noted) Read cycle
Symbol tCR ta(A) ta(CS) ta(OE) tdis(CS) tdis(OE) ten(CS) ten(OE) tv(A) Parameter Read cycle time Address access time Chip select access time Output enable access time Output disable time after CS (Note 5) Output disable time after OE (Note 5) Output enable time after CS (Note 5) Output enable time after OE (Note 5) Data effective time after Address Min. 70 Limits Typ. Max. 70 70 35 35 35 5 5 10 Unit ns ns ns ns ns ns ns ns ns
TIMING REQUIREMENTS (Ta = 0 ~ 70C, Vcc = 5V10%, unless otherwise noted) Write cycle
Symbol tCW tw(WE) tsu(A) tsu(A-WEH) tsu(CS) tsu(D) th(D) trec(WE) tdis(WE) tdis(OE) ten(WE) Parameter Write cycle time Write pulse width Address setup time Address setup time for rise of WE Chip select setup time (for WE) Data setup time Data hold time Write recovery time Output disable time after WE (Note 5) Output disable time after OE (Note 5) Output enable time after WE (Note 5) Min. 70 45 0 65 65 40 0 0 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns
35 35 0
Note 5: The time required for the output to change from a steady state to 500mV under the load conditions shown in Fig. 2. This parameter is guaranteed but is not tested at shipment.
NOT READY TIMING (Ta = 0 ~ 70C, Vcc = 5V10%, unless otherwise noted)
Symbol tNAA tNDA tNAC tNDC tAPS tNO tNW Parameter Not Ready access time from Address Not Ready disable time from Address Not Ready access time from CS Not Ready disable time from CS Arbitration priority setup time Data output access time from Not Ready Write hold time from Not Ready Min. Limits Typ. Max. 50 50 50 50 0 65 Unit ns ns ns ns ns ns ns
15
6
MITSUBISHI DIGITAL ASSP
M66221SP/FP
256 x 9-BIT MAIL-BOX
TIMING DIAGRAM Read Cycle (WE = VIH)
Read cycle No. 1 (Address control) (CS = OE = VIL)
tCR
A0~A7 ta(A) tv(A) I/O0~I/O8 (DOUT) Previous cycle data Data output determined tv(A)
Read cycle No. 2 (CS control) tCR
A0~A7 ta(A)
CS ta(CS) ten(CS) OE ta(OE) ten(OE) I/O0~I/O8 (DOUT) High impedance Data output determined tdis(OE) tdis(CS)
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MITSUBISHI DIGITAL ASSP
M66221SP/FP
256 x 9-BIT MAIL-BOX
Write Cycle
Write cycle No. 1 (WE control) See Notes 6, 7 and 8.
tCW
A0~A7 tsu(A-WEH) tsu(CS) CS tsu(A) WE tsu(D) I/O0~I/O8 (DIN) th(D) tw(WE) trec(WE)
Data input determined
OE tdis(OE) I/O0~I/O8 (DOUT)
Write cycle No. 2 (CS control)
See Notes 6, 7 and 8. tCW
A0~A7 tsu(A-WEH) tsu(A) CS tw(WE) WE tsu(D) I/O0~I/O8 (DIN) ten(CS) I/O0~I/O8 (DOUT) tdis(WE) th(D) tsu(CS) trec(WE)
Data input determined
Notes 6: 7: 8: 9:
The WE of the port must be set to "H" when an address input changes. A write operation is performed during the overlap period when both CS and WE are "L". Do not apply any negative-phase signal from outside when an I/O pin is in output state. The shaded part means a state in which a signal can be "H" or "L".
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MITSUBISHI DIGITAL ASSP
M66221SP/FP
256 x 9-BIT MAIL-BOX
Contention Read Cycle (WE = VIH, OE = VIL)
Contention read cycle No .1 (Address control)
Address A (Address B) tAPS Address B (Address A) tNAA Not Ready B (Not Ready A)
See Notes 10 and 11.
Address matching
Address not matching
tNDA
tv(A)
tNO
I/O0B~I/O8B (I/O0A~I/O8A)
Previous cycle data ta(A) Address A = Address B
Data output determined
Contention read cycle No. 2 (CS control) Addresses A&B
See Notes 10 and 12. Address matching
CSA (CSB) tAPS CSB (CSA) tNAC Not Ready B (Not Ready A) ten(CS) I/O0B~I/O8B (I/O0A~I/O8A) ta(CS) Address A = Address B
Notes 10: The Not Ready output of the first-in port holds "H". 11: When CS is set to "L" before the address input is determined. 12: When the address input is determined before CS transition to "L".
tNDC
tNO
Data output determined
9
MITSUBISHI DIGITAL ASSP
M66221SP/FP
256 x 9-BIT MAIL-BOX
Contention Write Cycle
Contention write cycle No. 1 (WE control) See Notes 6, 8, 10 and 11.
Address A (Address B) tAPS Address B (Address A)
Address matching
tNAA tNDA
Not Ready B (Not Ready A) tsu(A-WEH) tsu(A) WEB (WEA) tw(WE)
tNW
tsu(D) I/O0B~I/O8B (I/O0A~I/O8A) (DIN) tdis(WE) I/O0B~I/O8B (I/O0A~I/O8A) (DOUT) Address A = Address B
th(D)
Data input determined ten(WE)
Contention write cycle No. 2 (CS control)
See Notes 6, 8, 10 and 12.
Addresses A&B
Address matching
CSA (CSB) tAPS CSB (CSA) tNAC Not Ready B (Not Ready A) tsu(CS) tw(WE) WEB (WEA) tsu(D) I/O0B~I/O8B (I/O0A~I/O8A) (DIN) th(D) tNDC
tNW
Data input determined ten(CS) tdis(WE) ten(WE)
I/O0B~I/O8B (I/O0A~I/O8A) (DOUT)
Address A = Address B
10
MITSUBISHI DIGITAL ASSP
M66221SP/FP
256 x 9-BIT MAIL-BOX
SWITCHING CHARACTERISTICS MEASUREMENT CIRCUIT
Input pulse level Input pulse rise/fall time Input timing reference voltage Output timing decision voltage Output load : VIH = 3.0V, VIL = 0V : tr/tf = 5ns : 1.5V : 1.5V : Figure 1 ~ 3 (The capacitance includes stray wiring capacitance and the probe input capacitance.)
+ 5V + 5V + 5V
1250 I/O I/O
1250 Not Ready
575
775
100pF
775
5pF
50pF
Fig 1. I/O Output Load
Fig 2. I/O Output Load (to ten, tdis)
Fig 3. Not Ready Output Load
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