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MK74CG117A
16 Output Low Skew Clock Generator
Description
The MK74CG117A is a monolithic CMOS high-speed, low-skew clock driver that includes an on-chip PLL. Ideal for communications and other systems that require a large number of high-speed clocks, the unique combination of PLL and 16 low-skew outputs can eliminate oscillators and low-skew buffers from systems. The device has a number of built-in multipliers, making it possible to run from one inexpensive, low-frequency crystal, and produce high-frequency clock outputs. Another selection allows the chip to run as a divider, dividing the input clock by two (or 4 using the mode select). The device also has a buffered reference output, allowing multiple devices to be easily driven from one clock source.
Features
* 48-pin SSOP (300 mil) package * On-chip PLL generates output clocks up to 90 MHz
from a simple crystal or clock input
* 16 low-skew outputs * Output skew less than 350 ps on rising edges * Ability to configure as
- 16 clocks at full-frequency - 12 at full and 4 at half-frequency - 8 at full and 8 at half-frequency
* Tri-state mode for Output Enable function * 3.3 V 5% supply voltage
Block Diagram
VDD 9 S2:0 M1:0 3 2 Clock Synthesis and Mode Select Circuitry Clock 1 Clock 2
Crystal or clock input
X1/ICLK Crystal Ocsillator X2
Clock 16 REF
The crystal requires external capacitors for accurate tuning of the clock
10 GND
MDS 74CG117A D Integrated Circuit Systems, Inc.
1
525 Race Street, San Jose, CA 95126 tel (408) 297-1201
Revision 051304
www.icst.com
MK74CG117A 16 Output Low Skew Clock Generator
Pin Assignment
VDD X1/ICLK X2 NC NC GND GND S2 REF S1 GND GND CLK1 CLK2 VDD VDD CLK3 CLK4 GND GND NC CLK5 CLK6 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 S0 CLK16 VDD VDD NC CLK15 CLK14 GND GND M1 CLK13 CLK12 VDD VDD M0 CLK11 CLK10 CLK9 VDD NC GND GND CLK8 CLK7
48-pin (300 mil) SSOP
MDS 74CG117A D Integrated Circuit Systems, Inc.
2
525 Race Street, San Jose, CA 95126 tel (408) 297-1201
Revision 051304
www.icst.com
MK74CG117A 16 Output Low Skew Clock Generator
Pin Descriptions
Pin Number Pin Name Pin Type Pin Description
1, 15, 16, 24, 30, 35, 36, 45, 46 2 3 4, 5, 21, 29, 44 6, 7, 11, 12, 19, 20, 27, 28, 40, 41 8, 10, 48 9 13, 14, 17, 18 22, 23, 25, 26, 31, 32, 33, 37 34, 39 38, 42, 43, 47
VDD X1/ICLK X2 NC GND S2, S1, S0 REF CLK1 - 4 CLK5 - 12 M0, M1 CLK13 - 16
Power XI XO -- Power Input Output Output Output Input Output
Connect to VDD. Connect to a crystal input or clock. Connect to a crystal or leave unconnected for clock input. No connect. Nothing is connected to these pins. Connect to ground. Multiplier select pins. See table 2. Crystal oscillator buffered reference clock output. Clock 1-4. Can be either full or half-speed per Table 1. Clock outputs 5-12. At full (1x) speed unless tri-stated per Table 1. Mode Select pins. Selects tri-state or speed of outputs per Table 1. Clock 13-16. Can be either full or half-speed per Table 1. 3) An optimum layout is one with all components on the same side of the board, thus minimizing vias through other signal layers. Other signal traces should be routed away from the MK74CG117A device. This includes signal traces located underneath the device, or on layers adjacent to the ground plane layer used by the device.
External Components
The MK74CG117A requires a minimum number of external components for proper operation.
Decoupling Capacitor
A decoupling capacitor of 0.1F must be connected between each VDD and GND. Connect the capacitor as close to these pins as possible. For optimum device performance, mount the decoupling capacitor on the component side of the PCB. Avoid the use of vias in the decoupling circuit.
Crystal Information
The crystal used should be a fundamental mode (do not use third overtone), parallel resonant crystal. The oscillator has internal caps that provide the proper load for a crystal with CL = 18 pF. The value of these capacitors is given by the following equation: Crystal caps (pF) = (CL - 18) x 2
PCB Layout Recommendations
For optimum device performance and lowest output phase noise, observe the following guidelines: 1) Mount the 0.01F decoupling capacitor on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitor and VDD pin. The PCB trace to the VDD pin and the PCB trace to the ground via should be kept as short as possible. 2) To minimize EMI, place the 33 series-termination resistor (if needed) close to the clock output.
MDS 74CG117A D Integrated Circuit Systems, Inc.
3
525 Race Street, San Jose, CA 95126 tel (408) 297-1201
Revision 051304
www.icst.com
MK74CG117A 16 Output Low Skew Clock Generator
Power Dissipation, Termination, and Operating Frequency
As with all clock drivers, the power dissipated by the MK74CG117A is affected by the external loading on the output pins. This consists of the capacitance of the load that is being driven, as well as the PC board trace itself. Since this capacitance must be charged and discharged with each cycle of the output clock, as the frequency goes up, so does the power required. Operating below the specified maximum output clock frequency shown in Table 2 will keep the MK74CG117A power dissipation within acceptable limits. External series termination resistors must be used in series with each output. These resistors serve two purposes: The first is to match the source impedance to the line (PC board trace) that is being driven. This will minimize reflections that cause non-linear transitions on the output clock waveform. The output impedance of the MK74CG117A is approximately 20; assuming a 50 line, then a 33 resistor should be used at each output as shown in Figure 1.
Table 2. Multiplier Selections (Input and CLK Frequencies in MHz)
S2 S1 S0 0 0 0 Input 33-55 Multiplier 0.5 CLK Out 16.5-25 Comments Divider only; no PLL PLL PLL PLL PLL PLL PLL PLL
0 0 0 1 1 1 1
0 1 1 0 0 1 1
1 0 1 0 1 0 1
20-50 16-40 10-50 8-40 8-30 8-25 8-20
1 1.25 2 2.5 3.333 4 5
20-50 20-50 20-90 20-90 26.7-90 32-90 40-10
Figure 1. External Termination
33 ohm
MK74CG117 Output
To load
Table 1. Tri-state and Mode Select
M1 M0 Mode at CLK(1x) Z at CLK/2(0.5x) Z Max Output Freq.
0
0
All outputs, including REF, tri-stated 12 @ 1x, 4 @ 0.5x 8 @ 1x, 8 @ 0.5x 16 outputs @ 1x
As speeds rise, the limiting factor in device operation becomes the power generated by having a large number of drivers in one package. Using the external termination resistors reduces the power dissipated within the device, allowing output frequencies up to 100 MHz. Note that the maximum operating frequency of the MK74CG117A is determined by the Mode selected from Table 1 and the Multiplier selected from Table 2. For output frequencies above 83.3 MHz, all 16 outputs must be at the same frequency (M1=M0=1). When operating with a combination of 1X and 0.5X outputs, the output frequency cannot exceed 83.3 MHz.
0 1 1
1 0 1
CLK1-12 CLK5-12 CLK1-16
CLK13-16 CLK1-4, 13-16 None
83.3 MHz 0.8 83.3 MHz 1.25 90 MHz
MDS 74CG117A D Integrated Circuit Systems, Inc.
4
525 Race Street, San Jose, CA 95126 tel (408) 297-1201
Revision 051304
www.icst.com
MK74CG117A 16 Output Low Skew Clock Generator
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK74CG117A. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device, at these or any other conditions, above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD (referenced to GND) All Inputs and Outputs (referenced to GND) Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature 7V
Rating
0.5 V to VDD+0.5 V 0 to +70C -65 to +150C 125C 260C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured in respect to GND)
Min.
0 +3.14
Typ.
Max.
+70 3.47
Units
C V
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature 0 to +70C
Parameter
Operating Voltage Supply Current (at 50 MHz) Input High Voltage, ICLK Input Low Voltage, ICLK Output High Voltage Output High Voltage Output Low Voltage, 3.3 V Short Circuit Current Input Capacitance
Symbol
VDD IDD VIH VIL VOH VOH VOL No load pin 2 pin 2
Conditions
Min.
3.14
Typ.
3.3 63
Max.
3.47
Units
V mA V
VDD-1
VDD/2 VDD/2 1
V V V
IOH = -8 mA IOH = -12 mA IOL = 12 mA Each output
VDD-0.4 2.0 0.4 35 7 6
V mA pF
CIN
S0, S1, FRSEL pins
MDS 74CG117A D Integrated Circuit Systems, Inc.
5
525 Race Street, San Jose, CA 95126 tel (408) 297-1201
Revision 051304
www.icst.com
MK74CG117A 16 Output Low Skew Clock Generator
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature 0 to +70 C, CL = 15 pF
Parameter
Input Clock Frequency Input Crystal Frequency Output Clock Frequency (see tables 1, 2) Output Clock Duty Cycle Output Clock Rising Edge Skew Absolute Clock Period Jitter, except REF Absolute Clock Period Jitter, REF Output Clock Rise Time Output Clock Fall Time Maximum Load per Total of 16 Outputs, with 33 termination, Note 3
Symbol
Conditions
See table 2 Except when S2=S1=1 M1=M0=1 At VDD/2 VDD=3.3 V, Note 2 VDD=3.3 V VDD=3.3 V
Min.
8
Typ.
Max. Units
20 90 MHz MHz % ps ps ps 2 2 240 320 ns ns pF pF
45
50 200 300 500 1.5 1.5
55 350
tR tF
0.8 to 2.0 V, Note 1 2.0 V to 0.8 V, Note 1 100 MHz output clock 83.3 MHz output clock
Note 1: Based upon characterization data with a 33 series termination resistor and 15 pF capacitor to ground. Note 2: Between any two outputs with equal loading. Note 3: Additional load may be driven with the addition of an external heat sink. Contact ICS for details.
Thermal Characteristics for 48-pin SSOP
Parameter
Thermal Resistance Junction to Ambient
Symbol
JA JA JA
Conditions
Still air 1 m/s air flow 3 m/s air flow
Min.
Typ.
80 67 54 45
Max. Units
C/W C/W C/W C/W
Thermal Resistance Junction to Case
JC
MDS 74CG117A D Integrated Circuit Systems, Inc.
6
525 Race Street, San Jose, CA 95126 tel (408) 297-1201
Revision 051304
www.icst.com
MK74CG117A 16 Output Low Skew Clock Generator
Package Outline and Package Dimensions (48-pin SSOP, 300 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
48
Millimeters Symbol
E1 E
Inches Min Max
Min
Max
INDEX AREA
12 D
A A1 b c D E E1 e h L
2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 15.75 16.00 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 0 8
.095 .110 .008 .016 .008 .0135 .005 .010 .620 .630 .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 0 8
A2 A1
A c
- Ce
b SEATING PLANE
aaa C
L
Ordering Information
Part / Order Number
MK74CG117AF MK74CG117AFT
Marking
MK74CG117A MK74CG117A
Shipping Packaging
Tubes Tape and Reel
Package
48-pin SSOP 48-pin SSOP
Temperature
0 to +70 C 0 to +70 C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Inc. (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 74CG117A D Integrated Circuit Systems, Inc.
7
525 Race Street, San Jose, CA 95126 tel (408) 297-1201
Revision 051304
www.icst.com

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