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IS61LV6416 IS61LV6416L
64K x 16 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY
FEATURES
* High-speed access time: 8, 10, 12 ns * CMOS low power operation -- 61LV6416: 75 mW (typical) operating current 0.5 mW (typical) standby current -- 61LV6416L: 65 mW (typical) operating current 50 W (typical) standby current * TTL compatible interface levels * Single 3.3V power supply * Fully static operation: no clock or refresh required * Three state outputs * Data control for upper and lower bytes * Industrial temperature available
ISSI
OCTOBER 2003
(R)
DESCRIPTION The ISSI IS61LV6416/IS61LV6416L is a high-speed,
1,048,576-bit static RAM organized as 65,536 words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 8 ns with low power consumption. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61LV6416/IS61LV6416L is packaged in the JEDEC standard 44-pin 400-mil SOJ, 44-pin TSOP-II, and 48-pin mini BGA (6mm x 8mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A15
DECODER
64K x 16 MEMORY ARRAY
VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT
COLUMN I/O
CE OE WE UB LB CONTROL CIRCUIT
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc.
Rev. C 10/14/03
1
IS61LV6416 IS61LV6416L
PIN CONFIGURATIONS 44-Pin SOJ (K) 44-Pin TSOP-II (T)
A15 A14 A13 A12 A11 CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A10 A9 A8 A7 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
ISSI
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A0 A1 A2 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A3 A4 A5 A6 NC
(R)
A15 A14 A13 A12 A11 CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A10 A9 A8 A7 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A0 A1 A2 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A3 A4 A5 A6 NC
48-Pin mini BGA (6mm x 8mm) (B)
1 2 3 4 5 6
PIN DESCRIPTIONS
A0-A15 I/O0-I/O15 CE OE WE LB UB NC VDD GND Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground
A B C D E F G H
LB I/O8 I/O9 GND VDD I/O14 I/O15 NC
OE UB I/O10 I/O11 I/O12 I/O13 NC A8
A0 A3 A5 NC NC A14 A12 A9
A1 A4 A6 A7 NC A15 A13 A10
A2 CE I/O1 I/O3 I/O4 I/O5 WE A11
NC I/O0 I/O2 VDD GND I/O6 I/O7 NC
2
Integrated Silicon Solution, Inc.
Rev. C 10/14/03
IS61LV6416 IS61LV6416L
TRUTH TABLE
Mode Not Selected Output Disabled Read WE X H X H H H L L L CE H L L L L L L L L OE X H X L L L X X X LB X X H L H L L H L UB X X H H L L H L L I/O PIN I/O0-I/O7 I/O8-I/O15 High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN
ISSI
VDD Current ISB1, ISB2 ICC ICC
(R)
1 2 3 4
Write
ICC
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM TSTG PT IOUT Parameter Terminal Voltage with Respect to GND Storage Temperature Power Dissipation DC Output Current (LOW) Value -0.5 to VDD+0.5 -65 to +150 1.5 20 Unit V C W mA
5 6 7
VDD (12 ns) 3.3V 10% 3.3V 10%
Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING RANGE
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VDD (8,10 ns) 3.3V+10%,-5% 3.3V+10%,-5%
8 9 10
Max. -- 0.4 VDD + 0.3 0.8 2 2 Unit V V V V A A
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage GND VIN VDD GND VOUT VDD, Outputs Disabled Test Conditions VDD = Min., IOH = -4.0 mA VDD = Min., IOL = 8.0 mA Min. 2.4 -- 2 -0.3 -2 -2
11 12
Notes: 1. VIL (min.) = -2.0V for pulse width less than 10 ns.
Integrated Silicon Solution, Inc.
Rev. C 10/14/03
3
IS61LV6416 IS61LV6416L
IS61LV6416 POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter ICC VDD Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VDD = Max., IOUT = 0 mA, f = fMAX VDD = Max., VIN = VIH or VIL CE VIH , f = 0 VDD = Max., CE VDD - 0.2V, VIN VDD - 0.2V, or VIN 0.2V, f = 0 Com. Ind. typ.(2) Com. Ind. Com. Ind. typ.(2) -8 ns Min. Max. -- -- -- -- -- -- -- -- 140 150 105 15 20 5 10 0.5 -10 ns Min. Max. -- -- -- -- -- -- -- -- 120 130 95 15 20 5 10 0.5
ISSI
-12 ns Min. Max. -- -- -- -- -- -- -- -- 100 110 75 15 20 5 10 0.5
(R)
Unit mA
ISB1
mA
ISB2
mA
Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD=3.3V, TA=25oC. Not 100% Tested.
IS61LV6416L POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter ICC VDD Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VDD = Max., IOUT = 0 mA, f = fMAX VDD = Max., VIN = VIH or VIL CE VIH , f = 0 VDD = Max., CE VDD - 0.2V, VIN VDD - 0.2V, or VIN 0.2V, f = 0 Com. Ind. typ.(2) Com. Ind. Com. Ind. typ.(2) -8 ns Min. Max. -- -- -- -- -- -- -- -- 100 110 75 15 20 1 1.5 0.05 -10 ns Min. Max. -- -- -- -- -- -- -- -- 95 105 70 15 20 1 1.5 0.05 Unit mA
ISB1
mA
ISB2
mA
Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD=3.3V, TA=25oC. Not 100% Tested.
CAPACITANCE(1)
Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF
Note: 1. Tested initially and after any design or process changes that may affect these parameters.
4
Integrated Silicon Solution, Inc.
Rev. C 10/14/03
IS61LV6416 IS61LV6416L
AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1a and 1b
ISSI
(R)
1 2 3
319 3.3V
AC TEST LOADS
319 3.3V
4
5 pF Including jig and scope 353
OUTPUT 30 pF Including jig and scope 353
OUTPUT
5 6 7
Figure 1a.
Figure 1b.
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time
(2)
-8 ns Min. Max. 8 -- 3 -- -- -- 0 0 3 -- 0 0 -- 8 -- 8 5 5 -- 4 -- 6 4 --
-10 ns Min. Max. 10 -- 3 -- -- -- 0 0 3 -- 0 0 -- 10 -- 10 5 5 -- 5 -- 6 5 --
-12 ns Min. Max. 12 -- 3 -- -- -- 0 0 3 -- 0 0 -- 12 -- 12 6 6 -- 6 -- 6 6 --
Unit ns ns ns ns ns ns ns ns ns ns ns ns
tRC tAA tOHA tACE tDOE tHZOE tLZOE(2) tHZCE(2 tLZCE tBA tHZB tLZB
(2)
8 9 10 11 12
OE to High-Z Output OE to Low-Z Output CE to High-Z Output CE to Low-Z Output LB, UB Access Time LB, UB to High-Z Output LB, UB to Low-Z Output
Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested.
Integrated Silicon Solution, Inc.
Rev. C 10/14/03
5
IS61LV6416 IS61LV6416L
AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CS = OE = VIL, UB or LB = VIL)
t RC
ADDRESS
ISSI
(R)
t AA t OHA
DOUT
PREVIOUS DATA VALID
t OHA
DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3)
tRC
ADDRESS
tAA tOHA
OE
tDOE tHZOE
CE
tLZCE
tLZOE tACE tHZCE
LB, UB
tBA tHZB
DATA VALID
DOUT
HIGH-Z
tLZB
Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transition.
6
Integrated Silicon Solution, Inc.
Rev. C 10/14/03
IS61LV6416 IS61LV6416L
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width (OE = HIGH/LOW) Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output
(2)
ISSI
-8 ns Min. Max. 8 6 8 0 0 7 6 6 0 -- 3 -- -- -- -- -- -- -- -- -- 4 -- -10 ns Min. Max. 10 8 8 0 0 8 8 6 0 -- 3 -- -- -- -- -- -- -- -- -- 5 -- -12 ns Min. Max. 12 9 9 0 0 9 9 6 0 -- 3 -- -- -- -- -- -- -- -- -- 6 -- Unit ns ns ns ns ns ns ns ns ns ns ns
(R)
tWC tSCE tAW tHA tSA tPBW tPWE1/tPWE2 tSD tHD tHZWE(2) tLZWE
1 2 3 4 5 6 7 8 9 10 11 12
Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
Integrated Silicon Solution, Inc.
Rev. C 10/14/03
7
IS61LV6416 IS61LV6416L
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
ISSI
t WC
(R)
ADDRESS
VALID ADDRESS
t SA
CE
t SCE
t HA
WE
t AW t PWE1 t PWE2 t PBW
UB, LB
t HZWE
DOUT
DATA UNDEFINED
HIGH-Z
t LZWE
t SD
DIN
t HD
DATAIN VALID
UB_CEWR1.eps
8
Integrated Silicon Solution, Inc.
Rev. C 10/14/03
IS61LV6416 IS61LV6416L
WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle)
t WC
ADDRESS
VALID ADDRESS
ISSI
t HA
(R)
1 2
OE
CE
LOW
t AW t PWE1
WE
3 4
t LZWE
HIGH-Z
t SA
UB, LB
t PBW
t HZWE
DOUT
DATA UNDEFINED
5
t HD
t SD
DIN
DATAIN VALID
UB_CEWR2.eps
6 7 8
t HA
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t WC
ADDRESS OE CE
VALID ADDRESS
LOW
9
LOW
t AW t PWE2
WE
10
t LZWE
t SA
UB, LB
t PBW
t HZWE
DOUT
DATA UNDEFINED
HIGH-Z
11 12
UB_CEWR3.eps
t SD
DIN
t HD
DATAIN VALID
Integrated Silicon Solution, Inc.
Rev. C 10/14/03
9
IS61LV6416 IS61LV6416L
WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write)(1,3)
t WC
ADDRESS
ADDRESS 1
ISSI
t WC
ADDRESS 2
(R)
OE
t SA
CE
LOW
WE
t HA t SA t PBW t PBW
WORD 2
t HA
UB, LB
WORD 1
t HZWE
DOUT
HIGH-Z
t LZWE t HD
DATAIN VALID
DATA UNDEFINED
t SD
DIN
t SD
DATAIN VALID
t HD
UB_CEWR4.eps
Notes: 1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is referenced to the rising or falling edge of the signal that terminates the Write. 2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state. 3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
10
Integrated Silicon Solution, Inc.
Rev. C 10/14/03
IS61LV6416 IS61LV6416L
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter VDD for Data Retention Data Retention Current Data Retention Setup Time Recovery Time Test Condition See Data Retention Waveform VDD = 2.0V, CE VDD - 0.2V See Data Retention Waveform See Data Retention Waveform
O
ISSI
Options IS61LV6416 IS61LV6416L Min. 2.0 -- -- 0 Typ.(1) -- 0.5 0.05 -- -- Max. 3.6 10 1.5 -- -- Unit V mA ns ns
(R)
VDR
IDR
1 2 3 4
tSDR tRDR
tRC
Note 1: Typical values are measured at VDD = 3.0V, TA = 25 C and not 100% tested.
DATA RETENTION WAVEFORM (CE Controlled)
5
tSDR VDD Data Retention Mode tRDR
6 7
CE VDD - 0.2V
VDR
CE GND
8 9 10 11 12
Integrated Silicon Solution, Inc.
Rev. C 10/14/03
11
IS61LV6416 IS61LV6416L
IS61LV6416 ORDERING INFORMATION
Speed (ns) 8 8 8 10 10 10 10 10 10 12 12 12 12 12 12 Order Part No. IS61LV6416-8T IS61LV6416-8BI IS61LV6416-8TI IS61LV6416-10T IS61LV6416-10B IS61LV6416-10K IS61LV6416-10BI IS61LV6416-10TI IS61LV6416-10KI IS61LV6416-12B IS61LV6416-12T IS61LV6416-12K IS61LV6416-12BI IS61LV6416-12TI IS61LV6416-12KI Package Plastic TSOP mini BGA (6mm x 8mm) Plastic TSOP Plastic TSOP mini BGA (6mm x 8mm) 400-mil Plastic SOJ mini BGA (6mm x 8mm) Plastic TSOP 400-mil Plastic SOJ mini BGA (6mm x 8mm) Plastic TSOP 400-mil Plastic SOJ mini BGA (6mm x 8mm) Plastic TSOP 400-mil Plastic SOJ Temperature Range
ISSI
Commercial (0C to +70C ) Industrial (-40C to +85C ) Industrial (-40C to +85C ) Commercial (0C to +70C ) Commercial (0C to +70C ) Commercial (0C to +70C ) Industrial (-40C to +85C ) Industrial (-40C to +85C ) Industrial (-40C to +85C ) Commercial (0C to +70C ) Commercial (0C to +70C ) Commercial (0C to +70C ) Industrial (-40C to +85C ) Industrial (-40C to +85C ) Industrial (-40C to +85C )
(R)
IS61LV6416L ORDERING INFORMATION
Speed (ns) 8 8 8 8 10 10 10 10 Order Part No. IS61LV6416L-8T IS61LV6416L-8BI IS61LV6416L-8TI IS61LV6416L-8KI IS61LV6416L-10T IS61LV6416L-10BI IS61LV6416L-10TI IS61LV6416L-10KI Package Plastic TSOP mini BGA (6mm x 8mm) Plastic TSOP 400-mil Plastic SOJ Plastic TSOP mini BGA (6mm x 8mm) Plastic TSOP 400-mil Plastic SOJ Temperature Range Commercial (0C to +70C ) Industrial (-40C to +85C ) Industrial (-40C to +85C ) Industrial (-40C to +85C ) Commercial (0C to +70C ) Industrial (-40C to +85C ) Industrial (-40C to +85C ) Industrial (-40C to +85C )
12
Integrated Silicon Solution, Inc.
Rev. C 10/14/03
PACKAGING INFORMATION
Mini Ball Grid Array Package Code: B (48-pin)
Top View 1 2 3 4 56 6
ISSI
Bottom View
b (48x)
(R)
5
4
3
2
1
A B C D D E F G H D1
e
A B C D E F G H
e E E1
A2 SEATING PLANE A1
A
Notes: 1. Controlling dimensions are in millimeters.
mBGA - 6mm x 8mm
MILLIMETERS Sym.
N0. Leads A A1 A2 D D1 E E1 e b -- 0.24 0.60 7.90 5.90
mBGA - 8mm x 10mm
INCHES Min. Typ. Max. Sym.
N0. Leads
MILLIMETER Min. Typ. Max.
48 -- 0.24 0.60 9.90 7.90 -- -- -- -- -- 1.20 0.30 -- 10.10 8.10 --
INCHES Min. Typ. Max.
Min. Typ. Max.
48 -- -- -- -- -- 1.20 0.30 -- 8.10 6.10
-- 0.009 0.024 0.311 0.232
-- -- -- -- --
0.047 0.012 -- 0.319 0.240
A A1 A2 D D1 E E1 e b
-- -- -- -- --
0.047 0.012 -- 0.398 0.319
0.009 0.024 0.390 0.311
5.25 BSC 3.75 BSC 0.75 BSC 0.30 0.35 0.40
0.207 BSC 0.148 BSC 0.030 BSC 0.012 0.014 0.016
5.25 BSC 3.75 BSC 0.75 BSC 0.30 0.35 0.40
0.207 BSC 0.148 BSC 0.030 BSC 0.012 0.014 0.016
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. D 01/15/03
PACKAGING INFORMATION
K-400 mil SOJ PACKAGE OUTLINE
ISSI
Notes: 1. Controlling dimension: millimeters. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Reference document: JEDEC MS-027.
(R)
N
N/2+1
E1
E
1
N/2
D A
SEATING PLANE
b
C A2
e
B
A1
E2
400-mil Plastic SOIC (J-bend) (K)
Ref. Std. 28 No. Leads (N) inch mm Symbol Min Max Min Max A 0.128 0.148 3.250 3.750 A1 A2 B b C D E E1 E2 e 0.025 0.082 0.015 0.026 0.007 0.720 0.435 0.395 -- -- 0.020 0.032 0.013 0.730 0.445 0.405 0.635 2.080 0.380 0.660 0.180 18.29 11.05 10.03 -- -- 0.510 0.810 0.330 18.54 11.30 10.29 MS-027 32 inch Min Max 0.128 1.048 0.025 0.082 0.015 0.026 0.007 0.820 0.435 0.395 -- -- 0.020 0.032 0.013 0.830 0.445 0.405 mm Min Max 3.250 3.750 0.635 2.080 0.380 0.660 0.180 20.82 11.05 10.03 -- -- 0.510 0.810 0.330 21.08 11.30 10.29 inch Min Max 0.128 1.048 0.025 0.082 0.015 0.026 0.007 0.920 0.435 0.395 -- -- 0.020 0.032 0.013 0.930 0.445 0.405 36 mm Min Max 3.250 3.750 0.635 2.080 0.380 0.660 0.180 23.37 11.05 10.03 -- -- 0.510 0.810 0.330 23.62 11.30 10.29
0.370 BSC 0.050 BSC
9.40 BSC 1.27 BSC
0.370 BSC 0.050 BSC
9.40 BSC 1.27 BSC
0.370 BSC 0.050 BSC
9.40 BSC 1.27 BSC
Copyright (c) 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. E 10/03/02
PACKAGING INFORMATION
ISSI
MS-027 42 inch M in Max 0.128 1.048 0.025 0.082 0.015 0.026 0.007 1.070 0.435 0.395 -- -- 0.020 0.032 0.013 1.080 0.445 0.405 mm Min Max 3.250 3.750 0.635 2.080 0.380 0.660 0.180 27.18 11.05 10.03 -- -- 0.510 0.810 0.330 27.43 11.30 10.29 inch M in Max 0.128 1.048 0.025 0.082 0.015 0.026 0.007 1.120 0.435 0.395 -- -- 0.020 0.032 0.013 1.130 0.445 0.405 44
(R)
400-mil Plastic SOIC (J-bend) (K)
Ref. Std. 40 No. Leads (N) inch mm Sym bol Min M ax Min Max A 0.128 0.148 3.250 3.750 A1 A2 B b C D E E1 E2 e 0.025 0.082 0.015 0.026 0.007 1.020 0.435 0.395 -- -- 0.020 0.032 0.013 1.030 0.445 0.405 0.635 2.080 0.380 0.660 0.180 25.91 11.05 10.03 -- -- 0.510 0.810 0.330 26.16 11.30 10.29
mm Min Max 3.250 3.750 0.635 2.080 0.380 0.660 0.180 28.45 11.05 10.03 -- -- 0.510 0.810 0.330 28.70 11.30 10.29
0.370 BSC 0.050 BSC
9.40 BSC 1.27 BSC
0.370 BSC 0.050 BSC
9.40 BSC 1.27 BSC
0.370 BSC 0.050 BSC
9.40 BSC 1.27 BSC
Copyright (c) 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
2
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. E 10/03/02
PACKAGING INFORMATION
Plastic TSOP Package Code: T (Type II)
ISSI
Notes: 1. Controlling dimension: millimieters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane.
(R)
N
N/2+1
E1
E
1 D
N/2
SEATING PLANE
ZD
A
.
e b L A1 C
Symbol Ref. Std. No. Leads A A1 b C D E1 E e L ZD
Millimeters Min Max
Inches Min Max
Plastic TSOP (T - Type II) Millimeters Inches Min Max Min Max 44 -- 1.20 -- 0.047 0.05 0.15 0.002 0.006 0.30 0.45 0.012 0.018 0.12 0.21 0.005 0.008 18.31 18.52 0.721 0.729 10.03 10.29 0.395 0.405 11.56 11.96 0.455 0.471 0.80 BSC 0.032 BSC 0.41 0.60 0.016 0.024 0.81 REF 0.032 REF 0 5 0 5
Millimeters Min Max 50 -- 1.20 0.05 0.15 0.30 0.45 0.12 0.21 20.82 21.08 10.03 10.29 11.56 11.96 0.80 BSC 0.40 0.60 0.88 REF 0 5
Inches Min Max
(N) 32 -- 1.20 -- 0.047 0.05 0.15 0.002 0.006 0.30 0.52 0.012 0.020 0.12 0.21 0.005 0.008 20.82 21.08 0.820 0.830 10.03 10.29 0.391 0.400 11.56 11.96 0.451 0.466 1.27 BSC 0.050 BSC 0.40 0.60 0.016 0.024 0.95 REF 0.037 REF 0 5 0 5
-- 0.047 0.002 0.006 0.012 0.018 0.005 0.008 0.820 0.830 0.395 0.405 0.455 0.471 0.031 BSC 0.016 0.024 0.035 REF 0 5
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. F 06/18/03

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