View NGSF3443VT3_289003.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

NGSF3443V
Advance Information
Preferred Device
Low rDS(on) TMOS Single P-Channel Field Effect Transistors
MiniMOS devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives.
http://onsemi.com
* Ultra Low On-Resistance Provides Higher Efficiency and Extends * * * * * *
Battery Life Logic Level Gate Drive - Can Be Driven by Logic ICs Withstand High Energy in Avalanche and Commutation Modes Diode Characterized for Use in Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Avalanche Energy Specified
SINGLE TMOS POWER MOSFET 4.4 AMPERES 20 VOLTS RDS(on) = 0.065
1256 DRAIN
MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Negative sign for P-Channel devices omitted for clarity
Rating Drain-Source Voltage Drain-Gate Voltage (RGS = 1.0 M) Gate-Source Voltage -- Continuous Thermal Resistance, Junction-to-Ambient Total Power Dissipation Derate above 25C Drain -- Continuous -- Continuous @ 70C -- Pulsed Drain Current(1) Operating and Storage Temperature Range Symbol VDSS VDGR VGS RJA PD ID ID IDM TJ, Tstg Value 20 20 Unit Vdc Vdc Vdc C/W
TM
3 GATE SOURCE 4
"12
62.5 2.0 20 4.4 3.5 20 - 55 to 150
6 1
5
4
Watts mW/C Adc
2
3
TSOP 6 CASE 318G STYLE 1
C
Single Drain-to-Source Avalanche EAS 75 mJ Energy -- Starting TJ = 25C (VDD = 20 V, VGS = 4.5 Vdc, IL = 10 A, L = 1.5 mH, RG = 25 ) (1) Repetitive rating: pulse width limited by maximum junction temperature.
ORDERING INFORMATION
Device Package Shipping 7" Reel 8mm embossed tape 3000 Tape & Reel 13" Reel 8mm embossed tape 10000 Tape & Reel
NGSF3443VT1
TSOP 6
NGSF3443VT3
TSOP 6
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Preferred devices are recommended choices for future use and best overall value.
(c) Semiconductor Components Industries, LLC, 1999
1
December, 1999 - Rev. 1
Publication Order Number: NGSF3443V/D
NGSF3443V
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Collector Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ =70C) Gate-Body Leakage Current (VGS = 12 Vdc, VDS = 0) ON CHARACTERISTICS (1) Gate Threshold Voltage (ID = 250 A, VDS = VGS) Temperature Coefficient (Negative) On-State Drain Current (VDS = 5.0 Vdc, VGS = 4.5 Vdc) Static Drain-to-Source On-Resistance (VGS = 4.5 Vdc, ID = 4.4 Adc) (VGS = 2.7 Vdc, ID = 3.7 Adc) (VGS = 2.5 Vdc, ID = 3.5 Adc) Forward Transconductance (VDS = 10 Vdc, ID = 4.4 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge ( (VDS = 10 Vdc, ID = 4.4 Adc, VGS = 4.5 Vdc) (VDD = 10 Vdc, ID = 1.0 Adc, VGS = 4 5 Vdc, 4.5 Vdc RG = 6.0 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 1.7 Adc, VGS = 0 Vdc) (IS = 1.7 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 2.1 Adc, VGS = 0 Vdc 2 1 Adc Vdc, diS/dt = 100 A/s) Reverse Recovery Stored Charge (1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%. (2) Switching characteristics are independent of operating junction temperature. trr ta tb QRR VSD -- -- -- -- -- -- 0.93 0.87 27.5 11.3 16.2 0.0156 1.2 -- 80 -- -- -- C ns Vdc -- -- -- -- -- -- -- -- 9.2 20.3 29.4 37.3 8.1 1.4 2.6 2.7 50 60 100 80 15 -- -- -- nC ns (VDS = 16 Vdc, VGS = 0 Vdc, Vd Vd f = 1.0 MHz) Ciss Coss Crss -- -- -- 485 190 70 680 270 100 pF VGS(th) 0.6 -- IDS(on) RDS(on) -- -- -- gFS -- 56 73 78 11 65 90 100 -- Mhos 15 -- 2.4 -- -- -- -- Vdc mV/C Adc mW V(BR)DSS 20 -- IDSS -- -- IGSS -- -- -- -- 1.0 5.0 100 nAdc -- 10.9 -- -- Vdc mV/C Adc Symbol Min Typ Max Unit
http://onsemi.com
2
NGSF3443V
TYPICAL ELECTRICAL CHARACTERISTICS
7 ID, DRAIN CURRENT (AMPS) 6 5 4 3 2 1 0 0 0.4 0.8 1.2 1.6 2.0 10 V 4.5 V 2.5 V 2.1 V VGS = 10 V thru 1.5 V TJ = 25C 1.9 V 1.8 V 1.7 V 1.6 V 1.5 V ID, DRAIN CURRENT (AMPS) 7 6 5 4 3 2 1 0 0 1 2 3 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) TJ = 100C 25C - 55C VDS 10 V
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 1. On-Region Characteristics
R DS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.1
TJ = 25C ID = 3.5A
0.1 TJ = 25C 0.08 15 V VGS = 10 V
0.08
0.06
0.06
0.04
0.04
0.02
0.02
0
0
2.0
4.0
6.0
8.0
10
0
0
1
2
3
4
5
6
7
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On-Resistance versus Gate-to-Source Voltage
R DS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)
Figure 4. On-Resistance versus Drain Current and Gate Voltage
2.0 VGS = 2.5 V ID = 3.5 A
10,000 VGS = 0 V 1000 IDSS, LEAKAGE (nA) TJ = 125C 100C 100
1.5
1.0
10 25C 1
0.5
0 -50
0.1 -25 0 25 50 75 100 125 150 0 4 8 12 16 20 TJ, JUNCTION TEMPERATURE (C) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-To-Source Leakage Current versus Voltage
http://onsemi.com
3
NGSF3443V
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1600 Ciss C, CAPACITANCE (pF) 1200 Crss 800 Ciss 400 Coss 0 -10 VDS = 0 V -5 VGS 0 VDS Crss 5 10 15 20 VGS = 0 V TJ = 25C
The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
http://onsemi.com
4
NGSF3443V
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) 6 5 VDS 4 3 Q1 2 1 Q3 0 0 2 4 6 Q2 TJ = 25C VGS = 4.5V VDS = 10V ID = 4.4 A 8 4 2 0 10 VGS 8 6 QT 12 10 100 TJ = 25C ID = 1 A VDD = 10 V VGS = 4.5 V td(off) tf tr td(on)
t, TIME (ns)
10
1 1 10 RG, GATE RESISTANCE (OHMS) 100
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation versus Gate Resistance
DRAIN-TO-SOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable
3 I S , SOURCE CURRENT (AMPS) TJ = 25C VGS = 0 V
circuit parasitic inductances and capacitances acted upon by high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.
2
1
0 0 0.2 0.4 0.6 0.8 1 1.2 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
http://onsemi.com
5
NGSF3443V
Standard Cell Density trr I S , SOURCE CURRENT High Cell Density trr tb ta
t, TIME
Figure 11. Reverse Recovery Time (trr)
SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance -- General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For
EAS , SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 75 VDD = 20V VGS = 4.5V IL = 10 A L = 1.5mH RG = 25W
reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
50
25
0
25
50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C)
150
Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature
http://onsemi.com
6
NGSF3443V
2.0 NORMALIZED EFFECTIVE TRANSIENT THERMAL IMPEDANCE 1.0 DUTY CYCLE = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.0001 0.001 0.01 0.1 1.0 10 30 SQUARE WAVE PULSE DURATION (sec) t1 NOTES: PDM 1. DUTY CYCLE, D = t1/t2 2. PER UNIT BASE = 2. RthJA = 62.5C/W 3. TJM - TA = PDMZthJA(t) 4. SURFACE MOUNTED
SINGLE PULSE
t2
Figure 13. Thermal Response
di/dt IS trr ta tb TIME tp IS 0.25 IS
Figure 14. Diode Reverse Recovery Waveform
http://onsemi.com
7
NGSF3443V
PACKAGE DIMENSIONS TSOP 6 CASE 318G-02 ISSUE D
A L
6 5 1 2 4 STYLE 1: PIN 1. 2. 3. 4. 5. 6. DRAIN DRAIN GATE SOURCE DRAIN DRAIN NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. DIM A B C D G H J K L M S MILLIMETERS MIN MAX 2.90 3.10 1.30 1.70 0.90 1.10 0.25 0.50 0.85 1.05 0.013 0.100 0.10 0.26 0.20 0.60 1.25 1.55 0_ 10 _ 2.50 3.00 INCHES MIN MAX 0.1142 0.1220 0.0512 0.0669 0.0354 0.0433 0.0098 0.0197 0.0335 0.0413 0.0005 0.0040 0.0040 0.0102 0.0079 0.0236 0.0493 0.0610 0_ 10 _ 0.0985 0.1181
S
3
B
D G
M 0.05 (0.002) H C K J
HDTMOS and MiniMOS are trademarks of Semiconductor Components Industries, LLC. TMOS is a registered trademark of Semiconductor Components Industries, LLC. Thermal Clad is a trademark of the Bergquist Company.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
North America Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor - European Support German Phone: (+1) 303-308-7140 (M-F 2:30pm to 5:00pm Munich Time) Email: ONlit-german@hibbertco.com French Phone: (+1) 303-308-7141 (M-F 2:30pm to 5:00pm Toulouse Time) Email: ONlit-french@hibbertco.com English Phone: (+1) 303-308-7142 (M-F 1:30pm to 5:00pm UK Time) Email: ONlit@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor - Asia Support Phone: 303-675-2121 (Tue-Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong 800-4422-3781 Email: ONlit-asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-8549 Phone: 81-3-5740-2745 Email: r14525@onsemi.com Fax Response Line: 303-675-2167 800-344-3810 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative.
http://onsemi.com
8
NGSF3443V/D

▲Up To Search▲

Price & Availability of NGSF3443VT3

	To Download NGSF3443VT3 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .