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  Datasheet File OCR Text:
 DECT Receiver
PMB 2420
General Description The PMB 2420 is a high speed analog bipolar IC and is one of the Siemens chipset for the Digital European Cordless Telephone specified by the DECT standard. All control inputs and the RSSI signal output match with the PMB 27201/2 and 27221 and 27251/2 and 2728 and 2727 digital circuits. The IC operates as a heterodyne receiver using an intermediate frequency (IF) at 110 MHz. It consists of a mixer to downconvert the DECT-RF signal from 1.89 GHz to 110 MHz, a limiter amplifier, a field strength measurement unit (RSSI) with a peak-hold output, a coincidence demodulator, a sample-and-hold circuit for offset compensation and two operational amplifiers for basehand filtering. Features * Wide supply range 3.0 ... 5.5 V * Single conversion solution; advantages are: low supply current of total RF part no second IF image frequency and therefore insensitive to strong transmitters at FM radiofrequencies low total component count 1st mixer included on chip
Type PMB 2420-S
Package P-SSOP-28-1 (Shrink, SMD)
* Single balanced RF mixer with current-saving open collector output on chip * Limiter and RSSI dynamic range: 75 dB for IF between 40 MHz and 115 MHz * RSSI output independent of supply voltage and temperature with 3 dB accuracy * Peak-hold output for the RSSI signal, reset by the controller via RSSG * Sample-and-hold control circuit for baseband threshold acquisition, loop opened and closed via RXDSG, offset compensation value is stored during standby mode * Timing for RSSI and sample-and-hold determined by the controller * Two operational amplifiers on chip for baseband filtering, included in sample and hold control loop * Standby mode with reduced supply current * Balanced circuitry throughout the RF and IF * Parts to improve signal isolation * Maybe applied as part of a complete DECT-chipset solution
DSTP RXDSG RSTP 28 27 26
LO 25
LO 24
RXOFF GND2 23 Standby 22
RFB 21
RFE 20
RSSG 19
V CC
18 Bandgap V BG
MO 17
MO 16
RSSI 15
R stp
Integrator & Hold Interface Gating Sample & Hold + Ref
Gating Limiter Amplifier with RSSI Current Sources
Discharge Switch Peak-hold Stage
R BBL
Buffer Amp.
CK
+ -
+ -
CK
1 QUA
Block Diagram
2 QUA
3 OA
4
5
6 IFP
7 IFP
8
9
10
11 BBL
12 GND1
13 IFE
14 IFB
ITB05959
OP1I OP1Q
OP2I RXREF RXDI
Siemens Aktiengesellschaft
1


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