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PRELIMINARY DATASHEET
WMS7130 / 7131
NON-VOLATILE DIGITAL POTENTIOMETERS WITH UP/DOWN (3-WIRE) INTERFACE, 10KOHM, 50KOHM, 100KOHM RESISTANCE 32 TAPS WITHOUT / WITH OUTPUT BUFFER
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Publication Release Date: July 2003 Revision 1.0
WMS7130 / 7131
1. GENERAL DESCRIPTION
The WMS7130/7131 is a single channel 32-tap non-volatile linear digital potentiometer available in 10K, 50K and 100K resistance. The device consists of Up/Down serial interface, tap register, decoder, resistor array, wiper switches, NV memory and control logics. The WMS7130 device can be configured as a two-terminal variable resistor or a three-terminal voltage divider without an output buffer, but the WMS7131 device, which has a built-in output buffer, can only be configured as a three-terminal voltage divider. Both devices can be used in a wide variety of applications. The output of the potentiometer is determined by its wiper position, which varies linearly between its end terminals, RA/VA and RB/VB. The wiper position, Rw/Vw, is controlled by Up/Down serial interface ( CS , INC and U/ D ) through the Tap Register (TR). In addition, the wiper position can also be stored into a non-volatile memory location (NVMEM0), which is then automatically recalled upon power up.
2. FEATURES
* * * * * * * * * * * * Drop-in replacement for many popular parts Single linear-taper channel 32 taps 10K, 50K and 100K end-to-end resistance VSS to VDD terminal voltages Automatic recall of wiper position when power-on Potentiometer control through Up/Down (3-wire) serial interface Endurance 100,000 cycles Data retention 100 years Package options: 8-pin PDIP, SOIC or MSOP Industrial temperature range: -40 to 85C Single supply operation : 2.7V to 5.5V
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WMS7130 / 7131
3. BLOCK DIAGRAM
Tap Register
RA/VA
INC CS U/D
Decoder
Up/Down Serial Interface
RW /VW
RB/VB
NV Memory
VSS
NV Memory Control
NVMEM0
VDD
FIGURE 1 - WMS7130 BLOCK DIAGRAM (Rheostat/Divider Mode)
Tap Register
VA
INC CS U/D
Up/Down Serial Interface
Decoder
VW
VB
NV Memory
VSS
NV Memory Control
NVMEM0
VDD
FIGURE 2 - WMS7131 BLOCK DIAGRAM (Divider Mode)
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Publication Release Date: July 2003 Revision 1.0
WMS7130 / 7131
4. TABLE OF CONTENTS
1. GENERAL DESCRIPTION.................................................................................................................. 2 2. FEATURES ......................................................................................................................................... 2 3. BLOCK DIAGRAM............................................................................................................................... 3 4. TABLE OF CONTENTS ...................................................................................................................... 4 5. PIN CONFIGURATION ....................................................................................................................... 5 6. PIN DESCRIPTION ............................................................................................................................. 6 7. FUNCTIONAL DESCRIPTION............................................................................................................ 7
7.1. Rheostat And Divider Operations ........................................................................................... 7
7.1.1. Rheostat Configuration .......................................................................................................... 7 7.1.2. Divider Configuration.............................................................................................................. 7
7.2. Non-Volatile Memory (NVMEM0) ........................................................................................... 7 7.3. Serial Data Interface ................................................................................................................. 8 7.4. Operation Overview .................................................................................................................. 8
8. TIMING DIAGRAMS............................................................................................................................ 9 9. ABSOLUTE MAXIMUM RATINGS & OPERATING CONDITIONS .................................................. 11 10. ELECTRICAL CHARACTERISTICS ............................................................................................... 12
10.1 Test Circuits ............................................................................................................................ 14
11. TYPICAL APPLICATION CIRCUITS............................................................................................... 15
11.1. Layout Considerations.......................................................................................................... 17
12. PACKAGE DRAWINGS AND DIMENSIONS.................................................................................. 18 13. ORDERING INFORMATION........................................................................................................... 21 14. VERSION HISTORY ....................................................................................................................... 22
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WMS7130 / 7131
5. PIN CONFIGURATION
INC U/D R A /V A V SS
1 2 3 4
8 7 6 5
VDD CS R B /V B R w /V W
INC
1
8
V DD
U/D
2
7
CS
R A /V A V SS
3
6
R B /V B
8-M SOP
4
5
R w /V W
8-SOIC
INC
1
8
V DD
U/D
2
7
CS
R A /V A
3
6
R B /V B
V SS
4
5
R w /V W
8-PDIP
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Publication Release Date: July 2003 Revision 1.0
WMS7130 / 7131
6. PIN DESCRIPTION
TABLE 1 - PIN DESCRIPTION
Pin Name
Description Chip Select: When CS is LOW, the device is enabled.
CS
When CS is HIGH, the part is deselected and is in standby mode Up/Down Control: HIGH state enables the wiper to move towards the RA / VA terminal, while LOW state implies the wiper moves towards the RB / VB terminal Increment Control: When CS is LOW, a HIGH-LOW
U/ D
INC
transition on INC will move the wiper one increment either up or down based on the U/ D input High terminal of the device Low terminal of the device Wiper Terminal: Output of the resistor array is determined by the INC , U/ D and CS inputs Ground pin, logic ground reference Power Supply
RA/VA RB/VB RW/VW VSS VDD
Notes: The terminology of high and low terminals above references to the relative position of the terminal with respect to the wiper moving direction and not the voltage potential of the terminal.
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WMS7130 / 7131
7. FUNCTIONAL DESCRIPTION
7.1. RHEOSTAT AND DIVIDER OPERATIONS
The WMS7130 device can operate as either a two-terminal variable resistor or a three-terminal voltage divider without an output buffer. However, the WMS7131 can only operate in a three-terminal voltage divider with an output buffer. 7.1.1. Rheostat Configuration In the rheostat mode, the WMS7130 can be configured as a two-terminal resistive element, where one terminal is connected to one end of the resistor (RA or RB) and the other terminal is the wiper (RW). The moving direction of the wiper depends upon the setting of U/ D control signal. When the U/ D is set to Up, then the wiper moves towards RA. Conversely, when the U/ D is set to Down, then the wiper moves towards RB. The wiper movement to either direction is controlled by toggling the INC signal from HIGH to LOW. This configuration controls the resistance between the wiper and either end. The wiper resistance can be adjusted by either changing the wiper position or loading a stored wiper position value from NVMEM0 upon power up. 7.1.2. Divider Configuration Additionally, the WMS7130 can also be configured as a voltage divider. With an input voltage applied to one end (usually VA ), the ground is connected to the other end (usually VB). These input voltages cannot exceed the VDD level or go below the VSS level. The voltage on the wiper, VW, is proportional to the wiper position with respect to the voltage difference between VA and VB. The moving direction of the wiper depends upon the setting of the U/ D control signal. When the U/ D is set to Up, then the wiper moves towards VA. Conversely, when the U/ D is set to Down, then the wiper moves towards VB. The wiper movement to either direction is controlled by toggling the INC signal from HIGH to LOW. Nevertheless, the WMS7131 can only be configured as a voltage divider and operate similarly as the WMS7130 device. The only difference is WMS7131 has an output buffer, but WMS7130 doesn't have. Besides, the resistance cannot be directly measured in this configuration.
7.2. NON-VOLATILE MEMORY (NVMEM0)
The WMS7130/7131 has one NVMEM0 location available for storing the current wiper position via the Up/Down serial interface. This stored value is automatically recalled and loaded into the tap register upon power up.
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Publication Release Date: July 2003 Revision 1.0
WMS7130 / 7131
7.3. SERIAL DATA INTERFACE
The WMS7130/7131 device has a 3-wire Up/Down Serial Interface consisting of CS , INC and U/ D control signals. The key features of this interface include: * * * * * Enabling the device Determining the moving direction of the wiper Increment/Decrement operation on the wiper Non-volatile storage of the present wiper position into the NVMEM0 for automatic recall at power up Entering into the standby mode
7.4. OPERATION OVERVIEW
The wiper position can be changed either up or down by operating the CS , U/ D and INC control signals. When CS is LOW, the device is selected and the wiper can be moved by toggling the INC . As a result, the wiper moves up when U/ D is HIGH and moves down when U/ D is LOW. The status of the U/ D can be changed even though the CS remains LOW. This allows the system to enable the device and then move the wiper position either up or down until the desired position is reached. When the wiper is already at the lowest position, further Down operation won't change the wiper position. Similarly, when the wiper is at the highest position, further Up operation won't change the wiper position too. The current wiper position can be automatically stored into the NVMEM0 each time the CS goes from LOW to HIGH while the INC remains HIGH. Adversely, if the INC is LOW when the CS goes HIGH, the wiper position cannot be stored. Meanwhile, the NVMEM0 content is automatically loaded into the wiper during power on. When the CS is held HIGH, the device enters into Standby mode and the wiper position cannot be changed. Changing the CS to LOW exits the Standby mode and enables the device again. The operating modes of Up/Down interface are summarized in the table below:
CS
U/ D HIGH LOW x x x
INC
Operation Move Wiper toward RA /VA Move Wiper toward RB /VB Store Current Wiper Position No Store, Return to Standby Standby
LOW LOW LOW to HIGH LOW to HIGH HIGH
Note: x means don't care
HIGH to LOW HIGH to LOW HIGH LOW x
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WMS7130 / 7131
8. TIMING DIAGRAMS
Conditions: VDD = +2.7V to 5.5V, VA = VDD, VB = 0V, T = 25C
t PUD CS
[1]
tCI INC
tCYC tIL tIH
tCI
(store)
tCPH
90% 90%
10%
tDI U/D
tID
tF
tR
tIW
MI
[2]
VW
FIGURE 3 -WMS7130/1 TIMING DIAGRAM
Note:
[1] [2]
This only applies to the Power-Up sequence.
MI in the AC Timing diagram (Figure 3) refers to the minimum incremental change in the wiper output due to a change in the wiper position.
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Publication Release Date: July 2003 Revision 1.0
WMS7130 / 7131
TABLE 10 - TIMING PARAMETERS
PARAMETERS
CS to INC Setup
SYMBOL tCI tDI tID tIL tIH tIC tCPH tCPH tIW tCYC tR, tF tPUD
MIN. 100 50 100 250 250 1 100 15 (2.7V) 30 (5.5V)
MAX.
UNITS ns ns ns ns ns s ns ms
U/ D to INC Setup U/ D to INC Hold
INC LOW Period INC HIGH Period INC Inactive to CS Inactive CS Deselect Time (NO STORE) CS Deselect Time (STORE) INC to Wiper Change INC Cycle Time INC Input Rise and Fall Time
5 1 500 1 0.2 50 (54s 0-2.7V) (13ms 0-2.7V)
s s s ms V/ms
Power-Up Delay VCC Power-Up rate
tR VCC
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WMS7130 / 7131
9. ABSOLUTE MAXIMUM RATINGS & OPERATING CONDITIONS
TABLE 11 - ABSOLUTE MAXIMUM RATINGS (PACKAGED PARTS) [1] Conditions Junction temperature Storage temperature Voltage applied to any pad Lead temperature (soldering - 10 seconds) VSS - VDD 150C -65 to +150C (Vss - 0.3V) to (VDD + 0.3V) 300C -0.3 to 7.0V Values
TABLE 12 - OPERATING CONDITIONS (PACKAGED PARTS) Conditions Industrial operating temperature Supply voltage (VDD) Ground voltage (VSS) Values -40C to +85C +2.7V to +5.5V 0V
[1]
Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum ratings may affect device performance and reliability. Functional operation is not implied at these conditions. Publication Release Date: July 2003 Revision 1.0
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WMS7130 / 7131
10. ELECTRICAL CHARACTERISTICS
TABLE 12 - ELECTRICAL CHARACTERISTICS (Packaged parts) PARAMETERS Rheostat Mode Nominal Resistance Different Non Linearity Tempo [1] Wiper Resistance Wiper Current Divider Mode Resolution Different Non Linearity Integral Non Linearity Full Scale Error Zero Scale Error Resistor Terminal Voltage Range Terminal Capacitance Wiper Capacitance
[1] [1] [1] [2] [2] [2] [2]
SYMBOL R R-DNL R-INL RAB/T RW IW N DNL INL W /T VFSE VZSE VA, VB, VW CA, CB
MIN. -20 -1 -1
TYP.
MAX. +20
UNITS % LSB LSB ppm/C
CONDITIONDS [5] T=25C, Wiper open
[6] [6]
0.2 0.4 300 50 80
+1 +1
Integral Non Linearity [2]
VDD=5V, I=VDD/RTotal [7] VDD=2.7V, I=VDD/RTotal [7]
-1 8 -1 -1 -1 0 VSS 30 30 0.4 0.4 +20
1
mA Bits
+1 +1 0 1 VDD
LSB LSB ppm/C LSB LSB V pF pF MHz KHz KHz mA VO=1/2 scale IL = 100uA A =2.5V, VDD=5V, f=1kHz, VIN=1VRMS VDD=5V, B =VSS Wiper at center Wiper at center Wiper at highest position Wiper at lowest position
Temperature Coefficient [1]
Dynamic Characteristics Bandwidth -3dB
BW10K BW50K BW100K Analog Output (Buffer enables) Amp Output Current Amp Output Resistance Total Harmonic Distortion [1] Digital Inputs/Outputs Input High Voltage Input Low Voltage Output Low Voltage VIH VIL VOL 0.7xVDD IOUT Rout THD 3
1.5 300 200
1
10 0.08
%
V 0.3xVDD 0.4 V V IOL=2mA
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WMS7130 / 7131
TABLE 12 - ELECTRICAL CHARACTERISTICS (Packaged parts) - Cont'd PARAMETERS Input Leakage Current Output Leakage Current Input Capacitance [1] Output Capacitance Operating Voltage Operating Current
[1]
SYMBOL ILI ILo CIN COUT VDD IDDR, IDDW ISA [3]
MIN. -1 -1
TYP.
MAX. +1 +1
UNITS uA uA pF pF
CONDITIONDS [5]
CS =VDD,Vin=Vss ~ VDD CS =VDD,Vin=VSS ~ VDD
25 25 2.7 1 0.5 5.5 2 1
VDD=5V, fc = 1Mhz VDD=5V, fc = 1Mhz
Power Requirements V mA mA All operations Buffer = ON
CS = HIGH, no load
Standby Current ISB [4] Power Supply Rejection Ratio PSRR 0.1 1 1 uA LSB/V
Buffer = OFF
CS = HIGH, no load
VDD=5V10%, Wiper at center
Notes:
[1] [2]
Not subject to production test. LSB = (RA/VA - RB/VB) / (T - 1); DNL = (Vi - Vi+1) / LSB + 1 (if increment) or = (Vi Vi+1) / LSB - 1 (if decrement); INL = (Vi - i*LSB) / LSB; where i = [0, (T -1)] and T = # of taps of the device. WMS7131 only. WMS7130 only. Conditions: VCC = 2.7 to 5.5V, T = 25C and timing measured at 50% level, unless stated. Only guarantee by design. Rtotal = end-to-end resistance.
[3] [4] [5] [6] [7]
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Publication Release Date: July 2003 Revision 1.0
WMS7130 / 7131
10.1 TEST CIRCUITS
VA V+ VW
V+ = VDD 1LSB= V+/31 VMS*
VA VA V+ VW
VA = VDD V+ = VDD 10% PSRR(dB) = 20LOG( VMS ) VDD PSS(%/%) = VMS VDD
VB WMS71xx
*Assume infinite input impedance
VB WMS71xx
VMS*
*Assume infinite input impedance
Potentiometer divider nonlinearity error test circuit (INL, DNL) No Connection WMS71xx RA RW RB VMS * IW
Power supply sensitivity test circuit (PSS, PSRR)
VA W
WMS71xx VW
VB +5V VOUT
~
VIN
*Assume infinite input impedance
2.5V DC Offset Capacitance test circuit
Resistor position nonlinearity error test circuit (Rheostat Operation: R-INL, R-DNL) VMS * VA VW VB WMS71xx IW = V /RTotal DD IW
WMS71xx +5V VA VIN OFFSET GND 2.5V DC
~
VW VOUT VB
RW = V /IW MS
*Assume infinite input impedance
Wiper resistance test circuit
Gain vs. frequency test circuit FIGURE 4 - TEST CIRCUITS
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WMS7130 / 7131
11. TYPICAL APPLICATION CIRCUITS
RA RB
Vin WMS71XX
_ OP AMP +
VOUT
VOUT = - VIN RA =
RB RA
, RB = RAB*W 32
RAB (32-W) 32
RAB = Total resistance of potentiometer W = Wiper setting for WMS71XX FIGURE 5 - PROGRAMMABLE INVERTING GAIN AMPLIFIER USING THE WMS7130/7131
VIN
+
OP _ AMP
VOUT
RA
RB
WMS71XX VOUT = VIN (1+ RA =
RB ) RA
, RB = RAB*W 32
RAB (32-W) 32
RAB = Total resistance of potentiometer W = Wiper setting for WMS71XX
FIGURE 6 - PROGRAMMABLE NON-INVERTING GAIN AMPLIFIER USING THE WMS7130/7131
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Publication Release Date: July 2003 Revision 1.0
WMS7130 / 7131
V+
WMS71xx 5V Vout
VREFH
VREF = 5.0v 0V GND FIGURE 7 - WMS7131 TRIMMING VOLTAGE REFERENCE
L1 CHOKE C1 0.1uF CS\ U/D\ INC\ CS\ U/D\ INC\ VSS VDD RA/VA RW/VW RB/VB RF OUT FILTER C2 Q1 RF POWER AMP WMS71xx WINPOT
RF Input
FIGURE 8 - WMS7131 RF AMP CONTROL
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WMS7130 / 7131
11.1. LAYOUT CONSIDERATIONS
Use a 0.1F bypass capacitor as close as possible to the VDD pin. This is recommended for best performance. Often this can be done by placing the surface mount capacitor on the bottom side of the PC board, directly between the VDD and VSS pins. Care should be taken to separate the analog and digital traces. Sensitive traces should not run under the device or close to the bypass capacitors. A dedicated plane for analog ground helps in reducing ground noise for sensitive analog signals.
DIGITAL CONTROL LINES ANALOG SIGNAL LINE
INC U/D
CAP
V DD CS R B /V B R W /V W
DIGITAL CONTROL LINE ANALOG SIGNAL LINES
R A /V A V SS
FIGURE 9 - WMS7130/7131 LAYOUT
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Publication Release Date: July 2003 Revision 1.0
WMS7130 / 7131
12. PACKAGE DRAWINGS AND DIMENSIONS
8
5
E
1
4
Control demensions are in milmeters .
E
FIGURE 10: 8L 150MIL SOIC
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WMS7130 / 7131
D
8 5
E1
1
B B
1
4
S A1
E c
A A2 L e1
B a s e P la n e
S e a t in g P la n e
eA
S ym b o l
D im e n s io n in in c h
D im e n s io n in m m
M in
0 .0 1 0 0 .1 2 5 0 .0 1 6 0 .0 5 8 0 .0 0 8
Nom
M ax
0 .1 7 5
M in
0 .2 5
Nom
M ax
4 .4 5
A A1 A2 B B1 c D E E1 e1 L
0 .1 3 0 0 .0 1 8 0 .0 6 0 0 .0 1 0 0 .3 6 0
0 .1 3 5 0 .0 2 2 0 .0 6 4 0 .0 1 4 0 .3 8 0 0 .3 1 0 0 .2 5 5 0 .1 1 0 0 .1 4 0 15 0 .3 7 5 0 .0 4 5
3 .1 8 0 .4 1 1 .4 7 0 .2 0
3 .3 0 0 .4 6 1 .5 2 0 .2 5 9 .1 4
3 .4 3 0 .5 6 1 .6 3 0 .3 6 9 .6 5 7 .8 7 6 .4 8 2 .7 9 3 .5 6 15 9 .5 3 1 .1 4
0 .2 9 0 0 .2 4 5 0 .0 9 0 0 .1 2 0 0 0 .3 3 5
0 .3 0 0 0 .2 5 0 0 .1 0 0 0 .1 3 0 0 .3 5 5
7 .3 7 6 .2 2 2 .2 9 3 .0 5 0 8 .5 1
7 .6 2 6 .3 5 2 .5 4 3 .3 0 9 .0 2
e S
A
FIGURE 11: 8L 300MIL PDIP
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Publication Release Date: July 2003 Revision 1.0
WMS7130 / 7131
FIGURE 12: 8L 3MM MSOP
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WMS7130 / 7131
13. ORDERING INFORMATION
Winbond's WinPot Part Number Description:
WMS71 T
B
RRR P
Winbond WinPot Products w/ Up-Down Interface
Number Of Taps: 3 = 32 For Up/Down interface: 0 : No buffer 1 : With buffer End-to-end Resistance: 010: 10Kohm 050: 50Kohm 100: 100Kohm Package: S: SOIC P: PDIP M: MSOP
Output Buffer NO
End-to-End Resistance 10K 50K 100K
SOIC WMS7130010S WMS7130050S WMS7130100S WMS7131010S WMS7131050S WMS7131100S
PDIP WMS7130010P WMS7130050P WMS7130100P WMS7131010P WMS7131050P WMS7131100P
MSOP WMS7130010M WMS7130050M WMS7130100M WMS7131010M WMS7131050M WMS7131100M
YES
10K 50K 100K
For the latest product information, access Winbond's worldwide website at http://www.winbond-usa.com
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Publication Release Date: July 2003 Revision 1.0
WMS7130 / 7131
14. VERSION HISTORY
VERSION 1.0 DATE July 2003 Initial issue DESCRIPTION
The contents of this document are provided only as a guide for the applications of Winbond products. Winbond makes no representation or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to discontinue or make changes to specifications and product descriptions at any time without notice. No license, whether express or implied, to any intellectual property or other right of Winbond or others is granted by this publication. Except as set forth in Winbond's Standard Terms and Conditions of Sale, Winbond assumes no liability whatsoever and disclaims any express or implied warranty of merchantability, fitness for a particular purpose or infringement of any Intellectual property. Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipments intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental injury could occur.
Headquarters No. 4, Creation Rd. III Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441797 http://www.winbond-usa.com/
Winbond Electronics (Shanghai) Ltd. 27F, 299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62356998
Taipei Office
9F, No. 480, Pueiguang Rd. Neihu District Taipei, 114 Taiwan TEL: 886-2-81777168 FAX: 886-2-87153579
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Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners. This product incorporates SuperFlash(R) technology licensed from SST.
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