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PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
PM7380
FREEDM-32P672
DEVELOPMENT KIT BOARD
DESIGN DOCUMENT
ISSUE 1: DECEMBER 2000
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PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
REVISION HISTORY Issue No. Issue 1 Issue Date December 2000 Details of Change Document created
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PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
CONTENTS 1 2 ACRONYMS ............................................................................................ 1 OVERVIEW.............................................................................................. 2 2.1 3 SCOPE.......................................................................................... 2
FUNCTIONAL DESCRIPTION................................................................. 3 3.1 3.2 OVERVIEW ................................................................................... 3 FEATURES AND BENEFITS......................................................... 3 3.2.1 2.048 MBIT/S H-MVIP MODE ............................................ 4 3.2.2 8.192 MBIT/S H-MVIP MODE ............................................ 4 3.2.3 NON-HMVIP MODE ........................................................... 4 3.2.4 MIXED MODE..................................................................... 5 3.3 BLOCK DIAGRAM ........................................................................ 5
4
DETAILED DESCRIPTION ...................................................................... 7 4.1 DETAILED INTERFACE DEFINITIONS ........................................ 7 4.1.1 PHYSICAL INTERFACE ..................................................... 7 4.1.2 BERT INTERFACE ............................................................. 8 4.1.3 PCI INTERFACE ................................................................ 8 4.2 DESCRIPTION OF FUNCTIONAL BLOCKS............................... 10 4.2.1 CLOCK GENERATION..................................................... 10 4.2.2 CLOCK DISTRIBUTION ................................................... 12 4.2.3 RMV8DC AND TMV8DC PROVISION.............................. 13 4.2.4 RCLK DISTRIBUTION...................................................... 13 4.2.5 TCLK DISTRIBUTION ...................................................... 17
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PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
4.2.6 RMVCK AND TMVCK DISTRIBUTION............................. 19 4.2.7 CLOCK DRIVERS ............................................................ 20 4.2.8 PROVISION FOR LOOPBACK OF DATA ........................ 21 4.2.9 SIMULTANEOUS CROSS-CONNECT AND LOOPBACK OF TWO 52 MBIT/S DATA STREAMS.................................. 23 4.2.10 LOOPBACK OF UNCHANNELISED T1/E1 DATA STREAMS23 4.2.11 MISCELLANEOUS SIGNALS........................................... 23 4.2.12 SYSCLK PROVISION....................................................... 23 4.2.13 M66EN.............................................................................. 24 4.2.14 JTAG SIGNALS ................................................................ 24 4.2.15 PRODUCTION TEST INTERFACE SIGNALS.................. 25 4.2.16 POWER............................................................................ 25 4.2.17 POWER CALCULATIONS ............................................... 26 4.2.18 VOLTAGE REGULATION ................................................. 28 4.3 DESIGN ALTERNATIVES ........................................................... 30 4.3.1 USING ENABLE PINS OF CLOCK DRIVERS.................. 30 5 6 SOFTWARE INTERFACES ................................................................... 33 MECHANICAL........................................................................................ 34 6.1 6.2 6.3 7 8 9 BOARD SIZE/OUTLINE .............................................................. 34 ESTIMATE OF REAL ESTATE.................................................... 34 COOLING REQUIREMENTS ...................................................... 34
LIMITATIONS ......................................................................................... 35 REQUIREMENTS TRACEABILITY........................................................ 36 BILL OF MATERIALS............................................................................. 37
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PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
10 11 12
SCHEMATIC DIAGRAMS ...................................................................... 38 LAYOUT ................................................................................................. 39 REFERENCES....................................................................................... 40
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PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
LIST OF FIGURES FIGURE 1: BLOCK DIAGRAM OF THE DEVELOPMENT KIT........................... 5 FIGURE 2: CONFIGURATION FOR DISTRIBUTION OF RCLK ...................... 15 FIGURE 3: DISTRIBUTION OF TCLK.............................................................. 18 FIGURE 4: RMVCK AND TMVCK DISTRIBUTION .......................................... 19 FIGURE 5: CLOCK DRIVERS USED FOR DISTRIBUTION OF LINE CLOCKS20 FIGURE 6: CONFIGURATION FOR THE LOOPBACK OF DATA .................... 22 FIGURE 7: SIMULTANEOUS CROSS-CONNECT AND LOOPBACK OF 52 MBIT/S DATA STREAM (P2). ........................................................................... 23 FIGURE 8: SYSCLK PROVISION .................................................................... 24 FIGURE 9: JTAG SIGNALS.............................................................................. 25 FIGURE 10: PROVISION OF 2.5V, 3.3V AND 5V TO THE POWER PLANE... 26 FIGURE 11: ALTERNATIVE DESIGN FOR CLOCK DISTRIBUTION IN THE DEVELOPMENT KIT ........................................................................................ 30
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PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
LIST OF TABLES TABLE 1: CONFIGURATION FOR THE PROVISION OF FRAME PULSE SIGNALS ......................................................................................................... 7 TABLE 2: CONFIGURATION FOR PROVISION OF BERT DATA AND BERT CLOCK ......................................................................................................... 8 TABLE 3: REGULAR PCI PINS AND THE CORRESPONDING FREEDM32P672 DEVICE PINS........................................................................................ 9 TABLE 4: OPTIONAL PCI PINS AND THE CORRESPONDING FREEDM32P672 DEVICE PINS........................................................................................ 9 TABLE 5: FREQUENCIES OF OSCILLATORS FOR BOARD USE ..................11 TABLE 6: SOCKETS FOR THE VARIOUS OSCILLATORS ..............................11 TABLE 7: POSSIBLE CONFIGURATIONS OF RCLK AND TCLK.................... 12 TABLE 8: CONFIGURATION FOR RMV8DC AND TMV8DC PROVISION ...... 13 TABLE 9: CONFIGURATION FOR RCLK DISTRIBUTION .............................. 15 TABLE 10: FUNCTION TABLE OF 1-TO-8 CLOCK DRIVERS......................... 16 TABLE 11: CONFIGURATION FOR THE DISTRIBUTION OF TCLK ............... 18 TABLE 12: CONFIGURATION FOR RMVCK AND TMVCK.............................. 19 TABLE 13: CONFIGURATION FOR THE LOOPBACK OF DATA .................... 22 TABLE 14: POWER CALCULATIONS (5 V SIGNALING ENVIRONMENT) ..... 26 TABLE 15: POWER CALCULATIONS (3.3 V SIGNALING ENVIRONMENT) .. 27 TABLE 16: JUMPER CONFIGURATION IN THE ALTERNATIVE DESIGN...... 31 TABLE 17: TRACEABILITY MATRIX ................................................................ 36 TABLE 18: BILL OF MATERIALS ..................................................................... 37
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PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
1
ACRONYMS DS-1: T1: DS-3: E1: PCI: HDLC: BERT: FREEDM-32P672: H-MVIP: Digital Signal Level 1, 1.544 Mbit/s. Transmission at DS-1, 1.544 Mbit/s. Digital Signal Level 3, 44.736 Mbit/s. European Digital Signal Level 1, 2.048 Mbit/s. Peripheral Component Interconnect High Level Data Link Control Bit Error Rate Test Frame Engine and Data Link Manager High Speed Multi-Vendor Integration Protocol. A synchronous TDM bus of N X 64 Kbit/s constant bit rate data streams.
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PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
2 2.1
OVERVIEW Scope This document describes the FREEDM-32P672 Development Kit Board.
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PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
3 3.1
FUNCTIONAL DESCRIPTION Overview The FREEDM-32P672 chip is a multichannel HDLC controller, with a 33MHz/66-MHz, 32-bit PCI 2.1 compliant bus for configuration, monitoring, and packet data transfer. It supports up to 672 bidirectional HDLC channels. The following channel assignments are possible: * * * * 672 HDLC channels assigned to a maximum of 32 channelized T1/E1 links. 672 HDLC channels assigned to a maximum of 32 H-MVIP links (at 2.048 Mbps per link) or 8 H-MVIP links (at 8.192 Mbps per link). 32 HDLC channels assigned to arbitrary rate links, subject to a maximum aggregate link clock rate of 64 MHz. Channels assigned to links 0 to 2 that support a clock rate of up to 52 MHz. Channels assigned to links 3 to 31 that support a clock rate of up to 10 MHz.
The FREEDM-32P672 development kit consists of a PCI Universal card that contains the FREEDM-32P672 chip. Clock generation and distribution on the board enables the FREEDM-32P672 chip to operate in various supported modes. The 2.5 V and 3.3 V voltage regulators used on the board provide a regulated supply for the FREEDM-32P672 chip. External loopback on a per link basis is provided at the line interface of the chip. The PHY layer functionality is not implemented on the board. A provision is made for connecting the clock, data, and frame pulse signals from an external source. The development kit board provides a platform to implement and test software for the FREEDM32P672 chip. 3.2 Features and Benefits The Development Kit board supports up to 32 data links, which you can configure to operate in the following modes: * * * 2.048 Mbit/s H-MVIP 8.192 Mbit/s H-MVIP Non-HMVIP
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PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
*
Mixed
3.2.1 2.048 Mbit/s H-MVIP Mode You can configure the FREEDM-32P672 to interface with the H-MVIP digital telephony buses at 2.048 Mbps. For 2.048 Mbps H-MVIP links, TD[31..0] and RD[31..0] are the transmit and receive links respectively. For the 2.048 Mbps HMVIP operation, the links are grouped into four logical groups of eight links each. A common clock is shared among the links in each logical group. The four logical groups include links 0 through 7, 8 through 15, 16 through 23, and 24 through 31. The shared transmit clocks of these groups are respectively TMVCK[0], TMVCK[1], TMVCK[2], and TMVCK[3]. The shared receive clocks of these groups are respectively RMVCK[0], RMVCK[1], RMVCK[2], and RMVCK[3]. Both RMVCK[n] and TMVCK[n] have 4.096MHz clock frequency. For channelized operations, frame pulse signals must be generated from an external source. 3.2.2 8.192 Mbit/s H-MVIP Mode You can configure the FREEDM-32P672 to interface with the H-MVIP digital telephony buses at 8.192 Mbps. For 8.192 Mbps H-MVIP operation, the FREEDM-32P672 partitions the 32 physical links into eight logical groups of four links. In each logical group, only the first link, which must be located at physical links numbered 4m (m = 0,1,...,7 ), can be configured for 8.192 Mbps operation. The remaining three physical links in the logical group (numbered 4m+1, 4m+2 and 4m+3) are unused. All links configured for 8.192 Mbps H-MVIP operation share a common data clock. TMV8DC and RMV8DC are respectively the transmit and receive data clocks for this configuration. Operation in this mode requires frame pulse signals. These signals are not generated on the board. Hence this mode can be operated only with clock and frame pulse signals supplied from an external source. Headers are provided for making the external connections. 3.2.3 Non-HMVIP Mode The board supports 32 unchannelized T1/E1 links, with the following clock options: * * * All 32 links driven by one reference clock (T1/E1) Links 0 to 15 driven by one reference clock (T1/E1), and links 16 to 31 driven of another reference clock (T1/E1). Links 0 to 2 also driven by another reference clock (52 MHz/T3)
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PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
Gapping of the clock is not done on the board. For channelized operations, an external source must obtain the gapped clocks. 3.2.4 Mixed Mode The board supports mixing of up to 32 unchannelized T1/E1 and H-MVIP links. The total number of channels in each direction is limited to 32. The aggregate instantaneous clock rate, over all 32 possible links, is limited to 64 MHz. 3.3 Block Diagram The detailed operations of the line interface, the PCI interface, and the BERT Unit are provided in the next section. Figure 1: Block Diagram of the Development Kit
Host PCI Local bus
Voltage Regulators
FREEDM 32P672 System Clock
Header for Frame pulse signals
Tx and Rx Clocks
Rx Data
Tx Data
Clock Circuitry
Clock Selection (Jumpers)
Data Loopback Selection (Jumpers)
Header for external clocks
Header for external data
Figure 1 shows the basic components on the board. Voltage regulators provide the necessary 2.5 V and 3.3 V for the FREEDM-32P672 chip. Clock selection
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PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
is done using shorting jumpers. All resistors and ceramic capacitors on board are 0603 in size. Surface mount devices are used wherever possible.
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PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
4 4.1
DETAILED DESCRIPTION Detailed Interface Definitions The development kit has three interfaces: the physical interface, the BERT interface, and the PCI interface. Each interface is defined in the following sections.
4.1.1 Physical Interface The physical interface comprises the receive and transmit data links and the associated clocks. The physical interface is provided through headers. Wire to board connectors can be used to interface the external source with the development kit. The signals in this interface include RD[31..0], TD[31..0], RCLK[31..0], TCLK[31..0], RMVCK[3..0], TMVCK[3..0], RMV8DC, and TMV8DC. Traces from the headers are routed to the corresponding pins on the FREEDM-32P672 chip. The frame pulse signal and the frame pulse clock for the H-MVIP mode of operation has to be provided by an external source. For 2.048 Mbit/s, RFPB[3..0] and TFPB[3..0] are each provided by an external source by three-row, 12position headers (P8 and P1, respectively) on the PCB. Header P9 provides the frame pulse signals, RFP8B and TFP8B. TMV8FPC and RMV8FPC are connected through header P4. Traces from these header pins are routed to the corresponding pins on the FREEDM-32P672 chip (refer to the development kit Users Manual for information regarding header configuration). All the frame pulse signals can be pulled low when unused. For unchannelized operations in the HMVIP mode, the frame pulse signals must be pulled high. Table 1 shows the jumper settings for the provision of frame pulse signals. Table 1: Configuration for the Provision of Frame Pulse Signals
Pins Shorted Pins b0 to b3 shorted respectively to pins a0 to a3 of header P8 and P1. Wire to board connector plugged into header P9 Pins b0 to b1 shorted respectively to pins a0 to a1 of header P9. Wire to board connectors plugged into headers P8 and P1. Pins b0 to b3 shorted respectively to pins c0 to c3 of headers P8 and P1. Configuration Achieved Provision of frame pulse signals for 8.192 Mbit/s mode. Provision of frame pulse signals for 4.096 Mbit/s mode.
Unchannelized HMVIP operations
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PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
Pins b0 to b1 shorted respectively to pins c0 to c1 of header P9. Pins b0 to b3 shorted respectively to pins a0 to a3 of headers P8 and P1. Pins b0 to b1 shorted respectively to pins a0 to a1 of header P9. No provision for frame pulse signals (non-HMVIP mode)
4.1.2 BERT Interface The BERT signals are RBD, RBCLK, TBD, and TBCLK.These signals are connected to on board headers P15 (RBD and TBD) and P7 (RBCLK and TBCLK). The FREEDM-32P672 chip can perform BERT emulation, by shorting the RD[2] and RBD pins, and also the TD[2] and TBD pins on header P15. At the same time, RBCLK should be connected to RCLK[2] and TBCLK should be connected to TCLK[2] on header P7. To accomplish BERT emulation, configure the FREEDM-32P672 chip to transmit TBD on any one of the 31 links (not on TD[2]), and also to overwrite any one of the 31 links (not RD[2]) with RBD. Also, a test packet should be transmitted on link 2. RBCLK and TBCLK outputs are used as inputs to TCLK[2] and RCLK[2]. Table 2 shows the configuration for provision of BERT data and BERT clock. Table 2: Configuration for Provision of BERT Data and BERT Clock
Pins Shorted on Headers J7 and J8 RBD shorted to RD[2] in P15 TBD shorted to TD[2] in P15 RBCLK shorted to RCLK[2] in P7 TBCLK shorted to TCLK[2] in P7 Configuration Achieved. BERT Emulation.
4.1.3 PCI Interface The PCI Local Bus is a high performance 32-bit, 33/66-MHz bus with multiplexed address and data lines. The bus is used to connect the FREEDM-32P672 development kit board to the host. The FREEDM-32P672 chip provides a glueless interface to the PCI. Table 3 shows the signals on the PCI connector with the pins on the FREEDM32P672 device to which they are routed.
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PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
Table 3: Regular PCI Pins and the Corresponding FREEDM-32P672 Device Pins
PCI Pin AD[31..0] C/BE[3..0]# PAR FRAME# TRDY# IRDY# STOP# DEVSEL# IDSEL PERR# SERR# REQ# GNT# M66EN CLK RST# FREEDM-32P672 Device Pin AD[31..0] C/BEB[3..0] PAR FRAMEB TRDYB IRDYB STOPB DEVSELB IDSEL PERRB SERRB REQB GNTB M66EN PCICLK RSTB (through an AND gate)
Table 4 shows the optional PCI signals that are used on the development kit. Table 4: Optional PCI Pins and the Corresponding FREEDM-32P672 Device Pins
PCI Pin LOCK# Corresponding FREEDM-32P672 Device Pin LOCKB
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PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
INTA# TDI TDO TCK TMS TRST#
PCIINTB TDI TDO TCK TMS TRSTB (through an AND gate)
NOTE: The pound sign (#) that follows the signal name indicates that the signal is active low. PRSNT1# is kept open, whereas PRSNT2 is grounded on the board. (Power requirement is < 15 W.) Whenever PCI RST is asserted, the JTAG circuitry of the FREEDM-32P672 chip must obtain a reset (through TRSTB). To obtain the JTAG reset (TRSTB) of the FREEDM-32P672 chip, PCI TRST is ANDed with PCI RST. For more information about JTAG, see JTAG Signals. To prevent the PCI RST signal from being connected to two loads, the signal is passed through an AND gate with the other input being pulled high. The output of this AND gate is connected to the FREEDM-32P672 RSTB signal and is also used for generating the TRSTB signal. The FREEDM-32P672 chip has only one interrupt pin, PCIINTB. This chip is not a multifunction device, meaning that several independent functions are not integrated into a single device. Since there is only one interrupt pin, it is routed to INTA. The other three interrupt lines, INTB, INTC and INTD, remain unconnected. 4.2 Description of Functional Blocks
4.2.1 Clock Generation The development kit supports several modes of operation, resulting in the use of oscillators of specific frequencies. Table 5 shows the use of oscillators on the board and its corresponding frequency.
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PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
Table 5: Frequencies of Oscillators for Board Use
Clock Frequency 1.544 MHz 2.048 MHz 4.096 MHz 44.736 MHz 52.000 MHz 40 MHz Purpose of Use Needed for T1 mode of operation (clock fed to TCLK and RCLK). Needed for E1 mode of operation (clock fed to TCLK and RCLK). Needed for 2.048 Mbps H-MVIP mode (clock fed to TMVCK and RMVCK). Needed for DS-3 mode (clock fed only to TCLK[2..0] and RCLK[2..0]). Needed for Unchannelised mode (clock fed only to TCLK[2..0] and RCLK[2..0]). Needed in case PCICLKO is not used as SYSCLK.
The oscillator supplying a 16.384 MHz signal for the 8 Mbps HMVIP clock is not provided on the board. This mode of operation is possible only with frame pulse signals, which must be provided from an external source. The clock must also be provided by the external source. The oscillators have a stability of 25 ppm and can drive 10 TTL loads. They are all 14-pin DIP-type oscillators and fit in standard sockets. All the sockets used on the board are manufactured by ARIES Electronics (part no. 1107741, reference [9]). Table 6 provides the oscillators that can be used in these sockets. Test points are provided for testing the line clocks and the external clocks. Table 6: Sockets for the Various Oscillators
Socket Number OSC 1 OSC 2 OSC 3 OSC 4 OSC 5 Oscillator Placed in the Socket 1.544/2.048 MHz (links 0 through 15) 4.096 MHz 52/44.736 1.544/2.048 MHz (links 16 through 31 40 MHz
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The following different configurations are possible: * * * All 32 links are driven by the same reference clock. Links 0 to 15 are driven by one reference clock, and links 16 to 31 are driven of a different reference clock. Links 0 to 2 are driven by another reference clock of high frequency, up to 52 MHz.
All the oscillators are socketed. The oscillator in socket OSC1 drives RCLK[15..0] and TCLK[15..0]. The oscillator in socket OSC4 drives RCLK[31..16] and TCLK[31..16], ensuring that just changing the oscillator can provide different frequencies. Table 7 shows you how to place the oscillators in sockets to achieve the above-mentioned configurations. Table 7: Possible configurations of RCLK and TCLK
OSC1 1.544 MHz 2.048 MHz 1.544 MHz OSC4 1.544 MHz 2.048 MHz 2.048 MHz Configuration Achieved All transmit and receive links at 1.544 MHz All transmit and receive links at 2.048 MHz TCLK[15..0] at 1.544 MHz, TCLK[31..16] at 2.048 MHz RCLK[15..0] at 1.544 MHz, RCLK[31..16] at 2.048 MHz 2.048 MHz 1.544 MHz TCLK[15..0] at 2.048 MHz, TCLK[31..16] at 1.544 MHz RCLK[15..0] at 2.048 MHz, RCLK[31..16] at 1.544 MHz
4.2.2 Clock Distribution In the development kit, clock frequencies as high as 52 MHz are used on the board. Clock generation circuits (oscillators) only generate the various clock frequencies. It is the task of the clock distribution network to distribute the clock to the various pins of the FREEDM-32P672 chip. Clock drivers are used in preference to line drivers on the board to prevent excessive fan-out of the oscillators. The TCLK and RCLK signals from the clock driver outputs are routed to the various pins by using traces of equal lengths. One to eight clock drivers are used since the links in most of the cases are grouped in multiples of eight. Each
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output of the clock driver is connected to only one clock pin of the FREEDM32P672 chip. Series termination is used for each clock line driven out of the clock driver. RMVCK, TMVCK, RMV8DC, and TMV8DC are grounded when the development kit is configured to operate in unchannelized T1/E1 mode. RCLK, TCLK, RMV8DC, and TMV8DC are grounded when the development kit is configured to operate in 2.048 Mbit/s H-MVIP mode. RCLK, TCLK, RMVCK, and TMVCK are grounded when the development kit is configured to operate in 8.192 Mbit/s H-MVIP mode. 4.2.3 RMV8DC and TMV8DC Provision RMV8DC and TMV8DC, as mentioned earlier, are respectively the receive and transmit clocks for 8.192 Mbps H-MVIP operation. The clocks are not generated on the board. Header P4 is provided to allow for external connections. Table 8 shows the jumper settings over header P4 for two different configurations. Table 8: Configuration for RMV8DC and TMV8DC Provision
Pins Shorted (on header P4) c0 shorted to d0, c1 shorted to d1 Wire to board connector plugged into pins c0, c1, d0, and d1 Configuration Achieved TMV8DC and RMV8DC are grounded 16.384 MHz provided to TMV8DC and RMV8DC
NOTE: The RMV8DC and TMV8DC signals from the external source are made inputs to the FREEDM-32P672 chip by plugging a wire to board connector onto pins c0, c1, d0, and d1 of header P4. 4.2.4 RCLK Distribution RCLK is the receive data clock input to the FREEDM-32P672 chip for unchannelised T1/E1 and DS-3/unchannelised (52 MHz) mode of operation. RCLK should be grounded when the development kit is not configured for either of these two modes of operation. On the board, RCLK and TCLK are obtained from the same oscillator to facilitate external loopback. However, a provision is
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made for clocks from external sources, whereas RCLK and TCLK can be from different sources. Clock signals applied to RCLK have the following frequencies, depending on the modes of operation. * * * * 1.544 MHz - for T1 configuration 2.048 MHz - for E1 configuration 44.736 MHz - for DS3 configuration 52 MHz - for unchannelized mode configuration
For unchannelized T1/E1 configuration, the distribution of the clock is such that an oscillator placed in socket OSC1 can drive each of the links (receive and transmit) from 0 through 15. Also, the oscillator placed in socket OSC4 can drive each of the remaining links (transmit and receive). In the case of unchannelized 44.736/52 MHz configuration, all the receive links from 0 to 2 can be driven either at 44.736 MHz or at 52 MHz. The 44.736/52 MHz oscillator must be placed in socket OSC3. Links 3 to 31 are not used when all the links from 0 to 2 are driven at 52 MHz. If links 0 to 2 are not all used for the 52/44.736 MHz operation, the oscillator in socket OSC1 can drive each of the receive (and transmit) links from 3 to 15. The oscillator placed in socket OSC4 can drive the receive (and transmit) links from 16 to 31. However, in this configuration, the aggregate data rate over all links should not exceed 64 Mbit/s. The unused clock lines are grounded using jumpers. Proper configuration of the above-mentioned modes can be done using jumpers. Figure 2 shows the clock distribution to RCLK. Two drivers are used for driving the 52 MHz/ DS3 clock for TCLK[2..0] and RCLK[2..0]. The driver can operate in the 40 MHz - to 80 MHz range, only if one bank of four outputs is being used.
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Figure 2: Configuration for Distribution of RCLK
U3 P7 U3
5V 1G 2G C1 C3 C5 B1 B3 B5 A1 A3 A5 1G 2G 5V
OSC1
P12
A0 A1 A2 . . . A15 B0 B1 B2 . . . B15 C0 C1 C2 . . . C15
OSC1 U2
5V 1G 2G
FREEDM-32P672
RCLK[15..0]
P11 U7
5V 1G 2G A16 A17 A18 . . . A31 B16 B17 B18 . . . B31 C16 C17 C18 . . . C31
RCLK[31..16]
OSC4 U6
5V 1G 2G
Table 9 shows how the different configurations for RCLK can be achieved. Table 9: Configuration for RCLK Distribution
Jumper Settings at Header P7 c1...c3 shorted to b1...b3 Jumper Settings at Header P12, P11 P12 b0...b15 shorted to a0...a15 P11 b16...b31 shorted to a16...a31 b1...b3 shorted to a1...a3 P12 b0...b2 shorted to a0...a2 P12 b3...b15 shorted to c3...c15 P11 b16...b31 shorted to c16...c31 Unchannelized DS3/52 MHz operation on links 1-3 Configuration Achieved
Unchannelized T1/E1
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PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
P12 b0...b15 shorted to c0...c15 P11 b16...b31 shorted to c16...c31
RCLK disabled for H-MVIP mode
Two pin-shorting jumpers are used to achieve the above-mentioned configurations. For mixed mode operation, only a few RCLK are used. The rest are grounded. RCLK from an external source can be sourced to the FREEDM-32P672 chip by plugging a wire to board connector into pins b1...b32, c1...c32 of headers P11 and P12. The grounded c1...c32 pins provide the necessary shielding to the external cable. Sullins Electronics manufactures all the headers used on the board. Oupiin (part no. 2006A[13]) manufactures the jumpers used on the board. All clock drivers used on the board are 1 to 8 clock drivers manufactured by Texas Instruments (part no. CDC341 [10]). To enable the outputs of the clock drivers, apply logic high (H) voltages to the enable pins of the driver IC. Table 10 shows the functionality of the clock driver. Table 10: Function Table of 1-to-8 Clock Drivers Function Table of 1 to 8 Clock Drivers Inputs Outputs 1G 2G A 1Y1-1Y4 X X L L L L H L L H H L H L H H H H L L H H H H
2Y1-2Y4 L L H L L H
From Table 10, it is clear that pins 1G and 2G should both be at a high (H) logic level for driving the eight output lines. High logic level on pin 1G results in input A being driven onto output lines 1Y1-1Y4. Similarly, a high logic level on pin 2G results in input A being driven onto output lines 2Y1-2Y4. Providing 5V to 1G and 2G pins permanently enables the outputs of all clock drivers on the board.
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PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
4.2.5 TCLK Distribution TCLK is the transmit data clock input to the FREEDM-32P672 chip, for unchannelized T1/E1 and DS-3/ 52 MHz modes of operation. TCLK should be grounded when the development kit is not configured for these two modes of operation. To facilitate external loopback, RCLK and TCLK are obtained from the same oscillator. However, a provision is made for clocks from external sources, whereas RCLK and TCLK can be from different sources. Clock signals applied to TCLK have the following frequencies, depending on the mode of operation: * * * * 1.544 MHz - for T1 mode 2.048 MHz - for E1 mode 44.736 MHz - for DS3 mode 52 MHz - for unchannelized mode configuration
The distribution of the clock is such that each of the transmit links from 0 to 15 can be driven by an oscillator placed in socket OSC1. Each of the remaining transmit links can be driven by the oscillator placed in socket OSC4. TCLK[2..0] can also be driven at 44.736/52 MHz by the oscillator in socket OSC3. Figure 3 shows the distribution of TCLK, which is similar to that of RCLK. Two drivers are used for driving 52 MHz/ DS3 clock for TCLK[2..0] and RCLK[2..0]. The driver can operate in the 40 MHz to 80 MHz range only if one bank of 4 outputs is being used.
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PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
Figure 3: Distribution of TCLK
U10 P7 U4
5V 1G 2G C1 C3 C5 B1 B3 B5 A1 A3 A5 1G 2G 5V
OSC3
P13
A0 A1 A2 . . . A15 B0 B1 B2 . . . B15 C0 C1 C2 . . . C15
OSC1 U5
5V 1G 2G
FREEDM-32P672
TCLK[15..0]
P14 U9
5V 1G 2G A16 A17 A18 . . . A31 B16 B17 B18 . . . B31 C16 C17 C18 . . . C31
TCLK[31..16]
OSC4 U8
5V 1G 2G
Table 11 shows how the different configurations for TCLK can be achieved Table 11: Configuration for the Distribution of TCLK
Jumper Settings at Header P7 a0...a2 shorted to b0...b2 b0...b2 shorted to c0...c2 Jumper Settings at Header P13, P14 P13, P14 b0...b31 shorted to a0...a31 P13 b0...b2 shorted to a0...a2 P13 b3...b15 shorted to c3...c15 P14 b16...b31 shorted to c16...c31 P13, P14 b0...b31 shorted to c0...c31 TCLK disabled for H-MVIP mode Configuration Achieved
Unchannelized T1/E1 Unchannelized 44.736/52 MHz for links 1-3
Two pin-shorting jumpers are used to achieve the above-mentioned configurations. For mixed mode operation, only a few TCLK are used. The rest are grounded.
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PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
TCLK from an external source can be given to the FREEDM-32P672 chip by plugging a wire to board connector onto pins b0...b31, c0...c31 of headers P13 and P14. The grounded c0...c31 pins provide the shielding for the external cable. 4.2.6 RMVCK and TMVCK Distribution When the Development Kit is not configured for 2.048 Mbit/s H-MVIP operation, RMVCK[3..0] and TMVCK[3..0] are pulled down to ground. Figure 4 shows the distribution of RMVCK and TMVCK. Table 12 shows the jumper settings over headers P5 and P6 for two different configurations. Table 12: Configuration for RMVCK and TMVCK
Pins Shorted on Headers P5, P6 b0...b3 shorted to a0...a3 b0...b3 shorted to c0...c3 Configuration Achieved TMVCK and RMVCK frequency = 4.096 MHz TMVCK and RMVCK disabled for non-MVIP mode
Figure 4: RMVCK and TMVCK Distribution
TMVCK[3..0] P6
A0 A1 A2 A3 B0 B1 B2 B3 C0 C1 C2 C3
U1
OSC2 P5
A0 A1 A2 A3 B0 B1 B2 B3 C0 C1 C2 C3
RMVCK[3..0]
TMVCK and RMVCK from an external source can be given to the FREEDM32P672 chip by plugging a wire to board connector into pins b0...b3, c0...c3 of headers P5 and P6. The grounded c0...c3 pins provide the shielding for the external cable.
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PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
4.2.7 Clock Drivers The total number of clock lines (not including those for H-MVIP mode) to be driven by the clock drivers is 70. This includes: * * * 32 lines driven by oscillator in socket OSC1 (RCLK[15..0] and TCLK[15..0]). 32 lines driven by oscillator in socket OSC4 (RCLK[31..16] and TCLK[31..16]). 6 lines driven at 44.736 MHz/52 MHz (RCLK[2..0] and TCLK[2..0]).
Figure 5 shows the connections between the clock oscillators and the clock drivers. In total, 11 clock driver ICs (each one is a 1 to 8 clock driver) are used, including one for RMVCK and TMVCK. Figure 5: Clock Drivers Used for Distribution of Line Clocks
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PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
OSC1
U3
RCL1.5[7..0]
U2
RCL1.5[15..8]
U4
TCL1.5[7..0]
U5
TCL1.5[15..8]
OSC4
U7
RCL1.5[23..16]
U6
RCL1.5[31..24]
U9
TCL1.5[23..16]
U8
TCL1.5[31..24]
OSC3
U10
TCL52[2..0]
U11
RCL52[2..0]
OSC2
U1
TMVCK[3..0] RMVCK[3..0]
NOTE: U1 to U11 are 1 to 8 clock drivers (part no. CDC341 manufactured by Texas Instruments). 4.2.8 Provision for Loopback of Data There is a provision on the board for performing either loopback of TD[31..0] or connecting TD[31..0] to an external system. RD[31..0] can be connected to either TD[31..0] (in case of loopback) or an external system. Figure 6 shows the configuration of headers for performing loopback on a per link basis. P15 and P10 are dual row headers with 32 positions. Table 13 shows the jumper settings for loopback configuration.
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PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
Figure 6: Configuration for the Loopback of Data
P2 RBD P15 TBD
A0 B0 A1 B1 A2 B2 . . . . . . A15 B15 A1 A2 A3 A4 B1 B2 B3 B4
FREEDM-32P672
TD[0] TD[1] TD[15..2] TD[31..16]
P10
A16 A17 A18 . . . A31 B16 B17 B18 . . . B31
RD[0] RD[1] RD[15..2] RD[31..16]
Table 13: Configuration for the Loopback of Data
Jumper Setting at Headers P15, P10 P15 a2...a15 shorted to b2...b15 P10 a16...a31 shorted to b16...b31 P15 a2...a15 shorted to b2...b15 P10 a16...a31 shorted to b16...b31 a2 shorted to a3, b2 shorted to b3 Simultaneous loopback on links 0 to 31. Jumper Setting at Header P2 a2 shorted to b2, a3 shorted to b3 Configuration Achieved
Simultaneous cross-connect on links 0 and 1, loopback in others.
NOTE: Loopback can be performed on a per link basis by using two pin-shorting jumpers over headers P15 and P10. Pins a2...a15 of header P15, a16...a31 of header P10, and pins b3 and a2 of header P2 are used as the physical interface with the external source for TD. b2...b15 of header P15, b16...b31 of header P10, and pins b2 and a3 of header P2 are used as the physical interface with the external source for RD. Wire to
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PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
board connectors are used to interface the external source with FREEDM32P672 inputs TD and RD. The following configurations can be performed for the loopback of data from TD[31..0] to RD[31..0]. Figure 7: Simultaneous Cross-Connect and Loopback of 52 Mbit/s Data Stream (P2).
To RD[1] FROM TD[1] A2 B2 A3 B3 FROM TD[0] To RD[0] To RD[1] FROM TD[1] A2 B2 A3 B3 FROM TD[0] To RD[0]
4.2.9 Simultaneous Cross-Connect and Loopback of Two 52 Mbit/s Data Streams You can accomplish a simultaneous cross-connect by placing shorting jumpers over (a2, b2) and (a3, b3), as shown in Figure 7. In this configuration, RD[0] gets data from TD[1], whereas RD[1] gets data from TD[0]. You can perform a simultaneous loopback by placing shorting jumpers over (a2, a3) and (b2, b3), as shown in Figure 7. In this configuration, RD[0] gets data from TD[0], whereas RD[1] gets data from TD[1]. 4.2.10 Loopback of Unchannelised T1/E1 Data Streams In Figure 6, the loopback of unchannelized T1/E1 data streams on links 2 to 31 can be performed by using shorting jumpers on headers P15 and P10. The remaining two links can also be used for unchannelized T1/E1 operation. In that case, loopback is achieved by using shorting jumpers over header P2. 4.2.11 Miscellaneous Signals The FREEDM-32P672 chip has several miscellaneous signals on pins such as SYSCLK, RSTB, M66EN, PMCTEST, TCK, TMS, TDI, TDO, and TRSTB. 4.2.12 SYSCLK Provision With a frequency of 33 MHz/ 40MHz. SYSCLK can be provided in two different ways to the FREEDM-32P672 chip. One is to use the PCICLKO clock output of the FREEDM-32P672 device by feeding it back to the SYSCLK input. However, this will provide only a 33 MHz SYSCLK. When the PCI bus is operating at 66 MHz, to obtain a 40 MHz SYSCLK a 40 MHz oscillator needs to
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PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
be used. Figure 8 shows a jumper that enables configuration to any of the two frequencies. A single row 3 pin header (P3) is used for SYSCLK provision. The SYSCLK input can be fed the oscillator-generated clock by shorting pins a1 and b1 using a two-pin shorting jumper. PCICLKO clock output can be fed to the SYSCLK input by shorting pins b1 and c1 of header P3. Figure 8: SYSCLK Provision
AB C P3 To FREEDM SYSCLK I/P PCICLKO
40 MHz
4.2.13 M66EN The M66EN signal reflects the speed of operation of the PCI bus. M66EN is set high (by the system motherboard) for 66 MHz, and low for 33 MHz operation on the PCI bus. A trace from the M66EN pin of the PCI connector is routed to the M66EN pin of the FREEDM-32P672 chip. 4.2.14 JTAG Signals TCK, TMS, TDI, TDO, and TRSTB pins of the FREEDM-32P672 carry the JTAG signals. Traces from the JTAG pins TCK, TMS, TDI, and TDO, of the PCI connector, are directly routed to the corresponding pins of the FREEDM32P672 chip. However, TRSTB is asserted low whenever RST# (of PCI connector) is asserted low. Figure 9 shows how this is done by using AND gates on the board. The 74LCX08 from Fairchild Semiconductor is used for this purpose. Its inputs are 5V tolerant.
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PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
Figure 9: JTAG Signals
PCI Interface FREEDM-32P672
TCK TMS TDI TDO 3.3V RST#
U13
TCK TMS TDI TDO RSTB TRSTB
U13
TRST#
4.2.15 Production Test Interface Signals To enable normal operation of the FREEDM-32P672 chip, PMCTEST is grounded. 4.2.16 Power The FREEDM-32P672 development kit board consists of multiple planes. The ground plane has ground potential provided by the PCI connector. The power plane has islands of 5 V, 3.3 V, and 2.5 V. The PCI connector provides 5 V for the 5 V island. The 3.3 V island may be powered either by the 3.3 V supply from the PCI connector (as in the case of the 3.3 V signalling environment) or by a 3.3 V regulated supply on the PCB (as in the case of the 5 V signalling environment). The 2.5 V island on the power plane is connected to the 2.5V potential of the 2.5 Volt regulator. NOTE: The PCI connector is the only source of power for the development toolkit. Figure 10 shows the provision of voltages to the power plane. In a 3.3 V signalling environment, header pins b1 and b2 should be shorted respectively to pins c1 and c2, by means of jumpers. In a 5 V signalling environment, header pins a1 and a2 should be shorted respectively to pins b1 and b2, by means of jumpers.
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PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
Figure 10: Provision of 2.5V, 3.3V and 5V to the Power Plane
To 3.3V Plane
PCI Interface
To 5V Plane
2.5V Regulator 3.3V Regulator
P16
A1 B1 C1 A2 B2 C2
To 2.5V Plane
5V
3.3V
4.2.17 Power Calculations The maximum power allowed for the PCI board is 25 watts and represents the total power drawn from all of the power rails provided at the connector. In the worst case, all 25 watts could be drawn from either the +5V or +3.3V rail. The 5V rail powers the oscillators and the clock drivers. In the 3.3 V signaling environment, the 3.3 V rail powers the 2.5 V regulator, the AND gate, and the FREEDM-32P672 chip. In a 5 V signaling environment, the 3.3 V rail is obtained from the 5 V rail itself. Table 14 and Table 15 show the tabulations for the maximum power consumption values for all devices on the board. Table 14: Power Calculations (5 V Signaling Environment)
Device Consumed current (A) I = (no. of devices) x ( I device) 2 x 0.025 2 x 0.025 1 x 0.025 1 x 0.025 1 x 0.060 Consumed power (W) P 5 = 5.5 x I 0.275 0.275 0.1375 0.1375 0.33
1.544 MHz oscillator (2 nos.) 2.048 MHz oscillator (2 nos.) 4.096 MHz oscillator (1 no.) 8.192 MHz oscillator (1 no.) 52/44.736 MHz
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PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
oscillator (1 no.) 40 MHz oscillator (1 no.) CDC341 (11 nos.) LT1528CQ 1 x 0.040 11 x 0.033 x 1.0 (Current drawn by 3.3V and 2.5V power rail of FREEDM32P672) Maximum power required 8.8715 0.22 1.9965 5.5
Table 15: Power Calculations (3.3 V Signaling Environment)
Device Consumed current (A) I = (no. of devices) x ( I device) Consumed power (W) P 3.3 = 3.6 x I P 3.3 = 5.5 x I ( for devices with 5 V supply) 0.275 0.275 0.1375 0.1375 0.33 0.22 1.9965 0.36 2.52
1.544 MHz oscillator (2 nos.) 2.048 MHz oscillator (2 nos.) 4.096 MHz oscillator (1 no.) 8.192 MHz oscillator (1 no.) 52/44.736 MHz oscillator (1 no.) 40 MHz oscillator (1 no.) CDC341 ( 11 nos) AND gate MIC39150 (1 no.)
2 x 0.025 2 x 0.025 1 x 0.025 1 x 0.025 1 x 0.060 1 x 0.040 11 x 0.033 1 x 0.100 1 x 0.700 (2.5 V power rail of FREEDM-32P672)
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PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
FREEDM-32P672 (1 no.) Maximum power required
1 x 0.200 (3.3V power rail of FREEDM32P672)
0.72
6.9715
NOTE: The current taken by the FREEDM-32P672 chip from the 2.5 V rail is assumed to be 700 mA (maximum). The current taken by the FREEDM-32P672 chip from the 3.3 V rail is assumed to be 200 mA (maximum). 4.2.18 Voltage Regulation The FREEDM-32P672 chip needs 3.3 V I/O pad power and 2.5 V core logic power. Voltage regulators are required for providing 2.5 V and 3.3 V to the FREEDM-32P672 device. The various criteria for choosing a voltage regulator are: * * * * Stable output voltage with a good load regulation. Low dropout. Good thermal characteristics. Board space occupied by the regulators and their heat sinks.
The regulated 3.3 V (obtained from 5 V) would be used when the universal card is plugged into a 5V signaling environment. The 3.3 V from the PCI connector is used when the PCI card is plugged into a 3.3V signaling environment. Power requirement on the 3.3 V rail of the FREEDM-32P672 chip is about 227 mW. The corresponding current comes out to be around 68 mA. However, the 2.5 V regulator also sources current from the 3.3 V rail. This current is about 320 mA. Hence the current rating of the 3.3 V regulator should be the sum of these two currents. LT1528CQ, a 3.3 V regulator from Linear Technology [6] is used on the add-on card. Heat sink area calculations for this regulator are shown below. Calculation of maximum power dissipation in the 3.3 V regulator: For proper design, the worst case values for all the parameters are used. Worst case Vin is high supply; in this case, 5 V + 10% or 5.5 V. Worst case Vout for thermal conditions is minimum, or 3.3 V - 2%, or 3.234 V. Iout is taken at its
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PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
highest steady state value, that is, 1 A. The ground current value of 10 mA comes from the device's datasheet (reference), from the Ignd vs. Iout plot . Pd (max) = [ ( Vin - Vout ) x ( Iout ) ] + [ (Vin ) x ( Ignd ) ] = [ (5.5 - 3.234)x(1) ] + [ (5.5) x (.01) ] = 2.266 + 0.055 = 2.321 W Calculation of Junction to Ambient Thermal Resistance (for 3.3 V): ja ja = [ ( Tj - Ta ) / Pd ] - [jc + cs ] = [ (125 - 70) / 2.321] = 23.7 oC/W
From the device datasheets provided by Linear Technology (reference), 2500 square mm of copper area is required on both sides of the board for the 3.3 V regulator's heat sink. The voltage regulator used to provide 2.5 V to the VDD2V5 pin of the FREEDM-32P672 chip should have a current rating of at least 320 mA. MIC39150-2.5BU [5], manufactured by MICREL, comes in a TO-263 package and matches our requirements. Proper voltage regulator design involves calculation of the thermal resistance, from which heat sink area can be computed. This section shows the calculations for MIC39150-2.5BU (used in the development kit). Calculation of maximum power dissipation in the 2.5 V regulator: For proper design, the worst case values for all the parameters are used. Worst case Vin is high supply; in this case, 3.3 V + 10% or 3.63 V. Worst case Vout for thermal conditions is minimum, or 2.5 V - 2%, or 2.45V. Iout is taken at its highest steady state value, that is,. 700 mA. The ground current value of 7.5 mA comes from the device's datasheet [5], from the Ignd vs Iout plot . Pd (max) = [ ( Vin - Vout ) x ( Iout ) ] + [ (Vin ) x ( Ignd ) ] = [ (3.63 - 2.45)x(0.7) ] + [ (3.630) x (.0075) ] = 0.826 + 0.027225 = 0.853225 W Calculation of Heat Sink Thermal Resistance (for 2.5 V regulator): sa sa = [ ( Tj - Ta ) / Pd ] - [jc + cs ] = [ (125 - 70) /0.853225] - [ 2 + 2 ] = 64.46 - 4 = 60.46 oC/W
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PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
From the heat sink design curves provided by Micrel [7], at least 500 square mm of copper area is required on the board for the 2.5 V regulator's heat sink. 4.3 Design Alternatives
4.3.1 Using Enable Pins of Clock Drivers The clock inputs to the FREEDM-32P672 chip should not be kept hanging. If they are not used, they should be pulled down to ground. In the alternative design of the development kit, the enable pins of clock drivers are used to disable (pulled down to ground) the output of the clock drivers. The alternative design occupies lesser board space, but reduces the flexibility of configuring the modes of operation. This is because the output lines of the clock drivers can be disabled or enabled, only in groups of four [10]. Figure 11 shows the alternative design. Figure 11: Alternative Design for clock distribution in the Development Kit
3.3V 3.3V
A1 A2 A3 B1 B2 B3
1G 2G
A1 A2 A3
B1 B2 B3
C1 C2 C3
1G 2G
A1 B1 C1 A2 B2 C2
3.3V
OSC
OSC
A1 A2 A3 A4 A5 A6 A7 A8
B1 B2 B3 B4 B5 B6 B7 B8
A1 A2 A3 B1 B2 B3
3.3V
1G 2G A1 A2 A3 B1 B2 B3 C1 C2 C3
3.3V
OSC
A1 A2 A3 B1 B2 B3
1G 2G
1G 2G
A1 B1 C1 A2 B2 C2
3.3V
A1 A2 A3 B1 B2 B3
FREEDM-32P672
1G 2G
RCLK[15..0] TCLK[15..0]
3.3V
A1 A2 A3 B1 B2 B3
3.3V
1G 2G
RCLK[31..16] TCLK[31..16]
A1 A2 A3 B1 B2 B3
3.3V
1G 2G
A1 A2 A3 B1 B2 B3
3.3V
1G 2G
A1 A2 A3 B1 B2 B3
1G 2G
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PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
As shown in this figure, headers for the external interface are not placed after the clock drivers. A dual row header with eight positions is used for the external interface. A wire to board connector can be plugged into pins b1 to b8, to provide the external clock to RCLK and TCLK inputs of the FREEDM-32P672 chip. Dual row headers with three positions are associated with each clock driver. Pins 1G and 2G of each clock driver in the alternative design can be independently pulled high or low. The drawback of the alternative design is the reduced flexibility in configuring for the different modes of operation of the development kit. This drawback occurs because the clock inputs to the FREEDM-32P672 chip (that is, the outputs of the clock drivers) can be configured only in groups of four. For example, it is not possible to drive RCLK[1..0] at one frequency and have no drive on RCLK[3..2] at all. Table 16 lists the configurations that can be achieved by means of shorting jumpers. Table 16: Jumper Configuration in the Alternative Design
Jumper Settings on the Headers ( Figure 11 ) Wire to board connector plugged into pins b1 to b8 of header J1. Pins a1 to a3 shorted respectively to pins b1 to b3 on headers J10 and J11. Pins a1 and b1 shorted respectively to pins a2 and b2 on headers J2 through J9. Pins a1 to a8 shorted respectively to pins b1 to b8 on header J1. Pins a1 to a3 shorted to pins b1 to b3 on headers J10 and J11. Pins a1 and b1 shorted respectively to pins a2 and b2 on headers J2 through J9. Pins a1 to a8 shorted respectively to pins b1 to b8 on header J1. Pins c1 to c3 shorted to pins b1 to b3 on RCLK[15..3] and TCLK[15..3] driven by the oscillator in socket S1. RCLK[2..0] and TCLK[2..0] driven by the RCLK[15..0] and TCLK[15..0] driven by the oscillator in socket S1. RCLK[31..16] and TCLK[31..16] driven by the oscillator in socket S2. Configuration Achieved
All RCLK and TCLK from an external source.
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31
PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
headers J10 and J11. Pins a1 and b1 shorted respectively to pins a2 and b2 on headers J2 through J9.
oscillator in socket S0 ( 52/44.736 MHz ). RCLK[31..16] and TCLK[31..16] driven by the oscillator in socket S2.
NOTE: Except for those configurations mentioned in Table 16, several different configurations are possible. One such configuration is to have no drive on RCLK[31..16] and TCLK[31..16]. This is achieved by having pins a1 and b1 shorted to pins a2 and b2 respectively, on headers J6 to J9 (see Figure 11).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
32
PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
5
SOFTWARE INTERFACES The software interfaces are described in reference [3].
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
33
PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
6 6.1
MECHANICAL Board size/outline The Universal PCI short card will be used for the FREEDM-32P672 Development Toolkit Design. Its dimensions (form factor) are 6.875 inches x 4.2 inches as per PCI 2.1. The PCI card has an end bracket. All the oscillators on board are socketed. The first five boards also have the FREEDM-32P672 chip socketed. Boards thereafter will have the FREEDM32P672 chip directly soldered to the board. The PMC-Sierra logo is present on all the boards.
6.2
Estimate of real estate
The approximate area occupied by each component on the board is as follows: * * * * * *
1
FREEDM-32P672 CDC341 (11 nos.) MIC39150 (1 no.) LT1528CQ (1 no.) Socket 1107741(6 no Headers (total space) including copper area
: 31 mm x 31 mm : 10.3 mm x 10.3 mm : 640 square mm approx1 : 5140 square mm approx1 : 17.78 mm x 10.16 mm : 375 x 2.54 mm x 2.54 mm
The above-mentioned area sums up to approximately 11415 square mm. The area occupied by other passive components (resistors, capacitors and LEDs) has not been included in the real estate calculation, as they will be placed on the rear side of the board. The area of a universal PCI short card is 18628.995 2 square mm (i.e. 6.875 x 4.2 x (2.54) ). 6.3 Cooling requirements The ambient temperature should not exceed the maximum value of 70 degrees C. The heat sink has been designed considering a maximum ambient temperature value of 70 degrees Celsius.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
34
PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
7
LIMITATIONS There is no on-board provision for the gapping of clock and frame pulse generation. The PCI connector is the sole supplier of power to the development kit. The development kit as a stand alone board does not support the channelized mode of operation. It is assumed that all the clock signals from the external system are buffered. These clocks are not buffered by the drivers on the PCB.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
35
PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
8
REQUIREMENTS TRACEABILITY Table 17: Traceability Matrix
Functionality Supported [4] H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 Section Number
3.3, 6 0 4.2.1 4.1.1, 4.2.8 4.1.1 4.2.18 6.1 6.1 4.2.16, 4.2.1 4.2.8, 4.2.9 3.3 6.1 6.1
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
36
PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
9
BILL OF MATERIALS Table 18: Bill of Materials
Description 2.5 V, 1A Low Dropout Voltage regulator (TO-263) 3.3 V, 3A Low Dropout Voltage regulator Oscillator 1.544 MHz Oscillator 2.048 MHz Oscillator 4.096 MHz Oscillator 52 MHz Oscillator 44.736 MHz Oscillator 40 MHz Socket for Oscillator FREEDM-32P672 Device 1 to 8 clock driver AND gate Dual Row Header (32 positions) Single Row Header (32 positions) Single position shunt S13R8R S13R8R S13R8R S13R8R S13R8R S13R8R 1107741 PM7380 Connor Winfield Connor Winfield Connor Winfield Connor Winfield Connor Winfield Connor Winfield Aries Electronics PMC-Sierra 2 2 1 1 1 1 5 1 LT1528CQ Linear Technology 1 Part Number MIC39150-2.5BU Manufacturer Micrel Quantity 1
CDC341 74LCX08 PZC32DAAN PZC32SAAN 2006A
Texas Instruments Fairchild Semiconductor Sullins Electronics Sullins Electronics Oupiin
11 1 6 4 150
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
37
PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
10
SCHEMATIC DIAGRAMS
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
38
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G
G
F
F
E
PM7380DK
DRAWING TITLE_PAGE TITLE LAST_MODIFIED=Wed Mar 8 10:23:03 2000
E
D
D
C
C
B
B
PMC-Sierra, Inc.
A DOCUMENT NUMBER: DOCNUM DOCUMENT ISSUE NUMBER: ISSUE TITLE: FREEDM-32P672 DEVELOPMENT KIT TITLE PAGE ENGINEER: 10 9 8 7 6 5 4 3 2 ISSUE DATE: YY/MM/DD REVISION NUMBER: 2.0 PAGE:1 1 OF 13 A
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CONTENTS
G G
FREEDM-32P672 REGULATORS, SYSCLK FRAME PULSE
F
PAGE 3
PAGE 4
F
PCI DATA LOOPBACK
E
PAGE 5 PAGE 6 PAGE 7
E
HMVIP AND DS3 CLOCK RCLK AND TCLK DISTRIBUTION RCLK SELECTION
PAGE 8, 9 PAGE 10
D
D
TCLK SELECTION DS3 CLOCK SELECTION TEST POINTS
C
PAGE 11 PAGE 12 PAGE 13
C DRAWING CONTENTS CONTENTS LAST_MODIFIED=Wed Mar 8 10:23:16 2000
B
B
PMC-Sierra, Inc.
A DOCUMENT NUMBER: DOCNUM DOCUMENT ISSUE NUMBER: ISSUE TITLE: FREEDM-32P672 DEVELOPMENT KIT CONTENTS ENGINEER: 10 9 8 7 6 5 4 3 2 ISSUE DATE: YY/MM/DD REVISION NUMBER: 2.0 PAGE:2 1 OF 13 A
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7
6
5 VCC_3
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
VCC_25
C57 2 0.01UF
C83 2 0.01UF
C69 2 0.01UF
C58 2 0.01UF
C55 2 0.01UF
C88 2 0.01UF
C64 2 0.01UF
C84 2 0.01UF
C53 2 0.01UF
C72 2 0.01UF
C92 2 0.01UF
C85 2 0.01UF
H
H
C78 2 0.01UF C81 2 0.01UF C79 2 0.01UF C62 2 0.01UF C63 2 0.01UF C68 2 0.01UF C71 2 0.01UF C77 2 0.01UF C74 2 0.01UF C66 2 0.01UF C80 2 0.01UF C60 2 0.01UF C61 2 0.01UF C65 2 0.01UF
PCI_DEVSEL* PCI_LOCK* PCI_REQ* PCI_GNT*
BI IN OUT
5F4<> 5F4> 5F4< 5F4> 5E4< 5F4<> 5F4<
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DECOUPLING CAPACITORS FOR FREEDM VCC_25
5F4<> BI 5F4<> BI
1
DECOUPLING CAPACITORS FOR FREEDM VCC_3
IN OUT
PCI_INT* PCI_PERR*
PCI_STOP* PCI_IRDY* PCI_SERR*
BI
OUT
G
5G4<> BI
PCI_TRDY* PCI_PAR PCI_FRAME* PCI_CBE<3..0> PCI_AD<31..0> AD<0> AC01 0 AD<1> AB01 1 AD<2> AA03 2 AD<3> AA01 3 AD<4> AA02 4 AD<5> Y03 5 AD<6> W04 6 AD<7> Y01 7 AD<8> W03 8 AD<9> W01 9 AD<10>V03 10 AD<11>V01 11 AD<12>V02 12 AD<13>U01 13 AD<14>U04 14 AD<15>U02 15 AD<16>N04 16 AD<17>N01 17 ADN03 18 AD<19>N02 19 AD<20>M02 20 AD<21>M03 21 AD<22>L03 22 AD<23>L02 23 AD<24>K03 24 AD<25>K02 25 AD<26>K01 26 AD<27>J03 27 AD<28>J02 28 AD<29>J04 29 AD<30>J01 30 AD<31>H03 31 PCI_M66EN
P02 R03 P01 R04 R02 R01 H02 H01 G01 T03 T02 0 1 2 3 Y02 U03 P03 L04
BI
G
5G4<> 5F4> 4E7< 5G4> 5E3>
5G4<> BI 5E10<> BI 5E10<> BI
PCI_CLK PCICLKO PCI_IDSEL
IN
OUT IN
PAR T01 PCICLK G03 PCICLKO G04 IDSEL L01 M66EN AC02
IN
F
VCC_25
E
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
N20 N22 M21 L22 L23 K21 J21 J20 H23 G22 G23 F23 E23 D22 E20 C23 A22 D20 B21 D19 B20 A19 A18 A17 A16 C16 D15 C15 B14 D13 B13 C12 N23 N21 M22 L21 L20 K22 J22 J23 G21 G20 F22 F21 E21 D23 D21 C21 B22 A21 C20 A20 C19 C18 B18 D17 B16 A15 B15 A14 C14 A13 C13 B12 P22 H21 B23 B17 P21 H22 A23 C17 R22 P23 R21 R23 R20
6F9>6F3>6D9> IN
RD<31..0>
RD<0> RD<1> RD<2> RD<3> RD<4> RD<5> RD<6> RD<7> RD<8> RD<9> RD<10> RD<11> RD<12> RD<13> RD<14> RD<15> RD<16> RD<17> RD<18> RD<19> RD<20> RD<21> RD<22> RD<23> RD<24> RD<25> RD<26> RD<27> RD<28> RD<29> RD<30> RD<31>
U12 1P TD<0> W23 TD<1> Y22 TD<2> W20 TD<3> AA22 TD<4> Y20 TD<5> AB23 TD<6> AC22 TD<7> AC21 TD<8> AC20 TD<9> AA19 TD<10> AA18 TD<11> AB18 TD<12> Y17 TD<13> AA17 TD<14> AB16 TD<15> AC15 TD<16> AC14 TD<17> AA14 TD<18> AC13 TD<19> AB13 TD<20> AA12 TD<21> AB11 TD<22> Y11 TD<23> AB10 TD<24> Y09 TD<25> AA08 TD<26> AC08 TD<27> AB07 TD<28> AC07 TD<29> AC06 TD<30> AC05 TD<31> AB04 TCLK<0> TCLK<1> TCLK<2> TCLK<3> TCLK<4> TCLK<5> TCLK<6> TCLK<7> TCLK<8> TCLK<9> TCLK<10> TCLK<11> TCLK<12> TCLK<13> TCLK<14> TCLK<15> TCLK<16> TCLK<17> TCLK<18> TCLK<19> TCLK<20> TCLK<21> TCLK<22> TCLK<23> TCLK<24> TCLK<25> TCLK<26> TCLK<27> TCLK<28> TCLK<29> TCLK<30> TCLK<31> TFPB<0> TFPB<1> TFPB<2> TFPB<3> TMVCK<0> TMVCK<1> TMVCK<2> TMVCK<3> TMV8DC TMV8FPC TFP8B
W21 Y23 Y21 AA23 AB22 AC23 AA21 AB21 AB20 AC19 AC18 AC17 AB17 AC16 AA16 Y15 AB14 Y13 AA13 AB12 AA11 AC11 AA10 AC10 AC09 AB08 AA07 Y07 AB06 AA06 AA05 AC04 V23 AA20 AB15 AA09 V21 Y19 AA15 AB09 U20 V22 U23 Y05 AA04 0 1 2 3
REQB
DEVSELB
GNTB
PCIINTB
TRDYB
IRDYB
STOPB
LOCKB
PERRB
C/BEB<0> C/BEB<1> C/BEB<2> C/BEB<3>
FRAMEB
SERRB
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
F
C91 2 0.01UF
2 0.01UF
2 0.01UF
2 0.01UF
2 0.01UF 1
1
1
1
1
1
2 0.01UF
C51
C73
C56
C87
C75
E
TD<31..0>
OUT
6C3<6D9<6F9<
D
C
10F9> IN
RCLK<0> RCLK<1> RCLK<2> RCLK<3> RCLK<4> RCLK<5> RCLK<6> RCLK<7> RCLK<8> RCLK<9> RCLK<10> RCLK<11> RCLK<12> RCLK<13> RCLK<14> RCLK<15> RCLK<16> RCLK<17> RCLK<18> RCLK<19> RCLK<20> RCLK<21> RCLK<22> RCLK<23> RCLK<24> RCLK<25> RCLK<26> RCLK<27> RCLK<28> RCLK<29> RCLK<30> RCLK<31> RFPB<0> RFPB<1> RFPB<2> RFPB<3> RMVCK<0> RMVCK<1> RMVCK<2> RMVCK<3> RMV8DC RMV8FPC RFP8B PMCTEST TRSTB RSTB RBD RBCLK SYSCLK
FREEDM-32P672
VCC_25
1 1
VCC_3 TO BE PLACED CLOSE TO FREEDM
C2
D
22UF
2
C1
22UF 2
C TCLK<31..0>
IN
RCLK<31..0>
0 1 2 3 0 1 2 3
11F9>
4D1> IN
RFPB<3..0>
TFPB<3..0>
0 1 2 3
IN
4C1>
7E6> IN 7F3> IN 7F3> IN 4D6> IN 6F8< OUT 12F4< OUT
RMVCK<3..0> RMV8DC RMV8FPC RFP8B RBD RBCLK
TMVCK<3..0> TMV8DC TMV8FPC TFP8B TBD TBCLK
IN IN IN IN
7G5> 7F3> 7G3> 4D6>
TBD TBCLK
IN 6C8> 12E4< OUT
TCK TMS TDI TDO
B
B
AB03
T23 T22 U21 U22
C22
T21
K23
4D7> 5C5> 5D10> 5D10> 5E10>
IN IN IN IN IN
SYSCLK FRE_RST* PCI_TCK PCI_TMS PCI_TDI DRAWING FREEDM32P672 FREEDM
FRE_TRST* PCI_TDO
IN OUT
5C5> 5D10<
PMC-Sierra, Inc.
DOCUMENT NUMBER: DOCNUM DOCUMENT ISSUE NUMBER: ISSUE TITLE: FREEDM-32P672 DEVELOPMENT KIT FREEDM-32P672 ENGINEER: ISSUE DATE: YY/MM/DD REVISION NUMBER: 2.0 PAGE:3 2 1 OF 13 A
LAST_MODIFIED=Tue Mar 28 12:55:34 2000 A
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REVISIONS
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H
H
VCC_3 VCC_5
2
G
VCC_3 111P Q2
1 2 200
VCC_25
VCC_5
R8 5 1 4 10UF
G
B1 B2
300
Q1 94P
5V LT1528 3.3V GND SHDN#
1 1 A1 A2
P16 104P
C1
VCC_3 PCI_VCC3
IN
5H5>
1
GND
MIC39150 3.3V 2.5V
SENSE 2
68UF
3 1 2 10UF
A1 A2
B1 B2
C1 C2
C2 1 1 1 1 1 1 1 1 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF C59 0.01UF C54 0.01UF C70 0.01UF C76 0.01UF 2 1 C82
R9
100
C3
C49
C52
C67
1
2
VCC_25
2
2
2
2
C33
C4
R6
117P DS3 GREEN
C5
2
2
1
2
3
2
2
2
2
107P DS1 F YELLOW
2
1
112P DS2 RED
2
1
CAPACITORS FOR PLANE SPLITS F
1
3.3V VOLTAGE REGULATOR 2.5 VOLTAGE REGULATOR
VCC_5
1
0.01UF
0.1UF
E
1
ENABLE S13R8R
OSC5 33P 5V 14
VCC_3
C43
1
C45
2
E P3 32P BC
C1 1 B1 8 7 6 5 8 7 6 5
2
2
134P RN2
RES-PACK
135P RN1
RES-PACK
7
GND
OUTPUT 40MHZ OSC
8
1
22 R126
A
2 A1
22 R168
2
PCICLKO
IN
3G1>
4.7K RES_4_ARRAY
1 2 3 4
4.7K RES_4_ARRAY
SYSCLK
OUT
3B10<
SYSCLK SELECTION
A1
133P P8
B1 C1 B2 C2 B3 C3 B4 C4
1 2 3 4
RFPB<0> RFPB<1> RFPB<2> RFPB<3>
OUT
3C10< 3C10<
A1 B1 C1
D RFP8B TFP8B
OUT OUT
A2
OUT OUT OUT
D
3C10< 3C10<
A2 B2 C2
3B10< 3B2<
A3
A3 B3 C3
A4
A4 B4 C4
4*3 HEADER 132P P1
B1
B2
125P P9
1 C1
VCC_3
4.7K R163 C2 1 4.7K R152 2 A1
B1 C1 B2 C2 B3 C3 B4 C4
TFPB<0> TFPB<1> TFPB<2> TFPB<3>
OUT
3C2< 3C2< 3C2< 3C2<
A1 A2
A1 B1 C1
A2
A1 A2
B1 B2
C1 C2
OUT OUT OUT
A2 B2 C2
A3 2 A4
A3 B3 C3 A4 B4 C4
C
C
4*3 HEADER
FRAME PULSE SIGNALS 2.048 MBPS HMVIP MODE FRAME PULSE SIGNALS FOR 2.048HMVIP MODE
B
B
DRAWING SYSCLK SYSCLK LAST_MODIFIED=Tue Mar 28 12:55:36 2000 A
PMC-Sierra, Inc.
DOCUMENT NUMBER: DOCNUM DOCUMENT ISSUE NUMBER: ISSUE TITLE: FREEDM-32P672 DEVELOPMENT KIT REGULATORS, SYSCLOCK, FRAME PULSE ENGINEER: ISSUE DATE: YY/MM/DD REVISION NUMBER: 2.0 PAGE:4 2 1 OF 13 A
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REVISIONS
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H PCI_VCC3
1 1
H
OUT
4G3<5B5<
22UF
C89
22UF 2
2
C95
BULK CAPACITORS AT POWER ENTRY
VCC_5
1 1
B60
A5 A62 A16 A59 A10 B5 B6 B61 B62 B19 B59 A8 A61
22UF
G
BULK CAPACITORS AT POWER ENTRY
C93 22UF
C90
A27 A21 A33 A39 A45 A53 B25 B31 B36 B41 B43 B54
A60
P17 70P G PAR IDSEL FRAME# TRDY# IRDY# STOP# LOCK# DEVSEL# PERR# SERR# REQ# GNT# RST# CLK INTA# INTB# INTC#
A43 A26 A34 A36 B35 A38 B39 B37 B40 B42 B18 A17 A15 B16 A6 B7 A7 B8
3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
5V 5V VIO VIO VIO 5V 5V 5V 5V VIO VIO 5V 5V
ACK64#
REQ64#
2
2
F
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
A58 B58 A57 B56 A55 B55 A54 B53 B52 A49 B48 A47 B47 A46 B45 A44 A32 B32 A31 B30 A29 B29 A28 B27 A25 B24 A23 B23 A22 B21 A20 B20 A52 B44 B33 B26
3F10<> BI
PCI_AD<31..0>
0 1
AD<0> AD<1> AD<2> AD<3> AD<4> AD<5> AD<6> AD<7> AD<8> AD<9> AD<10> AD<11> AD<12> AD<13> AD<14> AD<15> AD<16> AD<17> AD<18> AD<19> AD<20> AD<21> AD<22> AD<23> AD<24> AD<25> AD<26> AD<27> AD<28> AD<29> AD<30> AD<31>
PCI_PAR PCI_IDSEL PCI_FRAME* PCI_TRDY* PCI_IRDY* PCI_STOP* PCI_LOCK* PCI_DEVSEL* PCI_PERR* PCI_SERR* PCI_REQ* PCI_GNT*
BI OUT BI BI BI BI OUT BI BI IN IN OUT
3G1<> 3F1< 3G10<> 3G10<> 3G10<> 3G10<> 3H1< 3H1<> 3G1<> 3G1> 3H1> 3G1<
UNI_PCI CONNECTOR
F
PCI_CLK PCI_INT*
OUT IN
3G1< 3G1>
C/BE<0># INTD# C/BE<1># PRSNT1# PRSNT2# C/BE<2># TDI TDO TCK TMS TRST# C/BE<3># GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED E SDONE SBO# M66EN
B49
E PCI_CBE<3..0>
2 3
3G10<> BI
A18 A24 A30 A35 A37 A42 A48 A56 B3 B15 B17 B22 B28 B34 B38 B46 B57
A9 A11 B10 A14 B14 A19
B11
A40 A41
A4 B4 B2 A3 A1
B9
B1 A2
-12V +12V
PCI_M66EN
0.01UF 1
OUT
3F1<
3A10< OUT 3B4> IN 3B10< OUT 3A10< OUT
PCI_TDI PCI_TDO PCI_TCK PCI_TMS
D
2
C94
D
VCC_3
1
2 0.01UF
C86
C
1 2 3 4 5 6 7
U13 VCC_3 93P VCC 14 I1 I5 13 I2 I6 12 O1 O3 11 I3 I4 I7 10 O2 PCI I8 9 GND O4 8 7408
4.7K 1 R174 2
FRE_TRST*
OUT
3B4<
RST CONNECTED TO ONLY ONE LOAD
VCC_3
FRE_RST*
C
OUT
3B10<
DRAWING PCI PCI LAST_MODIFIED=Tue Mar 28 12:55:38 2000
B VCC_5 PCI_VCC3
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 1 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF C115 C114 C113 C110 C109 C112 C108 C111 C107 C101 C100 C106 C105 C104 C103 C102 1
IN
B
5H5>
C99
C98
C97
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C96
PMC-Sierra, Inc.
A
DECOUPLING CAPACITORS FOR PCI VCC_5
DECOUPLING CAPACITORS FOR PCI VCC_3
DOCUMENT NUMBER: DOCNUM DOCUMENT ISSUE NUMBER: ISSUE TITLE: FREEDM-32P672 DEVELOPMENT KIT PCI CONNECTOR ENGINEER: ISSUE DATE: YY/MM/DD REVISION NUMBER: 2.0 PAGE:5 2 1 OF 13
A
10
9
8
7
6
5
4
3
C
D
A E F G H
B
10 4*2 HEADER P2 239P
A1
10
A1 A2
OUT IN
B1 B2
3E10< 3E2>
B2 B3 1 2 22
B1
TD<0>
1 R141 A3 22 2 A2
RD<1>
3E2> IN 3E10< OUT
9 A3 TD<1> A4 B4
B4 R138
9
B3
RD<0>
A4 A1
A1 A2
B2 B3 B4 B5 2
B1 B2 B3 B4 B5 B6 B7 B8
B1
RBD
TBD
A2 2 1 22 2 A3
3B2< OUT
IN
3B10>
A3 A4 A5 A6 A7 A8
8
4.7K 1 3 R173 4 5 6 7 8 1 1 R145 22 R146 22 R149 22 11 1 12 1 13 1 14 1 15 1 R148 22 R151 22 R150 22 R153 22 R154 R144 22 2 2 2 2 2 2 2 2 1 R143 22 2 A8 A9 A10 A11 10 1 A12 A13 A14 A15 1 R139 22 2 A7 1 R142 22 2 A6 1 2 A5 2 1 R140 22 2 A4 R147 22
8
3 4 B6 B7 B8 5 6 7
VCC_3 16*2 HEADER A9 A10 A11 A12 A13 A14 A15 A16
A16
B9 B10 B11 B12 B13
B9 B10 B11 B12 B13
8
7
9
7
9 10 11 12
B14
B14 13
B15
B15 14
B16
B16 15
DATA LOOPBACK CONNECTOR
6 5 DRAWING DATA_LOOPBACK LOOPBACK LAST_MODIFIED=Tue Mar 28 12:55:40 2000 4 3 ENGINEER: 2 PAGE:6 1 OF 13
3E2> IN
6
P15 236P
16 1 17 1 18 1 19 1 20 1 21 1 22 1 23 1 24 1 25 1 26 1 27 1 28 1 29 1 30 1 31 1
22 R155 22 R156 22 R158 22 R157 22 R161 22 R162 22 R159 22 R160 22 R166 22 R169 22 R165 22 R167 22 R164 22 R170 22 R171 22 R172
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12
16 17 18 19 20 21 22 23 24 25
5
16*2 HEADER
4
26 27
B13 B14 B15 B16
B13 B14 B15 B16
28 29 30 31
3
RD<31..2>
P10 170P
ZONE
TD<31..2>
OUT
3E10<
REV
2
DOCUMENT NUMBER: DOCNUM DOCUMENT ISSUE NUMBER: ISSUE ISSUE DATE: YY/MM/DD A REVISION NUMBER: 2.0
DESCRIPTION
REVISIONS
SERIES RESISTORS ARE PLACED CLOSE TO THE FREEDMCHIP
TITLE: FREEDM-32P672 DEVELOPMENT KIT DATA LOOPBACK
1
PMC-Sierra, Inc.
B C D
DATE APPR
E
F
G
H
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
VCC_5
1
1
0.01UF
0.01UF
0.01UF 2
1 C16 C6
C7
2
2
G
HEADER FOR 8.192MBPS HMVIP CLOCKS RMVCK AND TMVCK CLOCK DISTRIBUTION 2.048MBPS HMVIP MODE
A1 2 A2 R39
G
136P P6
B1 C1 B2 C2 B3 C3 B4 C4
TMVCK<0> TMVCK<1> TMVCK<2> TMVCK<3>
OUT OUT OUT OUT
3B2< 3B2< 3B2< 3B2<
A1 A2 A3 A4
A1 A2 A3 A4
P4 145P B1 B2 B3 B4
B1 B2 B3 B4
TMV8FPC
OUT
3B2<
A1 B1 C1 A2 B2 C2
2 A3 R30
TMV8DC
OUT
3B2<
VCC_5
1 1
VCC_5
1 2
47
A3 B3 C3
2 A4 2
47
R11 47
47
1
R2
112P OSC2 F
1
A4 B4 C4 4*3 HEADER
RMV8DC RMV8FPC
OUT OUT
3B10< 3B10<
0.01UF
C12 0.1UF
2 4.7K
R12 4.7K
C10
119P U1 1G 2G EN 5V 5V 5V 1Y1 1Y2 1Y3 1Y4
19 18 16 15 13 12 9 8 5 6
1
ENABLE S13R8R
5V 14
R4
F
2
1
2
1
7
GND
OUTPUT
2 8
22 R10
1
2 3 4 1 7 20 10 11 14 17
4.096MHZ OSC
2
R56
2
2
2Y1 2Y2 2Y3 GND 2Y4 GND P1 GND P2 GND CDC341
2
1
R41 100
100
R49 47
R13
E
1:8 CLOCK DRIVER
R57 47
2
125P P5
B1 A1 C1 B2 C2 B3 C3 B4 C4
R60 47
RMVCK<3> RMVCK<2> RMVCK<1> RMVCK<0>
47
1
1
1
1
1
OUT OUT OUT OUT
3B10< 3B10< 3B10< 3B10<
2
E
A1 B1 C1
A2
1
A2 B2 C2
A3
A3 B3 C3
A4
A4 B4 C4 4*3 HEADER
VCC_5
0.01UF 1 0.01UF 1 0.01UF 1
D
D
C46
C42
2
2
C48
VCC_5
1 0.01UF
VCC_5 TCL52<0> TCL52<1> TCL52<2>
2 2 2 2 R123 R124 R125 R133 4.7K 47 47 47
OUT OUT OUT
2
VCC_5
12D9< 12D9< 12D9<
2 2 2 2 R127 4.7K R134 R129 R128 47 47 47
1
ENABLE S13R8R
C28
C
C32 0.1UF
OSC3 29P 5V 14
RCL52<0> RCL52<1> RCL52<2>
OUT OUT OUT
12F9< 12F9< 12F9<
1
C
7
GND
OUTPUT
8
2
22 R80
1
2 3 4 1 7 20 R132 10 11 14 17
1G 2G EN 5V 5V 5V
U10 35P 1Y1 19 1Y2 18 1Y3 16 1Y4 15 2Y1 2Y2 2Y3 2Y4
13 12 9 8 5 6
2 3 4 1 7 20 R137 10 11 14 17
1G 2G EN 5V 5V 5V
U11 64P 1Y1 19 1Y2 18 1Y3 16 1Y4 15 2Y1 2Y2 2Y3 2Y4
13 12 9 8 5 6
2
2
1
1
1
1
1
1
1
1
VCC_5
0.01UF 1 0.01UF 1
0.01UF
2
2
52MHZ/DS3 OSC
C44
C47
100
GND GND GND P1 GND P2 CDC341
100
GND GND GND P1 GND P2 CDC341
C50
DRAWING HMVIP_CLKS HMVIP LAST_MODIFIED=Tue Mar 28 12:55:42 2000
2
1
2
1
1
2
2
R131
R135
R130
100
100
100
100
R136
1:8 CLOCK DRIVER
2
1:8 CLOCK DRIVER
2
2
B
B
1
1
2
22 R81
1
1
1
DISTRIBUTION OF TCLK<2..0> AND RCLK<2..0>
A
PMC-Sierra, Inc.
DOCUMENT NUMBER: DOCNUM DOCUMENT ISSUE NUMBER: ISSUE TITLE: FREEDM-32P672 DEVELOPMENT KIT HMVIP AND DS3 CLOCKS ENGINEER: ISSUE DATE: YY/MM/DD REVISION NUMBER: 2.0 PAGE:7 2 1 OF 13 A
52 MHZ OR DS3
10
9
8
7
6
5
4
3
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
VCC_5
2
2
0.01UF
0.01UF
0.01UF
2 C22
C17
C14
G
G
1
1
1
1.544MHZ/2.048MHZ RCLK<15..0> DISTRIBUTION
1.544MHZ/2.048MHZ TCLK<15..0> DISTRIBUTION
VCC_5
1 1 2 2
VCC_5
0.01UF
2
2
15P OSC1 F
1
2
2
2
2
2
0.1UF
C11
C26
4.7K
R53 1 4.7K
4.7K
R28 47
R55
R27 47
ENABLE S13R8R
5V 14
R58 4.7K
R59
2
2
2
RCL1.5<0> RCL1.5<1> RCL1.5<2> RCL1.5<3>
R29
VCC_5
OUT OUT OUT OUT
12F4< 12F4< 12F4< 10D3<
TCL1.5<0> TCL1.5<1> TCL1.5<2> TCL1.5<3>
R17 47 R16 47 R14 47 R15 47
OUT OUT OUT OUT
12E4< 12E4< 12E4< 11D3<
R26 47
40P U3 1G 2G EN 5V 5V 5V 1Y1 1Y2 1Y3 1Y4
19 18 16 15 13 12 9 8
72P U4 1G 2G EN 5V 5V 5V 1Y1 1Y2 1Y3 1Y4
19 18 16 15 13 12 9 8
F VCC_5
2 0.01UF 1 0.01UF 1 2 0.01UF 1 1 1 1 1
2
2
1
47
7
C19
R5
1.544MHZ/2.048MHZ OSC
1 7 20 10 11 14 17
2 R54 47 1 R48 47 1 R47 47 1 R38
R63 47
R62 47
R31 47
100
100
R46
E
1
RCL1.5<4> RCL1.5<6> RCL1.5<5> RCL1.5<7>
100
R65
1:8 CLOCK DRIVER
1:8 CLOCK DRIVER
R64 100
1
1
1
OUT OUT OUT OUT
10D3< 10D3< 10D3< 10D3<
1
1
R32
2Y1 2Y2 2Y3 GND 2Y4 GND P1 GND P2 GND CDC341
1 7 20 10 11 14 17 2 2 2 2
R37
47
2
2
47
5 6
2Y1 2Y2 2Y3 GND 2Y4 GND P1 GND P2 GND CDC341
2
2
5 6
2
2
2
TCL1.5<4> TCL1.5<5> TCL1.5<6> TCL1.5<7>
OUT OUT OUT OUT
11D3< 11D3< 11D3< 11D3<
1
1
2
C9
C21
GND
OUTPUT
8
1
22
2
2 3 4
1
1 2 3 4
1
1
1
1
1
22 R7
2
VCC_5 RCL1.5<15> RCL1.5<14> RCL1.5<13> RCL1.5<12>
2 R21 47 R20
OUT OUT OUT OUT
1
E
2
2
4.7K
R51 4.7K
R52
4.7K
R22 47
R61 4.7K
R23 47
R50
47
R18 47
R24 47
R25 47
R19
29P U2 1G 2G EN 5V 5V 5V 1Y1 1Y2 1Y3 1Y4
19 18 16 15 13 12 9 8 5 6 2 2
47
1
1
62P U5 1G 2G EN 5V 5V 5V 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4
19 18 16 15 13 12 9 8 5 6 2 2
2
10D3< 10D3< 10D3< 10D3<
VCC_5
2 2 2
TCL1.5<8> TCL1.5<9> TCL1.5<10> TCL1.5<11>
2
2
2
OUT OUT OUT OUT
11D3< 11D3< 11D3< 11D3<
2
2
1
1
1
1
1
VCC_5
1
22 R3
2
2 3 4 1 7 20 10 11 14 17
1
1
1
0.01UF 1
0.01UF 1
D
0.01UF 2 2 0.01UF 0.01UF 2 C18 C13 C20
0.01UF 1
2 3 4 1 7 20 10 11 14 17
1
1
VCC_5
D
C23
R42 47
R45 47
R36 47
47
R68 47
R67 47
R34 47
R43 100
100
R44
1:8 CLOCK DRIVER
1
1
1
1
R66 100
RCL1.5<11> RCL1.5<10> RCL1.5<8> RCL1.5<9>
OUT OUT OUT OUT
10D3< 10D3< 10D3< 10D3<
100
R40
1
1
1
1
R33
1:8 CLOCK DRIVER
R35
47
2Y1 2Y2 2Y3 GND 2Y4 GND GND P1 GND P2 CDC341
C24
2
2
C8
GND GND P1 GND P2 GND CDC341
1
1
2
1
2
2
2
2
2
2
2
TCL1.5<12> TCL1.5<13> TCL1.5<14> TCL1.5<15>
OUT OUT OUT OUT
11D3< 11D3< 11D3< 11D3<
1
1
1
C
1
2
C
1
22 R1
2
DRAWING CLK_DISTRIBUTION CLK LAST_MODIFIED=Tue Mar 28 12:55:44 2000
B
B
PMC-Sierra, Inc.
A DOCUMENT NUMBER: DOCNUM DOCUMENT ISSUE NUMBER: ISSUE TITLE: FREEDM-32P672 DEVELOPMENT KIT RCLK<15..0> AND TCLK<15..0> ENGINEER: 10 9 8 7 6 5 4 3 2 ISSUE DATE: YY/MM/DD REVISION NUMBER: 2.0 PAGE: 8 1 OF 13 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
VCC_5
2 2 2 0.01UF 1 C15 C41
0.01UF
1
1
0.01UF
C35
G
G
1.544MHZ/2.048MHZ RCLK<31..16> DISTRIBUTION
VCC_5 20P OSC4
1 1 1 2 2
1.544MHZ/2.048MHZ TCLK<31..16> DISTRIBUTION
VCC_5
2 2 2 2
0.01UF
2
2
C31 0.1UF
R101 4.7K
R102
R105 4.7K
4.7K
R85 47
R84 47
R83 47
R82
4.7K
R100
C29
47
R79 47
R73 47
2
R78 47
2
RCL1.5<16> RCL1.5<17> RCL1.5<18> RCL1.5<19>
OUT OUT OUT OUT
10D3< 10D3< 10D3< 10D3<
VCC_5
2 2
TCL1.5<16> TCL1.5<17> TCL1.5<18> TCL1.5<19>
R77
OUT OUT OUT OUT
11D3< 11D3< 11D3< 11D3<
ENABLE S13R8R
5V
14
2
F
1
1
1
1
32P U7
1
80P U9 1G 2G EN 5V 5V 5V 1Y1 1Y2 1Y3 1Y4
2
47
1
1
1
1
1
0.01UF
0.01UF
0.01UF
7
GND
OUTPUT
8
1
2
2
22 R72
2 3 4 1 7 20 10 11 14 17
1G 2G EN 5V 5V 5V
C40
C25
GND GND GND P1 GND P2 CDC341
1:8 CLOCK DRIVER
5 6 2 2 2 2 2 2 R112 47 R117 47 R110 100 R111 R98 47 R94 100
10 11 14 17
5 6 2 2 2 2 2 R109 47 R118 100 R108 47 R99 100 R91 47 2
1:8 CLOCK DRIVER
47
47
E
1 1 1 1 1 1 1 1 1 1 1 1
R92
1
1.544MHZ/2.048MHZ OSC
2Y1 2Y2 2Y3 2Y4
13 12 9 8
1
1
1 7 20
2Y1 2Y2 2Y3 GND 2Y4 GND GND P1 GND P2 CDC341
13 12 9 8
C39
1Y1 1Y2 1Y3 1Y4
19 18 16 15
2 3 4
19 18 16 15
1
1
VCC_5
2 2
F
RCL1.5<20> RCL1.5<21> RCL1.5<22> RCL1.5<23>
1 22 R70 2
OUT OUT OUT OUT
10D3< 10D3< 10D3< 10D3<
TCL1.5<20> TCL1.5<21> TCL1.5<22> TCL1.5<23>
E
OUT OUT OUT OUT
11D3< 11D3< 11D3< 11D3<
VCC_5
2 2 2 2 2 2
2
2
R103 4.7K
R104
R106 4.7K
4.7K
R89 47
R90 47
R88 47
R87
4.7K
R107
R76 47
2
R75 47
R74 47
2
RCL1.5<24> RCL1.5<25> RCL1.5<26> RCL1.5<27>
OUT OUT OUT OUT
10D3< 10D3< 10D3< 10D3<
VCC_5
2 2
TCL1.5<24> TCL1.5<25> TCL1.5<26> TCL1.5<27>
R86
OUT OUT OUT OUT
11D3< 11D3< 11D3< 11D3<
47
1
1
1
1
1
1
1
1
0.01UF
0.01UF
0.01UF
1
2
2
C34
2
22 R69
2 3 4 1 7 20 10 11 14 17
1G 2G EN 5V 5V 5V
R114 47
R113 47
R120 47
GND GND GND P1 GND P2 CDC341
1:8 CLOCK DRIVER
2Y1 2Y2 2Y3 2Y4
13 12 9 8 5 6 2 2 2 2 2 2 R115 100 R116 R95 47 R96 100
1
10 11 14 17
5 6 2 2 2 2 2 R121 100 R122 R119 47 R93 47 2 100 R97
1:8 CLOCK DRIVER
47
1
1
1
1
47
1
1
1
1
1
1
C
RCL1.5<28> RCL1.5<29> RCL1.5<30> RCL1.5<31>
1
1
OUT OUT OUT OUT
10D3< 10D3< 10D3< 10D3<
TCL1.5<28> TCL1.5<29> TCL1.5<30> TCL1.5<31>
1
1
1 7 20
5V 5V 5V
2Y1 2Y2 2Y3 GND 2Y4 GND GND P1 GND P2 CDC341
13 12 9 8
C27
C38
1Y1 1Y2 1Y3 1Y4
19 18 16 15
2 3 4
1G 2G EN
1Y1 1Y2 1Y3 1Y4
19 18 16 15
1
1
D
1
1
19P U6
67P U8
47
VCC_5
2
D
OUT OUT OUT OUT
11D3< 11D3< 11D3< 11D3<
C
1
22 R71
2
VCC_5 B
2 2 0.01UF 0.01UF 0.01UF 2
DRAWING CLK_DISTRIBUTION CLK LAST_MODIFIED=Tue Mar 28 12:55:46 2000 B
C36
1
C30
1
1
C37
PMC-Sierra, Inc.
A DOCUMENT NUMBER: DOCNUM DOCUMENT ISSUE NUMBER: ISSUE TITLE: FREEDM-32P672 DEVELOPMENT KIT RCLK<31..16> AND TCLK<31..16> ENGINEER: 10 9 8 7 6 5 4 3 2 ISSUE DATE: YY/MM/DD REVISION NUMBER: 2.0 PAGE:9 1 OF 13 A
C
D
A E F G H
B
10
3C10< OUT
10
RCLK<31..0>
16*3 HEADER
9
0 1 2 3 4 5 6 A7 A8 7 13 A9 10 A10 15 A11 14 A12 12 A13 11 A14 8 9 A15 A16 B7 C7 0 1 2 A3 A2 A1
9
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B3 C3 B4 C4 B5 C5 B2 C2
B3 C3 B4 C4 B5 C5 B6 C6 B2 C2
B1 C1
B1 C1
12F4> IN
8
3 4 5 6 A6 A5
8
RCL<2..0>
A4
B6 C6 B7 C7 B8 C8 B9 C9 B10 C10 B11 C11 B12 C12 B13 C13 B14 C14 B15 C15 B16 C16
B8 C8 B9 C9 B10 C10 B11 C11 B12 C12 B13 C13 B14 C14 B15 C15 B16 C16
7 13 10
SWAPPING OF PINS HAVE BEEN DONE FOR ROUTING
7
7
15 14 12 11 8 9
16 17 18
A1 A2 A3 19 20 21 22 23 24 A4 A5 A6 A7 A8 A9 25 A10
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
26 A11 27 A12 28 A13 29 A14 30 A15
B1 C1 B2 C2 B3 C3 B4 C4 B5 C5
B1 C1 B2 C2 B3 C3 B4 C4 B5 C5 B6 C6
P12 239P
SELECTION OF RCLK<31..0>
6 5 4
9F6>9E6>9D6>9C6>8F6>8E6>8D6>8C6> IN
6
16 17 18 19 20 21 B7 C7 22
5
B6 C6 B7 C7 B8 C8 B9 C9 B10 C10 A11 A12 A13 A14 A15 A16
31 A16
B8 C8 B9 C9 B10 C10
23 24 25
4
B11 C11 B12 C12 B13 C13 B14 C14 B15 C15 B16 C16
B11 C11 B12 C12 B13 C13 B14 C14 B15 C15 B16 C16
26 27 28 29 30 31
3
P11 240P
ZONE
16*3 HEADER
RCL1.5<31..3>
3 ENGINEER: 2 PAGE:10 1 OF 13 DOCUMENT NUMBER: DOCNUM DOCUMENT ISSUE NUMBER: ISSUE ISSUE DATE: YY/MM/DD A REVISION NUMBER: 2.0 TITLE: FREEDM-32P672 DEVELOPMENT KIT RCLK HEADERS
REV
DRAWING RCLK_SELECTION RCLK
2
DESCRIPTION
REVISIONS
LAST_MODIFIED=Tue Mar 28 12:55:48 2000
1
PMC-Sierra, Inc.
B
DATE APPR
C
D
E
F
G
H
C
D
A E F G H
B
10
3C2<
OUT
10
TCLK<31..0>
PIN NUMBERS 2, 1 AND 0 SWAPPED FOR ROUTING
9 16*3 HEADER
B1 C1 2 B2 C2 1 0 2 1 0 A3 A2 A1
9
A1 A2 A3 A4 A5
B1 C1 B2 C2 B3 C3 B4 C4 B5 C5
B3 C3 B4 C4 B5 C5
8
12D4> IN
3 5 4 6 7 8 A5 A6 A7 A8 A9 9 10 12 11 14 13 15 A10 A11 A12 A13 A14 A15 A4
8
3 5 B6 C6 4
TCL<2..0>
A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16
A16
B6 C6 B7 C7 B8 C8 B9 C9 B10 C10 B11 C11 B12 C12 B13 C13 B14 C14 B15 C15 B16 C16
B7 C7 B8 C8 B9 C9 B10 C10 B11 C11 B12 C12 B13 C13 B14 C14 B15 C15 B16 C16
6 7 8 9 10 12 11 14 13 15
7 PIN NUMBERS 14 AND 15 SWAPPED FOR ROUTING
7
SELECTION OF TCLK<31..0>
6 5 4 3 ENGINEER: 2 PAGE:11 1 OF 13 DRAWING TCLK_SELECTION TCLK DOCUMENT NUMBER: DOCNUM DOCUMENT ISSUE NUMBER: ISSUE ISSUE DATE: YY/MM/DD A REVISION NUMBER: 2.0 TITLE: FREEDM-32P672 DEVELOPMENT KIT TCLK HEADERS LAST_MODIFIED=Tue Mar 28 12:55:49 2000
6
6P P13
16 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 B1 C1
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16
A16
B1 C1 B2 C2 B3 C3 B4 C4 B5 C5
5
B2 C2 B3 C3 B4 C4 B5 C5 B6 C6
17 18 19 20 21 B7 C7 22
B6 C6 B7 C7 B8 C8 B9 C9 B10 C10 B11 C11 B12 C12 B13 C13 B14 C14 B15 C15 B16 C16
9F3>9E3>9D3>9C3>8F3>8E3>8D3>8C3> IN
B8 C8 B9 C9 B10 C10 B11 C11 B12 C12 B13 C13 B14 C14 B15 C15 B16 C16
23
4
24 25 26 27 28 29 30 31
3
ZONE REV
46P P14
16*3 HEADER
TCL1.5<31..3>
2
DESCRIPTION
REVISIONS
1
PMC-Sierra, Inc.
B
DATE APPR
C
D
E
F
G
H
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G
G
2P P7 F
7C4> IN 7C4> IN 7C4> IN
RCL52<0> RCL52<1> RCL52<2>
RCL<0> RCL<1> RCL<2>
B1 C1 B2 C2 B3 C3 B4 C4 B5 C5 B6 C6 B7 C7 B8 C8 B9 C9 B10 C10 B11 C11 B12 C12
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
B1 C1 B2 C2 B3 C3 B4 C4 B5 C5 B6 C6 B7 C7 B8 C8 B9 C9 B10 C10 B11 C11 B12 C12
OUT OUT OUT
10D8< 10D8< 10D8<
F
RCL1.5<0> RCL1.5<1> RCL1.5<2> RBCLK
IN IN IN IN
8F6> 8F6> 8F6> 3B10>
E
E TCL1.5<0> TCL1.5<1> TCL1.5<2> TBCLK
IN IN IN IN
8F3> 8F3> 8F3> 3B2>
7C7> IN 7C7> IN 7C7> IN
TCL52<0> TCL52<1> TCL52<2>
A11 A12
12*3 HEADER D
TCL<0> TCL<1> TCL<2>
OUT OUT OUT
11D8< 11D8< 11D8<
D
SELECTION OF TCLK<2..0> AND RCLK<2..0> FOR 1.544/2.048MHZ OR 52MHZ/DS3 CLOCK
C
C
DRAWING DS3_CLK_SELECTION DS3_CLK LAST_MODIFIED=Tue Mar 28 12:55:50 2000 B B
PMC-Sierra, Inc.
A DOCUMENT NUMBER: DOCNUM DOCUMENT ISSUE NUMBER: ISSUE TITLE: FREEDM-32P672 DEVELOPMENT KIT DS3 CLOCK HEADER ENGINEER: 10 9 8 7 6 5 4 3 2 ISSUE DATE: YY/MM/DD REVISION NUMBER: 2.0 PAGE:12 1 OF 13 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G
G
TEST POINT FOR GND,5V,3.3V AND 2.5V
VCC_5 F 7P TP2 GND T
1
VCC_3 19P TP19 23P TP9 2.5V T
1
VCC_25 F
17P TP5 5V T 16P TP1 5V T 11P TP6 5V T
1 1 1
3.3V
T
1
8P TP3 GND T
1
20P TP15 3.3V T
1
22P TP17 2.5V T
1
6P TP8 GND T E
1
12P TP14 T 3.3V 13P TP7 2.5V T 3.3V
1 1
14P TP18 2.5V T
1
5P TP4 5V GND T
1
10P TP16 T
1
15P TP11 E T
1
4P TP13 GND T
1
2P TP20 GND T
1
3P TP12 D GND T
1
D
1P TP10 GND T
1
C
C
DRAWING TEST_POINTS TEST_POINTS LAST_MODIFIED=Tue Mar 28 12:55:51 2000
B
B
PMC-Sierra, Inc.
A DOCUMENT NUMBER: DOCNUM DOCUMENT ISSUE NUMBER: ISSUE TITLE: FREEDM-32P672 DEVELOPMENT KIT TEST POINTS ENGINEER: 10 9 8 7 6 5 4 3 2 ISSUE DATE: YY/MM/DD REVISION NUMBER: 2.0 PAGE:13 1 OF 13 A
PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
11
LAYOUT
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
39
PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
12
REFERENCES
[1] FREEDM-32P672 DEVELOPMENT KIT Statement of Work (Issue 2: August 1999, Doc no. PMC-990913) [2] FREEDM-32P672 Development kit TEST PLAN (Issue 1, Document no PMC-990860) [3] FREEDM-32P672 Device Data Sheet (Issue 2:May 1999, Doc. No. PMC990262) [4] Requirement Specifications for FREEDM-32P672 DEVELOPMENT KIT (PM7380DK.1.0.RS.1.0) [5] Voltage regulator MIC39150 Device Datasheet. (Manufacturer MICREL, Inc) [6] Voltage regulator LT1528CQ Device Datasheet. (Manufacturer Linear Technology, Inc) [7] Designing PC Board Heat Sinks (Application Hint 17, by MICREL Inc) [8] Oscillator S13R8R Device Datasheet. (Manufacturer: CONNOR -WINFIELD CORPORATION) [9] Oscillator socket 1107741 Device Datasheet. (Manufacturer: ARIES Electronics, Inc) [10] Clock Driver CDC341 Device Datasheet. (Manufacturer: Texas Instruments) [11] Single row header PZCXXSAAN Device Datasheet. (Manufacturer: Sullins Electronics) [12] Dual row header PZCXXDAAN Device Datasheet. (Manufacturer: Sullins Electronics) [13] Jumper 2006A Device Datasheet (Manufacturer: Oupiin)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
40
PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
NOTES
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
41
PRELIMINARY DESIGN DOCUMENT PMC2001841 ISSUE 1
PM2352 FREEDM-32P672
DEVELOPMENT KIT BOARD
CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com (604) 415-4533 http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 2000 PMC-Sierra, Inc. PMC-2001841 (P1) Issue date: December 2000
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE

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