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November 2003 rev 1.1 3.3V Zero-Delay Buffer General Features
* Zero input - output propagation delay, adjustable by capacitive load on FBK input. * Zero input - output propagation delay, adjustable by capacitive load on FBK input. * Multiple configurations - Refer "ASM5P2308A Configurations Table". * * Input frequency range: 10MHz to 133MHz Multiple low-skew outputs. * * * Output-output skew less than 200 ps. Device-device skew less than 700 ps. Two banks of four outputs, three-stateable by two The ASM5P2308A is available
ASM5P2308A
which can be controlled by the select inputs as shown in the Select Input Decoding Table. If all the output clocks are not required, Bank B can be three-stated. The select input also allows the input clock to be directly applied to the outputs for chip and system testing purposes.
Multiple ASM5P2308A devices can accept the same input clock and distribute it. In this case the skew between the outputs of the two devices is guaranteed to be less than 700ps.
in
five
different
configurations (Refer "ASM5P2308A Configurations Table). The ASM5P2308A-1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The ASM5P2308A-1H is the high-drive version of the -1 and the rise and fall times on this device are much faster.
select inputs. * * * * * Less than 200 ps cycle-to-cycle jitter (-1, -1H, -4, -5H). Available in 16-pin SOIC and TSSOP packages. 3.3V operation. Advanced 0.35 CMOS technology. Industrial temperature available.
Functional Description
ASM5P2308A is a versatile, 3.3V zero-delay buffer designed to distribute high-speed clocks. It is available in a 16-pin package. The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback is required to be driven to FBK pin, and can be obtained from one of the outputs. The input-to-input propagation delay is guaranteed to be less than 350ps, and the output-to-output skew is guaranteed to be less than 250ps.
The ASM5P2308A-2 allows the user to obtain 2X and 1X frequencies on each output bank. The exact configuration and output frequencies depends on which output drives the feedback pin. The ASM5P2308A-3 allows the user to obtain 4X and 2X frequencies on the outputs.
The ASM5P2308A-4 enables the user to obtain 2X clocks on all outputs. Thus, the part is extremely versatile, and can be used in a variety of applications.
The ASM5P2308A-5H is a high-drive version with REF/2 on both banks.
The ASM5P2308A has two banks of four outputs each,
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
November 2003 rev 1.1 Block Diagram
/2
REF
ASM5P2308A
ASM5P2308A
PLL FBK MUX CLKA1 CLKA2
/2
Extra Divider (-3,-4) Extra Divider (-5H)
S2 S1 Select Input Decoding
CLKA3 CLKA4
/2
CLKB1 CLKB2
Extra Divider (-2,-3)
CLKB3 CLKB4
Select Input Decoding for ASM5P2308A
S2 0 0 1 1 S1 0 1 0 1 Clock A1 - A4 Three-state Driven Driven
1
Clock B1 - B4 Three-state Three-state Driven Driven
Output Source PLL PLL Reference PLL
PLL Shut-Down Y N Y N
Driven
ASM5P2308A Configurations
Device ASM5P2308A-1 ASM5P2308A-1H ASM5P2308A-2 ASM5P2308A-2 ASM5P2308A-3 ASM5P2308A-3 ASM5P2308A-4 ASM5P2308A-5H
Note: 1. Outputs inverted on 2308-2 and 2308-3 in bypass mode, S2 = 1 and S1 = 0. 2. Output phase is indeterminant (0 or 180 from input clock). If phase integrity is required, use the ASM5P2308A-2.
Feedback From Bank A or Bank B Bank A or Bank B Bank A Bank B Bank A Bank B Bank A or Bank B Bank A or Bank B
Bank A Frequency Reference Reference Reference 2 X Reference 2 X Reference 4 X Reference 2 X Reference Reference /2
Bank B Frequency Reference Reference Reference /2 Reference Reference or Reference2 2 X Reference 2 X Reference Reference /2
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
November 2003 rev 1.1 Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero Delay between input and output.
ASM5P2308A
1500
1000 REF- Input to CLKA/CLKB Delay
500
0 -30 -500 -25 -20 -15 -10 -5 0
5
10
15
20
25
30
-1000 -1500 Output Load Difference: FBK Load - CLKA/CLKB Load (pF)
To close the feedback loop of the ASM5P2308A, the FBK pin can be driven from any of the eight available output pins. The output driving the FBK pin will be driving a total load of 7 pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input output delay. This is shown in the above graph.
For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. For zero output-output skew, be sure to load outputs equally.
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
November 2003 rev 1.1 Pin Configuration
REF CLKA1 CLKA2 V
DD
ASM5P2308A
1 2 3 4 5 6 7 8
16 15 14
FBK CLKA4 CLKA3 V
DD
GND CLKB1 CLKB2 S2
ASM5P2308A
13 12 11 10 9
GND CLKB4 CLKB3 S1
Pin Description for ASM5P2308A
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Notes: 3. Weak pull-down. 4. Weak pull-down on all outputs. 5. Weak pull-up on these inputs.
Pin Name REF
3 4 4
Description Input reference frequency, 5V tolerant input Buffered clock output, bank A Buffered clock output, bank A 3.3V supply Ground
CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2 S1
5 5
4 4
Buffered clock output, bank B Buffered clock output, bank B Select input, bit 2 Select input, bit 1
CLKB3 CLKB4 GND VDD CLKA3 CLKA4 FBK
4 4
Buffered clock output, bank B Buffered clock output, bank B Ground 3.3V supply
4 4
Buffered clock output, bank A Buffered clock output, bank A PLL feedback input
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
November 2003 rev 1.1 Absolute Maximum Ratings
Parameter Supply Voltage to Ground Potential DC Input Voltage (Except REF) DC Input Voltage (REF) Storage Temperature Max. Soldering Temperature (10 sec) Junction Temperature Static Discharge Voltage (per MIL-STD-883, Method 3015) ratings for prolonged periods can affect device reliability. Min -0.5 -0.5 -0.5 -65 Max +7.0 VDD + 0.5 7 +150 260 150 >2000 Unit V V V C C C V
ASM5P2308A
Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum
Operating Conditions for ASM5P2308A Commercial Temperature Devices
Parameter VDD TA CL CL CIN
Note: 6. Applies to both Ref Clock and FBK.
Description Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance
6
Min 3.0 0
Max 3.6 70 30 10 7
Unit V C pF pF pF
Electrical Characteristics for ASM5P2308A Commercial Temperature Devices
Parameter VIL VIH IIL IIH VOL VOH Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage
7
Test Conditions
Min 2.0
Max 0.8
Unit V V A A V V
VIN = 0V VIN = VDD IOL = 8mA (-1, -2, -3, -4) IOH = 12mA (-1H, -5H) IOL = -8mA (-1, -2, -3, -4) IOH = -12mA (-1H, -5H) Unloaded outputs 100MHz REF 2.4
50.0 100.0 0.4
Output HIGH Voltage 7
TBD TBD TBD TBD mA
IDD
Supply Current
Select inputs at VDD or GND Unloaded outputs, 66MHz REF (-1, -2, -3, -4) Unloaded outputs, 33MHz REF (-1, -2, -3, -4)
Note: 7. Parameter is guaranteed by design and characterization. Not 100% tested in production.
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
November 2003 rev 1.1 Switching Characteristics for ASM5P2308A Commercial Temperature Devices
Parameter t1 t1 t1 Description Output Frequency Output Frequency Output Frequency Duty Cycle = (t2 / t1) * 100 (-1, -2, -3, -4, -1H, -5H) Duty Cycle = (t2 / t1) * 100 (-1, -2, -3, -4, -1H, -5H) t3 Output Rise Time (-1, -2, -3, -4) Output Rise Time (-1, -2, -3, -4) Output Rise Time (-1H, -5H) Output Fall Time (-1, -2, -3, -4) Output Fall Time (-1, -2, -3, -4) Output Fall Time (-1H, -5H) Output-to-output skew on same bank (-1, -2, -3, -4) (-1H, -5H) Output bank A -to- output bank B skew (-1, -4, -5H) Output bank A -to- output bank B skew (-2, -3) t6 t7 Delay, REF Rising Edge to FBK Rising Edge
6 7 7 7 7 7 7 7 7 7 7
ASM5P2308A
Test Conditions 30-pF load, All devices 20-pF load, -1H, -5H devices
8
Min 10 10 10 40.0 45.0
Typ
Max 100 133.3 133.3
Unit MHz MHz MHz % %
15-pF load, -1, -2, -3, -4 devices Measured at 1.4V, FOUT = <66.66 MHz 30-pF load Measured at 1.4V, FOUT = <50 MHz 15-pF load Measured between 0.8V and 2.0V 30-pF load
50.0 50.0
60.0 55.0
2.20
ns
t3
Measured between 0.8V and 2.0V 15-pF load
1.50
ns
t3 t4
Measured between 0.8V and 2.0V 30-pF load
1.50
ns
Measured between 2.0V and 0.8V 30-pF load Measured between 0.8V and 2.0V 15-pF load
2.20
ns
t4 t4
1.50
ns
Measured between 2.0V and 0.8V 30-pF load All outputs equally loaded All outputs equally loaded All outputs equally loaded All outputs equally loaded Measured at VDD /2 Measured at VDD/2 on the FBK pins of the device Measured at 66.67 MHz, loaded outputs, 15 pF load Measured at 66.67 MHz, loaded outputs, 30 pF load Measured at 133.3 MHz, loaded outputs, 15 pF load 0 0
1.25 200 200 200 400 250 700 200 200 100 400 400 1.0
ns ps
Output-to-output skew t5
ps ps ps
Device-to-Device Skew Cycle-to-cycle jitter (-1, -1H, -4, -5H) Cycle-to-cycle jitter (-2, -3) PLL Lock Time
7 7 7
tJ
tJ
Measured at 66.67 MHz, loaded outputs, 30pF load Measured at 66.67 MHz, loaded outputs, 15 pF load Stable power supply, valid clock presented on REF and FBK pins
ps
tLOCK
ms
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
November 2003 rev 1.1 Switching Characteristics for ASM5I2308A - Industrial Temperature Devices
Parameter t1 t1 t1 Description Output Frequency Output Frequency Output Frequency Duty Cycle = (t2 / t1) * 100 (-1, -2, -3, -4, -1H, -5H) Duty Cycle = (t2 / t1) * 100 (-1, -2, -3, -4, -1H, -5H) t3 Output Rise Time (-1, -2, -3, -4) t3 Output Rise Time (-1, -2, -3, -4) t3 Output Rise Time (-1H, -5H) t4 t4 Output Fall Time (-1, -2, -3, -4) Output Fall Time (-1, -2, -3, -4) t4 Output Fall Time (-1H, -5H) Output-to-output skew on same bank All outputs equally loaded (-1, -2, -3, -4) (-1H, -5H) Output bank A -to- output bank B skew (-1, -4, -5H) Output bank A -to- output bank B skew (-2, -3) t6 t7 Delay, REF Rising Edge to FBK Rising Edge
7 7 7 7 7 7 7 7 7 7 7
ASM5P2308A
Test Conditions 30-pF load, All devices 20-pF load, -1H, -5H devices
8
Min 10 10 10 40.0 45.0
Typ
Max 100 133.3 133.3
Unit MHz MHz MHz % % ns
15-pF load, -1, -2, -3, -4 devices Measured at 1.4V, FOUT = <66.66 MHz 30-pF load Measured at 1.4V, FOUT = <50 MHz 15-pF load Measured between 0.8V and 2.0V 30-pF load
50.0 50.0
60.0 55.0 2.50
Measured between 0.8V and 2.0V 15-pF load
1.50
ns
Measured between 0.8V and 2.0V 30-pF load
1.50
ns
Measured between 2.0V and 0.8V 30-pF load Measured between 0.8V and 2.0V 15-pF load
2.50 1.50
ns ns
Measured between 2.0V and 0.8V 30-pF load
1.25 200 200 200 400 0 0 250 700 200 200 100 400 400 1.0
ns ps
Output-to-output skew t5
All outputs equally loaded All outputs equally loaded All outputs equally loaded Measured at VDD /2 Measured at VDD/2 on the FBK pins of the device Measured at 66.67 MHz, loaded outputs,
ps ps ps
Device-to-Device Skew
tJ
Cycle-to-cycle jitter (-1, -1H, -4, -5H)
7
15 pF load Measured at 66.67 MHz, loaded outputs, 30 pF load Measured at 133.3 MHz, loaded outputs, 15 pF load
tJ
Cycle-to-cycle jitter (-2, -3)
7
Measured at 66.67 MHz, loaded outputs, 30pF load Measured at 66.67 MHz, loaded outputs, 15 pF load
ps
tLOCK
PLL Lock Time
7
Stable power supply, valid clock presented on REF and FBK pins
ms
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
November 2003 rev 1.1 Switching Waveforms Duty Cycle Timing
t1 t2
ASM5P2308A
1.4 V
1.4 V
1.4 V
All Outputs Rise/Fall Time
2.0 V OU TPUT 0V .8 t3 t4 2.0 V 0V .8 3.3 V 0V
Output - Output Skew
1.4 V
OUT PUT
1.4 V
OUT PUT
t5
Input - Output Propagation Delay
V
INP UT
D D
/ 2
V/ 2
OUT PUT
DD
t6
Device - Device Skew
V/ 2
DD
CLKOUT, D evice 1
CLKOUT, Device 2
V D/ 2 D
t7
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
November 2003 rev 1.1 Test Circuits
Test Circuit #1 Test Circuit #2
ASM5P2308A
V 0.1 F
DD
V OUTPUTS CLK OUT 0.1 F C
LOAD
DD
1k OUTPUTS 1k 10 pF
V 0.1 F
DD
V GND 0.1 F
DD
GND
GND
GND
For parameter t8 (output slew rate) on -1H devices
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
November 2003 rev 1.1
ASM5P2308A
Package Information: 16-lead (150 Mil) Molded SOIC
8 1 PIN 1 ID
E
H
9 D
16 Seating Plane A e
B
h
A2
D
0.004
L
C
A1
Symbol A A1 A2 B C D E e H h L
Dimensions (inches) MIN 0.061 0.004 0.055 0.013 0.0075 0.386 0.150 0.050 BSC 0.230 0.010 0.016 0 0.244 0.016 0.035 8 MAX 0.068 0.0098 0.061 0.019 0.0098 0.393 0.157
Dimensions (millimeters) MIN 1.55 0.102 1.40 0.33 0.191 9.80 3.81 1.27 BSC 5.84 0.25 0.41 0 6.20 0.41 0.89 8 MAX 1.73 0.249 1.55 0.49 0.249 9.98 3.99
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
November 2003 rev 1.1
ASM5P2308A
Package Information: 16-lead Thin Shrunk Small Outline Package (4.40-MM Body)
8
1
PIN 1 ID E H
9
16
A
Seating Plane L C
e D
A2
B
A1
Symbol A A1 A2 B C D E e H L
Dimensions (inches) MIN 0.002 0.003 0.007 0.004 0.193 0.169 0.026 BSC 0.246 0.020 0 0.256 0.028 8 MAX 0.043 0.006 0.37 0.012 0.008 2.008 0.177
D
Dimensions (mm) MIN 0.05 0.85 0.19 0.09 4.90 4.30 0.65 BSC 6.25 0.50 0 6.50 0.70 8 MAX 1.10 0.15 0.95 0.30 0.20 5.10 4.50
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
November 2003 rev 1.1 Ordering Codes
Ordering Code ASM5P2308A-1-16-ST ASM5I2308A-1-16-ST ASM5P2308A-1-16-SR ASM5I2308A-1-16-SR ASM5P2308A-1-16-TT ASM5I2308A-1-16-TT ASM5P2308A-1-16-TR ASM5I2308A-1-16-TR ASM5P2308A-1H-16-ST ASM5I2308A-1H-16-ST ASM5P2308A-1H-16-SR ASM5I2308A-1H-16-SR ASM5P2308A-1H-16-TT ASM5I2308A-1H-16-TT ASM5P2308A-1H-16-TR ASM5I2308A-1H-16-TR ASM5P2308A-2-16-ST ASM5I2308A-2-16-ST ASM5P2308A-2-16-SR ASM5I2308A-2-16-SR ASM5P2308A-2-16-TT ASM5I2308A-2-16-TT ASM5P2308A-2-16-TR ASM5I2308A-2-16-TR ASM5P2308A-3-16-ST ASM5I2308A-3-16-ST ASM5P2308A-3-16-SR ASM5I2308A-3-16-SR ASM5P2308A-3-16-TT ASM5I2308A-3-16-TT ASM5P2308A-3-16-TR ASM5I2308A-3-16-TR Package Type 16-pin 150-mil SOIC-TUBE 16-pin 150-mil SOIC- TUBE 16-pin 150-mil SOIC-TAPE & REEL 16-pin 150-mil SOIC-TAPE & REEL 16-PIN 150-mil TSSOP - TUBE 16-PIN 150-mil TSSOP - TUBE 16-PIN 150-mil TSSOP - TAPE & REEL 16-PIN 150-mil TSSOP - TAPE & REEL 16-pin 150-mil SOIC-TUBE 16-pin 150-mil SOIC- TUBE 16-pin 150-mil SOIC-TAPE & REEL 16-pin 150-mil SOIC-TAPE & REEL 16-PIN 150-mil TSSOP - TUBE 16-PIN 150-mil TSSOP - TUBE 16-PIN 150-mil TSSOP - TAPE & REEL 16-PIN 150-mil TSSOP - TAPE & REEL 16-pin 150-mil SOIC-TUBE 16-pin 150-mil SOIC- TUBE 16-pin 150-mil SOIC-TAPE & REEL 16-pin 150-mil SOIC-TAPE & REEL 16-PIN 150-mil TSSOP - TUBE 16-PIN 150-mil TSSOP - TUBE 16-PIN 150-mil TSSOP - TAPE & REEL 16-PIN 150-mil TSSOP - TAPE & REEL 16-pin 150-mil SOIC-TUBE 16-pin 150-mil SOIC- TUBE 16-pin 150-mil SOIC-TAPE & REEL 16-pin 150-mil SOIC-TAPE & REEL 16-PIN 150-mil TSSOP - TUBE 16-PIN 150-mil TSSOP - TUBE 16-PIN 150-mil TSSOP - TAPE & REEL 16-PIN 150-mil TSSOP - TAPE & REEL Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial
ASM5P2308A
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
November 2003 rev 1.1 Ordering Codes (contd)
Ordering Code ASM5P2308A-4-16-ST ASM5I2308A-4-16-ST ASM5P2308A-4-16-SR ASM5I2308A-4-16-SR ASM5P2308A-4-16-TT ASM5I2308A-4-16-TT ASM5P2308A-4-16-TR ASM5I2308A-4-16-TR ASM5P2308A-5H-16-ST ASM5I2308A-5H-16-ST ASM5P2308A-5H-16-SR ASM5I2308A-5H-16-SR ASM5P2308A-5H-16-TT ASM5I2308A-5H-16-TT ASM5P2308A-5H-16-TR ASM5I2308A-5H-16-TR Package Type 16-pin 150-mil SOIC-TUBE 16-pin 150-mil SOIC- TUBE 16-pin 150-mil SOIC-TAPE & REEL 16-pin 150-mil SOIC-TAPE & REEL 16-PIN 150-mil TSSOP - TUBE 16-PIN 150-mil TSSOP - TUBE 16-PIN 150-mil TSSOP - TAPE & REEL 16-PIN 150-mil TSSOP - TAPE & REEL 16-pin 150-mil SOIC-TUBE 16-pin 150-mil SOIC- TUBE 16-pin 150-mil SOIC-TAPE & REEL 16-pin 150-mil SOIC-TAPE & REEL 16-PIN 150-mil TSSOP - TUBE 16-PIN 150-mil TSSOP - TUBE 16-PIN 150-mil TSSOP - TAPE & REEL 16-PIN 150-mil TSSOP - TAPE & REEL Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial
ASM5P2308A
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
November 2003 rev 1.1
ASM5P2308A
Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com
Copyright (c) Alliance Semiconductor All Rights Reserved Preliminary Information Part Number: ASM5P2308A Document Version: v1.1
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Dan Hariton / Alliance Semiconductor, dated 11-11-2003
(c) Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.

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