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HB56A232D-5/6/7
2,097,152-word x 32-bit High Density Dynamic RAM Module
ADE-203-749A (Z) Rev.1.0 Feb. 27, 1997 Description
The HB56A232D is a 2M x 32 dynamic RAM Small Outline Dual In-line Memory Module (S.O.DIMM), mounted 4 pieces of 16-Mbit DRAM (HM5117800) sealed in TSOP package. An outline of the HB56A232D is 72-pin Zig Zag Dual tabs socket type compact and thin package. Therefore, the HB56A232D makes high density mounting possible without surface mount technology. The HB56A232D provides common data inputs and outputs. Decoupling capacitors are mounted on the module board.
Features
* 72-pin Zig Zag Dual tabs socket type Outline: 59.69 mm (Length) x 25.40 mm (Height) x 2.42 mm (Thickness) Lead pitch: 1.27 mm * Single 5 V (5%) supply * High speed Access time: tRAC = 50/60/70 ns (max) tCAC = 13/15/18 ns (max) * Low power dissipation Active mode: 2.31/2.10/1.89 W (max) Standby mode (TTL): 42 mW (max) (CMOS): 3.15 mW (max) (L-version) * Fast page mode capability * Refresh period 2048 refresh cycles: 32 ms 128 ms (L-version) * 4 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh Self refresh (L-version) * TTL compatible
HB56A232D-5/6/7
Ordering Information
Type No. HB56A232D-5 HB56A232D-6 HB56A232D-7 HB56A232D-5L HB56A232D-6L HB56A232D-7L Access time 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns Package 72-pin small outline DIMM Contact pad Gold
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HB56A232D-5/6/7
Pin Arrangement
1 pin 71 pin
Front side
2 pin Front side Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 Pin name VSS DQ1 DQ3 DQ5 DQ7 PD1 A1 A3 A5 A10 DQ9 DQ11 DQ13 DQ15 NC A8 NC DQ16 Pin No. 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 Pin name DQ18 VSS CE2 CE1 NC WE DQ20 DQ22 DQ24 NC DQ28 DQ31 VCC DQ33 NC PD3 PD5 PD7
Back side
72 pin
Back side Pin No. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 Pin name DQ0 DQ2 DQ4 DQ6 VCC A0 A2 A4 A6 NC DQ10 DQ12 DQ14 A7 VCC A9 RE2 NC Pin No. 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 Pin name DQ19 CE0 CE3 RE0 NC NC DQ21 DQ23 DQ25 DQ27 DQ29 DQ30 DQ32 DQ34 PD2 PD4 PD6 VSS
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HB56A232D-5/6/7
Pin Description
Pin name A0 to A10 Function Address inputs: Row address: Column address: Refresh address: DQ0 to DQ7, DQ9 to DQ16, DQ18 to DQ25, DQ27 to DQ34 RE0, RE2 CE0 to CE3 WE VCC VSS PD1 to PD7 NC Data-in/Data-out Row address strobe (RAS) column address strobe (CAS) Read/Write enable Power supply Ground Presence detect No connection A0 to A10 A0 to A9 A0 to A10
Presence Detect Pin Arrangement
Function Pin No. 11 66 67 68 69 70 71 Pin name PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD7 (L-version) 50 ns VSS NC VSS NC VSS VSS NC VSS 60 ns VSS NC VSS NC NC NC NC VSS 70 ns VSS NC VSS NC VSS NC NC VSS
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HB56A232D-5/6/7
Block Diagram
RE0 CE0 WE0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CE1 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 I/O I/O I/O I/O I/O I/O I/O I/O CAS RAS WE I/O I/O I/O I/O I/O I/O I/O I/O CAS RAS WE
D0
OE
D1
OE RE2 CE2 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 I/O I/O I/O I/O I/O I/O I/O I/O CAS RAS WE
D2
OE CE3 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 I/O I/O I/O I/O I/O I/O I/O I/O CAS RAS WE
D3
OE
A0 to A10 VCC VSS 0.22 F x 4 pcs
D0 to D3 D0 to D3 D0 to D3
* D0 to D3: HM5117800
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HB56A232D-5/6/7
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout Pt Topr Tstg Value -1.0 to +7.0 -1.0 to +7.0 50 4 0 to +70 -55 to +125 Unit V V mA W C C
Recommended DC Operating Conditions (Ta = 0 to 70C)
Parameter Supply voltage Symbol VSS VCC Input high voltage Input low voltage Note: 1. All voltage referred to VSS . VIH VIL Min 0 4.75 2.4 -1.0 Typ 0 5.0 -- -- Max 0 5.25 5.5 0.8 Unit V V V V 1 1 1 Note
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HB56A232D-5/6/7
DC Characteristics (Ta = 0 to 70C, VCC = 5 V 5%, VSS = 0 V)
50 ns Parameter Operating current Standby current 60 ns 70 ns Test conditions t RC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z t RC = min RAS = VIH, CAS = VIL Dout = enable t RC = min t PC = min CMOS interface Dout = High-Z CBR refresh: t RC = 62.5 s t RAS 0.3 s CMOS interface RAS, CAS 0.2 V Dout = High-Z 0 V Vin 5.5 V 0 V Vout 5.5 V Dout = disable High Iout = -5 mA Low Iout = 4.2 mA 1, 3 4 2 1 Notes 1, 2 Symbol Min Max Min Max Min Max Unit I CC1 I CC2 -- -- 440 -- 8 -- 400 -- 8 -- 360 mA 8 mA
--
4
--
4
--
4
mA
Standby current (Lversion) RAS-only refresh current Standby current CAS-before-RAS refresh current Fast page mode current
I CC2
--
0.6
--
0.6
--
0.6
mA
I CC3 I CC5 I CC6 I CC7
-- -- -- -- --
440 -- 20 --
400 -- 20 --
360 mA 20 mA
440 -- 400 -- 2 --
400 -- 360 -- 2 --
360 mA 340 mA 2 mA
Battery backup current I CC10 (Standby with CBR refresh) (L-version)
Self refresh mode current (L-version) Input leakage current
I CC11
--
1.2
--
1.2
--
1.2
mA
I LI
-10 10 -10 10 2.4 0 VCC 0.4
-10 10 -10 10 2.4 0 VCC 0.4
-10 10 -10 10 2.4 0 VCC 0.4
A A V V
Output leakage current I LO Output high voltage Output low voltage VOH VOL
Notes: 1. I CC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. CAS = L ( 0.2 V) while RAS = L ( 0.2 V).
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HB56A232D-5/6/7
Capacitance (Ta = 25C, VCC = 5 V 5%)
Parameter Input capacitance (Address) Input capacitance (WE) Input capacitance (RAS) Input capacitance (CAS) I/O capacitance (DQ) Symbol CI! CI2 CI3 CI4 CI/O Typ -- -- -- -- -- Max 40 48 30 23 23 Unit pF pF pF pF pF Notes 1 1 1 1 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout.
AC Characteristics (Ta = 0 to 70C, VCC = 5 V 5%, VSS = 0 V) *1, *2, *17
Test Conditions * * * * Input rise and fall times: 5 ns Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.4 V, 2.4 V Output load: 2 TTL gate + C L (100 pF) (Including scope and jig)
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HB56A232D-5/6/7
Read, Write, and Refresh Cycles (Common parameters)
50 ns Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS delay time from Din Symbol Min t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH 90 30 7 50 13 0 7 0 7 17 12 13 50 5 0 3 -- -- Max -- -- -- 60 ns Min 110 40 10 Max -- -- -- 70 ns Min 130 50 10 Max -- -- -- Unit ns ns ns Notes
10000 60 10000 15 -- -- -- -- 37 25 -- -- -- -- 50 32 128 0 10 0 10 20 15 15 60 5 0 3 -- --
10000 70 10000 18 -- -- -- -- 45 30 -- -- -- -- 50 32 128 0 10 0 15 20 15 18 70 5 0 3 -- --
10000 ns 10000 ns -- -- -- -- 52 35 -- -- -- -- 50 32 128 ns ns ns ns ns ns ns ns ns ns ns ms ms 5 3 4
CAS to RAS precharge time t CRP t DZC
Transition time (rise and fall) t T Refresh period (2,048 cycles) Refresh period (2,048 cycles) (L-version) t REF t REF
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HB56A232D-5/6/7
Read Cycle
50 ns Parameter Access time from RAS Access time from CAS Access time from address Read command setup time Symbol Min t RAC t CAC t AA t RCS -- -- -- 0 0 5 25 25 0 3 -- 13 Max 50 13 25 -- -- -- -- -- -- -- 13 -- 60 ns Min -- -- -- 0 0 5 30 30 0 3 -- 15 Max 60 15 30 -- -- -- -- -- -- -- 15 -- 70 ns Min -- -- -- 0 0 5 35 35 0 3 -- 18 Max 70 18 35 -- -- -- -- -- -- -- 15 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns 11 10 10 Notes 6, 7 7, 8, 15 7, 9, 15
Read command hold time to t RCH CAS Read command hold time to t RRH RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output buffer turn-off time CAS to Din delay time t RAL t CAL t CLZ t OH t OFF t CDD
Write Cycle
50 ns Parameter Write command setup time Write command hold time Write command pulse width Data-in setup time Data-in hold time Symbol Min t WCS t WCH t WP t DS t DH 0 7 7 0 7 Max -- -- -- -- -- 60 ns Min 0 10 10 0 10 Max -- -- -- -- -- 70 ns Min 0 15 10 0 15 Max -- -- -- -- -- Unit ns ns ns ns ns 13 13 Notes 12
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HB56A232D-5/6/7
Refresh Cycle
50 ns Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) WE setup time (CBR refresh cycle) WE hold time (CBR refresh cycle) Symbol Min t CSR t CHR t WRP t WRH 5 7 0 7 5 Max -- -- -- -- -- 60 ns Min 5 10 0 10 5 Max -- -- -- -- -- 70 ns Min 5 10 0 10 5 Max -- -- -- -- -- Unit ns ns ns ns ns Notes
RAS precharge to CAS hold t RPC time
Fast Page Mode Cycle
50 ns Parameter Fast page mode cycle time Symbol Min t PC 35 -- -- 30 Max -- 60 ns Min 40 Max -- 70 ns Min 45 Max -- Unit ns 14 7, 15 Notes
Fast page mode RAS pulse t RASP width Access time from CAS precharge RAS hold time from CAS precharge t CPA t CPRH
100000 -- 30 -- -- 35
100000 -- 35 -- -- 40
100000 ns 40 -- ns ns
Self Refresh Mode (L-version)
50 ns Parameter RAS pulse width (Self refresh) RAS precharge time (Self refresh) Symbol Min t RASS t RPS 100 90 -50 Max -- -- -- 60 ns Min 100 110 -50 Max -- -- -- 70 ns Min 100 130 -50 Max -- -- -- Unit s ns ns Notes
CAS hold time (Self refresh) t CHS
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HB56A232D-5/6/7
Notes: 1. AC measurements assume t T = 5 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh cycle or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 6. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 7. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 8. Assumes that t RCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max). 9. Assumes that t RAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max). 10. Either t RCH or tRRH must be satisfied for a read cycles. 11. t OFF (max) defines the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 12. Early write cycle only (tWCS tWCS (min)). 13. These parameters are referred to CAS leading edge in early write cycles. 14. t RASP defines RAS pulse width in Fast page mode cycles. 15. Access time is determined by the longest among t AA , t CAC and t CPA. 16. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large V CC / VSS line noise, which causes to degrade V IH min./ V IL max level. 17. All the V CC and VSS pins shall be supplied with the same voltages. 18. Please do not use tRASS timing, 10 s tRASS 100 s. During this period, the device is in transition state from normal operation mode to self refresh mode. If t RASS 100 s, then RAS precharge time should use tRPS instead of tRP. 19. If you use distributed CBR refresh mode with 15.6 s interval in normal read/write cycle, CBR refresh should be executed within 15.6 s immediately after exiting from and before entering into self refresh mode. 20. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 2048 cycles of distributed CBR refresh with 15.6 s interval should be executed within 32 ms immediately after exiting from and before entering into the self refresh mode. 21. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self fresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 22. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL.
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HB56A232D-5/6/7
Timing Waveforms*22
Read Cycle
t RC t RAS t RP
RAS t CSH t RCD tT t RSH t CAS t CRP
CAS
t RAD t ASR t ASC t RAL t CAL t CAH
t RAH
Address
Row
Column t RRH t RCS t RCH
WE
t DZC t CDD Din High-Z t CAC t AA t RAC t OFF t CLZ t OH Dout Dout
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HB56A232D-5/6/7
Early Write Cycle
t RC t RAS t RP
RAS t CSH t RCD tT CAS t RSH t CAS t CRP
t ASR
t RAH
t ASC
t CAH
Address
Row
Column t WP t WCS t WCH
WE
t DS
t DH
Din
Din
Dout
High-Z* * t WCS t WCS (min)
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HB56A232D-5/6/7
RAS-Only Refresh Cycle
t RC t RAS t RP
RAS tT t CRP CAS t RPC t CRP
t ASR t RAH Address Row t OFF Dout High-Z 15
HB56A232D-5/6/7
CAS-Before-RAS Refresh Cycle
t RC t RP RAS t RPC CAS t CSR tT t CHR t RPC t CRP t RAS t RP
,
t CP t WRP t WRH t CP WE Address t OFF Dout High-Z 16
HB56A232D-5/6/7
Hidden Refresh Cycle
t RC t RAS t RC t RAS t RC t RP t RAS t RP
t RP
RAS tT t RSH t RCD CAS t RAD t ASR t RAH Address Row t ASC t RAL t CAH t CHR t CRP
Column t WRP t RCS t RRH t WRH

WE t DZC High-Z Din t CAC t AA t RAC t CLZ Dout Dout
t WRP
t WRH
t CDD
t OFF t OH
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HB56A232D-5/6/7
Fast Page Mode Read Cycle
t RASP t CPRH t RP
RAS tT t CSH t RCD CAS t RAL t RAD t ASR t RAH Address Row t CAL t ASC t CAH Column 1 t CAL t ASC t CAH Column 2 t CAL t ASC t CAH Column N t CAS t CP t PC t CAS t CP t RSH t CAS t CRP
,
$ *
t RCS t RCS t RRH t RCS t RCH t RCH t RCH WE t DZC t DZC t DZC t CDD t CDD t CDD Din High-Z High-Z High-Z t RAC t AA t OH t CPA t AA t OH t CPA t AA t OH t CAC t CLZ t OFF t CAC t CLZ t OFF t CAC t CLZ t OFF Dout Dout 1 Dout 2 Dout N 18
HB56A232D-5/6/7
Fast Page Mode Early Write Cycle
t RASP t RP
RAS tT t CSH t RCD t CAS CAS t PC t CP t CAS t CP t RSH t CAS t CRP
t ASR t RAH
t ASC t CAH
t ASC t CAH
t ASC t CAH
Address
Row
Column 1 t WP t WCS t WCH
Column 2 t WP t WCS t WCH
Column N t WP t WCS t WCH
WE
t DS
t DH
t DS
t DH
t DS
t DH
Din
Din 1
Din 2
Din N
Dout
High-Z* * t WCS t WCS (min)
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HB56A232D-5/6/7
Self Refresh Cycle (L-version)* 18, 19, 20, 21
t RASS
t RP
t RPS
RAS t RPC tT t CRP t CHS
, ,
t CP t CSR CAS t WRP WE t OFF Dout 20
t WRH
, + & $
High-Z
HB56A232D-5/6/7
Physical Outline
Unit : mm inch
Front side
6.35 0.250 7.62 0.300 2.00 0.079 8.25 0.325 2 - O1.80 2 - O0.071 2 - R2.00 0.10 2 - R0.079 0.004
44.45 1.750
A
3.00 min 0.118 min
3.18 min 0.125 min
5.00 0.197 2 - R3.00 min 2 - R0.118 min R2.00 R0.079
,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,, 1 71 ,,,,,,,,,,,,,,,,,,
51.66 2.034
3.00 min 0.118 min
59.69 2.350
2.42 max 0.095 max
, , , , , , ,
1.00 0.10 0.039 0.004
Detail A 2.54 min 0.100 min 1.000.05 0.0390.002 0.25 max 0.010 max
1.27 typ 0.050 typ
17.78 0.700 25.40 1.000
72
2
Back side
44.45 1.750
1.80 0.071
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HB56A232D-5/6/7
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
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HB56A232D-5/6/7
Revision Record
Rev. Date 1.0 Feb. 27, 1997 Contents of Modification Initial issue Drawn by Approved by
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