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19-2498; Rev 1; 10/02
Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change
General Description
The MAX1937/MAX1938/MAX1939 comprise a family of synchronous, two-phase, step-down controllers capable of delivering load currents up to 60A. The controllers utilize Quick-PWMTM control architecture in conjunction with active load-current voltage positioning. Quick-PWM control provides instantaneous load-step response, while programmable voltage positioning allows the converter to utilize full transient regulation limits, reducing the output capacitance requirement. The two phases operate 180 out-of-phase with an effective 500kHz switching frequency, thus reducing input and output current ripple, as well as reducing input filter capacitor requirements. The MAX1937/MAX1938/MAX1939 are compliant with AMD Hammer, Intel Voltage-Regulator Module (VRM) 9.0/9.1, and AMD AthlonTM Mobile VID code specifications (see Table 1 for VID codes). The internal DAC provides ultra-high accuracy of 0.75%. A controlled VID voltage transition is implemented to minimize both undervoltage and overvoltage overshoot during VID input change. Remote sensing is available for high output-voltage accuracy. The MOSFET switches are driven by a 6V gate-drive circuit to minimize switching and crossover conduction losses to achieve efficiency as high as 90%. The MAX1937/MAX1938/MAX1939 feature cycleby-cycle current limit to ensure that the current limit is not exceeded. Crowbar protection is available to protect against output overvoltage. o o o o o o o o o o o o o o o o o o
Features
0.75% Output Voltage Accuracy Instant Load-Transient Response Up to 90% Efficiency Eliminates Heatsinks Up to 60A Output Current 8V to 24V Input Range User-Programmable Voltage Positioning Controlled VID Voltage Transition 500kHz Effective Switching Frequency MAX1937: AMD Hammer Compatible MAX1938: Intel VRM 9.0/9.1 Compatible MAX1939: AMD Athlon Mobile Compatible Soft-Start Power-Good (PWRGD) Output Cycle-by-Cycle Current Limit Output Overvoltage Protection (OVP) RDS(ON) or RSENSE Current Sensing Remote Voltage Sensing 28-Pin QSOP Package
MAX1937/MAX1938/MAX1939
Ordering Information
PART MAX1937EEI MAX1938EEI MAX1939EEI TEMP RANGE -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 28 QSOP 28 QSOP 28 QSOP
Applications
Notebook and Desktop Computers Servers and Workstations Blade Servers High-End Switches High-End Routers Macro Base Stations
TOP VIEW
VID0 1 VID1 2 TIME 3 VID2 4 VID3 5 VID4 6 VPOS 7 VDD 8 ILIM 9 28 VCC 27 BST1 26 DH1 25 LX1 24 CS1
Pin Configuration
MAX1937 MAX1938 MAX1939
23 DL1 22 VLG 21 PGND 20 DL2 19 CS2 18 LX2 17 DH2 16 BST2 15 PWRGD
Typical Application Circuits and Functional Diagram appear at end of data sheet.
GND 10 GNDS 11 REF 12
Quick-PWM is a trademark of Maxim Integrated Products, Inc. Athlon is a trademark of Advanced Micro Devices, Inc. Intel is a registered trademark of Intel Corp.
EN 13 FB 14
QSOP
________________________________________________________________ Maxim Integrated Products
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Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change MAX1937/MAX1938/MAX1939
ABSOLUTE MAXIMUM RATINGS
VCC to GND ............................................................-0.3V to +28V VDD, PWRGD, ILIM, FB to GND ...............................-0.3V to +6V EN, GNDS, VPOS, REF, VID_, TIME to GND ............................................0.3V to VVDD + 0.3V PGND to GND .......................................................-0.3V to +0.3V CS1, CS2 to GND ......................................................-2V to +28V VLG to GND..............................................................-0.3V to +7V BST1, BST2 to GND ...............................................-0.3V to +35V LX1 to BST1..............................................................-7V to +0.3V LX2 to BST2..............................................................-7V to +0.3V DH1 to LX1.................................................-0.3V to VBST1 + 0.3V DH2 to LX2.................................................-0.3V to VBST2 + 0.3V DL1, DL2 to PGND ......................................-0.3V to VVLG + 0.3V Continuous Power Dissipation (TA = +70C) 28-Pin QSOP (derate 20.8mW/C above +70C)......860.2mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 12V, VEN = VVDD = 5V, PGND = GNDS = GND = 0, VID_ = GND, CVPOS = 47pF, CREF = 0.1F, VILIM = 1V, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER GENERAL VCC Operating Range VDD Operating Range VLG Operating Range VCC Operating Supply Current VDD Operating Supply Current VLG Operating Supply Current VCC Shutdown Current VDD Shutdown Current VLG Shutdown Current TIME Output Voltage ILIM Input Bias VPOS Output Voltage REFERENCE Reference Voltage SOFT-START MAX1937 Ramp Period Soft-Start Voltage Step ERROR AMPLIFIER FB Input Resistance GNDS Input Bias Current Output Regulation Voltage Accuracy Resistance from FB to GND -5 -0.75 180 +5 +0.75 k A % MAX1938 MAX1939 1.1 1.5 1.3 25 5.5 6.2 6.5 mV ms -50A IREF 50A 1.987 2.000 2.013 V VILIM = 1.5V CS_= GND, VPOS connected to REF through a 75k resistor VVLG > VVDD FB above threshold (no switching) FB above threshold (no switching) FB above threshold (no switching) EN = GND EN = GND, VID_ not connected EN = GND 1.96 -250 1.96 2.0 20 <1 50 <1 2.00 MAX1937 MAX1938/MAX1939 6 8 4.5 4.5 20 1.4 5 24 24 5.5 6.5 40 2.5 60 5 100 5 2.04 +250 2.04 V V V A mA A A A A V nA V CONDITIONS MIN TYP MAX UNITS
2
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Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 12V, VEN = VVDD = 5V, PGND = GNDS = GND = 0, VID_ = GND, CVPOS = 47pF, CREF = 0.1F, VILIM = 1V, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER FAULT PROTECTION VDD Undervoltage Lockout (UVLO) Threshold VDD UVLO Hysteresis VLG UVLO Threshold VLG UVLO Hysteresis Thermal Shutdown Reference UVLO Threshold Output Overvoltage Fault Threshold Output UVLO Threshold CURRENT LIMIT PGND to CS_, VILIM = 1.5V Current-Limit Threshold CS Input Offset Voltage CS_ Input Bias Current VOLTAGE POSITIONING VPOS Input Offset Voltage VPOS Gain VPOS Gain TIMER AND DRIVERS On-Time Minimum Off-Time LX1 = LX2 = CS1 = CS2 = GND, VFB = 1.5V DH1 low to DH2 high, and DH2 low to DH1 high DH_ low to DL_ high Break-Before-Make Time DL_ low to DH_ high MAX1937/MAX1938 MAX1939 MAX1937/MAX1938 MAX1939 420 260 525 325 60 60 85 70 ns 630 390 ns ns From CS_ to FB; VCS1, VCS2 = 0, -100mV; RVPOS = 75k From CS1, CS2 to FB; VCS1, VCS2 = +13mV, -113mV; RVPOS = 75k -3 72.5 68 75.0 75 +3 77.5 82 mV %/V %/V PGND to CS_, VILIM = 1V PGND to CS_, VILIM = 0.5V CS_ = GND CS_ = GND 135 90 45 -3 -5 150 100 50 165 110 55 +3 +5 mV A mV Rising temperature, typical hysteresis = 15C Rising edge Falling edge Rising and falling MAX1937/MAX1938 MAX1939 1.97 2.215 65 Rising or falling VLG 4.00 Rising or falling VDD 4.00 4.25 80 4.25 40 160 1.600 1.584 2.00 2.250 70 2.03 2.285 75 4.45 4.45 V mV V mV C V V % CONDITIONS MIN TYP MAX UNITS
MAX1937/MAX1938/MAX1939
Rising and falling percentage of the nominal regulation voltage
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Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change MAX1937/MAX1938/MAX1939
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 12V, VEN = VVDD = 5V, PGND = GNDS = GND = 0, VID_ = GND, CVPOS = 47pF, CREF = 0.1F, VILIM = 1V, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DH_ On-Resistance in Low State DL_ On-Resistance in Low State DL_ On-Resistance in High State BST_ Leakage Current LX_ Leakage Current EN AND VID Low Level Threshold High Level Threshold Pullup Resistance PWRGD PWRGD Upper Trip Level PWRGD Lower Trip Level Output Low Level Output High Leakage CONTROLLED VID CHANGE On-the-Fly VID Change Slew Rate VID_ Change Frequency Range PWRGD Blanking Time VVDD = 4.5V to 5.5V RTIME = 120k 25mV per step RTIME = 47k RTIME = 470k 6.17 2.35 23.5 38 125 200 6.67 2.63 26.3 7.25 2.99 29.9 380 350 kHz s s 10.0 -15 12.5 -12.5 15.0 -10 0.4 1 % % V A Internally pulled up to VDD 1.6 50 100 200 0.8 V V k VBST_ = 30V, VLX_ = 24V VBST_ = 30V, VLX_ = 24V CONDITIONS VBST1 = VBST2 = 6V, LX1 = LX2 = GND MIN TYP 1.5 1.5 0.5 1.5 MAX 3.0 3.0 1.7 3.0 50 50 UNITS A A
DH_ On-Resistance in High State VBST_ = 6V, LX_ = GND
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Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change
ELECTRICAL CHARACTERISTICS
(VVCC = 12V, VEN = VVDD = 5V, PGND = GNDS = GND, VID_= GND, CVPOS = 47pF, CREF = 0.1F, VILIM = 1V, TA = -40C to +85C, unless otherwise noted.) (Note 1)
PARAMETER GENERAL VCC Operating Range VDD Operating Range VLG Operating Range VCC Operating Supply Current VDD Operating Supply Current VLG Operating Supply Current VCC Shutdown Current VDD Shutdown Current VLG Shutdown Current TIME Output Voltage ILIM Input Bias VPOS Output Voltage REFERENCE Reference Voltage SOFT-START MAX1937 Ramp Period ERROR AMPLIFIER GNDS Input Bias Current Output Regulation Voltage Accuracy FAULT PROTECTION VDD UVLO Threshold VLG UVLO Threshold Output Overvoltage Fault Threshold Output UVLO Threshold CURRENT LIMIT PGND to CS_, VILIM = 1.5V Current-Limit Threshold PGND to CS_, VILIM = 1V PGND to CS_, VILIM = 0.5V 135 90 45 165 110 55 mV Rising or falling VDD Rising or falling VLG Rising and falling MAX1937/MAX1938 MAX1939 4.00 4.00 1.97 2.215 65 4.45 4.45 2.03 2.285 75 V V V % -5 -1 +5 +1 A % MAX1938 MAX1939 1.1 1.5 1.3 5.5 6.6 7.0 ms -50A IREF 50A 1.98 2.02 V VILIM = 1V CS_ = GND, VPOS connected to REF through a 75k resistor VVLG VVDD FB above threshold (no switching) FB above threshold (no switching) FB above threshold (no switching) EN = GND EN = GND, VID_ not connected EN = GND 1.96 -250 1.96 20 MAX1937 MAX1938/MAX1939 6 8 4.5 4.5 24 24 5.5 6.5 40 2.5 60 5 100 5 2.04 +250 2.04 V V V A mA A A A A V nA V CONDITIONS MIN TYP MAX UNITS
MAX1937/MAX1938/MAX1939
Rising and falling percentage of the nominal regulation voltage
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Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change MAX1937/MAX1938/MAX1939
ELECTRICAL CHARACTERISTICS (continued)
(VVCC = 12V, VEN = VVDD = 5V, PGND = GNDS = GND, VID_= GND, CVPOS = 47pF, CREF = 0.1F, VILIM = 1V, TA = -40C to +85C, unless otherwise noted.) (Note 1)
PARAMETER CS Input Offset Voltage CS_ Input Bias Current VOLTAGE POSITIONING VPOS Input Offset Voltage VPOS Gain VPOS Gain TIMER AND DRIVERS On-Time Minimum Off-Time DH_ On-Resistance in Low State DL_ On-Resistance in Low State DL_ On-Resistance in High State BST_ Leakage Current LX_ Leakage Current EN AND VID_ Low Level Threshold High Level Threshold Pullup Resistance PWRGD PWRGD Upper Trip Level PWRGD Lower Trip Level Output Low Level Output High Leakage CONTROLLED VID CHANGE On-the-Fly VID Change Slew Rate VID_ Change Frequency Range PWRGD Blanking Time VVDD = 4.5V to 5.5V RTIME = 120k 25mV per step RTIME = 47k RTIME = 470k 6.17 2.35 23.5 38 125 7.25 2.99 29.9 380 350 kHz s s 10 -15 15 -10 0.4 1 % % V A Internally pulled up to VDD 1.6 50 200 0.8 V V k VBST_ = 30V, VLX_ = 24V VBST_ = 30V, VLX_ = 24V From CS_ to FB; VCS1, VCS2 = 0, -100mV; RVPOS = 75k From CS1, CS2 to FB; VCS1, VCS2 = +13mV, -113mV; RVPOS = 75k LX1 = LX2 = CS1 = CS2 = GND, VFB = 1.5V DH1 low to DH2 high, and DH2 low to DH1 high VBST1 = VBST2 = 6V, LX1 = LX2 = GND -5 72.5 68 +5 77.5 82 mV %/V %/V CS_ = GND CS_ = GND CONDITIONS MIN -5 -5 TYP MAX +5 +5 UNITS mV A
420 260
630 390 3 3 1.7 3 50 50
ns ns A A
DH_ On-Resistance in High State VBST_ = 6V, LX_ = GND
Note 1: Specifications to -40C are guaranteed by design and not production tested.
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Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change
Typical Operating Characteristics
(VIN = 12V, VOUT = 1.45V, TA = +25C, unless otherwise noted.)
EFFICIENCY vs. LOAD CURRENT AT 1.45V OUTPUT
MAX1937 toc01
MAX1937/MAX1938/MAX1939
EFFICIENCY vs. LOAD CURRENT AT 1.85V OUTPUT
90
MAX1937 toc02
FREQUENCY vs. LOAD CURRENT
MAX1937 toc03
90
350 300 FREQUENCY (kHz) 250 200 150 100
80 EFFICIENCY (%)
VIN = 12V 70
EFFICIENCY (%)
VIN = 8V VIN = 14V
80
VIN = 12V VIN = 14V
70 VIN = 8V 60
60 VOUT = 1.45V 50 1 10 LOAD CURRENT (A) 100
VOUT = 1.85V 50 1 10 LOAD CURRENT (A) 100
50 0 0
VIN = 12V VOUT = 1.45V 10 20 30 40 50 60
LOAD CURRENT (A)
FREQUENCY vs. INPUT VOLTAGE
MAX1937 toc04
FREQUENCY vs. TEMPERATURE
255 250 FREQUENCY (kHz) 245 240 235 230 VIN = 12V VOUT = 1.45V ILOAD = 10A -40 -20 0 20 40 60 80 100
MAX1937 toc05
325 300 FREQUENCY (kHz) 275 250 225 200 175 150 8 9 10 11 12 13 ILOAD = 1A ILOAD = 46A
260
VOUT = 1.45V 14
225 220 INPUT VOLTAGE (V)
TEMPERATURE (C)
VCC INPUT CURRENT vs. INPUT VOLTAGE
MAX1937 toc06
VDD CURRENT vs. VDD VOLTAGE
MAX1937 toc07
25
1.80 1.75 VDD CURRENT (mA) 1.70 1.65 1.60 1.55
VCC INPUT CURRENT (A)
20
15
10
5 VOUT = 1.45V 0 8 9 10 11 12 13 14 INPUT VOLTAGE (V)
1.50 4.5 4.7 4.9 5.1 5.3 5.5 VDD VOLTAGE (V)
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Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change MAX1937/MAX1938/MAX1939
Typical Operating Characteristics (continued)
(VIN = 12V, VOUT = 1.45V, TA = +25C, unless otherwise noted.)
VDD CURRENT vs. VDD VOLTAGE IN SHUTDOWN
65 60 VDD CURRENT (mA) 55 VOUT 50 45 40 35 30 4.5 4.7 4.9 5.1 5.3 5.5 VDD VOLTAGE (V) VID_ NOT CONNECTED 1.350 0 10 20 30 40 50 LOAD CURRENT (A) 1.375 VIN = 12V 1.400 RVPOS = 120k
MAX1937 toc08
OUTPUT VOLTAGE vs. LOAD CURRENT AT 1.45V OUTPUT
MAX1937 toc09
70
1.450
1.425 RVPOS = 90.9k
CURRENT SHARING
MAX1937 toc10
CURRENT SHARING
MAX1937 toc11
30 25 INDUCTOR CURRENTS (A) 20 15 10 5 0 -5 0 10 20 30 40 VIN = 12V VOUT = 1.45V TA = +25C
30 25 INDUCTOR CURRENTS (A) 20 15 10 5 0 -5 VIN = 12V VOUT = 1.45V TA = +80C 0 10 20 30 40
50
50
LOAD CURRENT (A)
LOAD CURRENT (A)
INDUCTOR CURRENT WAVEFORMS WITH 0A LOAD
MAX1937 toc12
INDUCTOR CURRENT WAVEFORMS WITH 40A LOAD
MAX1937 toc13
OUTPUT RIPPLE VOLTAGE: 20mV/div
OUTPUT RIPPLE VOLTAGE: 20mV/div OUTPUT INDUCTOR CURRENTS: 10A/div
0A
2s/div
OUTPUT INDUCTOR CURRENTS: 10A/div VIN = 12V VOUT = 1.45V IOUT = 0A
0A
VIN = 12V VOUT = 1.45V IOUT = 40A 2s/div
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Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change
Typical Operating Characteristics (continued)
(VIN = 12V, VOUT = 1.45V, TA = +25C, unless otherwise noted.)
LOAD TRANSIENT 1A TO 40A TO 1A
MAX1937 toc14
MAX1937/MAX1938/MAX1939
SOFT-START WAVEFORMS WITH NO LOAD
MAX1937 toc15
OUTPUT VOLTAGE: 50mV/div
POK SIGNAL OUTPUT VOLTAGE: 0.5V/div
INDUCTOR CURRENTS: 10A/div
TRANSIENT CONTROL SIGNAL: C6 = 47pF R2 = 91.1k 40s/div 1ms/div
INDUCTOR CURRENT: 10A/div ENABLE SIGNAL
SOFT-START WAVEFORMS WITH 40A LOAD
MAX1937 toc16
SHUTDOWN WAVEFORM WITH NO LOAD
MAX1937 toc17
POK SIGNAL OUTPUT VOLTAGE: 0.5V/div INDUCTOR CURRENT: 10A/div
POK SIGNAL OUTPUT VOLTAGE: 0.5V/div
INDUCTOR CURRENT: 10A/div ENABLE SIGNAL 1ms/div 20ms/div ENABLE SIGNAL
SHUTDOWN WAVEFORM WITH 40A LOAD
MAX1937 toc18
CURRENT-SENSE THRESHOLD vs. VILIM
POK SIGNAL CURRENT-SENSE THRESHOLD (mV) 140 120 100 80 60 40 0.5 0.7 0.9 1.1 1.3 1.5 VILIM (V) TA = +25C TA = +80C OUTPUT VOLTAGE: 0.5V/div INDUCTOR CURRENT: 10A/div
MAX1937 toc19
160
ENABLE SIGNAL 20ms/div
VIN = 12V VOUT = 1.45V
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Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change MAX1937/MAX1938/MAX1939
Typical Operating Characteristics (continued)
(VIN = 12V, VOUT = 1.45V, TA = +25C, unless otherwise noted.)
VID CODE CHANGE ON-THE-FLY WITH 40A LOAD 1.2V TO 1.45V TO 1.2V
MAX1937 toc20
VID CODE CHANGE ON-THE-FLY WITH 1A LOAD 1.2V TO 1.45V TO 1.2V
MAX1937 toc21
POK SIGNAL
POK SIGNAL
OUTPUT VOLTAGE: 200mV/div VID CODE CHANGE CONTROL SIGNAL
OUTPUT VOLTAGE: 200mV/div
VID CONTROL SIGNAL
40s/div
40s/div
REFERENCE VOLTAGE vs. TEMPERATURE
MAX1937 toc22
FB VOLTAGE vs. TEMPERATURE
MAX1937 toc23
2.000
0.810
REFERENCE VOLTAGE (V)
1.998
0.805 1.996 FB VOLTAGE (V) VOUT = 0.8V 0.800
1.994 VIN = 12V VOUT = 1.45V NO LOAD -40 -20 0 20 40 60 80 100
1.992
0.795 VIN = 12V NO LOAD 0.790 -40 -15 10 35 60 85
1.990 TEMPERATURE (C)
TEMPERATURE (C)
FB VOLTAGE vs. TEMPERATURE
MAX1937 toc24
1.465
1.460 FB VOLTAGE (V)
1.455
VOUT = 1.45V
1.450 VIN = 12V NO LOAD 1.445 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
10
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Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 NAME VID0 VID1 TIME VID2 VID3 VID4 VPOS VDD ILIM GND GNDS REF EN FB FUNCTION Voltage Identification Input Bit 0. See Table 1. Internal 100k pullup resistor to VDD. Voltage Identification Input Bit 1. See Table 1. Internal 100k pullup resistor to VDD. Connect to an external resistor (47k to 470k) for VID change slew-rate control. Voltage Identification Input Bit 2. See Table 1. Internal 100k pullup resistor to VDD. Voltage Identification Input Bit 3. See Table 1. Internal 100k pullup resistor to VDD. Voltage Identification Input Bit 4. See Table 1. Internal 100k pullup resistor to VDD. Voltage Positioning. Connect a resistor between VPOS and REF to set the output voltage-positioning droop, or connect directly to REF for no output voltage positioning. Connect a 47pF capacitor from VPOS to GND. IC Analog Power-Supply Input. Connect a 5V supply to VDD. Current-Limit Threshold per Phase. Connect ILIM to VDD to set a default current limit of 120mV, or connect to a voltage-divider from REF to GND to adjust the current limit. See the Setting the Current Limit section. Ground Remote Ground Sense. Connect GNDS to the output ground at the load. For VRM applications, also connect a 100 resistor from GNDS to PGND locally. Reference Output. Connect a 0.1F capacitor from REF to GND. Enable Input. Leave unconnected or drive high for normal operation. Drive low for shutdown. Remote Feedback Sense. Connect FB to the output at the load. For VRM applications, also connect a 100 resistor from FB to the output locally. Power-Good Output. Open-drain output is high impedance when the output is in regulation and pulled low when the output deviates more than 12.5% from the voltage set by the VID code. PWRGD is also low in shutdown or during any fault condition. To use as a logic output, connect a pullup resistor from PWRGD to the logic supply. High-Side MOSFET Gate-Driver Bootstrap Input. Connect 0.22F or higher value bypass capacitor from BST2 to LX2. Keep trace length as short as possible. Connect a Schottky diode between BST2 and VLG. See the Selecting a BST Capacitor section. High-Side MOSFET Gate-Drive Output. Connect to the high-side MOSFET gate. DH2 is pulled low in shutdown. Inductor Connection. Connect to the switched side of the inductor. Negative Current-Sense Input. Connect to a current-sense resistor in series with the low-side MOSFET, or connect to LX2 to use the low-side MOSFET's on-resistance for current sensing. Low-Side MOSFET Gate-Driver Output. Connect to the low-side MOSFET gate. DL2 is pulled low in shutdown. Power Ground. Connect to power ground at the point where the current-sense resistors or low-side MOSFET sources connect. PGND is used as the positive current-sense connection.
MAX1937/MAX1938/MAX1939
15
PWRGD
16
BST2
17 18 19 20 21
DH2 LX2 CS2 DL2 PGND
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Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change MAX1937/MAX1938/MAX1939
Pin Description (continued)
PIN 22 NAME VLG FUNCTION DL_ Driver Power-Supply Input. Connect to a 4.5V to 6.5V supply for powering the low-side MOSFET gate drive, and the bootstrap circuit for driving the high-side MOSFETs. Ensure that VVLG is greater than or equal to VVDD. Low-Side MOSFET Gate-Driver Output. Connect to the low-side MOSFET gate. DL1 is pulled low in shutdown. Negative Current-Sense Input. Connect to a current-sense resistor in series with the low-side MOSFET or connect to LX1 to use the low-side MOSFET's on-resistance for current sensing. Inductor Connection. Connect to the switched side of the inductor. High-Side MOSFET Gate-Drive Output. Connect to the high-side MOSFET gate. DH1 is pulled low in shutdown. High-Side MOSFET Gate-Driver Bootstrap Input. Connect 0.22F or higher value bypass capacitor from BST1 to LX1. Keep trace length as short as possible. Connect a Schottky diode between BST1 and VLG. See the Selecting a BST Capacitor section. Input Voltage Sense. Connect to the input supply at the high-side MOSFET drain. The voltage sensed at VCC is used to set the on-time.
23 24 25 26
DL1 CS1 LX1 DH1
27
BST1
28
VCC
Detailed Description
The MAX1937/MAX1938/MAX1939 is a family of synchronous, two-phase step-down controllers capable of delivering load currents up to 60A. The controllers use Quick-PWM control architecture in conjunction with active load current voltage positioning. Quick-PWM control provides instantaneous load-step response, while programmable voltage positioning allows the converter to utilize full transient regulation limits, reducing the output capacitance requirement. Furthermore, the two phases operate 180 out-of-phase with an effective 500kHz switching frequency, thus reducing input and output current ripple, as well as reducing input filter capacitor requirements. The MAX1937/MAX1938/MAX1939 are compliant with the AMD Hammer, Intel VRM 9.0/VRM 9.1, and AMD Athlon Mobile VID code specifications (see Table 1 for VID codes). The internal DAC provides ultra-high accuracy of 0.75%. A controlled VID voltage transition is implemented to minimize both undervoltage and overvoltage overshoot during VID input change. Remote sensing is available for high output-voltage accuracy. The MOSFET switches are driven by with a 6V gate-drive circuit to minimize switching and crossover conduction losses to achieve efficiency as high as 90%. The MAX1937/MAX1938/ MAX1939 feature cycle-by-cycle current limit to ensure current limit is not exceeded. Crowbar protection is available to protect against output overvoltage.
12
On-Time One-Shot
The heart of the Quick-PWM core is the one-shot that sets the high-side switch on-time. This fast, low-jitter, one-shot circuitry varies the on-time in response to the input and output voltages. The high-side switch on-time is inversely proportional to the voltage applied to VCC and directly proportional to the output voltage. This algorithm results in a nearly constant switching frequency, despite the lack of a fixed-frequency clock generator. The benefits of a constant switching frequency are twofold: the frequency selected avoids noise-sensitive regions, and the inductor ripple current operating point remains relatively constant, resulting in easy design methodology and predictable output voltage ripple: t ON = K VOUT + VDROP VVCC
(
)
where the constant K is 4s and VDROP is the voltage drop across the low-side MOSFET's on-resistance plus the drop across the current-sense resistor (VDROP 75mV), if used. The on-time one-shot has good accuracy at the operating point specified in the Electrical Characteristics. Ontimes at operating points far removed from the conditions specified in the Electrical Characteristics can vary over a wide range. For example, the regulators run slower with input voltages greater than 12V because of the very short on-times required.
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Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change MAX1937/MAX1938/MAX1939
Table 1. VID Programmed Output Voltage
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VOUT (V) MAX1937 1.550 1.525 1.500 1.475 1.450 1.425 1.400 1.375 1.350 1.325 1.300 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925 0.900 0.875 0.850 0.825 0.800 Shutdown MAX1938 1.850 1.825 1.800 1.775 1.750 1.725 1.700 1.675 1.650 1.625 1.600 1.575 1.550 1.525 1.500 1.475 1.450 1.425 1.400 1.375 1.350 1.325 1.300 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 Shutdown MAX1939 2.000 1.950 1.900 1.850 1.800 1.750 1.700 1.650 1.600 1.550 1.500 1.450 1.400 1.350 1.300 Shutdown 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925 Shutdown
Note: In the above table, a zero indicates the VID_ pin is connected to GND or driven low, indicates the VID_ pin is driven high or not connected.
While the on-time is set by the input and output voltage, other factors contribute to the switching frequency. The on-time guaranteed in the Electrical Characteristics is influenced by switching delays in the external high-side MOSFET. Resistive losses in the inductor, both MOSFETs, output capacitor ESR, and PC board copper losses in
the output and ground, tend to raise the switching frequency at higher output currents. Switch dead-time can also increase the effective on-time, reducing the switching frequency. This effect occurs when the inductor current reverses at light or negative load currents. With reversed inductor current, the inductor's
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Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change MAX1937/MAX1938/MAX1939
EMF causes LX to go high earlier than normal, extending the on-time by a period equal to the DH rising dead-time. When the controller operates in continuous mode, the dead-time is no longer a factor, and the actual switching frequency is: fSW = VOUT + VDROP1 t ON (VVCC + VDROP1 - VDROP2 ) Once regulation is achieved, the controller returns to 180 out-of-phase operation. A minimum current-adaptive phase-selection algorithm is used to determine which phase is used to start the first out-of-phase cycle. Once the output voltage returns to the nominal output voltage regulation value, the subsequent cycle starts with the phase that has the lowest inductor current. For example, if the current-sense inputs indicate that phase 2 has lower inductor current than phase 1, the controller turns on phase 2's high-side MOSFET first when returning to normal operation.
where VDROP1 is the sum of the parasitic voltage drops in the inductor discharge path, including the synchronous rectifier, inductor, and PC board resistances; VDROP2 is the sum of the resistances in the charging path, including the high-side MOSFET, inductor, and PC board resistances.
Differential Voltage Sensing and Error Comparator
The MAX1937/MAX1938/MAX1939 use differential sensing of the output voltage to achieve the highest possible accuracy of the output voltage. This allows the error comparator to sense the actual voltage at the load, so that the controller can compensate for losses in the power output and ground lines. FB and GNDS are used for the differential output voltage sensing. The controller triggers the next cycle (turn on the high-side MOSFET) when the error comparator is low (VFB - VGNDS is less than the VID regulation voltage), VCS is below the current-limit threshold, and the minimum off-time one-shot has timed out. Traces from FB and GNDS should be routed close to each other and as far away as possible from sources of noise (such as the inductors and high di/dt traces). If noise on these connections cannot be prevented, then use RC filters. To filter FB, connect a 100 series resistor from the positive sense trace to FB, and connect a 1000pF capacitor from FB to GND right at the FB pin. For GNDS, connect a 100 series resistor from the negative sense trace to GNDS, and connect a 1000pF capacitor from GNDS to GND at the GNDS pin. For VRM applications, connect a 10k resistor from FB to the output locally (on the VRM board), and connect a 10k resistor from GNDS to PGND locally (on the VRM board). FB and GNDS also connect to the output at the load (off the VRM board, at the microprocessor). This provides the benefits of differential output voltage sensing mentioned above and the safety of regulating the output voltage on the board in case the external sense connections get disconnected.
Synchronized 2-Phase Operation
The two phases of the MAX1937/MAX1938/MAX1939 operate 180 out-of-phase to reduce input filtering requirements, reduce electromagnetic interference (EMI), and improve efficiency. This effectively lowers cost and saves board space, making the MAX1937/ MAX1938/MAX1939 ideal for cost-sensitive applications. With dual synchronized out-of-phase operation, the MAX1937/MAX1938/MAX1939s' high-side MOSFETs turn on 180 out-of-phase. The instantaneous input current peaks of both regulators do not overlap, resulting in reduced input voltage ripple and RMS ripple current. This reduces the input capacitance requirement, allowing fewer or less expensive capacitors, and reduces shielding requirements for EMI. The 180 out-of-phase waveforms are shown in the Typical Operating Characteristics. Each phase operates with a 250kHz switching frequency. Since the two regulators operate 180 out-of-phase, an effective switching of 500kHz is seen at the input and output. In addition to being at a higher frequency (compared to a single-phase regulator), both the input and output ripple have lower amplitude.
Phase Overlap
To minimize the crosstalk noise in the two phases, the maximum duty cycle of the MAX1937/MAX1938/ MAX1939 is less than 50%. To provide a fast transient response, these devices have a phase-overlap mode that allows the two phases to operate in phase when a heavy-load transient is detected. In-phase operation continues until the output voltage returns to the nominal output voltage regulation value.
External Linear Regulator
A 6V linear regulator (U2) is used to step down the main supply. The output of this linear regulator is connected to VLG to provide power for the low-side gate drive and bootstrap circuit. Using 6V for this supply improves efficiency by providing a stronger gate drive than a 5V supply. To reduce switching noise on VLG,
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Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change MAX1937/MAX1938/MAX1939
VIN INPUT: 8V TO 14V 6 x 10F CERAMIC CAPACITORS TAIYO YUDEN TMK432BJ106MM AND 2 x 100F OS-CON SANYO 16SP100M IR: 2 x IRLR7811W L1 0.66H VOUT OUTPUT 0.8V TO 1.55V 46A
U2 KA78M06 3 1 IN OUT GND 2 C2 2.2F
1
D1
2
R1 10
VDD
CVLG 1F 28 8 26 25 1
CIN N3 2 N1 3 CBST1 0.22F N3
CENTRAL C1 CMHD4448 2.2F C3 2.2F
VCC VDD
DH1 LX1
CVDD 0.01F 1 2 4 5 6 13 RTIME 120k
VID0 VID1 VID2 VID3 VID4 EN
VID0 VID1 VID2 VID3 U1 VID4 EN MAX1937
BST1 DL1 CS1
27 23 24 2 22 3 D2 CENTRAL CMPSH-3A 1 1
SUMIDA CDEP134-6 2 FAIRCHILD 2 x ISL9N303AS3ST 3 1m RCS1
VLG
PGND CS2 DL2 BST2
21 19 20 16 18 17 1 14 N2 R6 10k 2 CBST2 0.22F N4 1
1m RCS2 3 FAIRCHILD 2 x ISL9N303AS3ST L2 0.66H 2 SUMIDA CDEP134-6 3 IR: 2 x 1RLR7811W VIN
3
CVPOS 47pF CREF 0.47F RVPOS 51.1k
TIME
7
VPOS
LX2 DH2
12 R3 200k 9 10 11 R5 10k
REF
R4 68k
ILIM GND GNDS
BF
FB
GNDS
PWRGD
13
VDD R2 100k 6 x 390F SP-CAP PANASONIC EEFUE0D391XR AND 4 x 1F CERAMIC CAPACITORS TAIYO YUDEN LMK212BJ105MG PWRGD COUT
Figure 1. MAX1937 Application Circuit
connect a capacitor (CVLG) from VLG to PGND. Place this capacitor as close as possible to the VLG pin. The MAX1937/MAX1938/MAX1939 also require an external 5V supply connected to VDD. A diode with a forward voltage drop of about 1V (D1) is used to stepdown the 6V supply to power the IC, as shown in Figure 1. The diode connects between the linear regulator output and the RC filter used to filter the voltage at VDD (R1, CVDD, and C3). In the PC board layout, place CVDD as close as possible to the VDD pin.
High-Side Gate-Drive Supply (BST_)
The drive voltage for the high-side MOSFETs is generated using a bootstrap circuit. The capacitor, CBST_, should be sized properly to minimize the ripple voltage for switching. The ripple voltage should be less than 200mV. For more information on selecting capacitors for the BST circuit, see the Selecting a BST Capacitor section. To minimize the forward voltage drop across the bootstrap diodes (D2), use Schottky diodes. The recommended value for the boost capacitors (CBST_) is 0.22F.
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Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change MAX1937/MAX1938/MAX1939
MOSFET Drivers
The DH_ and DL_ drivers are optimized for driving large high-side (N1 and N2) and larger low-side MOSFETs (N3 and N4). This is consistent with the low duty-cycle operation of the controller. The DL_ low-side drive waveform is always the complement of the DH_ high-side drive waveform, with a fixed dead-time between one MOSFET turning off and the other turning on to prevent cross-conduction or shoot-through current. The internal transistor that drives DL_ low is robust with a 0.5 (typ) on-resistance. This helps prevent DL_ from being pulled up during the fast rise time of the LX_ node due to capacitive coupling from the drain to the gate of the low-side synchronous-rectifier MOSFET. However, some combinations of high-side and low-side MOSFETs may cause excessive gate-drain coupling, leading to poor efficiency, EMI, and shoot-through currents. This is often remedied by adding a resistor (typically less than 5) in series with BST_, which increases the turn-on time of the high-side MOSFET without degrading the turn-off time.
Current Balancing
The DC current balancing between phases depends on the accuracy of the current-sense elements and the offset of the current-balance amplifier. The maximum offset of the current-balance amplifier (VCBOFFSET) is 3mV. The current-balance accuracy can be calculated from: Current-balance accuracy = VCBOFFSET / (IL RCS) where IL is the peak inductor current and RCS is the value of the current-sense resistor. The current-balance accuracy is most important at full load. With a load current of 50A (IL = 25A) and 2m current-sense resistors, the worst-case current-balance accuracy is: Current-balance accuracy = 0.003 / (25 0.002) = 6% If the on-resistance of the low-side MOSFETs is used for current sensing, the part-to-part variation of the MOSFET on-resistance is a significant factor in the current balance. The matching between MOSFETs should be on the order of 15%, worst case. Thus, even if the current-balance amplifier has no offset, the DC-current balance could be as bad as 15%. In practice, a little help is received from the thermal ballasting of the MOSFETs. That is to say, the positive temperature coefficient of the on-resistance of MOSFETs reduces the mismatch current between the two phases.
Current-Limit Circuit
The MAX1937/MAX1938/MAX1939 use either the onresistance of the low-side MOSFETs or a current-sense resistor to monitor the inductor current. Using the lowside MOSFETs' on-resistance as the current-sense element provides a lossless and inexpensive solution ideal for high-efficiency or cost-sensitive applications. The disadvantage to this method is that the on-resistance of MOSFETs vary from part to part, and overtemperature, which means it cannot be counted on for high accuracy. If high accuracy is needed, use current-sense resistors, which provide an accurate current limit under all conditions but reduce efficiency slightly because of the power lost in the resistors. The current-limit circuit employs a "valley" currentsensing algorithm to monitor the inductor current. If the current-sense signal does not drop below the currentlimit threshold, the controller does not initiate a new cycle. This limits the maximum value of IVALLEY to the current set by the current-limit threshold (Figure 2). The current-limit threshold is adjustable over a wide range, allowing for a range of current-sense resistor values. The voltage on ILIM sets the current-limit threshold between PGND and CS_ to 0.1 VILIM. The 10mV to 200mV adjustment range corresponds to ILIM voltages from 100mV to 2V. The ILIM voltage is set by a resistor-divider between REF and GND. See the Setting the Current Limit section for details.
Voltage Positioning (VPOS)
During a load transient, the output voltage instantly changes by the ESR of the output capacitors times the change in load current (VOUT = -ESRCOUT ILOAD). Conventional DC-DC converters respond by regulating the output voltage back to its nominal state after the load transient occurs (Figure 3). However, the CPU requires that the output voltage remain within a specific voltage band. Dynamically positioning the output voltage allows the use of fewer output capacitors and reduces power consumption under heavy load. For a conventional (nonvoltage-positioned) circuit, the total output voltage deviation from light load to full load and back to light load is: VP-P1 = 2 (ESRCOUT ILOAD) + VSAG + VSOAR where V SAG and V SOAR are defined in the Output Capacitor Selection section. Setting the converter to regulate at a lower voltage when under load allows a larger voltage step when the output current suddenly decreases. The total voltage change for a voltage-positioned circuit is: VP-P2 = (ESRCOUT ILOAD) + VSAG +VSOAR
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Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change MAX1937/MAX1938/MAX1939
VOLTAGE POSITIONING THE OUTPUT
IPEAK 1.4V ILOAD INDUCTOR CURRENT A
IVALLEY 1.4V B
TIME
A. CONVENTIONAL CONVERTER (50mV/div) B. VOLTAGE-POSITIONED OUTPUT (50mV/div)
Figure 2. Inductor Current Waveform
Figure 3. Voltage-Positioning and Nonvoltage-Positioning Waveforms
The maximum allowable voltage change during a transient is fixed by the supply range of the CPU (VP-P1 = VP-P2). This means that the voltage-positioned circuit tolerates twice the ESR in the output capacitors. Because the ESR specification is achieved by paralleling several capacitors, fewer capacitors are needed for the voltage-positioned circuit. Figure 4 shows transient response regions. An additional benefit of voltage positioning is reduced power consumption at high-load currents. Because the output voltage is lower under heavy load, the CPU draws less current. The result is lower power dissipation in the CPU.
In the case of shutdown by VID code, only DL_ and DH_ are held low. The rest of the controller is enabled. When EN is driven high, the startup sequence begins. Once the reference voltage rises above its 1.6V UVLO threshold, the controller begins switching and starts to ramp up the output voltage. The output voltage is ramped up in 25mV steps every 50s until the output reaches the nominal output voltage.
Fault Conditions
The MAX1937/MAX1938/MAX1939 contain internal circuitry to protect themselves and surrounding circuitry from damage from output overvoltage and output undervoltage conditions. When either of these conditions occurs, DH_ is pulled low, DL_ is driven high, and PWRGD is pulled low. These pins remain in this state until either power is cycled on VDD or EN is toggled high-low-high.
Voltage Reference (REF)
A 2V reference is provided on the MAX1937/MAX1938/ MAX1939 through the REF pin. REF is capable of sourcing or sinking up to 50A. In addition to providing a reference for the IC, REF is used for setting the current limit and voltage positioning. Connect a 0.47F capacitor from REF to GND. This capacitor should be placed as close as possible to the REF pin. A UVLO is provided for the reference voltage. The reference voltage must rise above 1.600V to activate the controller. The controller is disabled if the reference voltage falls below 1.584V.
Setting the Output Voltage (VID_)
An internal DAC is used to set the output regulation voltage. A 5-bit code on inputs VID0-VID4 is used to specify the output voltage. Some codes disable the output. There is an internal 100k pullup resistor to VDD on each of the VID_ inputs. Connecting VID_ to GND sets the bit to logic low (0); connecting VID_ to VDD or leaving it unconnected sets the bit to logic high (1). Use external pullup resistors to speed the low-tohigh logic transition, or for lower logic voltages. See Table 1 for a list of codes and corresponding output regulation voltages for each of the parts. The VID_ codes for the MAX1937 comply with AMD Hammer code. The VID_ codes on the MAX1938 are
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Enable Input (EN) and Soft-Start
When EN is low, DL_ and DH_ are held low (turning off the MOSFETs), leaving LX_ high impedance. In addition, the reference is turned off and PWRGD is pulled low. In shutdown, total current consumption is about 50A (typ).
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Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change MAX1937/MAX1938/MAX1939
CAPACITIVE SOAR (dV/dt = IOUT/COUT) ESR VOLTAGE STEP (ISTEP x RESR)
Design Procedure
Output Inductor Selection
For most applications, an inductor value of 0.5H to 1H is recommended. The inductance is set by the desired amount of inductor current ripple (LIR). A larger inductance value minimizes output ripple current and increases efficiency, but slows transient response. For the best compromise of size, cost, and efficiency, a LIR of 30% to 40% is recommended (LIR = 0.3 to 0.4). The inductor value is found from:
VOUT
CAPACITIVE SAG (dV/dt = IOUT/COUT)
RECOVERY
L=
ILOAD
VOUT x VIN - VOUT
(
)
VIN x fSW x ILOAD(MAX) x LIR
Figure 4. Transient Response Regions
set for Intel VRM 9.0/9.1 and AMD Athlon. The MAX1939 is set for AMD Athlon Mobile.
where fsw is the actual switching frequency of a phase. The selected inductor should have the lowest possible equivalent DC resistance and a saturation current greater than the peak inductor current (IPEAK). IPEAK is found from: LIR IPEAK = ILOAD(MAX) x 1+ 2
VID_ Change Slew Rate (TIME)
The MAX1937/MAX1938/MAX1939 allow the VID_ code to be changed while the converter is operating (on-thefly). The slew rate at which the output voltage is changing is controlled through TIME. The slew rate is adjusted externally by connecting a 47k to 470k resistor (RTIME) from TIME to GND. To set the slew rate, select the RTIME resistor using the following equation: RTIME = 521 () SR
Output Capacitor Selection
The output capacitor must have low enough ESR to meet output ripple and load-transient requirements. Also, the capacitance value must be high enough to absorb the inductor energy going from a full-load to a no-load condition without tripping the OVP circuit. In CPU core power supplies and other applications where the output is subject to large load transients, the output capacitor's size typically depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance: RESR = VSTEP(MAX) / ILOAD(MAX) The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of OSCONs, SP capacitors, POSCAPs, and other electrolytic capacitors). Generally, ceramic capacitors are not recommended for bulk output capacitance but make excellent high-frequency decoupling capacitors. Once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge
where SR is the slew rate of the output voltage in V/s. The output voltage is stepped up or down in 25mV steps until it reaches the voltage set by the new VID code.
Power-Good Output (PWRGD)
PWRGD is an open-drain output that is pulled low when the output voltage deviates more than 12.5% from its regulation voltage (set by VID_ inputs). PWRGD is pulled low in shutdown, input UVLO, and during startup. Any fault condition forces PWRGD low until the fault is cleared, and the IC is reset by cycling power at VDD or momentarily toggling EN. For logic-level output voltages, connect an external pullup resistor between PWRGD and the logic power supply. A 100k resistor works well in most applications.
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Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change
(VSAG) is no longer a problem. The amount of overshoot from stored inductor energy can be calculated as: VSOAR = I2PEAK x L 2 x COUT x VOUT tems that may be powered from very low impedance sources. Multiple smaller value capacitors can be used in parallel to satisfy the ESR and capacitance requirements.
MAX1937/MAX1938/MAX1939
Selecting a BST Capacitor
The BST capacitors must be large enough to handle the gate-charging requirements of the high-side MOSFETs. For most applications, 0.22F ceramic capacitors are recommended. BST capacitors are needed to keep the voltage on the BST_ pins from dropping too much when the high-side MOSFET gates are charged. A capacitor value that prevents VBST_ from dropping more than 100mV to 200mV is adequate. The capacitance needed for the BST_ capacitor is calculated from: CBST _ = QGH VBST _
where IPEAK is the peak inductor current. The undershoot at the rising load edge of a load transient is calculated from:
V xK L x I2LOAD x OUT + t OFF(MIN) VIN VSAG = (VIN - VOUT ) x K 2 x COUT x VOUT x - t OFF(MIN) VIN
where ILOAD is the change in load current, and K is 4s. To ensure stability, make sure that the zero frequency created by the output capacitance, and the ESR of the output capacitor do not exceed 50kHz. The zero frequency is found from: fzESR = 1 2 x ESRCOUT x COUT
where QGH is the total gate charge of the high-side MOSFET and VBST_ is the amount that the voltage on the BST_ pin drops when the gate is charged. If using multiple MOSFETs in parallel, use the sum of all the gate charges for QGH.
Setting the Current Limit
Current limit sets the maximum value of the inductor "valley" current. IVALLEY is calculated from the following equation: IVALLEY = ILOAD(MAX) 2 LIR x 1 - 2
Currently, aluminum electrolytic, Sanyo POSCAP, and Panasonic SP capacitors have ESR zero frequencies well below 50kHz. When using ceramic capacitors, it might be necessary to use a series resistance to ensure that the ESR zero is below 50kHz.
Input Capacitor Selection
The input capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the circuit's switching. The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents as defined by the following equation: I IRMS = LOAD 2 VOUT x (VIN - VOUT ) VIN
The current-limit threshold (ILIMIT) must be set higher than the valley current: ILIMIT > IVALLEY The current-limit threshold is set by the voltage at ILIM and the value of the current-sense resistors: ILIMIT = VILIM 10 x RCS
I RMS has a maximum value when the input voltage equals twice the output voltage (V IN = 2V OUT ), so IRMS(MAX) = ILOAD / 2. For most applications, nontantalum capacitors (ceramic, aluminum electrolytic, polymer, or OS-CON) are preferred at the input because of their robustness with high inrush currents typical of sys-
where VILIM is the voltage on the ILIM pin (0.1V to 2V) and RCS is the value of the current-sense resistor. If the on-resistance of the low-side MOSFET is used for current sensing, then the maximum value of the on-resistance (overtemperature and part-to-part variation) must be used for RCS.
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Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change MAX1937/MAX1938/MAX1939
VILIM is set from 0.5V to 2V by connecting ILIM to a resistor-divider from REF to GND. Select resistors R3 and R4 such that the current through the divider is at least 5A: R3 + R4 400k A typical value for R3 is 200k; then solve for R4 using: R4 = R3 x VILIM 2 - VILIM PD(HS)COND = VOUT x I2LOADMAX x RDS(ON) 4 x VIN
where RDS(ON) is the on-resistance of the high-side MOSFET and VIN is the input voltage. To minimize conduction losses, select a MOSFET with a low RDS(ON). Switching losses are also a major contributor to power dissipation in the high-side MOSFET. Switching losses are difficult to precisely calculate and should be measured in the circuit. To estimate the switching losses, use the following equation: V xf PD(HS)SW (IPEAK x t fall + IVALLEY x trise ) IN SW 2 where IPEAK and IVALLEY are the maximum peak and valley inductor currents, tFALL and tRISE are the fall and rise times of the high-side MOSFET, and fSW is the switching frequency (about 250kHz). The total power dissipated in the high-side MOSFET is then found from: PD(HS) = PD(HS)COND + PD(HS)SW The power dissipation in the low-side MOSFET is highest at low duty cycles (high input voltage, low output voltage), and is mainly because of conduction losses: V I2LOADMAX PD(LS)COND = 1- OUT x x RDS(ON) VIN 4 Switching losses in the low-side MOSFET are small because of its voltage being clamped by the body diode. Switching losses can be estimated from: I PD(LS)SW LOADMAX x tDT x VDF x fSW 2 where ILOADMAX/2 is the maximum average inductor current, tDT is the time/cycle that the low-side MOSFET conducts through its body diode, and VDF is the forward voltage drop across the body diode. The total power dissipation in the low-side MOSFET is: PD(LS) = PD(LS)COND + PD(LS)SW
Setting the Voltage Positioning
Voltage positioning dynamically changes the outputvoltage set point in response to the load current. When the output is loaded, the signals fed back from the current-sense inputs adjust the output voltage set point, thereby decreasing power dissipation. The load-transient response of this control loop is extremely fast yet well controlled, so the amount of voltage change can be accurately confined within the limits stipulated in the microprocessor power-supply guidelines. To understand the benefits of dynamically adjusting the output voltage, see the Voltage Positioning (VPOS) section. The amount of output voltage change is adjusted by an external gain resistor (RVPOS). Connect RVPOS between REF and VPOS. The output voltage changes in response to the load current as follows: I x RCS VOUT = VVID - gm(VPOS) x RVPOS x OUT 2 where VVID is the programmed output voltage set by the VID code (Table 1), and the voltage-positioning transconductance (gm(VPOS)) is typically 20S. RCS is the value of the current-sense resistor connected from CS_ to PGND. If the on-resistance of the low-side MOSFETs is used instead of current-sense resistors for current sensing, then use the maximum on-resistance of the low-side MOSFETs for R CS in the equation above.
MOSFET Power Dissipation
Power dissipation in the high-side MOSFET is worst at high duty cycles (maximum output voltage, minimum input voltage). Two major factors contribute to the highside power dissipation, conduction losses, and switching losses. Conduction losses are because of current flowing through a resistance, and can be calculated from:
IC Power Dissipation
During normal operation, power dissipation in the controller is mostly from the gate drivers. This can be calculated from the following equation: PGATE = 2 VVLG fSW ( QGH + QGL)
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Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change
where fSW is approximately 250kHz, QGH is the gate charge of the high-side MOSFET, and QGL is the gate charge of the low-side MOSFET. The values used for the gate charge are at the gate drive voltage (VVLG). The "2" in the above equation is due to the two phases of the converter. If multiple MOSFETs are used in parallel, add the gate charges of each MOSFET to find the total gate charge used in the above equation. Make sure that the maximum power dissipation of the IC is not exceeded (see the Absolute Maximum Ratings). rent traces short and wide to reduce the resistance in these traces. Also make the gate-drive connections (DH_ and DL_) short and wide, measuring 10 to 20 squares (50mils to 100mils wide if the MOSFET is 1in from the controller IC). Use Kelvin sense connections for the current-sense resistors. Place the REF capacitor, the VDD capacitor, and the BST_ diode and capacitor as close as possible to the IC. If the IC is far from the input capacitors, bypass VCC to GND with an additional 0.1F or greater ceramic capacitor close to the VCC pin. For an example PC board layout, refer to the MAX1937 or MAX1938 evaluation kit.
MAX1937/MAX1938/MAX1939
Applications Information
PC Board Layout Guidelines
A properly designed PC board layout is important in any switching DC-DC converter circuit. If possible, mount the MOSFETs, inductor, input/output capacitors, and current-sense resistor on the top side of the PC board. Connect the ground for these devices close together on a power ground plane. Make all other ground connections to a separate analog ground plane. Connect the analog ground plane to power ground at a single point. To help dissipate heat, place high-power components (MOSFETs, inductor, and current-sense resistor) on a large PC board area, or use a heat sink. Keep high cur-
Chip Information
TRANSISTOR COUNT: 6243 PROCESS: BiCMOS
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Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change MAX1937/MAX1938/MAX1939
Functional Diagram
EN VDD VCC
ENABLE/ SHUTDOWN
BIAS
CS1 CS2 FB ON-TIME COMPUTE
ON-TIME ONE-SHOT MIN OFF TIME ONE-SHOT BST1
REF - 12.5%
DH1
LX1 REF + 12.5% VLG PWRGD CONTROL LOGIC DL1
CS1 gm CS2
PGND
BST2
DH2
VLG VPOS
LX2 DL2
CURRENT BALANCE
REF ERROR AMP 2V UVLO/ OVLO DL2
FB
CURRENT LIMIT DL2
GNDS
VID DAC
GND
VID0-VID4
TIME
ILIM
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Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change
MAX1938 Typical Application Circuit
VIN INPUT: 8V TO 14V 10 x 10F CERAMIC CAPACITORS TAIYO YUDEN TMK432BJ106MM AND 4 x 330F SANYO 25MV330WX
MAX1937/MAX1938/MAX1939
1
U2 KA78M06 3 IN OUT GND 2
1
D1
2
R1 10
VDD
CVLG 1F 28 8 26 25 1
CIN N3 2 N1 3
C2 2.2F
CENTRAL C1 CMHD4448 2.2F C3 2.2F
VCC VDD
DH1 LX1
IR: 3X1RLR7811W CBST1 0.22F N3
CVDD 0.01F 1 2 4 5 6 13 RTIME 120k
L1 0.5H VOUT OUTPUT 0.8V TO 1.55V 60A
VID0 VID1 VID2 VID3 VID4 EN
VID0 VID1 VID2 VID3 U1 VID4 EN MAX1938
BST1 DL1 CS1
27 23 24 2 22 3 D2 CENTRAL CMPSH-3A 1 1
BI TECHNOLOGIES HM73-40R50 2 FAIRCHILD 2 x 1SL9N303AS3ST 3 1m RCS1
VLG
PGND CS2 DL2 BST2
21 19 20 16 18 17 CBST2 0.22F N4 IR: 3 x 1RLR7811W 1 14 N2 R6 10k 2 1
1m RCS2 3 FAIRCHILD 2 x 1SL9N303AS3ST L2 0.5H 2 BI TECHNOLOGIES HM73-40R50 3 IR: 2 x 1RLR7811W VIN
3
CVPOS 47pF CREF 0.47F RVPOS 51.1k
TIME
7
VPOS
LX2 DH2
12 R3 200k 9 10 11 R5 10k
REF
R4 82.5k
ILIM GND GNDS
BF
FB
GNDS
PWRGD
13
VDD R2 100k 6 x 560F/4V OS-CAN CAPACITORS SANYO SP560M AND 2 x 1F CERAMIC CAPACITORS TAIYO YUDEN: LMK212BJ105MG PWRGD
______________________________________________________________________________________
23
Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change MAX1937/MAX1938/MAX1939
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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