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| Features * Pixel Size: 11 m x 13 m (13 m Pitch) * High Data Output Rate: 20 MHz * High Responsivity and Resolution Over a Wide Spectral Range: from Blue (400 nm) up to Near Infrared (1,100 nm) * Low Dark Signal and Improved Uniformity * Low Temporal Noise and High Dynamic Range: Over 6000/1 * Ease and Flexibility of Operation: - Only Two External Basic Drive Clocks - Choice of Internal or External Sampling and Reset * 28-lead DIL Package * Available with Standard Window or Antireflective Window in the Bandwidth 450 to 750 nm Pin Identification Pin Number 2 3 4 5 9 10 11 12 13 14, 15, 28 16 18 19 20 21 24 25 26 27 1, 6, 7, 8, 17, 22, 23 Symbol VOSA Designation Video Output Signal A (Odd Channel) A Sample-and-hold Gate Input Channel A Internal Sampling Clock Output Channel A External Reset Clock Input Channel Output Amplifier Drain And Internal Logic Supply Test Point 3 Test Point 2 Register and Photosensitive Zone DC Bias Test Point 1 Substrate Bias (Ground) Internal Sampling Clock Inhibiting Input (Dc Bias) Transfer Clock Register Transport Clock Output Gate DC Bias B External Reset Clock Output Channel B Internal Sampling Clock Output Channel B Sample-and-hold Gate Input Channel Video Output Signal B (Even Channel) Reset DC Bias Do not Connect 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS VDR VOSB ECHB SECHB DNC DNC RB VGS T P DNC VINH VSS Linear CCD Image Sensor (2048 Pixels) TH7841A ECHA SECHA RA VDD TP3 TP2 VT TP1 VSS VINH P T VGS RB SECHB ECHB VOSB VDR DNC DNC VOSA ECHA SECHA RA DNC DNC DNC VDD TP3 TP2 VT TP1 VSS Rev. 1998A-IMAGE-05/02 1 T Absolute Maximum Ratings* Storage Temperature ..................................... -55C to +150C Operating Temperature........................................0C to +70C Thermal Cycling..........................................................15C/mn Maximum Voltages: * Pins: 3, 5, 9, 10, 11, 13, 16, 19, 20, 21, 25, 27........................................-0.3V to +18V * Pins: 12. 18 ......................................................-0.3V to +16V * Pins: 14, 15, 28 ................................................................. 0V *NOTICE: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. Operating Range Operating Precautions Operating range defines the temperature limits between which the functionality is guaranteed: 0C to 70C. Shorting the video output to VSS to VDD, even temporarily, can permanently damage the output amplifier. 2 TH7841A 1998A-IMAGE-05/02 TH7841A Operating Conditions (T = 25C) Table 1. DC Characteristics Values Parameter Output Amplifier Drain Supply Reset DC Bias Output Gate DC Bias Photosensitive Zone and Register DC Bias Substrate Bias Test Point 1 Test Points 2 and 3 Notes: Symbol VDD VDR VGS VT VSS TP1 TP2, TP3 Min 14 12 5.5 6 0.0 Typ 15 13 6 6.5 0.0 VDD VSS V V (3) (3) Max 16 14.5 6.5 7 Unit V V V V Note (1) (2) 1. It is recommended to maintain VDR at VDD - 2V. 2. VT nominal = ( V T )high + ( V T )low ----------------------------------------------------------- 5% 2 3. No use for operation - For testing purpose only. Basic Internal Configuration SECHA and RA SECHB and RB internal to TH7841A Table 2. Selection of Nominal Mode Option Internal Sampling Internal Reset Note: Implementation VINH (16) Connected to VSS SECHA (4) and ECHA (3) Strapped SECHB (24) and ECHB (25) Strapped RA (5) and RB (21) Connected to VDD Note (1) 1. Make the straps as short as possible to avoid any parasitic coupling to these connections. The load capacitance introduced by the strap should not exceed 5 pF. 3 1998A-IMAGE-05/02 Figure 1. Timing Diagram -- Clocks and Video Output Timing Diagram in Internal Sampling Mode Table 3. Drive Clock Characteristics (see Figure 1) Values Parameter Transfer Clock Register Transport Clock Register Transport Clock Capacitance Symbol PT CT Logic High Low Min 12 0.0 Typ 13 0.4 800 Max 14 0.6 1200 pF Unit V Note (1) Transfer Clock Capacitance CP 200 300 pF Note: 1. Transients under 0.0V in the clock pulses will lead to charge injection, causing a localized increase in the dark signal if such spurious negative transients are present, they can be suppressed by inserting a serial resistor of appropriate value (typically 20 to 100) in the corresponding driver output. 4 TH7841A 1998A-IMAGE-05/02 TH7841A Table 4. Static and Dynamic Electrical Characteristics Values Parameter DC Output Level Output Impedance Register Single-stage Transfer Efficiency Max. Data Output Frequency Input Current on Pins: 3, 5, 10,11,12, 13, 18, 19, 20, 21, 25 Peak Current Sink on T Clock Peak Current Sink on P Clock Output Amplifier Drain Supply Current Static Power Dissipation Notes: Symbol VREF ZS CTE FS max. Ie (IT )P (IP)P IDD PD 500 125 17 255 300 99.992 12 Min 8 Typ 10 500 99.998 20 2 Max 12 Unit V % MHz A mA mA mA mW VOS = 1V (1) (2) Note Ve = 15V All other pins: 0V trise = 15 ns trise = 15 ns VINH = 0V VDD = 15V VINH = 0V VDD = 15V 1. VOS = average video output voltage. Measurement excludes first and last pixels. 2. FS = 2FT . The minimum clock frequency is limited by the increase in dark signal. Electro-optical Performance General measurement conditions: TC = 25C; Ti = 1 ms; FT = 2.5 MHz. Light source: tungsten filament lamp (2854 K) + BG 38 filter (2 mm thick) + F/3.5 aperture. The filter limits the spectrum to 700 nm; in these conditions, 1 J/cm2 corresponds to 3.5 lux.s. Typical operating conditions; internal clock mode (see Table 2). First and last pixels, as well as reference elements, are excluded from the specification. Measurements taken on each output in succession. 5 1998A-IMAGE-05/02 Table 5. Electro-optical Performance Values Parameter Saturation Output Voltage Saturation Exposure Responsivity Responsivity Unbalance Photo-response No-uniformity Peak-topeak Contrast Transfer Function at FN (38 I p/mm) Temporal Noise in Darkness Dynamic Range (Relative to rms Noise) Average Dark Signal DR VDS 3000 Symbol VSAT ESAT R R/R PRNU CTF 2.5 Min 1.3 Typ 1.8 0.33 2.9 2 5 70 160 6000 0.08 0.5 0.5 mV mV (1) Max 2.2 Unit V J/cm2 V/J/cm2 Note (1)(2) 8 10 % % VOS % Vrms (3) VOS = 50 mV to 1V VOS = 0.75V (4) Dark Signal Non-uniformity DSNU 0.15 Notes: 1. Value measured with respect to zero reference level (see Figure 1). 2. Conversion factor is typically 1.1 V/e-. 3. R/R is defined as 200 RA - RB--------------------------------RA + RB where RA is responsivity of video output A RB is responsivity of video output B 4. Measured in Correlated Double Sampling (C.D.S.) mode. Figure 2. Typical Spectral Response 6 TH7841A 1998A-IMAGE-05/02 TH7841A Figure 3. CTF Typical Curves (2854 K Source) Electro-optical Performance Without Infrared Cut-off Filtering The TH7841A special semiconductor process exploits the silicon's high near infrared sensitivity while maintaining good imaging performance in terms of response uniformity and resolution. Typical changes in performance with and without IR filtering are summarized below. With IR Cut-off Filter Average Video Signal Due To a Given Scene Illumination PRNU (Single Defects Excluded) CTF at Nyquist Frequency VOS 5% 70% No IR Cut-off Filter VOS x 4 5% 50% Complementary Operating Modes The TH7841A may be used in several configurations in regards to video output sampling and charge sensing reset. 1. Sampling options Inhibition of internal sampling pulses allows two possibilities: a. no sampling: video output delivered in unsampled form, b. sampling by external clocks: external sampling pulses directly applied to ECHA, ECHB inputs. If internal sampling clocks S ECHA and SECHB are not used, it is recommended to unpower the corresponding clock drivers, as this will greatly reduce on-chip power consumption. 2. External reset position The position and period of the charge reset clocks may be optimized by using external clocks on RA and RB inputs. This is especially interesting to optimize the video outputs for Correlated Double Sampling (in order to reduce noise and improve S/N Ratio). Control signals to be applied in the different configurations are shown in Table 6. 7 1998A-IMAGE-05/02 Table 6. Selection of Operating Modes Option No Sampling Implementation Note (1) ECHA (3) and ECHB (25) Connected to VDD SECHA (4) and SECHB (24) Unconnected VINH (16) Connected to V DD Sampling Clocks Connected to ECHA - ECHB SECHA and SECHB Unconnected VINH (16) Connected to V DD Sampling By External Clocks See Figure 4 for sampling clock timing (1) Reset Control By External Clocks Note: 1. Drain supply current IDD 15V). Ext. RA on RA (5) Input See Figure 4 for reset clock timing Ext. RB on RB (21) Input decreases from 10 mA to 8 mA typically when internal sampling clock is disabled (VINH = V DD = Table 7. External RA, RB, ECHA, ECHB Clocks Characteristics Values Parameter External Reset Clock Sampling Clock Symbol Logic High Low Min 12 0.0 Typ 13 0.4 Max 14 0.6 Unit V V RA, RB, ECHA, ECHB CRA CRB CECHA CECHB Reset And Sampling Clock Capacitance 10 15 pF Insertion of a serial resistor (typically 100) at the driver output avoids spurious negative transients. 8 TH7841A 1998A-IMAGE-05/02 TH7841A Figure 4. Timing Diagram -- Clocks and Video Output Timing Diagram With and Without On-chip Sampling Table 8. Performance Improvement with External RA, RB Configuration(1)(2) Values Parameter Saturation Output Voltage Responsivity Dynamic Range Notes: Symbol VSAT R DR (Typ) 2.0 5.0 8,000 Unit V V/J/cm 2 1. Electro-optical performances obtained with complementary modes are not guaranteed for standard products. 2. The Conversion factor is typically 1.8 V/e-. 9 1998A-IMAGE-05/02 Packaging Information TH 7841A with standard window. Z = 1.28 0.23 2.16 Notes: 1. If an optical reference is needed, it is recommended to use the window face plane. 2. Variation of Z (azimuth) on the photosensitive area of a device is 0.1 mm 3. Variation of Y between the first and the last pixel of the linear area is 130 m. Ordering Code The ordering code is: TH7841 ACC 10 TH7841A 1998A-IMAGE-05/02 TH7841A TH7841A With Antireflective Window Improvements in the bandwidth 450-750 nm: * * 5% increase in responsivity (typical value: 3.0 V/J/cm2). limitation of the parasitic reflections. Package Drawing 2.16 Notes: 1. If an optical reference is needed, it is recommended to use the window face plane. 2. Variation of Z (azimuth) on the photosensitive area of a device is 0.1 mm 3. Variation of Y between the first and the last pixel of the linear area is 130 m. Ordering Code The ordering code is: TH7841 ACC-R 11 1998A-IMAGE-05/02 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-76-58-30-00 FAX (33) 4-76-58-34-80 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 literature@atmel.com Web Site http://www.atmel.com (c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the registered trademark of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper. 1998A-IMAGE-05/02 0M |
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