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19-3089; Rev 2; 11/04
KIT ATION EVALU BLE AVAILA
High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones
General Description Features
Six Regulators in One Package Step-Down DC-DC for I/O at 1.3A Step-Down DC-DC for Memory at 0.9A Step-Down Serial-Programmed DC-DC for CORE Up to 0.9A Three LDO Outputs for SRAM, PLL, and USIM Always-On Output for VCC_BATT Low Operating Current 60A in Sleep Mode (Sleep LDOs On) 130A with DC-DCs On (Core Off) 200A All Regulators On, No Load 5A Shutdown Current Optimized for X-Scale Processors Backup-Battery Input 1MHz PWM Switching Allows Small External Components Tiny 6mm x 6mm, 40-Pin and 7mm x 7mm, 48-Pin Thin QFN Packages
MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
The MAX1586/MAX1587 power-management ICs are optimized for devices using Intel X-ScaleTM microprocessors, including Smart Phones, PDAs, internet appliances, and other portable devices requiring substantial computing and multimedia capability at low power. The ICs integrate seven high-performance, low-operatingcurrent power supplies along with supervisory and management functions. Included are three step-down DC-DC outputs, three linear regulators, and a seventh always-on output. DC-DC converters power I/O, DRAM, and the CPU core. The I/O supply can be preset to 3.3V or adjusted to other values. The DRAM supply on the A and C devices is preset for 1.8V or 2.5V, while the MAX1586B DRAM supply is preset for 3.3V or 2.5V. The DRAM supply on all parts can also be adjusted with external resistors. The CPU core supply is serial programmed for dynamic voltage management and, on C devices, can supply up to 0.9A. Linear-regulated outputs are provided for SRAM, PLL, and USIM supplies. To minimize quiescent current, critical power supplies have bypass "sleep" LDOs that can be activated when output current is very low. Other functions include separate on/off control for all DC-DC converters, low-battery and dead-battery detection, a reset and power-OK output, a backup-battery input, and a two-wire serial interface. All DC-DC outputs use fast, 1MHz PWM switching and small external components. They operate with fixed-frequency PWM control and automatically switch from PWM to skip-mode operation at light loads to reduce operating current and extend battery life. The core output can be forced into PWM mode at all loads to minimize noise. A 2.6V to 5.5V input voltage range allows 1-cell lithium-ion (Li+), 3-cell NiMH, or a regulated 5V input. The MAX1587 is available in a tiny 6mm x 6mm, 40-pin thin QFN package. The MAX1586 features an additional linear regulator (V6) for VCC_USIM and lowbattery and dead- battery comparators. The MAX1586 is available in a 7mm x 7mm, 48-pin thin QFN package.
Ordering Information
PART MAX1586AETM MAX1586BETM MAX1586CETM MAX1587AETL MAX1587CETL TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 48 Thin QFN 7mm x 7mm 48 Thin QFN 7mm x 7mm 48 Thin QFN 7mm x 7mm 40 Thin QFN 6mm x 6mm 40 Thin QFN 6mm x 6mm
Pin Configurations and Selector Guide appear at end of data sheet.
Simplified Functional Diagram
MAIN BATTERY BACKUP BATTERY
IN
MAX1586 MAX1587
V1 V2 V3 VCC_IO 3.3V VCC_MEM 2.5V VCC_CORE 0.8V TO 1.3V VCC_PLL 1.3V VCC_SRAM 1.1V VCC_USIM 0V, 1.8V, 3.0V VCC_BATT
BKBT
Applications
PDA, Palmtop, and Wireless Handhelds Third-Generation Smart Cell Phones Internet Appliances and Web-Books
nRESET nVCC_FAULT nBATT_FAULT SYS_EN PWR_EN MR RSO POK DBO ON1-2 ON3-6
V4 V5 V6 V7
X-Scale is a trademark of Intel Corp. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
ABSOLUTE MAXIMUM RATINGS
IN, IN45, IN6, MR, LBO, DBO, RSO, POK, SCL, SDA, BKBT, V7, SLP, SRAD, PWM3 to GND...............-0.3V to +6V REF, CC_, ON_, FB_, DBI, LBI, V1, V2, RAMP, BYP, MR to GND ...........................................-0.3V to (VIN + 0.3V) PV1, PV2, PV3, SLPIN to IN...................................-0.3V to +0.3V V4, V5 to GND ..........................................-0.3V to (VIN45 + 0.3V) V6 to GND ..................................................-0.3V to (VIN6 + 0.3V) PV1 to PG1 ............................................................-0.3V to +6.0V PV2 to PG2 ............................................................-0.3V to +6.0V PV3 to PG3 ............................................................-0.3V to +6.0V LX1 Continuous Current....................................-1.30A to +1.30A LX2 Continuous Current........................................-0.9A to +0.9A LX3 Continuous Current........................................-0.9A to +0.9A PG1, PG2, PG3 to GND.........................................-0.3V to +0.3V V1, V2, V4, V5, V6 Output Short-Circuit Duration.......Continuous Continuous Power Dissipation (TA = +70C) 6mm x 6mm 40-Pin Thin QFN (derate 26.3mW/C above +70C) ...........................2105mW 7mm x 7mm 48-Pin Thin QFN (derate 26.3mW/C above +70C) ...........................2105mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = 3.6V, VBKBT = 3.0V, VLBI = 1.1V, VDBI = 1.35V, circuit of Figure 5, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER PV1, PV2, PV3, SLPIN, IN Supply Voltage Range IN45, IN6 Supply Voltage Range IN Undervoltage-Lockout (UVLO) Threshold VIN rising VIN falling MAX1586 Only V7 on, VIN below DBI threshold VIN = 3.0V MAX1587 No load (IPV1 + IPV2 + IPV3 + IIN + ISLPIN + IIN45 + IIN6) REG1 and REG2 on in switch mode, REG3 off REG1 and REG2 on in sleep mode, REG3 off All REGs on BKBT Input Current REF Output Voltage SYNCHRONOUS-BUCK PWM REG1 REG1 Voltage Accuracy FB1 Voltage Accuracy FB1 Input Current Error-Amplifier Transconductance Dropout Voltage (Note 1) FB1 = GND, 3.6V VPV1 5.5V, load = 0 to 1300mA FB1 used with external resistors, 3.6V VPV1 5.5V, load = 0 to 1300mA FB1 used with external resistors Referred to FB Load = 800mA Load = 1300mA 87 180 293 280 450 3.25 1.231 3.3 1.25 3.35 1.269 100 V V nA S mV ON1 = 0 ON1 = IN 0 to 10A load 1.2375 MAX1586 MAX1587 MAX1586 MAX1587 MAX1586 MAX1587 CONDITIONS PV1, PV2, PV3, IN, and SLPIN must connect together externally MIN 2.6 2.4 2.25 2.200 2.40 2.35 32 5 130 130 60 60 225 200 4 0.8 1.25 1.2625 A V A TYP MAX 5.5 5.5 2.55 2.525 UNITS V V V
Quiescent Current
2
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High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 3.6V, VBKBT = 3.0V, VLBI = 1.1V, VDBI = 1.35V, circuit of Figure 5, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER p-Channel On-Resistance n-Channel On-Resistance Current-Sense Transresistance p-Channel Current-Limit Threshold PWM Skip-Mode Transition Load Current OUT1 Maximum Output Current LX1 Leakage Current SYNCHRONOUS-BUCK PWM REG2 FB2 = GND, 3.6V VPV2 5.5V, load = 0 to 900mA REG2 Voltage Accuracy MAX1586A, MAX1587A, FB2 = IN, 3.6V VPV2 5.5V, load = 0 to 900mA MAX1586B, FB2 = IN, 3.6V VPV2 5.5V, load = 0 to 900mA FB2 Voltage Accuracy FB2 Input Current Error-Amplifier Transconductance Dropout Voltage p-Channel On-Resistance n-Channel On-Resistance Current-Sense Transresistance p-Channel Current-Limit Threshold PWM Skip-Mode Transition Load Current OUT2 Maximum Output Current LX2 Leakage Current SYNCHRONOUS-BUCK PWM REG3 REG3 from 0.7V to 1.475V, 2.6V VPV3 5.5V MAX1586A, MAX1586B, MAX1587A, load = 0 to 500mA MAX1586C, MAX1587C, load = 0 to 900mA -1.5 -1.5 68 +1.5 % +1.5 S Decreasing load current (Note 2) 2.6V VPV2_ 5.5V (Note 3) VPV2_ = 5.5V, LX2 = GND or PV2, VON2 = 0V 0.9 -10 +0.1 +10 -1.1 FB2 used with external resistors, 3.6V VPV2 5.5V, load = 0 to 900mA FB2 used with external resistors, VFB2 = 1.25V Referred to FB Load = 900mA (Note 1) ILX2 = -180mA ILX2 = -180mA, VPV2 = 2.6V ILX2 = 180mA ILX2 = 180mA, VPV2 = 2.6V 87 243 0.225 0.26 0.15 0.17 0.7 -1.275 30 -1.50 380 0.375 0.425 0.25 0.275 2.463 1.773 3.25 1.231 2.5 1.8 3.3 1.25 2.537 1.827 3.35 1.269 100 V nA S mV V/A A mA A A V Decreasing load current (Note 2) 2.6V VPV1 5.5V (Note 3) VPV1 = 5.5V, LX1 = GND or PV1, VON1 = 0V 1.3 -20 +0.1 +20 -1.55 ILX1 = -180mA ILX1 = -180mA, VPV1 = 2.6V ILX1 = 180mA ILX1 = 180mA, VPV1 = 2.6V CONDITIONS MIN TYP 0.18 0.21 0.13 0.15 0.5 -1.80 30 -2.10 MAX 0.3 0.35 0.225 0.25 UNITS V/A A mA A A
MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
REG3 Output Voltage Accuracy
Error-Amplifier Transconductance
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High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 3.6V, VBKBT = 3.0V, VLBI = 1.1V, VDBI = 1.35V, circuit of Figure 5, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER p-Channel On-Resistance n-Channel On-Resistance Current-Sense Transresistance p-Channel Current-Limit Threshold PWM Skip-Mode Transition Load Current OUT3 Maximum Output Current LX3 Leakage Current V4, V5, V6, V1 SLEEP, V2 SLEEP Output Current V7 Output Current REG4 Output Voltage REG4 Noise REG5 Output Voltage IN45, IN6 Input Voltage Range 0V setting (either ON6 low or serial programmed) REG6 Output Voltage (POR Default to 0V, Set by Serial Input) MAX1586 1.8V setting, load = 0.1mA to 35mA 2.5V setting, load = 0.1mA to 35mA 3.0V setting, load = 0.1mA to 35mA V7 Output Voltage V1 and V2 SLEEP Output Voltage Accuracy V1 and V2 SLEEP Dropout Voltage V6 Dropout Voltage V7 Switch Voltage Drop V4, V5, V6 Output Current Limit BKBT Leakage OSCILLATOR PWM Switching Frequency SUPERVISORY/MANAGEMENT FUNCTIONS POK Trip Threshold (Note 4) Rising Falling 92 88.5 94.75 90.5 97 92.5 % 0.93 1 1.07 MHz V1 on and in regulation V1 off Set to same output voltage as REG1 and REG2 LOAD = 20mA MAX1586 3V mode, load = 30mA, 2.5V mode, load = 30mA LOAD = 20mA, VBKBT = VV1 = 3.0V 40 -3.0 75 110 100 90 1 1.746 2.425 2.91 Load = 0.1mA to 35mA With 1F COUT and 0.01F CBYP Load = 0.1mA to 35mA 1.067 2.4 0 1.8 2.5 3.0 VV1 VBKBT +3.0 150 200 200 1.854 2.575 3.09 V % mV mV mV mA A V ILX3 = -180mA ILX2 = -180mA, VPV3 = 2.6V ILX3 = 180mA ILX3 = 180mA, VPV3 = 2.6V MAX1586A, MAX1586B, MAX1587A MAX1586C, MAX1587C MAX1586A, MAX1586B, MAX1587A MAX1586C, MAX1587C Decreasing load current (Note 2) 2.6V VPV3_ 5.5V (Note 3) MAX1586A, MAX1586B, MAX1587A MAX 1586C, MAX1587C 0.5 0.9 -10 +0.1 +10 -0.60 -1.125 CONDITIONS MIN TYP 0.225 0.26 0.15 0.17 1.1 0.55 -0.7 -1.35 30 -0.85 -1.700 MAX 0.375 0.425 0.25 0.275 UNITS V/A A mA A A
VPV3_ = 5.5V, LX3 = GND or PV2, VON3 = 0V
LDOS V4, V5, V6, V1 SLEEP, V2 SLEEP, AND V7 OUTPUT 35 30 1.261 1.3 15 1.1 1.133 5.5 1.339 mA mA V VRMS V V
4
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High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 3.6V, VBKBT = 3.0V, VLBI = 1.1V, VDBI = 1.35V, circuit of Figure 5, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER LBI Threshold (Falling) DBI Threshold (Falling) RSO Threshold (Falling) RSO Deassert Delay LBI Input Bias Current DBI Input Bias Current Thermal-Shutdown Temperature Thermal-Shutdown Hysteresis LOGIC INPUTS AND OUTPUTS LBO, DBO, POK, RSO, SDA Output Low Level LBO, DBO, POK, RSO Output Low Level LBO, DBO, POK, RSO Output-High Leakage Current ON_, SCL, SDA, SLP, PWM3, MR, SRAD Input High Level ON_, SCL, SDA, SLP, PWM3, MR, SRAD Input Low Level ON_, SCL, SDA, SLP, PWM3, MR, SRAD Input Leakage Current SERIAL INTERFACE Clock Frequency Bus-Free Time Between START and STOP Hold Time Repeated START Condition CLK Low Period CLK High Period Setup Time Repeated START Condition DATA Hold Time DATA Setup Time Maximum Pulse Width of Spikes that Must be Suppressed by the Input Filter of Both DATA and CLK Signals Setup Time for STOP Condition 0.6 1.3 0.6 1.3 0.6 0.6 0 100 50 400 kHz s s s s s s ns ns s 2.6V V7 5.5V, sinking 1mA V7 = 1V, sinking 100A Pin = 5.5V 2.6V VIN 5.5V 2.6V VIN 5.5V Pin = GND, 5.5V -1 1.6 0.4 +1 0.4 0.4 0.2 V V A V V A MAX1586 MAX1586 TJ rising CONDITIONS MAX1586 hysteresis is 5% (typ) MAX1586 hysteresis is 5% (typ) LBI = IN (for preset) With resistors at LBI DBI = IN (for preset) With resistors at LBI MIN 3.51 0.98 3.024 1.208 2.25 61 -50 TYP 3.6 1.00 3.15 1.232 2.41 65.5 -5 15 +160 15 50 MAX 3.69 1.02 3.276 1.256 2.56 70 UNITS V V V ms nA nA C C
MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
Voltage on REG7, hysteresis is 5% (typ)
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High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
ELECTRICAL CHARACTERISTICS
(VIN = 3.6V, VBKBT = 3.0V, VLBI = 1.1V, VDBI = 1.35V, circuit of Figure 5, TA = -40C to +85C, unless otherwise noted.) (Note 5)
PARAMETER PV1, PV2, PV3, SLPIN, IN Supply Voltage Range IN45, IN6 Supply Voltage Range IN Undervoltage-Lockout (UVLO) Threshold SYNCHRONOUS-BUCK PWM REG1 REG1 Voltage Accuracy FB1 Voltage Accuracy FB1 Input Current Dropout Voltage p-Channel On-Resistance n-Channel On-Resistance p-Channel Current-Limit Threshold OUT1 Maximum Output Current LX1 Leakage Current SYNCHRONOUS-BUCK PWM REG2 FB2 = GND, 3.6V VPV2 5.5V, load = 0 to 900mA REG2 Voltage Accuracy MAX1586A, MAX1587A, FB2 = IN, 3.6V VPV2 5.5V, load = 0 to 900mA MAX1586B, FB2 = IN, 3.6V VPV2 5.5V, load = 0 to 900mA FB2 Voltage Accuracy FB2 Input Current Dropout Voltage p-Channel On-Resistance n-Channel On-Resistance p-Channel Current-Limit Threshold OUT2 Maximum Output Current LX2 Leakage Current 2.6V VPV2_ 5.5V (Note 3) VPV2 = 5.5V, LX2 = GND or PV2, VON2 = 0V FB2 used with external resistors, 3.6V VPV2 5.5V, load = 0 to 900mA FB2 used with external resistors, VFB2 = 1.25V Load = 900mA (Note 1) ILX2 = -180mA ILX2 = -180mA, VPV2 = 2.6V ILX2 = -180mA ILX2 = -180mA, VPV2 = 2.6V -1.1 0.9 -10 +10 2.463 1.773 3.25 1.231 2.537 1.827 3.35 1.269 100 380 0.375 0.425 0.25 0.275 -1.50 V nA mV A A A V 2.6V VPV1 5.5V (Note 3) VPV1 = 5.5V, LX1 = GND or PV1, VON1 = 0V FB1 = GND, 3.6V VPV1 5.5V, load = 0 to 1300mA FB1 = IN, 3.6V VPV1 5.5V, load = 0 to 1300mA FB1 used with external resistors, 3.6V VPV1 5.5V, load = 0 to 1300mA FB1 used with external resistors Load = 800mA (Note 1) Load = 1300mA (Note 1) ILX1 = -180mA ILX1 = -180mA, VPV1 = 2.6V ILX1 = 180mA ILX1 = 180mA, VPV1 = 2.6V -1.55 1.30 -10 +10 3.25 2.955 1.231 3.35 3.045 1.269 100 280 450 0.3 0.35 0.225 0.25 -2.10 V V nA mV A A A VIN rising VIN falling CONDITIONS PV1, PV2, PV3, IN, and SLPIN must connect together externally MIN 2.6 2.4 2.25 2.200 MAX 5.5 5.5 2.55 2.525 UNITS V V V
6
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High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 3.6V, VBKBT = 3.0V, VLBI = 1.1V, VDBI = 1.35V, circuit of Figure 5, TA = -40C to +85C, unless otherwise noted.) (Note 5)
PARAMETER SYNCHRONOUS-BUCK PWM REG3 REG3 from 0.7V to 1.475V, 2.6V VPV3 5.5V ILX3 = -180mA ILX2 = -180mA, VPV3 = 2.6V ILX3 = 180mA ILX3 = 180mA, VPV3 = 2.6V MAX1586A, MAX1586B, MAX1587A MAX1586C, MAX1587C 2.6V VPV3_ 5.5V (Note 3) MAX1586A, MAX1586B, MAX1587A MAX1586C, MAX1587C -0.60 -1.125 0.5 0.9 -10 +10 MAX1586A, MAX1586B, MAX1587A, load = 0 to 500mA MAX1586C, MAX1587C, load = 0 to 900mA -1.5 -1.5 +1.5 % +1.5 0.375 0.425 0.25 0.275 -0.85 -1.700 A A A CONDITIONS MIN MAX UNITS
MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
REG3 Output Voltage Accuracy
p-Channel On-Resistance n-Channel On-Resistance p-Channel Current-Limit Threshold OUT3 Maximum Output Current LX3 Leakage Current V4, V5, V6, V1 SLEEP, V2 SLEEP Output Current V7 Output Current REG4 Output Voltage REG5 Output Voltage IN45, IN6 Input Voltage Range
VPV3 = 5.5V, LX3 = GND or PV2, VON3 = 0V
LDOs V4, V5, V6, V1 SLEEP, V2 SLEEP, AND V7 OUTPUT 35 30 Load = 0.1mA to 35mA Load = 0.1mA to 35mA 1.8V setting, load = 0.1mA to 35mA REG6 Output Voltage (POR Default to 0V, Set by Serial Input) V1 and V2 SLEEP Output Voltage Accuracy V1 and V2 SLEEP Dropout Voltage V6 Dropout Voltage V7 Switch Voltage Drop V4, V5, V6 Output Current Limit BKBT Leakage OSCILLATOR PWM Switching Frequency SUPERVISORY/MANAGEMENT FUNCTIONS POK Trip Threshold (Note 4) LBI Threshold (Falling) Rising Falling MAX1586, hysteresis is 5% (typ) LBI = IN (for preset) With resistors at LBI 92 88.5 3.51 0.98 97 92.5 3.69 1.02 % V 0.93 1.07 MHz MAX1586 2.5V setting, load = 0.1mA to 35mA 3.0V setting, load = 0.1mA to 35mA Set to same output voltage as REG1 and REG2 Load = 20mA MAX1586 3V mode, load = 30mA; 2.5V mode, load = 30mA Load = 20mA, VBKBT = VV1 = 3.0V 40 1 1.254 1.061 2.4 1.737 2.412 2.895 -3.5 1.346 1.139 5.5 1.863 2.588 3.105 +3.5 150 200 200 % mV mV mV mA A V mA mA V V V
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High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 3.6V, VBKBT = 3.0V, VLBI = 1.1V, VDBI = 1.35V, circuit of Figure 5, TA = -40C to +85C, unless otherwise noted.) (Note 5)
PARAMETER DBI Threshold (Falling) RSO Threshold (Falling) RSO Deassert Delay LBI Input Bias Current DBI Input Bias Current LOGIC INPUTS AND OUTPUTS LBO, DBO, POK, RSO, SDA Output Low Level LBO, DBO, POK, RSO, SDA Output Low Level LBO, DBO, POK, RSO Output-High Leakage Current ON_, SCL, SDA, SLP, PWM3, MR, SRAD Input High Level ON_, SCL, SDA, SLP, PWM3, MR, SRAD Input Low Level ON_, SCL, SDA, SLP, PWM3, MR, SRAD Input Leakage Current SERIAL INTERFACE Clock Frequency Bus-Free Time Between START and STOP Hold Time Repeated START Condition CLK Low Period CLK High Period Setup Time Repeated START Condition DATA Hold Time DATA Setup Time Setup Time for STOP Condition 1.3 0.6 1.3 0.6 0.6 0 100 0.6 400 kHz s s s s s s ns s 2.6V V7 5.5V, sinking 1mA V7 = 1V, sinking 100A Pin = 5.5V 2.6V VIN 5.5V 2.6V VIN 5.5V Pin = GND, 5.5V -1 1.6 0.4 +1 0.4 0.4 0.2 V V A V V A MAX1586 MAX1586 MAX1586, hysteresis is 5% (typ) CONDITIONS DBI = IN (for preset) With resistors at LBI MIN 2.993 1.208 2.25 62 -50 75 MAX 3.307 1.256 2.60 69 UNITS V V ms nA nA
Voltage on REG7, hysteresis is 5% (typ)
8
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High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones
ELECTRICAL CHARACTERISTICS (continued)
Note 1: Dropout voltage is guaranteed by the P-channel switch resistance and assumes a maximum inductor resistance of 45m. Note 2: The PWM-skip-mode transition has approximately 10mA of hysteresis. Note 3: The maximum output current is guaranteed by the following equation:
MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
IOUT max
VOUT (1 - D) 2xfxL = (1 - D) 1 + (RN + RL) 2xfxL ILIM -
where:
D=
VOUT + IOUT(MAX) (RN + RL) VIN + IOUT(MAX) (RN - RP)
RN = N-channel synchronous rectifier RDS(ON) RP = P-channel power switch RDS(ON) RL = external inductor ESR IOUT(MAX) = maximum required load current f = operating frequency minimum L = external inductor value ILIM can be substituted for IOUT(MAX) (desired) when solving for D. This assumes that the inductor ripple current is small relative to the absolute value. Note 4: POK only indicates the status of supplies that are enabled (except V7). When a supply is turned off, POK does not trigger low. When a supply is turned on, POK immediately goes low until that supply reaches regulation. POK is forced low when all supplies (except V7) are disabled. Note 5: Specifications to -40C are guaranteed by design, not production tested. and
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High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
Typical Operating Characteristics
(Circuit of Figure 6, VIN = 3.6V, TA = +25C, unless otherwise noted.)
REG1 3.3V OUTPUT EFFICIENCY vs. LOAD CURRENT
VIN = 3.6V 90 VIN = 4.0V EFFICIENCY (%) 80 70 60 50 40 0.1 1 10 100 1000 10,000 LOAD CURRENT (mA) VIN = 5.0V
MAX1586A/86B/87A toc01
REG2 2.5V OUTPUT EFFICIENCY vs. LOAD CURRENT
MAX1586A/86B/87A toc02
REG3 1.3V OUTPUT EFFICIENCY vs. LOAD CURRENT
MAX1586A/86B/87A toc03
100
100 90 80 70 60 50 40 0.1 1 10 100 VIN = 3.6V VIN = 4.0V VIN = 5.0V
100 90 80 VIN = 4.0V 70 60 50 40 VIN = 5.0V
VIN = 3.6V
EFFICIENCY (%)
1000
EFFICIENCY (%)
0.1
1
10
100
1000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
REG3 1.3V OUTPUT EFFICIENCY vs. LOAD CURRENT
MAX1586A/86B/87A toc03B
REG3 1.3V OUTPUT WITH FORCED-PWM EFFICIENCY vs. LOAD CURRENT
MAX1586A/86B/87A toc04
REG3 1.3V OUTPUT WITH FORCED-PWM EFFICIENCY vs. LOAD CURRENT
90 80 EFFICIENCY (%) 70 60 50 40 30 VIN = 4.0V VIN = 5.0V L3 = 4.7H C17 = 44F MAX1586C MAX1587C
MAX1586A/86B/87A toc04B
100 90 VIN = 3.6V 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0.1 1 10 100 MAX1586C MAX1587C L3 = 4.7H C17 = 44F VIN = 4.0V VIN = 5.0V
100 90 80 VIN = 5.0V 70 60 50 VIN = 4.0V VIN = 3.6V
100
VIN = 3.6V
EFFICIENCY (%)
20 40 10 0.1 1 10 100 1000 0.1 1 10 100 1000 LOAD CURRENT (mA) LOAD CURRENT (mA)
1000
LOAD CURRENT (mA)
REG1 SLEEP LDO 3.3V OUTPUT EFFICIENCY vs. LOAD CURRENT
MAX1586A/86B/87A toc05
REG2 SLEEP LDO 2.5V OUTPUT EFFICIENCY vs. LOAD CURRENT
MAX1586A/86B/87A toc06
QUIESCENT CURRENT vs. SUPPLY VOLTAGE
200 180 INPUT CURRENT (A) 160 140 120 100 80 60 40 20 0 V1 AND V2 SLEEP V1 SLEEP ALL BUT V7 OFF 0 1 2 3 4 5 V1 ON V1, V2, AND V3 ON V1 AND V2 ON BKBT BIASED AT 3.6V
MAX1586A/86B/87A toc07
100 VIN = 4.0V 90 80 VIN = 5.0V 70 60 50 40 0.1 1 LOAD CURRENT (mA) VIN = 3.6V
90 80 EFFICIENCY (%) 70 60 50 40 30 VIN = 5.0V VIN = 3.6V VIN = 4.0V
220
EFFICIENCY (%)
10
0.1
1 LOAD CURRENT (mA)
10
INPUT VOLTAGE (V)
10
______________________________________________________________________________________
High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
Typical Operating Characteristics (continued)
(Circuit of Figure 6, VIN = 3.6V, TA = +25C, unless otherwise noted.)
DROPOUT VOLTAGE vs. LOAD CURRENT
MAX1586A/86B/87A toc08
CHANGE IN OUTPUT VOLTAGE vs. LOAD CURRENT
MAX1586A/86B/87A toc09
300 250 DROPOUT VOLTAGE (mV) 200 150 100 50 0 0 200 400 600 800 1000 REG1 3.3V OUTPUT
200 CHANGE IN OUTPUT VOLTAGE (mV) 150 100 REG1 3.3V OUTPUT 50 0 -50 -100 VIN = 3.6V 0 200 400 600 800 1000 REG2 2.5V OUTPUT REG3 1.3V OUTPUT
1200
1200
LOAD CURRENT (mA)
LOAD CURRENT (mA)
SWITCHING FREQUENCY vs. SUPPLY VOLTAGE
1040 TA = +85C SWITCHING FREQUENCY (kHz) 1000
MAX1586A/86B/87A toc10
REFERENCE VOLTAGE vs. TEMPERATURE
1.260 1.255 REFERENCE VOLTAGE (V) 1.250 1.245 1.240 1.235 1.230 1.225 -40 -15 10 35 60 85
MAX1586A/86B/87A toc11
1.265
960 TA = +25C 920 TA = -40C
880 2.5 3.0 3.5 4.0 4.5 5.0 5.5
INPUT VOLTAGE (V)
TEMPERATURE (C)
REG1 SWITCHING WAVEFORMS WITH 800mA LOAD
MAX1586A/86B/87A toc12
REG1 SWITCHING WAVEFORMS WITH 10mA LOAD
MAX1586A/86B/87A toc13
V1
10mv/div AC-COUPLED
V1
50mv/div AC-COUPLED
VLX1 2V/div 0 IL1 500mA/div
VLX1 2V/div 0 500mA/div IL1 0 400ns/div 20s/div 0
______________________________________________________________________________________
11
High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
Typical Operating Characteristics (continued)
(Circuit of Figure 6, VIN = 3.6V, TA = +25C, unless otherwise noted.)
REG3 SWITCHING WAVEFORMS WITH 250mA LOAD
MAX1586A/86B/87A toc14
REG3 PULSE-SKIP SWITCHING WAVEFORMS WITH 10mA LOAD
MAX1586A/86B/87A toc15
V3
10mv/div AC-COUPLED
V3
10mv/div AC-COUPLED
VLX3
2V/div 0
VLX3
2V/div 0 500mA/div
IL3
500mA/div 0 IL3 10s/div
0
400ns/div
REG3 FORCED-PWM SWITCHING WAVEFORMS WITH 10mA LOAD
MAX1586A/86B/87A toc16
V7 AND RSO STARTUP WAVEFORMS
MAX1586A/86B/87A toc17
V3
10mv/div AC-COUPLED VIN
2V/div 0V
VLX3 2V/div 0V IL3 500mA/div 0mA RSO V7
2V/div 0V 2V/div 0V 10ms/div
400ns/div
SYS_EN STARTUP WAVEFORMS
MAX1586A/86B/87A toc18
PWR_EN STARTUP WAVEFORMS
MAX1586A/86B/87A toc19
VEN1 AND VEN2
2V/div
VEN3 AND VEN45
2V/div
2V/div V3 V1 V2 2V/div VPOK 2V/div V4 V5 VPOK
2V/div 2V/div 2V/div
2V/div
2ms/div
1ms/div
12
______________________________________________________________________________________
High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
Typical Operating Characteristics (continued)
(Circuit of Figure 6, VIN = 3.6V, TA = +25C, unless otherwise noted.)
REG1 LOAD-TRANSIENT RESPONSE
MAX1586A/86B/87A toc20
REG2 LOAD-TRANSIENT RESPONSE
MAX1586A/86B/87A toc21
V1 100mV/div AC-COUPLED
V2 100mV/div AC-COUPLED
ILOAD1 200mA/div
ILOAD2 200mA/div
0A 200s/div 200s/div
0A
REG3 LOAD-TRANSIENT RESPONSE
MAX1586A/86B/87A toc22
REG3 LOAD-TRANSIENT RESPONSE
MAX1586A/86B/87A toc22B
V3 100mV/div AC-COUPLED
MAX1586C MAX1587C
V3 100mV/div
ILOAD3 200mA/div
850mA
ILOAD3 500mA/div
50mA 0A 200s/div 100s/div
REG3 OUTPUT VOLTAGE CHANGING FROM 1.3V TO 1.0V WITH DIFFERENT VALUES OF CRAMP
MAX1586A/86B/87A toc23
REG6 USIM TRANSITIONS
MAX1586A/86B/87A toc24
CRAMP = 2200pF
V6 2.5V TO 3.0V V6 1.8V TO 2.5V
500mV/div
CRAMP = 1500pF
CRAMP = 1000pF V6 0 TO 1.8V 10s/div 0
CRAMP = 330pF 200s/div
______________________________________________________________________________________
13
High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
Pin Description
PIN MAX 1586 MAX 1587 NAME FUNCTION
1
--
LBI
Dual-ModeTM, Low-Battery Input. Connect to IN to set the low-battery threshold to 3.6V (no resistors needed). Connect LBI to a resistor-divider for an adjustable LBI threshold. When IN is below the set threshold, LBO output switches low. LBO is deactivated and forced low when IN is below the dead-battery (DBI) threshold and when all REGs are disabled. REG1 Compensation Node. Connect a series resistor and capacitor from CC1 to GND to compensate the regulation loop. See the Compensation and Stability section. REG1 Feedback Input. Connect FB1 to GND to set V1 to 3.3V. Connect FB1 to external feedback resistors for other output voltages. Input Connection for Backup Battery. This input can also accept the output of an external boost converter. Also known as VCC_BATT. V7 is always active if main or backup power is present. It is the first regulator that powers up. V7 has two states: 1) V7 tracks V1 if ON1 is high and V1 is in regulation. 2) V7 tracks VBKBT when ON1 is low or V1 is out of regulation. REG1 Voltage-Sense Input. Connect directly to the REG1 output voltage. The output voltage is set by FB1 to either 3.3V or adjustable with resistors.
2 3 4
40 1 2
CC1 FB1 BKBT
5
3
V7
6 7 8
4 5 6
V1
SLPIN Input to V1 and V2 Sleep Regulators. The input to the standby regulators at V1 and V2. Connect SLPIN to IN. V2 REG2 Voltage-Sense Input. Connect directly to the REG2 output voltage. The output voltage is set by FB2 to either 1.8V/2.5V (MAX1586A, MAX1587A), 3.3V/2.5V (MAX1586B), or adjustable with resistors. REG2 Feedback Input. Connect to GND to set V2 to 2.5V on all devices. Connect FB2 to IN to set V2 to 1.8V on the MAX1586A and MAX1587A. Connect FB2 to IN to set V2 to 3.3V on the MAX1586B. Connect FB2 to external feedback resistors for other voltages. REG2 Compensation Node. Connect a series resistor and capacitor from CC2 to GND to compensate the regulation loop. See the Compensation and Stability section. Power-OK Output. Open-drain output that is low when any of the V1-V6 outputs are below their regulation threshold. When all activated outputs are in regulation, POK is high impedance. POK maintains a valid low output with V7 as low as 1V. POK does not flag an out-of-regulation condition while REG3 is transitioning between voltages set by serial programming. POK also does not flag for any REG channel that has been turned off; however, if all REG channels are off (V1-V6), then POK is forced low. If IN < UVLO, then POK is low. POK is expected to connect to nVCC_FAULT. Serial Clock Input Serial Data Input. Data is read on the rising edge of SCL. Serial data programs the REG3 (core) and REG6 (VCC_USIM) voltage. REG3 and REG6 can be programmed even when off, but at least one of the ON_ pins must be logic-high to activate the serial interface. On power-up, REG3 defaults to 1.3V and REG6 defaults to 0V. Force V3 to PWM at All Loads. Connect PWM3 to GND for normal operation (skip mode at light loads). Drive or connect high for forced-PWM operation at all loads for V3 only. Low-Battery Output. Open-drain output that goes low when IN is below the threshold set by LBI.
9
7
FB2
10
8
CC2
11
9
POK
12
10
SCL
13
11
SDA
14 15
12 --
PWM3 LBO
Dual Mode is a trademark of Maxim Integrated Products, Inc. 14 ______________________________________________________________________________________
High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones
Pin Description (continued)
PIN MAX 1586 16 17 18 19 20 21 22 23 24 MAX 1587 13 14 15 16 17 18 19 20 -- NAME FUNCTION REG2 Power Input. Bypass to PG2 with a 4.7F or greater low-ESR capacitor. PV1, PV2, PV3, and IN must connect together externally. REG2 Switching Node. Connects to REG2 inductor. REG2 Power Ground. Connect directly to a power-ground plane. Connect PG1, PG2, PG3, and GND together at a single point as close to the IC as possible. Main Battery Input. This input provides power to the IC. V3 Ramp-Rate Control. A capacitor connected from RAMP to GND sets the rate-of-change when V3 is changed. The output impedance of RAMP is 100k. FB3 regulates to 1.28 x VRAMP. Analog Ground Reference Output. Output of the 1.25V reference. Bypass to GND with a 0.1F or greater capacitor. Low-Noise LDO Bypass. Low-noise bypass pin for V4 LDO. Connect a 0.01F capacitor from BYP to GND. Dead or Missing Battery Output. DBO is an open-drain output that goes low when IN is below the threshold set by DBI. DBO does not deactivate any MAX1586/MAX1587 regulator outputs. DBO is expected to connect to nBATT_FAULT on Intel CPUs. On/Off Input for REG2. Drive high to turn on. When enabled, the REG2 output soft-starts. ON2 has hysteresis so an RC can be used to implement manual sequencing with respect to other inputs. It is expected that ON1, ON2, and ON6 are connected to SYS_EN. On/Off Input for REG4. Drive high to turn on. When enabled, the REG4 output activates. ON4 has hysteresis so an RC can be used to implement manual sequencing with respect to other inputs. It is expected that ON4 is connected to PWR_EN. Also Known as VCC_PLL. 1.3V, 35mA linear-regulator output for PLL. Regulator input is IN45. Power Input to V4 and V5 LDOs. Typically connected to V2, but can also connect to IN or another voltage from 2.5V to VIN. Also Known as VCC_SRAM. 1.1V, 35mA linear-regulator output for CPU SRAM. Regulator input is IN45. On/Off Input for REG5. Drive high to turn on. When enabled, the MAX1586/MAX1587 soft-starts the REG5 output. ON5 has hysteresis so an RC can be used to implement manual sequencing with respect to other inputs. It is expected that ON5 is connected to PWR_EN. REG3 Power Ground. Connect directly to a power-ground plane. Connect PG1, PG2, PG3, and GND together at a single point as close to the IC as possible. REG3 Switching Node. Connects to the REG3 inductor. REG3 Power Input. Bypass to PG3 with a 4.7F or greater low-ESR ceramic capacitor. PV1, PV2, PV3, and IN must connect together externally. On/Off Input for REG3 (Core). Drive high to turn on. When enabled, the REG3 output ramps up. ON3 has hysteresis so an RC can be used to implement manual sequencing with respect to other inputs. It is expected that ON3 is driven from CPU SYS_EN.
MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
PV2 LX2 PG2 IN RAMP GND REF BYP DBO
25
21
ON2
26 27 28 29 30
-- 23 24 25 --
ON4 V4 IN45 V5 ON5
31 32 33
26 27 28
PG3 LX3 PV3
34
34
ON3
______________________________________________________________________________________
15
High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
Pin Description (continued)
PIN MAX 1586 35 36 37 38 39 MAX 1587 29 30 31 32 33 NAME FUNCTION Serial Address Bit. SRAD allows the serial address of the MAX1586/MAX1587 to be changed in case it conflicts with another serial device. If SRAD = GND, A1 = 0. If SRAD = IN, A1 = 1. Open-Drain Reset Output. Deasserts when V7 exceeds 2.55V (typ rising). Has 65ms delay before release. RSO is expected to connect to nRESET on the CPU. Manual Reset Input. A low input at MR causes the RSO output to go low and also resets the V3 output to its default 1.3V setting. MR impacts no other MAX1586/MAX1587 functions. REG 3 Compensation Node. Connect a series resistor and capacitor from CC3 to GND to compensate the regulation loop. See the Compensation and Stability section. REG3 Feedback-Sense Input. Connect directly to the REG3 output voltage. Output voltage is set by the serial interface. On/Off Input for REG6. Drive high to turn on. When enabled, the REG6 output activates. ON6 has hysteresis so an RC can be used to implement manual sequencing with respect to other inputs. It is expected that ON1, ON2, and ON6 are connected to SYS_EN. Also known as VCC_USIM. Linear-regulator output. This voltage is programmable through the I2C interface to 0V, 1.8V, 2.5V, or 3.0V. The default voltage is 0V. REG6 is activated when ON6 is high. Power Input to the V6 LDO. Typically connected to V1, but can also connect to IN. REG1 Power Ground. Connect directly to a power-ground plane. Connect PG1, PG2, PG3, and GND together at a single point as close to the IC as possible. REG1 Switching Node. Connects to the REG1 inductor. REG1 Power Input. Bypass to PG2 with a 4.7F or greater low-ESR ceramic capacitor. PV1, PV2, PV3, and IN must connect together externally. On/Off Input for REG1. Drive high to turn on REG1. When enabled, the REG1 output soft-starts. ON1 has hysteresis so an RC can be used to implement manual sequencing with respect to other inputs. It is expected that ON1, ON2, and ON6 connect to SYS_EN. Sleep Input. SLP selects which regulators ON1 and ON2 turn on. SLP = high is normal operation (ON1 and ON2 are the enables for the V1 and V2 DC-DC converters). SLP = low is sleep operation (ON1 and ON2 are the enables for the V1 and V2 LDOs). Dual-Mode, Dead-Battery Input. Connect DBI to IN to set the dead-battery falling threshold to 3.15V (no resistors needed). Connect DBI to a resistor-divider for an adjustable DBI threshold. On/Off Input for REG4 and REG5. Drive high to turn on. When enabled, the REG4 and REG5 outputs activate. ON45 has hysteresis so an RC can be used to implement manual sequencing with respect to other inputs. It is expected that ON45 is connected to PWR_EN. Exposed Metal Pad. Connect the exposed pad to ground. Connecting the exposed pad to ground does not remove the requirement for proper ground connections to the appropriate ground pins.
SRAD RSO MR CC3 FB3
40
--
ON6
41 42 43 44 45
-- -- 36 37 38
V6 IN6 PG1 LX1 PV1
46
35
ON1
47
39
SLP
48
--
DBI
--
22
ON45
EP
EP
EP
Purchase of I2C components from Maxim Integrated Products, Inc. or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 16 ______________________________________________________________________________________
High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
BATT MAIN BATT IN DBI (3.15V OR ADJ) UVLO AND BATT MON SLPIN
MAX1586
PV1 STEP-DOWN PWM REG1 ON
LBI (3.6V OR ADJ) REF REF 1.25V OPEN-DRAIN LOW-BATT OUT OPEN-DRAIN DEAD-BATT OUT TO nBATT_FAULT LBO DBO
LX1
V1, VCC_IO 3.3V WITH FB1 = GND, OR ADJ WITH RESISTORS
PG1 V1 SLEEP LDO FB1
FROM CPU SYS_EN RUN SLEEP
ON1 ON2 SLP TO V1 ON STEP-DOWN PWM REG2
PV2
TO BATT
LX2
Li+ BACKUP BATTERY V7, VCC_BATT (1ST SUPPLY, ALWAYS ON) TO CPU nRESET
BKBT REG1 OK PG2 V7 V2 RSO V7 RESET 2.425V 65ms SLEEP LDO FB2
V2, VCC_MEM 2.5V WITH FB2 = GND, 1.8V WITH FB2 = IN (MAX1586A, MAX1587A) 3.3V WITH FB2 = IN (MAX1586B) OR ADJ WITH RESISTORS
PV3 STEP-DOWN PWM REG3 PWM V1-V6 POWEROK PG3 ADJ ON FB3 ON3 IN45 RAMP V4 BYP 100k LDO REG 4 ON4 ON5 LDO REG 5 V5 CC1 CC2 CC3 I2 C SERIAL IN6 V6
TO BATT
RESET INPUT FORCE REG3 TO PWM TO CPU nVCC_FAULT
MR PWM3 POK
LX3
V3, VCC_CORE 0.7V TO 1.475V 500mA (MAX1586A, MAX1586B, MAX1587A) 900mA (MAX1586C, MAX1587C)
TO V2
FROM CPU PWR_EN V4, VCC_PLL 1.3V, 35mA
V3 DAC
V5, VCC_SRAM 1.1V, 35mA
TO V2 VCC_USIM 0V, 1.8V, 3.0V (DEF = 0V)
LDO REG 6
ON6
GND SRAD SCL SDA
FROM CPU SYS_EN
Figure 1. MAX1586 Functional Diagram (The MAX1587 omits some features. See the Pin Description section.) ______________________________________________________________________________________ 17
High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
Detailed Description
The MAX1586/MAX1587 power-management ICs are optimized for devices using Intel X-Scale microprocessors, including third-generation smart cell phones, PDAs, internet appliances, and other portable devices requiring substantial computing and multimedia capability at low power. The MAX1586A/MAX1586B/ MAX1587A comply with Intel Processor Power specifications. The ICs integrate seven high-performance, low-operating-current power supplies along with supervisory and management functions. Regulator outputs include three step-down DC-DC outputs (V1, V2, and V3), three linear regulators (V4, V5, and V6), and one always-on output, V7 (Intel VCC_BATT). The V1 step-down DC-DC converter provides 3.3V or adjustable output voltage for I/O and peripherals. The V2 step-down DC-DC converter on the MAX1586A and MAX1587A is preset for 1.8V or 2.5V, while the MAX1586B V2 supply is preset for 3.3V or 2.5V. V2 can also be adjusted with external resistors on all parts. The V3 step-down DC-DC converter provides a serial-programmed output for powering microprocessor cores. The three linear regulators (V4, V5, and V6) provide power for PLL, SRAM, and USIM. To minimize sleep-state quiescent current, V1 and V2 have bypass "sleep" LDOs that can be activated to minimize battery drain when output current is very low. Other functions include separate on/off control for all DC-DC converters, low-battery and dead-battery detection, a power-OK output, a backup-battery input, and a two-wire serial interface. All DC-DC outputs use fast, 1MHz PWM switching and small external components. They operate with fixed-frequency PWM control and automatically switch from PWM to skip-mode operation at light loads to reduce operating current and extend battery life. The V3 core output is capable of forced-PWM operation at all loads. The 2.6V to 5.5V input voltage range allows 1-cell Li+, 3-cell NiMH, or a regulated 5V input. The following power-supply descriptions include the Intel terms for the various voltages in parenthesis. For example, the MAX1586/MAX1587 V1 output is referred to as VCC_IO in Intel documentation. See Figure 1. V2 is also a 1MHz current-mode step-down converter. The V2 step-down DC-DC converter on the MAX1586A and MAX1587A is preset for 1.8V or 2.5V, while the MAX1586B V2 supply is preset for 3.3V or 2.5V. V2 can also be adjusted with external resistors on all parts. V2 supplies loads up to 900mA. Under moderate to heavy loading, the converters operate in a low-noise PWM mode with constant frequency and modulated pulse width. Switching harmonics generated by fixed-frequency operation are consistent and easily filtered. Efficiency is enhanced under light loading (<30mA typ), by assuming an Idle Mode during which the converter switches only as needed to service the load. Synchronous Rectification Internal n-channel synchronous rectifiers eliminate the need for external Schottky diodes and improve efficiency. The synchronous rectifier turns on during the second half of each cycle (off-time). During this time, the voltage across the inductor is reversed, and the inductor current falls. In normal operation (not forced PWM), the synchronous rectifier turns off at the end of the cycle (at which time another on-time begins) or when the inductor current approaches zero. 100% Duty-Cycle Operation If the inductor current does not rise sufficiently to supply the load during the on-time, the switch remains on, allowing operation up to 100% duty cycle. This allows the output voltage to maintain regulation while the input voltage approaches the regulation voltage. Dropout voltage is approximately 180mV for an 800mA load on V1 and 220mV for an 800mA load on V2. During dropout, the high-side p-channel MOSFET turns on, and the controller enters a low-current-consumption mode. The device remains in this mode until the regulator channel is no longer in dropout. Sleep LDOs In addition to the high-efficiency step-down converters, V1 and V2 can also be supplied with low-quiescent current, low-dropout (LDO) linear regulators that can be used in sleep mode or at any time when the load current is very low. The sleep LDOs can source up to 35mA. To enable the sleep LDOs, drive SLP low. When SLP is high, the switching step-down converters are active. The output voltage of the sleep LDOs is set to be the same as the switching step-down converters as described in the Setting the Output Voltages section. SLPIN is the input to the V1 and V2 sleep LDOs and must connect to IN.
V1 and V2 (VCC_IO, VCC_MEM) Step-Down DC-DC Converters
V1 is a 1MHz current-mode step-down converter. The V1 output voltage can be preset to 3.3V or adjusted using a resistor voltage-divider. V1 supplies loads up to 1300mA.
Idle Mode is a trademark of Maxim Integrated Products, Inc. 18
______________________________________________________________________________________
High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones
V3 (VCC_CORE) Step-Down DC-DC Converter
V3 is a 1MHz current-mode step-down converter. The MAX1586A, MAX1586B, and MAX1587A supply loads up to 500mA from V3 while the MAX1586C and MAX1587C supply loads up to 1A. The V3 output is set by the I 2 C serial interface to between 0.7V and 1.475V in 25mV increments. The default output voltage on power-up and after a reset is 1.3V. See the Serial Interface section for programming details. See the Applications Information for instructions on how to increase the V3 output voltage. Forced PWM on REG3 Under moderate to heavy loading, the V3 always operates in a low-noise PWM mode with constant frequency and modulated pulse width. Switching harmonics generated by fixed-frequency operation are consistent and easily filtered. With light loads (<30mA) and PWM3 low, V3 operates in an enhanced-efficiency Idle Mode during which the converter switches only as needed to service the load. With PWM3 high, V3 operates in low-noise forced-PWM mode under all load conditions. V4 and V5 linear regulators is IN45, which is typically connected to V2. To enable V5 on the MAX1586, drive ON5 high, or drive ON5 low for shutdown. On the MAX1587, the enable pins for V4 and V5 are combined. Drive ON45 high to enable V4 and V5, or drive ON45 low for shutdown. V5 is intended to connect to VCC_SRAM. V6 (VCC_USIM--MAX1586 Only) V6 is a linear regulator on the MAX1586 that supplies loads up to 35mA. The V6 output voltage is programmed with the I2C serial interface to 0V, 1.8V, 2.5V, or 3.0V. The power-up default for V6 is 0V. See the Serial Interface section for details on changing the voltage. The power input for the V6 linear regulator is IN6, which is typically connected to V1. To enable V6, drive ON6 high, or drive ON6 low for shutdown. V6 is intended to connect to VCC_USIM.
MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
V7 Always-On Output (VCC_BATT)
The V7 output is always active if V1 is enabled and in regulation or if backup power is present. When ON1 is high and V1 is in regulation, V7 is sourced from V1 by an internal MOSFET switch. When ON1 is low or V1 is out of regulation, V7 is sourced from BKBT by a second on-chip MOSFET. V7 can supply loads up to 30mA. V7 is intended to connect to VCC_BATT on Intel CPUs. Due to variations in system implementation, BKBT and V7 can be utilized in different ways. See the BackupBattery and V7 Configurations section for information on how to use BKBT and V7.
Linear Regulators (V4, V5, and V6)
V4 (VCC_PLL) V4 is a linear regulator that provides a fixed 1.3V output and supplies loads up to 35mA. The power input for the V4 and V5 linear regulators is IN45, which is typically connected to V2. To enable V4 on the MAX1586, drive ON4 high, or drive ON4 low for shutdown. On the MAX1587, the enable pins for V4 and V5 are combined. Drive ON45 high to enable V4 and V5, or drive ON45 low for shutdown. V4 is intended to connect to VCC_PLL. V5 (VCC_SRAM) V5 is a linear regulator that provides a fixed 1.1V output and supplies loads up to 35mA. The power input for the
Quiescent Operating Current in Various States
The MAX1586/MAX1587 are designed for optimum efficiency and minimum operating current for all typical operating modes, including sleep and deep sleep. These states are outlined in Table 1.
Table 1. Quiescent Operating Current in Various States
OPERATING POWER MODE RUN IDLE SENSE STANDBY SLEEP DESCRIPTION All supplies on and running All supplies on and running, peripherals on All supplies on, minimal loading, peripherals monitored All supplies on, minimal loading, peripherals not monitored PWR_EN controlled voltages (V3, V4, V5) are off. V1 and V2 on. 60A if V1 and V2 SLEEP LDOs on; 130A if V1, V2 step-down DC-DCs enabled 5A MAX1587 if IN > DBI threshold; 32A MAX1586 if IN > DBI threshold; 4A if IN < DBI threshold 200A MAX1587, 225A MAX1586 TYPICAL MAX1586/MAX1587 NO-LOAD OPERATING CURRENT
DEEP SLEEP
All supplies off except V7. V7 biased from backup battery.
______________________________________________________________________________________
19
High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
Voltage Monitors, Reset, and Undervoltage-Lockout Functions
Undervoltage Lockout When the input voltage is below 2.35V (typ), an undervoltage-lockout (UVLO) circuit disables the IC. The inputs remain high impedance while in UVLO, reducing battery load under this condition. All serial registers are maintained with the input voltage down to at least 2.35V. Reset Output (RSO) and MR Input The reset output (RSO) is low when the MR input is low or when V7 is below 2.425V. V7 is powered from V1 (when enabled) or the backup-battery input (BKBT). RSO normally goes low: 1) When power is first applied in configurations with no separate backup battery (external diode from IN to BKBT). 2) When power is removed in configurations with no separate backup battery (external diode from IN to BKBT). 3) If the backup battery falls below 2.425V when V1 is off or out of regulation. 4) When the manual reset button is pressed (MR goes low). If VIN is >2.4V, an internal timer delays the release of RSO for 65ms after V7 rises above 2.3V. However, if VIN < 2.4V when V7 exceeds 2.3V, or if VIN and V7 rise at the same time, RSO deasserts immediately with no 65ms delay. There is no delay in the second case because the timer circuitry is deactivated to minimize operating current during VIN undervoltage lockout. If it is desired to have a 65ms RSO release delay for any sequence of VIN and V7, the circuit in Figure 2 may be used. An RC connected from IN to MR delays the rise of MR until after VIN powers up. The 65ms timer is valid for either sequence of V7 and VIN and does not release until 65ms after both are up. The only regulator output that affects RSO is V7. RSO will not respond to V1-V6, which are monitored by POK. Also, RSO is high impedance and does not function if BKBT is not powered. MR is a manual reset input for hardware reset. A low input at MR causes the RSO output to go low for at least 65ms and also resets the V3 output to its default 1.3V setting. MR impacts no other MAX1586/MAX1587 functions. Dead-Battery and Low-Battery Comparators-- DBI, LBI (MAX1586 only) The DBI and LBI inputs monitor input power (usually a battery) and trigger the DBO and LBO outputs. The dead-battery comparator triggers DBO when the battery (VIN) discharges to the dead-battery threshold. The
20
IN
MAX1586 MAX1587
MR
Figure 2. An RC delay connected from IN to MR ensures that the 65ms RSO release delay remains in effect for any sequence of IN and V7.
MAIN BATTERY R1 438k
IN
MAX1586
DBI (1.232V THRESHOLD)
R2 62k LBI (1.00V THRESHOLD) R3 200k
Figure 3. Setting the Low-Battery and Dead-Battery Thresholds with One Resistor Chain. The values shown set a DBI threshold of 3.3V and an LBI threshold of 3.5V (no resistors are needed for the factory preset thresholds).
factory-set 3.15V threshold is selected by connecting DBI to IN, or the threshold can be programmed with a resistor-divider at DBI. The low-battery comparator has a factory-set 3.6V threshold that is selected by connecting LBI to IN, or its threshold can be programmed with a resistor-divider at LBI. One three-resistor-divider can set both DBI and LBI (R1, R2, and R3 in Figure 3) according to the following equations: 1) Choose R3 to be less than 250k 2) R1 = R3 x VLB (1 - (1.232 / VDB)) 3) R2 = R3 (1.232 x (VLB / VDB) - 1) where VLB is the low-battery threshold and VDB is the dead-battery threshold. Alternately, LBI and DBI can be set with separate tworesistor-dividers. Choose the lower resistor of the divider
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High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones
Connection to Processor and Power Sequencing
MAIN BATTERY R4 334k R6 500k IN
MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
MAX1586
DBI (1.232V THRESHOLD)
R5 200k R7 200k
LBI (1.00V THRESHOLD)
Typical processor connections have only power-control pins, typically labeled PWR_EN and SYS_EN. The MAX1586/MAX1587 provide numerous on/off control pins for maximum flexibility. In a typical application, many of these pins are connected together. ON1, ON2, and ON6 typically connect to SYS_EN. ON3, ON4, and ON5 typically connect to PWR_EN. V7 remains on as long as the main or backup power is connected. Sequencing is not performed internally on the MAX1586/MAX1587; however, all ON_ inputs have hysteresis and can connect to RC networks to set sequencing. For typical connections to Intel CPUs, no external sequencing is required.
Figure 4. Setting the Low-Battery and Dead-Battery Thresholds with Separate Resistor-Dividers. The values shown set a DBI threshold of 3.3V and an LBI threshold of 3.5V (no resistors are needed for factory-preset thresholds).
Backup-Battery Input
The backup-battery input (BKBT) provides backup power for V7 when V1 is disabled. Normally, a primary or rechargeable backup battery is connected to this pin. If a backup battery is not used, then BKBT should connect to IN through a diode or external regulator. See the Backup-Battery and V7 Configurations section for information on how to use BKBT and V7.
chain to be 250k or less (R5 and R7 in Figure 4). The equations for upper divider-resistors as a function of each threshold are then: R4 = R5 (VDB / 1.232) - 1) R6 = R7 (VLB - 1) When resistors are used to set VLB, the threshold at LBI is 1.00V. When resistors are used to set V DB , the threshold at DBI is 1.232V. A resistor-set threshold can also be used for only one of DBI or LBI. The other threshold can then be factory set by connecting the appropriate input to IN. If BKBT is not powered, DBO does not function and is high impedance. DBO is expected to connect to nBATT_FAULT on Intel CPUs. If BKBT is not powered, LBO does not function and is high impedance. Power-OK Output (POK) POK is an open-drain output that goes low when any activated regulator (V1-V6) is below its regulation threshold. POK does not monitor V7. When all active output voltages are within 10% of regulation, POK is high impedance. POK does not flag an out-of-regulation condition while V3 is transitioning between voltages set by serial programming or when any regulator channel has been turned off. POK momentarily goes low when any regulator is turned on, but returns high when that regulator reaches regulation. When all regulators (V1-V6) are off, POK is forced low. If the input voltage is below the UVLO threshold, POK is held low and maintains a valid low output with IN as low as 1V. If BKBT is not powered, POK does not function and is high impedance.
Serial Interface
An I2C-compatible, two-wire serial interface controls REG3 on the MAX1587, and REG3 and REG6 on the MAX1586. The serial interface operates when IN exceeds the 2.40V UVLO threshold and at least one of ON1-ON6 is asserted. The serial interface is shut down to minimize off-current drain when no regulators are enabled. The serial interface consists of a serial data line (SDA) and a serial clock line (SCL). Standard I2C-compatible write-byte commands are used. Figure 4 shows a timing diagram for the I 2 C protocol. The MAX1586/ MAX1587 are slave-only devices, relying upon a master to generate a clock signal. The master (typically a microprocessor) initiates data transfer on the bus and generates SCL to permit data transfer. A master device communicates to the MAX1586/MAX1587 by transmitting the proper address followed by the 8-bit data code (Table 2). Each transmit sequence is framed by a START (A) condition and a STOP (L) condition. Each word transmitted over the bus is 8 bits long and is always followed by an acknowledge clock pulse. Table 2 shows the serial data codes used to program V3 and V6. The default power-up voltage for V3 is 1.3V and for V6 is 0V.
Bit Transfer
One data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA
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High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
Table 2. V3 and V6 Serial Programming Codes
D7 D6 D5 0 = PROG V3 1 = PROG V6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X X X X D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X X X X D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X X X X D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 OUTPUT (V) 0.700 0.725 0.750 0.775 0.800 0.825 0.850 0.875 0.900 0.925 0.950 0.975 1.000 1.025 1.050 1.075 1.100 1.125 1.150 1.175 1.200 1.225 1.250 1.275 1.300 1.325 1.350 1.375 1.400 1.425 1.450 1.475 0 1.8 2.5 3.0 V6, USIM VOLTAGES [MAX1586 ONLY] V3, CORE VOLTAGES DESCRIPTION
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High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
A tLOW B tHIGH C D E F G H I J K L M
SCL
SDA tSU:STA tHD:STA tSU:DAT tHD:DAT F = ACKNOWLEDGE BIT CLOCKED INTO MASTER G = MSB OF DATA CLOCKED INTO SLAVE (OP/SUS BIT) H = LSB OF DATA CLOCKED INTO SLAVE I = SLAVE PULLS SMB DATA LINE LOW
tSU:STO tBUF J = ACKNOWLEDGE CLOCKED INTO MASTER K = ACKNOWLEDGE CLOCK PULSE L = STOP CONDITION, DATA EXECUTED BY SLAVE M = NEW START CONDITION
A = START CONDITION B = MSB OF ADDRESS CLOCKED INTO SLAVE C = LSB OF ADDRESS CLOCKED INTO SLAVE D = R/W BIT CLOCKED INTO SLAVE E = SLAVE PULLS SMB DATA LINE LOW
Figure 5. I2C-Compatible Serial-Interface Timing Diagram
while SCL is high are control signals (see the START and STOP Conditions section). Both SDA and SCL idle high when the bus is not busy.
START and STOP Conditions
When the serial interface is inactive, SDA and SCL idle high. A master device initiates communication by issuing a START condition. A START condition is a high-tolow transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA while SCL is high (Figure 5). A START condition from the master signals the beginning of a transmission to the MAX1586/ MAX1587. The master terminates transmission by issuing a not acknowledge followed by a STOP condition (see the Acknowledge Bit section). The STOP condition frees the bus. When a STOP condition or incorrect address is detected, the MAX1586/MAX1587 internally disconnect SCL from the serial interface until the next START condition, minimizing digital noise and feedthrough. Acknowledge Bit (ACK) The acknowledge bit (ACK) is the ninth bit attached to every 8-bit data word. The receiving device always generates ACK. The MAX1586/MAX1587 generate an ACK when receiving an address or data by pulling SDA low during the ninth clock period. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time.
Serial Address A bus master initiates communication with a slave device by issuing a START condition followed by the 7-bit slave address (Table 3). When idle, the MAX1586/MAX1587 wait for a START condition followed by its slave address. The serial interface compares each address value bit by bit, allowing the interface to power down immediately if an incorrect address is detected. The LSB of the address word is the read/write (R/W) bit. R/W indicates whether the master is writing or reading (RD/W 0 = write, RD/W 1 = read). The MAX1586/ MAX1587 only support the SEND BYTE format; therefore, RD/W is required to be 0. After receiving the proper address, the MAX1586/ MAX1587 issue an ACK by pulling SDA low for one clock cycle. The MAX1586/MAX1587 have two userprogrammed addresses (Table 3). Address bits A7 through A2 are fixed, while A1 is controlled by SRAD. Connecting SRAD to GND sets A1 = 0. Connecting SRAD to IN sets A1 = 1. V3 Output Ramp-Rate Control When V3 is dynamically changed with the serial interface, the output voltage changes at a rate controlled by
Table 3. Serial Address
SRAD 0 1 A7 0 0 A6 0 0 A5 1 1 A4 0 0 A3 1 1 A2 0 0 A1 0 1 A0 RD/W 0 0
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High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
a capacitor (CRAMP) connected from RAMP to ground. The voltage change is a conventional RC exponential described by: Vo(t) = Vo(0) + dV(1 - exp(-t / (100k CRAMP))) A useful approximation is that it takes approximately 2.2 RC time constants for V3 to move from 10% to 90% of the voltage difference. For CRAMP = 1500pF, this time is 330s. For 1V to 1.3V change, this equates to 1mV/s. See the Typical Operating Characteristics for examples of different ramp-rate settings. The maximum capacitor value that can be used at RAMP is 2200pF. If larger values are used, the V3 ramp rate is still controlled according to the above equation, but when V3 is first activated, POK indicates an "in regulation" condition before V3 reaches its final voltage. The RAMP pin is effectively the reference for REG3. FB3 regulates to 1.28 times the voltage on RAMP.
Inductor Selection
The external components required for the step-down are an inductor, input and output filter capacitors, and a compensation RC network. The MAX1586/MAX1587 step-down converters provide best efficiency with continuous inductor current. A reasonable inductor value (LIDEAL) is derived from: LIDEAL = [2(VIN) x D(1 - D)] / (IOUT(MAX) x fOSC) This sets the peak-to-peak inductor current at 1/2 the DC inductor current. D is the duty cycle: D = VOUT / VIN Given LIDEAL, the peak-to-peak inductor ripple current is 0.5 x I OUT . The peak inductor current is 1.25 x I OUT(MAX) . Make sure the saturation current of the inductor exceeds the peak inductor current and the rated maximum DC inductor current exceeds the maximum output current (I OUT(MAX)). Inductance values larger than LIDEAL can be used to optimize efficiency or to obtain the maximum possible output current. Larger inductance values accomplish this by supplying a given load current with a lower inductor peak current. Typically, output current and efficiency are improved for inductor values up to about two times LIDEAL. If the inductance is raised too much, however, the inductor size may become too large, or the increased inductor resistance may reduce efficiency more than the gain derived from lower peak current. Smaller inductance values allow smaller inductor sizes, but also result in larger peak inductor current for a given load. Larger output capacitance may then be needed to suppress the increase in output ripple caused by larger peak current.
Design Procedure
Setting the Output Voltages
The outputs V1 and V2 have preset output voltages, but can also be adjusted using a resistor voltage-divider. To set V1 to 3.3V, connect FB1 to GND. V2 can be preset to 1.8V or 2.5V on the MAX1586A and MAX1587A. To set V2 to 1.8V on the MAX1586A and MAX1587A, connect FB2 to IN. To set to 2.5V, connect FB2 to GND. V2 can preset to 3.3V or 2.5V on the MAX1587B. To set V2 to 3.3V on the MAX1587B, connect FB2 to IN. To set to 2.5V, connect FB2 to GND. To set V1 or V2 to other than the preset output voltages, connect a resistor voltage-divider from the output voltage to the corresponding FB input. The FB_ input bias current is less than 100nA, so choose the low-side (FB_to-GND) resistor (RL) to be 100k or less. Then calculate the high-side (output-to-FB_) resistor (RH) using: RH = RL [(VOUT / 1.25) - 1] The V3 (VCC_CORE) output voltage is set from 0.7V to 1.475V in 25mV steps by the I2C serial interface. See the Serial Interface section for details. Linear regulator V4 provides a fixed 1.3V output voltage. Linear regulator V5 provides a fixed 1.1V output voltage. V4 and V5 voltages are not adjustable. The output voltage of linear regulator V6 (VCC_USIM) is set to 0V, 1.8V, 2.5V, or 3.0V by the I2C serial interface. See the Serial Interface section for details. Linear regulator V7 (VCC_BATT) tracks the voltage at V1 as long as ON1 is high and V1 is in regulation. When ON1 is low or V1 is not in regulation, V7 switches to the backup battery (VBKBT).
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Capacitor Selection
The input capacitor in a DC-DC converter reduces current peaks drawn from the battery or other input power source and reduces switching noise in the controller. The impedance of the input capacitor at the switching frequency should be less than that of the input source so high-frequency switching currents do not pass through the input source. The output capacitor keeps output ripple small and ensures control-loop stability. The output capacitor must also have low impedance at the switching frequency. Ceramic, polymer, and tantalum capacitors are suitable, with ceramic exhibiting the lowest ESR and lowest high-frequency impedance. Output ripple with a ceramic output capacitor is approximately: VRIPPLE = IL(PEAK) [1 / (2 x fOSC x COUT)]
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High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones
If the capacitor has significant ESR, the output ripple component due to capacitor ESR is: VRIPPLE(ESR) = IL(PEAK) x ESR Output capacitor specifics are also discussed in the Compensation and Stability section.
MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
Table 4. Compensation Parameters
PARAMETER Error-Amplifier Transconductance, gmEA Current-Sense Amp Transresistance, RCS REG1 87S 0.5V/A REG2 87S 0.75V/A REG3 68S 1.25V/A
Compensation and Stability
The relevant characteristics for REG1, REG2, and REG3 compensation are: 1) Transconductance (from FB_ to CC_), gmEA 2) Current-sense amplifier transresistance, RCS 3) Feedback regulation voltage, VFB (1.25V) 4) Step-down output voltage, VOUT, in V 5) Output load equivalent resistance, RLOAD = VOUT / ILOAD The key steps for step-down compensation are: 1) Set the compensation RC zero to cancel the RLOAD COUT pole. 2) Set the loop crossover at or below approximately 1/10th the switching frequency. For example, with V IN(MAX) = 5V, V OUT = 2.5V for REG2, and IOUT = 800mA, then RLOAD = 3.125. For REG2, RCS = 0.75V/A and gmEA = 87S. Choose the crossover frequency, f C f OSC / 10. Choose 100kHz. Then calculate the value of the compensation capacitor, CC: CC = (VFB / VOUT) x (RLOAD / RCS) x (gm / (2 x fC)) = (1.25 / 2.5) x (3.125 / 0.75) x (87 x 10-6 / (6.28 x 100,000)) = 289pF Choose 330pF, the next highest standard value. Now select the compensation resistor, RC, so transientdroop requirements are met. As an example, if 3% transient droop is allowed for the desired load step, the input to the error amplifier moves 0.03 x 1.25V, or 37.5mV. The error-amplifier output drives 37.5mV x gmEA, or IEAO = 37.5mV x 87S = 3.26A across RC to provide transient gain. Find the value of RC that allows the required load-step swing from: RC = RCS x IIND(PK) / IEAO where IIND(PK) is the peak inductor current. In a stepdown DC-DC converter, if LIDEAL is used, output current relates to inductor current by: IIND(PK) = 1.25 x IOUT So for an 800mA output load step with VIN = 3.6V and VOUT = 2.5V:
Table 5. Typical Compensation Values
COMPONENT OR PARAMETER VOUT Output Current Inductor Load-Step Droop Loop Crossover Freq (fC) CC RC COUT REG1 3.3V 1300mA 3.3H 3% 100kHz 330pF 240k 22F REG2 2.5V 900mA 6.8H 3% 100kHz 270pF 240k 22F REG3 1.3V 500mA 10H 3% 100kHz 330pF 240k 22F
RC = RCS x IIND(PK) / IEAO = (0.75V/A) x (1.25 x 0.8A) / 3.26A = 230k We choose 240k. Note that the inductor does not limit the response in this case since it can ramp at (VIN VOUT) / L, or (3.6 - 2.5) / 3.3H = 242mA/s. The output filter capacitor is then selected so that the COUT RLOAD pole cancels the RC CC zero: COUT x RLOAD = RC x CC For the example: RLOAD = VOUTx ILOAD = 2.5V / 0.8A = 3.125 COUT = RC x CC / RLOAD = 240k x 330pF / 3.125 = 25F We choose 22F. Recalculate RC using the selected COUT. RC = COUT x RLOAD / CC = 208k
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High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
BATT C11 10F IN DBI (3.2V OR ADJ) UVLO AND BATT MON SLPIN
MAIN BATT
MAX1586
PV1 STEP-DOWN PWM REG1 ON C12 4.7F LX1 L1 3.3H PG1 V1 SLEEP LDO FB1 C15 22F
LBI (3.6V OR ADJ) TO BATT R19 1M LOW-BATT WARNING TO CPU nBATT_FAULT TO V1 R20 1M C19 0.1F LBO DBO REF REF 1.25V
V1 VCC_IO 3.3V 1300mA
FROM CPU SYS_EN RUN SLEEP
ON1 ON2 SLP TO V1 ON STEP-DOWN PWM REG2
PV2
TO BATT C13 4.7F V2 VCC_MEM 2.5V 900mA
LX2 L2 6.8H C16 22F
Li+ BACKUP BATTERY V7, VCC_BATT (ALWAYS ON)
BKBT C25 1F V7 C24 1F RSO V7 RESET 2.3V 65ms SLEEP LDO REG1 OK PG2 V2 FB2
TO CPU nRESET
PV3 STEP-DOWN PWM REG3 PWM
TO BATT C14 4.7F
RESET INPUT
MR PWM3
LX3 L3 10H PG3 C17 22F
R18 1M TO V1 ADJ TO CPU nVCC-FAULT POK V1-V6 POWEROK RAMP C18 1500pF 100k LDO REG 4 ON
V3 VCC_CORE 0.7V TO 1.475V 500mA (MAX1586A, MAX1586B, MAX1587A) 900mA (MAX1586C, MAX1587C)
FB3 ON3 IN45 V4 BYP C23 1F C20 0.01F ON4 ON5 LDO REG 5 FROM CPU PWR_EN V4, VCC_PLL 1.3V, 35mA
TO V2
V3 DAC
R21 240k C26 330pF
CC1 CC2 CC3 R22 240k C27 270pF R23 240k C28 330pF GND SRAD SCL SDA
V5 IN6 V6 I2 C SERIAL
C22 1F TO V2 C21 1F
V5 VCC_SRAM 1.1V, 35mA
LDO REG 6
V6 VCC_USIM 0V, 1.8V, 3.0V (DEF = 0V) 35mA
ON6
FROM CPU SYS_EN
Figure 6. MAX1586 Typical Applications Circuit (The MAX1587 omits some features. See the Pin Description section.) 26 ______________________________________________________________________________________
High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones
Note that the pole cancellation does not have to be exact. RC x CC need only be within 0.75 to 1.25 times RLOAD x COUT. This provides flexibility in component selection. If the output filter capacitor has significant ESR, a zero occurs at: ZESR = 1 / (2 x COUT x RESR) If ZESR > fC, it can be ignored, as is typically the case with ceramic or polymer output capacitors. If ZESR is less than fC, it should be cancelled with a pole set by capacitor CP connected from CC_ to GND: CP = COUT RESR / RC If CP is calculated to be < 10pF, it can be omitted. Optimizing Transient Response In applications that require load-transient response to be optimized in favor of minimum component values, increase the output filter capacitor to increase the R in the compensation RC. From the equations in the previous section, doubling the output cap allows a doubling of the compensation R, which then doubles the transient gain.
MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
MAX1586 MAX1587
PV3
TO BATT V3 VCC_CORE 1.55V MAX R24** 3.3
LX3 STEP-DOWN PWM REG3
PG3 FB3 R25 100k
185.5k
**OTHER R24 VALUES: R24 = 5.5k, V3: 0.759V TO 1.60V R24 = 7.7k, V3: 0.783V TO 1.65V
Figure 7. Addition of R24 and R25 increases maximum core voltage. The values shown raise the maximum core from 1.475V to 1.55V.
Applications Information
Extending the Maximum Core Voltage Range
The V3 output can be serially programmed to supply from 0.7V to 1.475V in 25mV steps. In some cases, a higher CPU core voltage may be desired. The V3 voltage range can be increased by adding two resistors as shown in Figure 7. R24 and R25 add a small amount of gain. They are set so that an internally programmed value of 1.475V results in a higher actual output at V3. The resistors shown in Figure 1 set a maximum output of 1.55V, 1.6V, or 1.65V. All output steps are shifted and the step size is also slightly increased. The output voltage for each programmed step of V3 in Figure 7 is: V3 = V3PROG + (R24[(V3PROG / R25) + (V3PROG / 185,500)]) where V3 is the actual output voltage, V3PROG is the original programmed voltage from the "OUTPUT (V)" column in Table 2, and 185,500 is the internal resistance of the FB3 pin.
Backup-Battery and V7 Configurations
The MAX1586/MAX1587 include a backup-battery connection, BKBT, and an output, V7. These can be utilized in different ways for various system configurations. Primary Backup Battery A connection with a primary (nonrechargeable) lithium coin cell is shown in Figure 6. The lithium cell connects to BKBT directly. V7 powers the CPU VCC_BATT from either V1 (if enabled) or the backup battery. It is assumed whenever the main battery is good, V1 is on (either with its DC-DC converter or sleep LDO) to supply V7. No Backup Battery (or Alternate Backup) If no backup battery is used, or if an alternate backup and VCC_BATT scheme is used that does not use the MAX1586/MAX1587, then BKBT should be biased from IN with a small silicon diode (1N4148 or similar, as in Figure 8). BKBT must still be powered when no backup battery is used because DBO, RSO, and POK require this supply to function. If BKBT is not powered, these outputs do not function and are high impedance. Rechargeable Li+ Backup Battery If more backup power is needed and a primary cell has inadequate capacity, a rechargeable lithium cell can be accommodated as shown in Figure 9. A series resistor
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High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
and diode charge the cell when the 3.3V V1 supply is active. In addition to biasing V7, the rechargeable battery may be required to also power other supplies.
MAIN POWER IN 4.7F D1 1N4148
MAX1586 MAX1587 BKBT
V7
1F
Figure 8. BKBT connection when no backup battery is used, or if an alternate backup scheme, not involving the MAX1586/MAX1587, is used.
Rechargeable NiMH Backup Battery In some systems, a NiMH battery may be desired for backup. Usually this requires multiple cells because the typical NiMH cell voltage is only 1.2V. By adding a small DC-DC converter (MAX1724), the low-battery voltage is boosted to 3V to bias BKBT (Figure 10). The DC-DC converter's low operating current (1.5A typ) allows it to remain on constantly so the 3V BKBT bias is always present. A resistor and diode trickle charge the NiMH cell when the main power is present.
PC Board Layout and Routing
Good PC board layout is important to achieve optimal performance. Conductors carrying discontinuous currents and any high-current path should be made as short and wide as possible. A separate low-noise ground plane containing the reference and signal grounds should connect to the power-ground plane at only one point to minimize the effects of power-ground currents. Typically, the ground planes are best joined right at the IC. Keep the voltage feedback network very close to the IC, preferably within 0.2in (5mm) of the FB_ pin. Nodes with high dV/dt (switching nodes) should be kept as small as possible and should be routed away from high-impedance nodes such as FB_. Refer to the MAX1586 or MAX1587 evaluation kit data sheets for a full PC board example.
MAIN POWER
IN 4.7F 1k V1
MAX1586 MAX1587
BKBT 1-CELL Li+ RECHARGEABLE BACKUP BATTERY 4.7F V7 1F
Figure 9. A 1-cell rechargeable Li+ battery provides more backup power when a primary cell is insufficient. The cell is charged to 3.3V when V1 is active. Alternately, the battery can be charged from IN if the voltages are appropriate for the cell type.
1N4148
10k MURATA LQH32C 10H
MAIN POWER IN 4.7F
1-CELL NiMH RECHARGEABLE BACKUP BATTERY
4.7F
BATT
LX
MAX1586 MAX1587
3.0V
MAX1724 EZK30
SHDN GND OUT 10F
BKBT V7
1F
Figure 10. A 1-cell NiMH battery can provide backup by boosting with a low-power DC-DC converter. A series resistor-diode trickle charges the battery when the main power is on. 28 ______________________________________________________________________________________
High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones
Selector Guide
PART MAX1586A MAX1586B MAX1586C MAX1587A MAX1587C REG2 PRESET VOLTAGE (ALSO ADJUSTABLE) 1.8V, 2.5V 3.3V, 2.5V 1.8V, 2.5V 1.8V, 2.5V 1.8V, 2.5V REG3 (VCC_CORE) OUTPUT CURRENT 0.5A 0.5A 0.9A 0.5A 0.9A -- VCC_USIM (V6) linear regulator, LBO and DBO battery monitors OTHER FUNCTIONS
MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
Pin Configurations
SLP ON1 PV1 CC1 LX1 PG1 ON1 ON3 FB3 CC3 SLP PV1 LX1 PG1 IN6 V6 DBI MR MR
36 RSO 35 SRAD 34 ON3 33 PV3 32 LX3 31 PG3 30 ON5 29 V5 28 IN45 27 V4 26 ON4 25 ON2 13 14 15 16 17 18 19 20 21 22 23 24
TOP VIEW
40 39 38 37 36 35 34 33 32 31
48 47 46 45 44 43 42 41 40 39 38 37 30 RSO 29 SRAD 28 PV3 27 LX3 26 PG3
FB1 BKBT V7 V1 SLPIN V2 FB2 CC2 POK
1 2 3 4 5 6 7 8 9
LB1 CC1 FB1 BKBT
1 2 3 4
MAX1587AETL MAX1587CETL
25 V5 24 IN45 23 V4 22 ON45 21 ON2
V7 5 V1 6 SLPIN 7 V2 8 FB2 9 CC2 10 POK 11 SCL 12 SDA PWM3
MAX1586AETM MAX1586BETM MAX1586CETM
SCL 10
11 12 13 14 15 16 17 18 19 20
PWM3
PV2 LX2 PG2 IN RAMP
GND
SDA
REF BYP
LBO PV2
LX2
PG2 IN
RAMP GND
REF BYP
ON6 FB3 CC3
THIN QFN 6mm x 6mm
THIN QFN 7mm x 7mm
Chip Information
TRANSISTOR COUNT: 13,958 PROCESS: BiCMOS
______________________________________________________________________________________
DBO
29
High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
D2 D D/2 k
C L
b D2/2
E/2 E2/2 E (NE-1) X e
C L
E2
k
e (ND-1) X e
L
e L
C L C L
L1 L L
e
e
A1
A2
A
PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm
21-0141
E
1
2
30
______________________________________________________________________________________
QFN THIN 6x6x0.8.EPS
High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1. 10. WARPAGE SHALL NOT EXCEED 0.10 mm.
PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm
21-0141
E
2
2
______________________________________________________________________________________
31
High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
D2 D D/2 k
C L
b D2/2
E/2 E2/2
E
(NE-1) X e
C L
E2
k L DETAIL A e (ND-1) X e DETAIL B
e L
C L
C L
L1
L
L
e
e
A1
A2
A
TITLE:
SEMICONDUCTOR
PROPRIETARY INFORMATION
DALLAS
PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm
DOCUMENT CONTROL NO. REV.
APPROVAL
21-0144
1 2
D
32
______________________________________________________________________________________
32, 44, 48L QFN.EPS
High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX1586A/MAX1586B/MAX1586C/MAX1587A/MAX1587C
SEMICONDUCTOR
PROPRIETARY INFORMATION TITLE:
DALLAS
PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm
DOCUMENT CONTROL NO. REV.
APPROVAL
21-0144
2 2
D
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 33 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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