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| Wideband, Ring Demodulator CORPORATION SD8901 FEATURES DESCRIPTION The SD8901 is a ring demodulator/balanced mixer. Designed to utilize Calogic's ultra high speed and low capacitance lateral DMOS process. The SD8901 offers significant performance improvements over JFET and diode balanced mixers when low third order harmonic distortion has been a problem. PACKAGE INFORMATION Part Package Temperature Range -55oC to 125oC -55oC to 125oC -55oC to 125oC SD8901HD Hermetic TO-78 SD8901CY Plastic Surface Mount XSD8901 Sorted Chips in Carriers PIN CONFIGURATIONS Functional block diagram * High Frequency Operation * Wide Dynamic Range * Low Capacitance * Communications * RF Mixers APPLICATIONS SO-14 TO-78 LO1 5 IF2 7 RF2 3 C IF 2 LO1 LO 2 IF1 RF2 RF 1 TOP VIEW LO1 SUB LO2 SUB IF2 SUB NC RF 2 SUB RF 1 SUB IF 1 SUB NC 1 2 3 4 5 6 7 IF 1 RF1 RF2 CASE LO 1 LO 2 IF 2 45 3 2 1 6 6 7 2 1 LO2 RF1 IF1 4 SUBSTRATE BOTTOM VIEW CD4 SD8901 CORPORATION ABSOLUTE MAXIMUM RATINGS (TA = +25oC unless otherwise noted) VDS VDB VSB VGS VGB VGD Drain to Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V Drain to Substrate . . . . . . . . . . . . . . . . . . . . . . . . 22.5 V Source to Substrate . . . . . . . . . . . . . . . . . . . . . . . 22.5 V Gate to Source. . . . . . . . . . . . . . . . . . . . -22.5 V to 30 V Gate to Substrate. . . . . . . . . . . . . . . . . . . . -0.3V to 30 V Gate to Drain . . . . . . . . . . . . . . . . . . . . . . -22.5V to 30 V ID Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Operating Temperature . . . . . . . . . . . . . . . . . . . . -55 to 125oC Storage Temperature . . . . . . . . . . . . . . . . . . . . . . -65 to 150oC Power Dissipation (A Package)* . . . . . . . . . . . . . . . . 640 mW * Derate 5 mW/ oC above 25oC ELECTRICAL CHARACTERISTCIS (TA = +25oC unless otherwise noted) SYMBOL STATIC V(BR)DS V(BR)SD V(BR)DB V(BR)SB VT Drain-Source Breakdown Voltage Source-Drain Breakdown Voltage Drain-Substrate Breakdown Voltage Source-Substrate Breakdown Voltage Threshold Voltage 15 15 22.5 22.5 0.1 1 50 rDS(ON) Drain-Source "ON" Resistance 30 23 19 rDS(ON) DYNAMIC Cgg Lc IMD3 fMAX LO1 - LO2 Capacitance Conversion Loss Third Order Intercept Maximum Operation Frequency 4.4 8 +35 250 MHz pF VDS = 0 V, VBS = -5.5 V VGS = 4 V See Figure 1, PLO = +17 dBm Resistance Matching 3 7 ID = 1 mA VSB = 0 V 2.0 75 V 25 VGS = VSB = -5 V Is = 10 nA VGD = VDB = - 5 V ID = 10 nA Source Open VGB = 0 V, ID = 10 nA Drain Open VGB = 0 V, ID = 10 nA VDS = VGS = VT IS = 1 A, VSB = 0V VGS = 5 V VGS = 10 V VGS = 15 V VGS = 20 V VGS = 5 V CHARACTERISTICS MIN TYP MAX UNIT TEST CONDITIONS dB Note: Guaranteed by design, not subject to production test PERFORMANCE COMPARISON 40 3rd ORDER INPUT INTERCEPT POINT (+dBM) 30 20 10 0 0 5 SD8901 U350 DIODE RING 10 15 20 25 30 35 POWER LOCAL OSC. (+dBm) SD8901 CORPORATION FIGURE 1. SD8901 +V GG u T1-1T OR T4-1 u T4-1 LO SIGNAL u LOW-PASS IMAGE TERMINATING FILTER (OPTIONAL) u 680 pF T4-1 -Vu 680 pF i-f FIGURE 2. First and third Quadrand I-E Characteristic Showing Effect of Gate Voltage Leading to Large-Signal Overload Distortion. ID (ma) 16 V 50.00 8V 12 V 10.00 /DIV 4V 0V 0 -50.00 -5.000 VDS 0 1.000/DIV (V) 5.000 |
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