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Wireless Components
ASK/FSK 915MHz Single Conversion Receiver TDA 5212 Version 1.1
Specification May 2003
preliminary
Revision History Current Version: 1.1 as of 09.05.03 Previous Version: 1.0 Page (in previous Version) 5-12, 5-13 Page (in current Version) 5-12, 5-13 Subjects (major changes since last revision)
Table 5-4, Table 5-5, Bill of Materials
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Edition 05.03 Published by Infineon Technologies AG, Balanstrae 73, 81541 Munchen (c) Infineon Technologies AG May 2003. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Infineon Technologies AG, may only be used in life-support devices or systems2 with the express written approval of the Infineon Technologies AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that lifesupport device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
TDA 5212
preliminary
Product Info
Product Info
General Description The IC is a very low power consump- Package tion single chip FSK/ASK Superheterodyne Receiver (SHR) for the receive frequency range between 910 and 920 MHz that is pin compatible to the ASK Receiver TDA5202. The IC offers a high level of integration and needs only a few external components. The device contains a low noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a PLL synthesiser, a crystal oscillator, a limiter with RSSI generator, a PLL FSK demodulator, a data filter, a data comparator (slicer) and a peak detector. Additionally there is a power down feature to save battery life. Low supply current (Is = 5.4 mA typ. in FSK mode, Is = 4.8 mA typ. in ASK mode) Supply voltage range 5 V 10% Power down mode with very low supply current (90 nA typ.) FSK and ASK demodulation capability Fully integrated VCO and PLL Synthesiser ASK sensitivity better than -109 dBm over specified temperature range (- 40 to +85C) Application Keyless Entry Systems Remote Control Systems Receive frequency range 910 to 920 MHz Limiter with RSSI generation, operating at 10.7 MHz Selectable reference frequency 2nd order low pass data filter with external capacitors Data slicer with self-adjusting threshold FSK sensitivity better than -102 dBm over specified temperature range (- 40 to +85C)
Features
Low Bitrate ISM-band Communication Systems
Ordering Information
Type TDA 5212 samples available Ordering Code Package P-TSSOP-28-1
Wireless Components
Product Info
Specification, May 2003
1
2.1 2.2 2.3 2.4
Table of Contents
i
1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1 2-2 2-2 2-2 2-3
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 3.2 3.3 3.4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1 3-2 3-3 3-9 3-10 3-10 3-10 3-10 3-11 3-11 3-11 3-12 3-12 3-12 3-13
3.4.1 Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3 PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.4 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.5 Limiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.6 FSK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.7 Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.8 Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.9 Peak Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.10 Bandgap Reference Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 4.2 4.3 4.4 4.5 4.6 Choice of LNA Threshold Voltage and Time Constant. . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ASK/FSK Switch Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-1 4-2 4-4 4-5 4-6 4-7 4-8 4-8 4-10 4-11
4.6.1 FSK Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.2 ASK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 Principle of the Precharge Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-1 5-2 5-2 5-3 5-4 5-9 5-10 5-12
5.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 5.3 5.4 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Board Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
i
7 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
i
2
Product Description
Contents of this Chapter 2.1 2.2 2.3 2.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
TDA 5212
preliminary
Product Description
2.1 Overview
The IC is a very low power consumption single chip FSK/ASK Superheterodyne Receiver (SHR) for receive frequencies between 910 and 920 MHz that is pin compatible to the ASK Receiver TDA5202. The IC offers a high level of integration and needs only a few external components. The device contains a low noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a PLL synthesiser, a crystal oscillator, a limiter with RSSI generator, a PLL FSK demodulator, a data filter, a data comparator (slicer) and a peak detector. Additionally there is a power down feature to save battery life.
2.2 Application
Keyless Entry Systems Remote Control Systems Low Bitrate ISM-band Communication Systems
2.3 Features
Low supply current (Is = 5.4 mA typ.FSK mode, 4.8 mA typ. ASK mode) Supply voltage range 5V 10% Power down mode with very low supply current (90nA typ.) FSK and ASK demodulation capability Fully integrated VCO and PLL Synthesiser RF input sensitivity ASK -112dBm typ. at 25C, better than -109dBm over complete specified operating temperature range (-40 to +85C) RF input sensitivity FSK -105dBm typ. at 25C, better than -102dBm over complete specified operating temperature range (-40 to +85C) Receive frequency range between 910 and 920 MHz Selectable reference frequency Limiter with RSSI generation, operating at 10.7MHz 2nd order low pass data filter with external capacitors Data slicer with self-adjusting threshold
Wireless Components
2-2
Specification, May 2003
TDA 5212
preliminary
Product Description
2.4 Package Outlines
P_TSSOP_28.EPS
Figure 2-1
P-TSSOP-28-1 package outlines
Wireless Components
2-3
Specification, May 2003
3
Functional Description
Contents of this Chapter 3.1 3.2 3.3 3.4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
TDA 5212
preliminary
Functional Description
3.1 Pin Configuration
CRST1 VCC LNI TAGC AGND LNO VCC MI M IX AGND FSEL IF O DGND VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23
CRST2 PDW N PDO DATA 3VO UT THRES FFB OPP SLN SLP L IM X L IM CSEL M SEL
TDA 5212
22 21 20 19 18 17 16 15
Pin_Configuration_5212_V1.0.wmf
Figure 3-1
IC Pin Configuration
Wireless Components
3-2
Specification, May 2003
TDA 5212
preliminary
Functional Description
3.2 Pin Definition and Function
Table 3-1 Pin Definition and Function Pin No. 1 Symbol CRST1 Equivalent I/O-Schematic Function External Crystal Connector 1
4.1 5V
1
5 0 uA
2 3
VCC LNI
5V Supply LNA Input
57uA
3
500uA 4k
1k
Wireless Components
3-3
Specification, May 2003
TDA 5212
preliminary
Functional Description
4
TAGC
4 .3 V
AGC Time Constant Control
3u A 4
1k
1 .4 u A
1 .7V
5 6
AGND LNO
5V
5V
Analogue Ground Return LNA Output
1k
1k
6
6
7 8
VCC MI
1 .7 V
5V Supply Mixer Input
2k
2k
9
MIX
8 9
Complementary Mixer Input
40 0u A
10 11
AGND BUF
Analogue Ground Return Mixer Buffer Ground
Wireless Components
3-4
Specification, May 2003
TDA 5212
preliminary
Functional Description
12
IFO
10.7 MHz IF Mixer Output
300uA
2 .2 V
60 12
4 .5 k
13 14 15
DGND VDD MSEL
60 12
300uA
Digital Ground Return 5V Supply (PLL Counter Circuitry)
2 .2 V
ASK/FSK Modulation Format Selector
1.2V
4 .5 k
3.6k 15
16
CSEL
7.xx or 14.xx MHz Quartz Selector
1 .2 V
8 0k 16
Wireless Components
3-5
Specification, May 2003
TDA 5212
preliminary
Functional Description
17
LIM
2.4V
Limiter Input
1 5k 17
18
LIMX
3 30 7 5 uA
Complementary Limiter Input
18
1 5k
19
SLP
Data Slicer Positive Input
15 uA
1 00 19
3k
80 A
20
SLN
Data Slicer Negative Input
5uA
10k 20
Wireless Components
3-6
Specification, May 2003
TDA 5212
preliminary
Functional Description
21
OPP
OpAmp Noninverting Input
5uA
200 21
22
FFB
Data Filter Feedback Pin
5 uA
100 k 22
23
THRES
AGC Threshold Input
5uA
10k 23
24
3VOUT
24 2 0k 3 .1 V
3V Reference Output
Wireless Components
3-7
Specification, May 2003
TDA 5212
preliminary
Functional Description
25
DATA
Data Output
500 25 40k
26
PDO
Peak Detector Output
200 26
27
PDWN
27
Power Down Input
220k
220k
28
CRST2
External Crystal Connector 2
4 .1 5 V
28
50uA
Wireless Components
3-8
Specification, May 2003
TDA 5212
preliminary
Functional Description
3.3 Functional Block Diagram
VCC
IF Filter
MSEL LNO 6 MI 8 MIX 9 IFO 12 LIM 17 LIMX 18 15 FFB 22 OPP 21 SLP 19 SLN 20
RF
LNI
3
LNA FSK PLL Demod
+
OP
LIMITER
TAGC
4
OTA
TDA 5212
: 128 / 64 F DET CRYSTAL OSC UREF AGC Reference
BUF VCC 14
VCO
DGND
13 2,7 5,10 11
Loop Filter 16 1 28
VCC AGND
BUF
CSEL Crystal
Figure 3-2
Main Block Diagram
Wireless Components
3-9
-
+ FSK - ASK +
SLICER +
25
DATA
PEAK 26 PDO DETECTOR
23
THRES
24
3VOUT
Bandgap Reference 27
PDWN
Functional_diagram_5212.wmf
Specification, May 2003
TDA 5212
preliminary
Functional Description
3.4 Functional Blocks
3.4.1
Low Noise Amplifier (LNA)
The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20dB. The gain figure is determined by the external matching networks situated ahead of LNA and between the LNA output LNO (Pin 6) and the Mixer Inputs MI and MIX (Pins 8 and 9). The noise figure of the LNA is approximately 2dB, the current consumption is 500A. The gain can be reduced by approximately 18dB. The switching point of this AGC action can be determined externally by applying a threshold voltage at the THRES pin (Pin 23). This voltage is compared internally with the received signal (RSSI) level generated by the limiter circuitry. In case that the RSSI level is higher than the threshold voltage the LNA gain is reduced and vice versa. The threshold voltage can be generated by attaching a voltage divider between the 3VOUT pin (Pin 24) which provides a temperature stable 3V output generated from the internal bandgap voltage and the THRES pin as described in Section 4.1. The time constant of the AGC action can be determined by connecting a capacitor to the TAGC pin (Pin 4) and should be chosen along with the appropriate threshold voltage according to the intended operating case and interference scenario to be expected during operation. The optimum choice of AGC time constant and the threshold voltage is described in Section 4.1.
3.4.2
Mixer
The Double Balanced Mixer downconverts the input frequency (RF) in the range of 910 to 920 MHz to the intermediate frequency (IF) at 10.7MHz with a voltage gain of approximately 21dB. A low pass filter with a corner frequency of 20MHz is built on chip in order to suppress RF signals to appear at the IF output ( IFO pin). The IF output is internally consisting of an emitter follower that has a source impedance of approximately 330 W to facilitate interfacing the pin directly to a standard 10.7MHz ceramic filter without additional matching circuitry.
3.4.3
PLL Synthesizer
The Phase Locked Loop synthesiser consists of a VCO, an asynchronous divider chain, a phase detector with charge pump and a loop filter and is fully implemented on-chip. The VCO is including spiral inductors and varactor diodes. The oscillator signal is fed both to the synthesiser divider chain and to the downconverting mixer via a buffer amplifier. The BUF pin (Pin 11) has to be tied to ground. No additional components are necessary. The loop filter is also realised fully on-chip. High-side injection of the local oscillator has to be used for the receive frequency band of 910 to 920 MHz, yielding local oscillator frequencies in the region of 920 to 930 MHz. See also Section 4.4.
Wireless Components
3 - 10
Specification, May 2003
TDA 5212
preliminary
Functional Description
3.4.4
Crystal Oscillator
The on-chip crystal oscillator circuitry allows for utilisation of quartzes both in the 7 and 14MHz range as the overall division ratio of the PLL can be switched between 64 and 128 via the CSEL (Pin 16 ) pin according to the following table.
Table 3-2 CSEL Pin Operating States CSEL Open Shorted to ground Crystal Frequency 7.xx MHz 14.xx MHz
The calculation of the value of the necessary quartz load capacitance is shown in Section 4.3, the quartz frequency calculation is expained in Section 4.4.
3.4.5
Limiter
The Limiter is an AC coupled multistage amplifier with a cumulative gain of approximately 80dB that has a bandpass-characteristic centred around 10.7MHz. It has an input impedance of 330 W to allow for easy interfacing to a 10.7MHz ceramic IF filter. The limiter circuit acts as a Receive Signal Strength Indicator (RSSI) generator which produces a DC voltage that is directly proportional to the input signal level as can be seen in Figure 4-2. This signal is used to demodulate the ASK receive signal in the subsequent baseband circuitry and to turn down the LNA gain by approximately 18dB in case the input signal strength is too strong as described in Section 3.4.1 and Section 4.1.
3.4.6
FSK Demodulator
To demodulate frequency shift keyed (FSK) signals a PLL circuit is used that is contained fully on chip. The Limiter output differential signal is fed to the linear phase detector as is the output of the 10.7 MHz center frequency VCO. The demodulator gain is typically 180V/kHz. The passive loop filter output that is comprised fully on chip is fed to both the VCO and the modulation format switch.This signal is representing the demodulated signal. This switch is actually a switchable amplifier with an AC gain of 11 that is controlled by the MSEL pin (Pin 15) as shown in the following table. This gain was chosen to facilitate detection in the subsequent circuits.
Table 3-3 MSEL Pin Operating States MSEL Open Shorted to ground Modulation Format ASK FSK
Wireless Components
3 - 11
Specification, May 2003
TDA 5212
preliminary
Functional Description
The DC gain is 1 in order not to saturate the subsequent Data Filter wih the DC offset produced by the demodulator in case of large frequency offsets of the IF signal. The resulting frequency characteristic and details on the principle of operation of the switch are described in Section 4.6. The demodulator circuit is switched off in case of reception of ASK signals.
3.4.7
Data Filter
The data filter comprises an OP-Amp with a bandwidth of 100kHz used as a voltage follower and two 100kW on-chip resistors. Along with two external capacitors a 2nd order Sallen-Key low pass filter is formed. The selection of the capacitor values is described in Section 4.2.
3.4.8
Data Slicer
The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows for a maximum receive data rate of approximately 120kBaud. The maximum achievable data rate also depends on the IF Filter bandwidth and the local oscillator tolerance values. Both inputs are accessible. The output delivers a digital data signal (CMOS-like levels) for the detector. The self-adjusting threshold on pin 20 its generated by RC-term or peak detector depending on the baseband coding scheme. The data slicer threshold generation alternatives are described in more detail in Section 4.5.
3.4.9
Peak Detector
The peak detector generates a DC voltage which is proportional to the peak value of the receive data signal. An external RC network is necessary. The input is connected to the output of the RSSI-output of the Limiter, the output is connected to the PDO pin (Pin 26 ). This output can be used as an indicator for the received signal strength to use in wake-up circuits and as a reference for the data slicer in ASK mode. The output current is typically 850A, the leakage current is typically 700nA. Note that the RSSI level is also output in case of FSK mode.
Wireless Components
3 - 12
Specification, May 2003
TDA 5212
preliminary
Functional Description
3.4.10
Bandgap Reference Circuitry
A Bandgap Reference Circuit provides a temperature stable reference voltage for the device. A power down mode is available to switch off all subcircuits which is controlled by the PWDN pin (Pin 27) as shown in the following table. The supply current drawn in this case is typically 90nA.
Table 3-4 PDWN Pin Operating States PDWN Open or tied to ground Tied to Vs Operating State Powerdown Mode Receiver On
Wireless Components
3 - 13
Specification, May 2003
4
Applications
Contents of this Chapter 4.1 4.2 4.3 4.4 4.5 4.6 4.7 Choice of LNA Threshold Voltage and Time Constant . . . . . . . . . . . . 4-2 Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Crystal Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Crystal Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 ASK/FSK Switch Functional Description . . . . . . . . . . . . . . . . . . . . . . 4-8 Principle of the Precharge Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
TDA 5212
preliminary
Applications
4.1 Choice of LNA Threshold Voltage and Time Constant
In the following figure the internal circuitry of the LNA automatic gain control is shown.
R1
R2
Uthr e s h o ld Pins: 24 23
20kW
RSSI (0.8 - 2.8V)
OTA +3.1 V
VCC
Ilo ad RSSI > Uthr e s h o ld : Iloa d =4.2A RSSI < Uthr e s h o ld : Iloa d = -1.5A 4 UC C
LNA Gain control v oltage
Uc :< 2.6V : Gain high Uc :> 2.6V : Gain low Uc max = VC C - 0.7V Uc min = 1.67V
LNA_autom.wmf
Figure 4-1
LNA Automatic Gain Control Circuitry
The LNA automatic gain control circuitry consists of an operational transimpedance amplifier that is used to compare the received signal strength signal (RSSI) generated by the Limiter with an externally provided threshold voltage Uthres. As shown in the following figure the threshold voltage can have any value between approximately 0.8 and 2.8V to provide a switching point within the receive signal dynamic range. This voltage Uthres is applied to the THRES pin (Pin 23) The threshold voltage can be generated by attaching a voltage divider between the 3VOUT pin (i.e. Pin 24) which provides a temperature stable 3V output generated from the internal bandgap voltage and the THRES pin. If the RSSI level generated by the Limiter is higher than Uthres, the OTA generates a positive current Iload. This yields a voltage rise on the TAGC pin (Pin 4). Otherwise, the OTA generates a negative current. These currents do not have the same values in order to achieve a fast-attack and slow-release action of the AGC and are used to charge an external capacitor which finally generates the LNA gain control voltage.
Wireless Components
4-2
Specification, May 2003
TDA 5212
preliminary
Applications
LNA always in high gain mode
3
2.5
UTHRES Voltage Range
2
RSSI Level Range
RSSI Level
1.5
1
LNA always in low gain mode
0.5
0 -120
-110
-100
-90
-80
-70
-60
-50
-40
-30
Input Level at LNA Input [dBm]
RSSI-AGC.wmf
Figure 4-2
RSSI Level and Permissive AGC Threshold Levels
The switching point should be chosen according to the intended operating scenario. The determination of the optimum point is described in the accompanying Application Note, a threshold voltage level of 1.8V is apparently a viable choice. It should be noted that the output of the 3VOUT pin is capable of driving up to 50A, but that the THRES pin input current is only in the region of 40nA. As the current drawn out of the 3VOUT pin is directly related to the receiver power consumption, the power divider resistors should have high impedance values. The sum of R1 and R2 has to be 600kW in order to yield 3V at the 3VOUT pin. R1 can thus be chosen as 240kW, R2 as 360kW to yield an overall 3VOUT output current of 5A1 and a threshold voltage of 1.8V Note: If the LNA gain shall be kept in either high or low gain mode this has to be accomplished by tying the THRES pin to a fixed voltage. In order to achieve high gain mode operation, a voltage higher than 2.8V shall be applied to the THRES pin, such as a short to the 3VOLT pin. In order to achieve low gain mode operation a voltage lower than 0.7V shall be applied to the THRES, such as a short to ground. As stated above the capacitor connected to the TAGC pin is generating the gain control voltage of the LNA due to the charging and discharging currents of the OTA and thus is also responsible for the AGC time constant. As the charging and discharging currents are not equal two different time constants will result. The time constant corresponding to the charging process of the capacitor shall be chosen according to the data rate. According to measurements performed at Infineon the capacitor value should be greater than 47nF.
1. note the 20kW resistor in series with the 3.1V internal voltage source
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4-3
Specification, May 2003
TDA 5212
preliminary
Applications
4.2 Data Filter Design
Utilising the on-board voltage follower and the two 100kW on-chip resistors a 2nd order Sallen-Key low pass data filter can be constructed by adding 2 external capacitors between pins 19 (SLP) and 22 (FFB) and to pin 21 (OPP) as depicted in the following figure and described in the following formulas1.
C1
C2
Pins: R 100k
22 R 100k
21
19
Filter_Design.wmf
Figure 4-3
Data Filter Design
(1)
(2)
2Q b C1 = ---------------------R2Pf 3dB
with
b C2 = -------------------------4QRPf 3dB
b Q = -----a
where in case of a Bessel filter and thus
(3)
the quality factor of the poles
a = 1.3617, b = 0.618 Q = 0.577
and in case of a Butterworth filter and thus
a = 1.141, b = 1 Q = 0.71
Example: Butterworth filter with f3dB = 5kHz and R = 100kW: C1 = 450pF, C2 = 225pF
1. taken from Tietze/Schenk: Halbleiterschaltungstechnik, Springer Berlin, 1999
Wireless Components
4-4
Specification, May 2003
TDA 5212
preliminary
Applications
4.3 Crystal Load Capacitance Calculation
The value of the capacitor necessary to achieve that the crystal oscillator is operating at the intended frequency is determined by the reactive part of the negative resistance of the oscillator circuit as shown in Section 5.1.3 and by the crystal specifications given by the crystal manufacturer.
CS Pin 28 Crystal Input impedance Z1-28
TDA5212 Pin 1
Quartz_load_5212.wmf
Figure 4-4
Determination of Series Capacitance Value for the Crystal Oscillator
Crystal specified with load capacitance
CS =
1 1 + 2p f X L Cl
with Cl the load capacitance (refer to the crystal specification). Examples: 7.2 MHz: 14.5 MHz: CL = 12 pF CL = 12 pF XL=500 W XL=1050 W CS = 9.5 pF CS = 5.6 pF
These values may be obtained in high accuracy by putting two capacitors in series to the quartz, such as 18pF and 20pF in the 7.2MHz case and 18pF and 8.2pF in the 14.5MHz case.
Wireless Components
4-5
Specification, May 2003
TDA 5212
preliminary
Applications
4.4 Crystal Frequency Calculation
The local oscillator (UHF PLL) signal has to be high-side injected into the downconverting mixer. Thus the crystal frequency is calculated by using the following formula:
QU = (RF + 10.7) / r with RF LO QU r .... .... .... .... receive frequency local oscillator (PLL) frequency (RF + 10.7) crystal oscillator frequency ratio of local oscillator (PLL) frequency and crystal frequency as shown in the subsequent table.
Table 4-1 PLL Division Ratio Dependence on States of CSEL CSEL Ratio r = (fLO/fQU) 128 64
open GND
This yields the following example: CSEL tied to GND:
f QU = (915 MHz + 10 .7 MHz ) / 64 = 14 .4641 MHz
Wireless Components
4-6
Specification, May 2003
TDA 5212
preliminary
Applications
4.5 Data Slicer Threshold Generation
The threshold of the data slicer can be generated in two ways, depending on the signal coding scheme used. In case of a signal coding scheme without DC content such as Manchester coding the threshold can be generated using an external R-C integrator as shown in the following . The cut-off frequency of the R-C integrator has to be lower than the lowest frequency appearing in the data signal. In order to keep distortion low, the minimum value for R is 20kW.
R C
Pins:
19
20 Uthreshold
data out 25
data filter data slicer
Data_slice1.wmf
Figure 4-5
Data Slicer Threshold Generation with External R-C Integrator
Another possibility for threshold generation is to use the peak detector in connection with two resistors and one capacitor as shown in the following figure. The component values are depending on the coding scheme and the protocol used.
R C R data out 25 Uthreshold
Pins: peak detector
26
19
20
data slicer
data filter
Data_slice2.wmf
Figure 4-6
Data Slicer Threshold Generation Utilising the Peak Detector
Wireless Components
4-7
Specification, May 2003
TDA 5212
preliminary
Applications
4.6 ASK/FSK Switch Functional Description
The TDA5211 is containing an ASK/FSK switch which can be controlled via Pin 15 (MSEL). This switch is actually consisting of 2 operational amplifiers that are having a gain of 1 in case of the ASK amplifier and a gain of 11 in case of the FSK amplifier in order to achieve an appropriate demodulation gain characteristic. In order to compensate for the DC-offset generated especially in case of the FSK PLL demodulator there is a feedback connection between the threshold voltage of the bit slicer comparator (Pin 20) to the negative input of the FSK switch amplifier. This is shown in the figure below:
15 RSSI (ASK signal)
MSEL
ASK/FSK Switch Data Filter FSK PLL Demodulator + ASK + FSK 0.18 mV/kHz
AC
R1=100k
R2=100k v=1 + Comp
DATA Out 25
R3=300k typ. 2 V 1.5 V......2.5 V
DC
R4=30k ASK mode : v=1 FSK mode : v=11
FFB 22
21
OPP
SLP
19
20
SLN
C2
C1
R C
ask_fsk_datapath.WMF
Figure 4-7
ASK/FSK mode datapath
4.6.1
FSK Mode
The FSK datapath has a bandpass characterisitc due to the feedback shown above (highpass) and the data filter (lowpass). The lower cutoff frequency f2 is determined by the external RC-combination. The upper cutoff frequency f3 is determined by the data filter bandwidth. The demodulation gain of the FSK PLL demodulator is 180V/kHz. This gain is increased by the gain v of the FSK switch, which is 11. Therefore the resulting dynamic gain of this circuit is 2mV/kHz within the bandpass. The gain for the DC
Wireless Components
4-8
Specification, May 2003
TDA 5212
preliminary
Applications
content of FSK signal remains at 180V/kHz. The cutoff frequencies of the bandpass have to be chosen such that the spectrum of the data signal is influenced in an acceptable amount. In case that the user data is containing long sequences of logical zeros the effect of the drift-off of the bit slicer threshold voltage can be lowered if the offset voltage inherent at the negative input of the slicer comparator (Pin20) is used. The comparator has no hysteresis built in. This offset voltage is generated by the bias current of the negative input of the comparator (i.e. 20nA) running over the external resistor R. This voltage raises the voltage appearing at pin 20 (e.g. 1mV with R = 100kW). In order to obtain benefit of this asymmetrical offset for the demodulation of long zeros the lower of the two FSK frequencies should be chosen in the transmitter as the zerosymbol frequency. In the following figure the shape of the above mentioned bandpass is shown.
gain (pin19)
v v-3dB
20dB/dec
-40dB/dec
3dB 0dB f DC f1 f2 f3
0.18m V/kHz
2mV/k Hz
frequenzgang.WMF
Figure 4-8
Frequency characterstic in case of FSK mode
The cutoff frequencies are calculated with the following formulas:
f1 =
1 R x 330kW xC 2p R + 330kW
Wireless Components
4-9
Specification, May 2003
TDA 5212
preliminary
Applications
f 2 = v x f1 =11 x f1
f 3 = f 3dB
f3 is the 3dB cutoff frequency of the data filter - see Section 4.2. Example: R = 100kW C = 47nF
This leads to f1 = 44Hz and f2 = 485Hz
4.6.2
ASK Mode
In case the receiver is operated in ASK mode the datapath frequency charactersitic is dominated by the data filter alone, thus it is lowpass shaped.The cutoff frequency is determined by the external capacitors C12 and C14 and the internal 100k resistors as described in Section 4.2
0dB -3dB
-40dB/dec
f f3dB
freq_ask.WMF
Figure 4-9
Frequency charcteristic in case of ASK mode
Wireless Components
4 - 10
Specification, May 2003
TDA 5212
preliminary
Applications
4.7 Principle of the Precharge Circuit
In case the data slicer threshold shall be generated with an external RC network as described in Section 4.5 it is necessary to use large values for the capacitor C attached to the SLN pin (pin 20) in order to achieve long time constants. This results also from the fact that the choice of the value for R connected between the SLP and SLN pins (pins 19 and 20) is limited by the 330kW resistor appearing in parallel to R as can be seen in Figure 4-6. Apart from this a resistor value of 100kW leads to a voltage offset of 1mv at the comparator input as described in Section 4.6.1. The resulting startup time constant t1 can be calculated with:
t1 = (R // 330kW) * C
In case R is chosen to be 100kW and C is chosen as 47nF this leads to
t1 = (100kW // 330kW) * 47nF = 77kW * 47nF = 3.6ms
When the device is turned on this time constant dominates the time necessary for the device to be able to demodulate data properly. In the powerdown mode the capacitor is only discharged by leakage currents. In order to reduce the turn-on time in the presence of large values of C a precharge circuit was included in the TDA5210 as shown in the following figure.
C2
R1+R2=600k R1 R2 C R Uth r es h o ld 24 23 Uc>Us U2 0 / 240uA OTA 20k +3.1V +2.4V Uc+ Us
U2<2.4V : I=240uA U2>2.4V : I=0
Figure 4-10
Principle of the precharge circuit
Wireless Components
4 - 11
+
precharge.WMF
Specification, May 2003
TDA 5212
preliminary
Applications
This circuit charges the capacitor C with an inrush current Iload of 240A for a duration of T2 until the voltage Uc appearing on the capacitor is equal to the voltage Us at the input of the data filter. This voltage is limited to 2.5V. As soon as these voltages are equal or the duration T2 is exceeded the precharge circuit is disabled.
t2 is the time constant of the charging process of C which can be calculated as t2 20kW * C2
as the sum of R1 and R2 is sufficiently large and thus can be neglected. T2 can then be calculated according to the following formula:
ae c 1 T 2 = t 2 ln c c 1 - 2 . 4V c 3V e o / / t 2 x1 . 6 / / o
The voltage transient during the charging of C2 is shown in the following figure:
U2
3V 2.4V
2
T2
e-fkt1.WMF
Figure 4-11
Voltage appearing on C2 during precharging process
The voltage appearing on the capacitor C connected to pin 20 is shown in the following figure. It can be seen that due to the fact that it is charged by a constant current source it exhibits is a linear increase in voltage which is limited to
Wireless Components
4 - 12
Specification, May 2003
TDA 5212
preliminary
Applications
USmax = 2.5V which is also the approximate operating point of the data filter input. The time constant appearing in this case can be denoted as T3, which can be calculated with
USmax x C 2,5V T3 = ----------------------- = ---------------- x C 240mA 240mA
Uc
Us
T3
e-Fkt2.WMF
Figure 4-12
Voltage transient on capacitor C attached to pin 20
As an example the choice of C2 = 20nF and C = 47nF yields
t2 = 0.4ms
T2 = 0.64ms T3 = 0.49ms This means that in this case the inrush current could flow for a duration of 0.64ms but stops already after 0.49ms when the USmax limit has been reached. T3 should always be chosen to be shorter than T2. It has to be noted finally that during the turn-on duration T2 the overall device power consumption is increased by the 240A needed to charge C.
Wireless Components
4 - 13
Specification, May 2003
TDA 5212
preliminary
Applications
The precharge circuit may be disabled if C2 is not equipped. This yields a T2 close to zero. Note that the sum of R4 and R5 has to be 600kW in order to produce 3V at the THRES pin as this voltage is internally used also as the reference for the FSK demodulator.
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4 - 14
Specification, May 2003
5
Reference
Contents of this Chapter 5.1 5.2 5.3 5.4 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 Test Board Layouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
TDA 5212
preliminary
Reference
5.1 Electrical Data
5.1.1
Absolute Maximum Ratings
WARNING
The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result.
Table 5-1 Absolute Maximum Ratings, Ambient temperature TAMB=-40C ... + 85C # Parameter Symbol Limit Values min 1 2 3 4 5 Supply Voltage Junction Temperature Storage Temperature Thermal Resistance ESD integrity, all pins Vs Tj Ts RthJA VESD -1 -0.3 -40 -40 max 5.5 +150 +125 114 +1 V C C K/W kV HBM according to MIL STD 883D, method 3015.7 Unit Remarks
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5-2
Specification, May 2003
TDA 5212
preliminary
Reference
5.1.2
Operating Range
Within the operating range the IC operates as explained in the circuit description. The AC/DC characteristic limits are not guaranteed.
Supply voltage: VCC = 4.5V .. 5.5V
Table 5-2 Operating Range, Ambient temperature TAMB= -40C ... + 85C # Parameter Symbol Limit Values min 1 Supply Current ISF ISA RFin -109 -102 max 6 5.4 -13 -13 mA mA dBm dBm fRF = 915MHz, FSK Mode fRF = 915MHz, ASK Mode @ source impedance 50W, BER 2E-3, average power level, Manchester encoded datarate 4kBit, 280kHz IF Bandwidth Unit Test Conditions L Item
2
Receiver Input Level ASK FSK, frequ. dev. 50kHz
3 4 6 7 8 9 10 11
LNI Input Frequency MI/X Input Frequency UHF Local Oscillator Frequency Range 3dB IF Frequency Range Powerdown Mode On Powerdown Mode Off Gain Control Voltage, LNA high gain state Gain Control Voltage, LNA low gain state
fRF fMI fLO fIF -3dB PWDNON PWDNOFF VTHRES VTHRES
910 910 920 5 0 2 2.8 0
920 920 930 23 0.8 VS VS 0.7V
MHz MHz MHz MHz V V V V
This value is guaranteed by design.
Wireless Components
5-3
Specification, May 2003
TDA 5212
preliminary
Reference
5.1.3
AC/DC Characteristics
AC/DC characteristics involve the spread of values guaranteed within the specified voltage and ambient temperature range. Typical characteristics are the median of the production. The device performance parameters marked with were measured on an Infineon evaluation board as desdribed in Section 5.2
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V # Parameter Symbol min Supply Supply Current 1 2 Supply current, standby mode Supply current, device operating in FSK mode IS PDWN ISF 90 5.4 120 5.7 nA mA Pin 27 (PDWN) open or tied to 0 V Pin 11 (FSEL) open, Pin 15 (MSEL) tied to GND Pin 11 (FSEL) open, Pin 15 (MSEL) open Limit Values typ max Unit Test Conditions L Item
3
Supply current, device operating in ASK mode
ISA
4.8
5.1
mA
LNA Signal Input LNI (PIN 3), VTHRES > 2.8V, high gain mode 1 Average Power Level at BER = 2E-3 (Sensitivity) ASK Average Power Level at BER = 2E-3 (Sensitivity) FSK Input impedance, fRF = 915 MHz Input level @ 1dB C.P. fRF=915 MHz Input 3rd order intercept point fRF = 915 MHz LO signal feedthrough at antenna port RFin -112 dBm Manchester encoded datarate 4kBit, 280kHz IF Bandwidth Manchester enc. datarate 4kBit, 280kHz IF Bandw., 50kHz pk. dev.
2
RFin
-105
dBm
3 4 5
S11 LNA P1dBLNA IIP3LNA LOLNI
0.717 / -78.4 deg t.b.d. t.b.d. dBm dBm fin = 914 & 916MHz
6
t.b.d.
dBm
Signal Output LNO (PIN 6), VTHRES > 2.8V, high gain mode 1 2 Gain fRF = 915 MHz Output impedance, fRF = 915 MHz S21 LNA S22 LNA 1.401 / 98.4 deg 0.869 / -25.7 deg
Wireless Components
5-4
Specification, May 2003
TDA 5212
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V (continued) # Parameter Symbol min 3 4 Voltage Gain Antenna to MI fRF = 915 MHz Noise Figure GAntMI NFLNA Limit Values typ t.b.d. t.b.d. max dB dB Unit Test Conditions L Item
Signal Input LNI, VTHRES = GND, low gain mode 1 2 Input impedance, fRF = 915 MHz Input level @ 1dB C. P. fRF = 915 MHz S11 LNA P1dBLNA 0.753 / -86.26 deg t.b.d. dBm
Signal Input LNI, VTHRES = GND, low gain mode 3 Input 3rd order intercept point fRF = 915 MHz IIP3LNA t.b.d. dBm fin = 914 & 916MHz
Signal Output LNO, VTHRES = GND, low gain mode 1 2 3 Gain fRF = 915 MHz Output impedance, fRF = 915 MHz Voltage Gain Antenna to MI fRF = 915 MHz S21 LNA S22 LNA GAntMI 0.174 / 107.4 deg 0.868 / -28.1 deg t.b.d. dB
Signal 3VOUT (PIN 24) 1 2 Output voltage Current out V3VOUT I3VOUT 2.9 3 3.1 50 V A I3Vout = 5A
Signal THRES (PIN 23) 1 2 3 4 Input Voltage range LNA low gain mode LNA high gain mode Current in VTHRES VTHRES VTHRES ITHRES_in 0 0 2.8 3 5 VS VS-1V V V V nA or shorted to Pin 24 see Section 4.1
Signal TAGC (PIN 4) 1 2 Current out, LNA low gain state Current in, LNA high gain state ITAGC_out ITAGC_in 3.8 1 4.2 1.5 4.8 2 A A RSSI > VTHRES RSSI < VTHRES
MIXER Signal Input MI/MIX (PINS 8/9) 1 2 Input impedance, fRF = 915 MHz Input 3rd order intercept point S11 MIX IIP3MIX 0.912 / -30.13 deg -25 dBm
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5-5
Specification, May 2003
TDA 5212
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V (continued) Parameter Symbol min Signal Output IFO (PIN 12) 1 2 3 4 Output impedance Conversion Voltage Gain fRF=869 MHz Noise Figure, SSB (~DSB NF+3dB) RF to IF isolation ZIFO GMIX NFMIX ARF-IF 330 t.b.d. t.b.d. t.b.d. W dB dB dB Limit Values typ max Unit Test Conditions L Item
LIMITER Signal Input LIM/X (PINS 17/18) 1 2 3 4 Input Impedance RSSI dynamic range RSSI linearity Operating frequency (3dB points) ZLIM DRRSSI LINRSSI fLIM 5 264 60 330 396 80 W dB dB 23 MHz
1
10.7
DATA FILTER 1 Useable bandwidth BWBB
FILT
100
kHz
SLICER Signal Output DATA (PIN 25) 1 2 3 4 5 6 Useable bandwith Capacitive loading of output LOW output voltage HIGH output voltage Output current Leakage current BWBB
SLIC
100 20 0
VS-1.1V VS-1V
kHz pF V V A A
Cmax
SLIC
VSLIC_L VSLIC_H ISLIC_out ISLIC_in
0.1
VS-0.9V
600 30
750 33
900 36
PEAK DETECTOR Signal Output PDO (PIN 26) 1 2 3 4 LOW output voltage HIGH output voltage Load current Leakage current VSLIC_L VSLIC_H Iload Ileakage 2.9 700 580 0 3 850 700 0.1 3.1 1000 820 V V A nA
Wireless Components
5-6
Specification, May 2003
TDA 5212
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V (continued) Parameter Symbol min CRYSTAL OSCILLATOR Signals CRSTL1, CRISTL 2, (PINS 1/28) 1 2 3 4 5 Operating frequency Input Impedance @ ~7.2MHz Input Impedance @ ~14.5MHz Serial Capacity @ ~7.2MHz Serial Capacity @ ~14.5MHz fCRSTL Z1-28 Z1-28 CS7=C1 CS14=C1 6
- 860 + j500 - 550 + j1050
Limit Values typ max
Unit
Test Conditions
L
Item
15
MHz W W pF pF
fundamental mode, series resonance
9.5 5.6
ASK/FSK Signal Switch Signal MSEL (PIN 15) 1 2 FSK Mode ASK Mode VMSEL VMSEL 1.4 0 4 0.2 V V or open
FSK DEMODULATOR 1 2 Demodulation Gain Useable IF Bandwidth GFMDEM BWIFPLL 180 10.2 200 10.7 220 11.2 V/ kHz MHz
POWER DOWN MODE Signal PDWN (PIN 27) 1 2 3 4 Powerdown Mode On Powerdown Mode Off Input bias current PDWN Start-up Time until valid IF signal is detected PWDNON PWDNOff IPDWN TSU 0 2.8 t.b.d. 1 0.8 VS V V A ms
note: startup - time is also dependent on data filter and data slicer time constants
PLL DIVIDER Signal CSEL (PIN 16) 1 fCRSTL range 7.xxMHz VCSEL 1.4 4 V or open
Wireless Components
5-7
Specification, May 2003
TDA 5212
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V (continued) Parameter Symbol min 2 3 fCRSTL range 14.xxMHz Input bias current CSEL Measured only in lab. VCSEL ICSEL 0 5 Limit Values typ max 0.2 V A CSEL tied to GND Unit Test Conditions L Item
Wireless Components
5-8
Specification, May 2003
TDA 5212
preliminary
Reference
5.2 Test Circuit
The device performance parameters marked with sured on an Infineon evaluation board.
in Section 5.1.3 were mea-
Infineon Technologies
TDA52xx Evaluation Board
Test_circuit.wmf
Figure 5-1
Schematic of the Evaluation Board
Wireless Components
5-9
Specification, May 2003
FILE: -10 V 2.0
TITLE:
DATE: Jul.19, 1999
TDA 5212
preliminary
Reference
5.3 Test Board Layouts
Figure 5-2
Top Side of the Evaluation Board
Figure 5-3
Bottom Side of the Evaluation Board
Wireless Components
5 - 10
Specification, May 2003
TDA 5212
preliminary
Reference
Figure 5-4
Component Placement on the Evaluation Board
Wireless Components
5 - 11
Specification, May 2003
TDA 5212
preliminary
Reference
5.4 Bill of Materials
The following components are necessary for evaluation of the TDA5212 at 915 MHz without use of a Microchip HCS515 decoder.
Table 5-4 Bill of Materials Ref R1 R2 R3 R4 R5 R6 L1 L2 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 Q1 Q2 X2, X3 X1, X4, S1, S5 S4 IC1 Value 100kW 100kW 820kW 240kW 360kW 10kW 3.3nH 3.9nH 1pF 3.3pF 4.7pF 100pF 47nF 3.3pF 100pF 22pF 100pF 10nF 10nF 220pF 47nF 470pF 47nF 8.2pF 18pF 14.129690MHz SFE10.7MA5-A 142-0701-801 STL_2POL STL_3POL TDA 5212 Specification 0805, 5% 0805, 5% 0805, 5% 0805, 5% 0805, 5% 0805, 5% Toko, PTL2012-F15N0G 0805,COG, 2% 0805, COG, 0.1pF 0805, COG, 0.1pF 0805, COG, 0.1pF 0805, COG, 5% 1206, X7R, 10% Toko, PTL2012-F15N0G 0805, COG, 5% 0805, COG, 5% 0805, COG, 5% 0805, X7R, 10% 0805, X7R, 10% 0805, COG, 5% 0805, X7R, 10% 0805, COG, 5% 0805, X7R, 10% 0805, COG, 1% 0805, COG, 0.25pF Jauch Q 14.129690-S1 Murata Johnson 2-pole pin connector 3-pole pin connector, or not equipped Infineon
Wireless Components
5 - 12
Specification, May 2003
TDA 5212
preliminary
Reference
The following components are necessary in addition to the above mentioned ones for evaluation of the TDA5212 in conjunction with a Microchip HCS515 decoder.
Table 5-5 Bill of Materials Addendum Ref R21 R22 R23 R24 R25 C21 C22 IC2 T1 D1 Value 22kW 10kW 22kW 820kW 560kW 100nF 100nF HCS512 BC 847B LS T670-JL Specification 0805, 5% 0805, 5% 0805, 5% 0805, 5% 0805, 5% 1206, X7R, 10% 1206, X7R, 10% Microchip Infineon Infineon
Wireless Components
5 - 13
Specification, May 2003
TDA 5212
preliminary
Reference
Wireless Components
5 - 14
Specification, May 2003
TDA 5212
preliminary
List of Figures
6
Figure 2-1 Figure 3-1 Figure 3-2 Figure 4-1 Figure 4-2 Figure 4-3 Figure 4-4 Figure 4-5 Figure 4-6 Figure 4-7 Figure 4-8 Figure 4-9
List of Figures
P-TSSOP-28-1 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LNA Automatic Gain Control Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RSSI Level and Permissive AGC Threshold Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Determination of Series Capacitance Value for the Crystal Oscillator . . . . . . . . . . . . . Data Slicer Threshold Generation with External R-C Integrator . . . . . . . . . . . . . . . . . . Data Slicer Threshold Generation Utilising the Peak Detector . . . . . . . . . . . . . . . . . . . ASK/FSK mode datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency characterstic in case of FSK mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency charcteristic in case of ASK mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 3-2 3-9 4-2 4-3 4-4 4-5 4-7 4-7 4-8 4-9 4-10 4-11 4-12 4-13 5-9 5-10 5-10 5-11
Figure 4-10 Principle of the precharge circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4-11 Voltage appearing on C2 during precharging process . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4-12 Voltage transient on capacitor C attached to pin 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 5-1 Figure 5-2 Figure 5-3 Figure 5-4 Schematic of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Top Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bottom Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Placement on the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wireless Components
List of Figures - i
Specification, May 2003
TDA 5212
preliminary
List of Tables
7
Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 5-1 Table 5-2 Table 5-3 Table 5-4 Table 5-5
List of Tables
Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CSEL Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSEL Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PDWN Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings, Ambient temperature TAMB=-40C ... + 85C . . . . . . . . . Operating Range, Ambient temperature TAMB= -40C ... + 85C . . . . . . . . . . . . . . . . . AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V . . . . . . . . . . . . . . . . . . . . . Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bill of Materials Addendum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-11 3-11 3-13 5-2 5-3 5-4 5-12 5-13
Wireless Components
List of Tables - i
Specification, May 2003

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