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DG534A/538A
Vishay Siliconix
4-/8-Channel Wideband Video Multiplexers
FEATURES
D Wide Bandwidth: 500 MHz D Very Low Crosstalk: -97 dB @ 5 MHz D On-Board TTL-Compatible Latches with Readback D Optional Negative Supply D Low rDS(on): 45 W D Single-Ended or Differential Operation D Latch-up Proof
BENEFITS
D D D D D D D Improved System Bandwidth Improved Channel Off-Isolation Simplified Logic Interfacing High-Speed Readback Allows Bipolar Signal Swings Reduced Insertion Loss Allows Differential Signal Switching
APPLICATIONS
D Wideband Signal Routing and Multiplexing D Video Switchers D ATE Systems D Infrared Imaging D Ultrasound Imaging
DESCRIPTION
The DG534A is a digitally selectable 4-channel or dual 2-channel multiplexer. The DG538A is an 8-channel or dual 4-channel multiplexer. On-chip TTL-compatible address decoding logic and latches with data readback are included to simplify the interface to a microprocessor data bus. The low on-resistance and low capacitance of the these devices make them ideal for wideband data multiplexing and video and audio signal routing in channel selectors and crosspoint arrays. An optional negative supply pin allows the handling of bipolar signals without dc biasing. The DG534A/DG538A are built on a D/CMOS process that combines n-channel DMOS switching FETs with low-power CMOS control logic, drivers and latches. The low-capacitance DMOS FETs are connected in a "T" configuration to achieve extremely high levels of off isolation. Crosstalk is reduced to -97 dB at 5 MHz by including a ground line between adjacent signal paths. An epitaxial layer prevents latch-up.
For more information refer to Vishay Siliconix applications note AN502.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG534ADJ
Dual-In-Line V+ GND DA V+ SA1 GND SA2 4/2 RS WR 1 2 3 4 5 6 7 8 Latches/Drivers 9 12 11 Top View EN A0 9 WR 10 11 12 13 EN I/O A1 A0 A1 10 20 NC 19 DB 18 V- 17 SB1 16 GND 15 SB2 14 VL 13 I/O SA1 GND SA2 4/2 RS 4 5 6 7 8 Latch/Drivers 18 SB1 17 GND 16 SB2 15 VL 14 NC
DG534ADN
PLCC GND DB DA V-
3
2
1
20 19
Top View
Document Number: 70069 S-05734--Rev. G, 29-Jan-02
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DG534A/538A
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG538ADJ
Dual-In-Line GND DA V+ SA1 GND SA2 GND SA3 GND 1 2 3 4 5 6 7 8 9 28 DB S A1 V+ 27 V- 26 SB1 25 GND 24 SB2 23 GND 22 SB3 21 GND 20 SB4 19 VL 18 I/O Latch/Drivers 17 EN 16 A0 15 A1 Top View GND SA2 GND SA3 GND SA4 8/4 5 6 7 8 9 10 11 Latch/Drivers 12 13 14 15 16 17 18 WR A2 RS EN I/O A1 A0 25 24 23 22 21 20 19 GND SB2 GND SB3 GND SB4 VL
DG538ADN
PLCC DA GND S B1 DB V-
4
3
2
1 28 27 26
SA4 10 8/4 11 RS 12 WR 13 A2 14
Top View
TRUTH TABLE
I/O
X X X 0 0 0 0 0 0 1
DG534A
4/2a
1 X X 0 0 0 0 1 1 Note c None (latches cleared) None SA1 SA2 SB1 SB2 SA1 and SB1 SA2 and SB2 DA and DB may be connected externally
A1
X X X 0 0 1 1 X X
A0
X X X 0 1 0 1 0 1 Note b
EN
X X 0 1 1 1 1 1 1
WR
X 0 0 0 0 0 0 0 1
RS
1 0 1 1 1 1 1 1 1 1
On Switch
Maintains previous state
Latches Transparent
Logic "0" = VAL v 0.8 V Logic "1" = VAH w 2.4 V X = Don't Care
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Document Number: 70069 S-05734--Rev. G, 29-Jan-02
DG534A/538A
Vishay Siliconix
TRUTH TABLE
I/O
X X X 0 0 0 0 0 0 0 0 0 0 0 0 1
DG538A
8/4a
1 X X 0 0 0 0 0 0 0 0 1 1 1 1 Note c Maintains previous state None (latches cleared) None SA1 SA2 SA3 SA4 SB1 SB2 SB3 SB4 SA1 and SB1 SA2 and SB2 SA3 and SB3 SA4 and SB4 DA and DB should be connected externally Latches Transparent
A2
X X X 0 0 0 0 1 1 1 1 X X X X
A1
X X X 0 0 1 1 0 0 1 1 0 0 1 1 Note b
A0
X X X 0 1 0 1 0 1 0 1 0 1 0 1
EN
X X 0 1 1 1 1 1 1 1 1 1 1 1 1
WR
X 0 0 0 0 0 0 0 0 0 0 0 0 0 1
RS
1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
On Switch
Logic "0" = VAL v 0.8 V Logic "1" = VAH w 2 V X = Don't Care Notes: a. Connect DA and DB together externally for single-ended operation. b. With I/O high, An and EN pins become outputs and reflect latch contents. See timing diagrams for more detail. c. 8/4 can be either "1" or "0" but should not change during these operations.
ORDERING INFORMATION
Temperature Range Package Part Number
DG534A
-40 to 85_C _ -55 to 125_C 20-Pin Plastic DIP 20-Pin PLCC 20-Pin Sidebraze DG534ADJ DG534ADN DG534AAP/883, 5962-906021MRC
DG538A
-40 to 85_C _ -55 to 125_C 28-Pin Plastic DIP 28-Pin PLCC 28-Pin Sidebraze DG538ADJ DG538ADN DG538AAP/883, 5962-8976001MXA
Document Number: 70069 S-05734--Rev. G, 29-Jan-02
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DG534A/538A
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +21 V V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +21 V V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10 V to +0.3 V VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to (V+) + 0.3 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V-) -0.3 V to (VL) + 0.3 V or 20 mA, whichever occurs first VS, VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V-) -0.3 V to (V-) + 14 V or 20 mA, whichever occurs first Current (any terminal) Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Current(S or D) Pulsed l ms 10% Duty . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA Storage Temperature (A Suffix) . . . . . . . . . . . . . . . . . . . -65 to 150_C (D Suffix) . . . . . . . . . . . . . . . . . . . -65 to 125_C
Power Dissipation (Package)a Plastic DIPb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 mW PLCCc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW Sidebrazed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200 mW Notes: a. All leads soldered or welded to PC board. b. Derate 8.3 mW/_C above 75_C. c. Derate 6 mW/_C above 75_C. d. Derate 16 mW/_C above 75_C.
SPECIFICATIONSa
Test Conditions Unless Otherwise Specified Parameter Analog Switch
Analog Signal Rangeg Drain-Source On-Resistance Resistance Match Between Channels Source Off Leakage Current Drain Off Leakage Current Drain On Leakage Current VANALOG rDS(on) DrDS(on) IS(off) ID(off) ID(on) V- = -5 V IS = -10 mA, VS = 0 V VAIL = 0.8 V, VAIH = 2 V Sequence Each Switch On VS = 8 V, VD = 0 V, EN = 0.8 V VS = 0 V, VD = 8 V, EN = 0.8 V VS = VD = 8 V Full Room Full Room Room Full Room Full Room Full 0.05 0.1 0.1 -5 -50 -20 -500 -20 -1000 45 -5 8 90 120 9 5 50 20 500 20 1000 -5 -50 -20 -100 -20 -200 -5 8 90 120 9 5 50 20 100 20 200 nA V
A Suffix
-55 to 125_C
D Suffix
-40 to 85_C
Symbol
V+ = 15 V, V- = -3 V, VL = 5 V WR = 0.8 V, RS, EN= 2 V
Tempb
Typc
Mind
Maxd
Mind
Maxd
Unit
W
Digital Control
Input Voltage High Input Voltage Low Address Input Current Address Output Current VAIH VAIL IAI IAO VAI = 0 V, or 2 V or 5 V VAO = 2.7 V VAO = 0.4 V Full Full Room Full Room Room -0.1 -21 3.5 2.5 -1 -10 2 0.8 1 10 -2.5 2.5 -1 -10 2 0.8 1 10 -2.5 mA V mA
Dynamic Characteristics
On State Input Capacitanceg Off State Input Capacitanceg Off State Output Capacitanceg Transition Time Break-Before-Make Interval EN, WR Turn On Time EN, Turn Off Time Charge Injection www.vishay.com PLCC CS(on) CS(off) See Figure 12 CD(off) tTRANS See Figure 4 tOPEN tON tOFF Qi See Figure 2 and 3 See Figure 2 See Figure 5 See Figure 11 DIP PLCC DIP PLCC DIP Room Room Room Room Room Room Room Full Room Full Room Full Room Full Room 28 31 3 4 6 8 160 80 150 105 -70 50 25 300 500 175 300 300 500 50 25 300 500 175 300 pC Document Number: 70069 S-05734--Rev. G, 29-Jan-02 ns 10 40 45 5 40 45 4 5 8 10 300 500 pF
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DG534A/538A
Vishay Siliconix
SPECIFICATIONSa
Test Conditions Unless Otherwise Specified Parameter Symbol
V+ = 15 V, V- = -3 V, VL = 5 V WR = 0.8 V, RS, EN= 2 V
A Suffix
-55 to 125_C
D Suffix
-40 to 85_C
Tempb
Typc
Mind
Maxd
Mind
Maxd
Unit
Dynamic Characteristics (Cont'd)
Chip Disabled Crosstalkf XTALK(CD) RL = 75 W , f = 5 MHz EN = 0.8 V See Figure 8 RIN = 10 W RL = 10 kW f = 5 MHz SeeFigure 9 RIN = 75 W , RL = 75 W f = 5 MHz See Figure 7 RIN = 10 W RL = 10 kW f = 5 MHz See Figure 7 RIN = 75 W , RL = 75 W f = 5 MHz See Figure 7 PLCC DIP PLCC DIP PLCC DIP PLCC DIP PLCC DIP Room Room Room Room Room Room Room Room Room Room Room Room Room -75 -65 -97 -87 -80 -70 -77 -72 -77 -72 -84 -84 500 MHz dB
Adjacent Input Crosstalkf
XTALK(AI)
All Hostile Crosstalk
XTALK(AH)
RIN = 10 W , RL = 10 kW f = 5 MHz, See Figure 10 Differential Crosstalk XTALK(DIFF) RIN = RL = 75 W f = 5 MHz, See Figure 10 RL = 50 W , See Figure 6
Bandwidth
BW
Power Supplies
Positive Supply Current Negative Supply Current Functional Check of Maximum Operating Supply Voltage Range Logic Supply Current I+ I- V+ to V- V- to GND V+ to GND IL Functional Test Only Any One Channel Selected with Address Inputs at GND or 5 V Room Full Room Full Full Full Full Full 150 0.6 0.6 -1.8 -2 10 -5.5 10 21 0 21 500 2 5 -1.8 -2 10 -5.5 10 21 0 21 500 mA V 2 5 mA
Timing
Reset to Write WR, RS Minimum Pulse Width A0, A1, EN Data Valid to Strobe A0, A1, EN Data Valid after Strobe Address Bus Tri-Statee Address Bus Output Address Bus Input tRW tMPW tDW See Figure 1 tWD tAZ tAO tAI Room Full Room Full Room Full Room Full Room Room Room -22 50 60 200 20 100 -20 50 25 95 110 50 100 ns 200 50
Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25_C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Defined by system bus requirements. f. Each individual pin shown as GND must be grounded. g. Guaranteed by design, not subject to production test.
Document Number: 70069 S-05734--Rev. G, 29-Jan-02
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DG534A/538A
Vishay Siliconix
CONTROL CIRCUITRY
SA1 SA2 SA3 SA4 DA DB SB1 SB2 SB3 SB4
SA1 - SA4 SB1 - SB4
V- DA, DB
V-
Decode
EN
A0
A0
A1
A1
A2
A2
V- Latch VREF 8/4 I/O Decode
VL V-
Tri-State Buffer
VREF * V+ I/O V- EN
VREF * VL A0
VREF
VREF
VREF
VREF
VREF
A1
A2
RS
WR
VL
*Typical all Readback (AX, EN) pins
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Document Number: 70069 S-05734--Rev. G, 29-Jan-02
DG534A/538A
Vishay Siliconix
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Supply Currents vs. Temperature
1.4 1.0 0.6 Current (mA) IL 0.2 -0.2 I- -0.6 -1.0 -1.4 -40 -20 0 20 40 60 80 100 120 Temperature (_C) 10 pA Leakage 1 nA ID(off) 100 pA IS(off) I+ V+ = 15 V V- = -3 V VL = 5 V 1 mA 100 nA 10 nA ID(on) V+ = 15 V V- = -3 V VL = 5 V
Leakage vs. Temperature
1 pA -40 -20 0 20 40 60 80 100 120
Temperature (_C)
Address, EN Output Current vs. Temperature
8 r DS(on) Drain-Source On-Resistance ( W ) - (Source) 0 VAO = 0.4 V 70
rDS(on) vs. V-, V+
VD = 0 V VL = 5 V IS = -10 mA
V+ = 10 V 60 V+ = 12 V 50 V+ = 15 V 40
Current (mA)
-8
-16 (Sink) -24
VAO = 2.7 V
V+ = 15 V V- = -3 V VL = 5 V
-32 -40 -20 0 20 40 60 80 100 120
30 -6 -5 -4 -3 -2 -1 0 Temperature (_C) V- - Negative Supply (V)
rDS(on) vs. VD and Temperature
200 r DS(on) Drain-Source On-Resistance ( W ) - 180 160 140 120 100 80 60 40 20 -2 0 2 4 6 8 10 -55_C -20 1 125_C 25_C V+ = 15 V V- = -3 V VL = 5 V IS = - 10 mA X TALK(AI) (dB) -100
Adjacent Input Crosstalk vs. Frequency
V+ = 15 V V- = -3 V VL = 5 V RIN = 10 W RL = 10 kW PLCC -60
DIP -80
-40
10 f - Frequency (MHz)
100
VD - Drain Voltage (V) Document Number: 70069 S-05734--Rev. G, 29-Jan-02
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DG534A/538A
Vishay Siliconix
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Adjacent Input Crosstalk vs. Frequency
-100 V+ = 15 V V- = -3 V VL = 5 V RIN = RL = 75 W X TALK(AI) (dB) -100
Adjacent Input Crosstalk vs. Frequency
-80 X TALK(AI) (dB)
-80
PLCC
-60
PLCC DIP
DIP -60
-40
-40
V+ = 15 V V- = -3 V VL = 5 V RIN = 10 W RL = 10 kW
-20 1 10 f - Frequency (MHz) 100
-20 1 10 f - Frequency (MHz) 100
All Hostile Crosstalk vs. Frequency
-100 -100
All Hostile Crosstalk vs. Frequency
-80 X TALK(AH) (dB) X TALK(AH) (dB) PLCC DIP -60
-80 PLCC -60 DIP
-40
V+ = 15 V V- = -3 V VL = 5 V RIN = 10 W RL = 10 kW
-40
V+ = 15 V V- = -3 V VL = 5 V RIN = RL = 75 W
-20 1 10 f - Frequency (MHz) 100
-20 1 10 f - Frequency (MHz) 100
Differential Crosstalk vs. Frequency
-100 -100
Differential Crosstalk vs. Frequency
PLCC -80 X TALK(DIFF) (dB) X TALK(DIFF) (dB) PLCC -80
-60
DIP
-60
DIP
-40
V+ = 15 V V- = -3 V VL = 5 V RIN = 10 W RL = 10 kW
-40
V+ = 15 V V- = -3 V VL = 5 V RIN = 75 W RL = 75 W
-20 1 10 f - Frequency (MHz) 100
-20 1 10 f - Frequency (MHz) 100
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Document Number: 70069 S-05734--Rev. G, 29-Jan-02
DG534A/538A
Vishay Siliconix
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Switching Times vs. Temperature
225 200 175 tON Time (ns) Time (ns) 150 125 100 tBBM 75 50 -40 -20 0 20 40 60 80 100 120 Temperature (_C) 100 75 -40 -20 0 20 40 60 80 100 120 Temperature (_C) tOFF 175 150 125 tTRANS 250 225 200
Transition Time vs. Temperature
OUTPUT TIMING REQUIREMENTS
3V 0V tDW 3V A0, A1, A2, EN Don't Care 0V Writing Data to Device Write Data Don't Care tWD tMPW
WR
WR
3V 0V 3V
A0, A1, A2, EN 0V RS 3V 0V
Don't Care
New Data
Don't Care
tMPW Delay Time Required after Reset before Write
tRW
WR
3V 0V 3V
A0, A1, A2, EN 0V 3V 0V
Driven Bus
Hi Z
Device Data* Out
Hi Z
Driven Bus
I/O
Reading Data From Device
tAZ
tAO
tAI
FIGURE 1.
Document Number: 70069 S-05734--Rev. G, 29-Jan-02
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DG534A/538A
Vishay Siliconix
TEST CIRCUITS
+15 V + 10 mF +5 V V+ VL A0 A1, A2 RS SBn SA1 - SBn-1 8/4, 4/2 WR DA EN I/O GND V- 1 kW + 10 mF -3 V 100 nF 45 pF 0V tON tOFF DB VO Switch Output VOUT 90% +1 V 0V Logic Input tr <20 ns tf <20 ns
100 nF
3V 50% EN
FIGURE 2. EN, CS, CS, Turn On/Off Time
+15 V
+ 10 mF +5 V V+ EN, VL, RS A1, A2 8/4, 4/2 I/O Address Logic A0 WR GND V- DA DB SA1 SA2 - SBn
100 nF
Logic Input tr <20 ns tf <20 ns WR +3 V 0V +3 V 0V tON(WR) VOUT 90%
+1 V A0
VO
1 kW Logic Input -3 V + 10 mF 100 nF
45 pF
FIGURE 3. WR, Turn On Time
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Document Number: 70069 S-05734--Rev. G, 29-Jan-02
DG534A/538A
Vishay Siliconix
TEST CIRCUITS
+15 V
+ 10 mF +5 V V+ EN VL RS A0, A1, A2 8/4 or GND 4/2 DA DB I/O V- SA1 SB1 SA2 - SBn
100 nF
Logic Input tr <20 ns tf <20 ns 3V 0V 50% 90% S1 Turning Off BBM Interval VO Transition Time (tTRANS) VOUT S16 Turning On A0, A1, A2
+1 V
Logic Input
WR
1 kW + 10 mF -3 V 100 nF
45 pF
FIGURE 4. Transition Time and Break-Before-Make Interval
+15 V
+5 V
+ 10 mF VL A0, A1, A2, RS SBn EN DA WR I/O V- V+
100 nF
EN DB VO CL = 1000 pF VOUT DVOUT
8/4 or GND 4/2
DVOUT is the measured voltage error due to charge injection. The charge injection in Coulombs is Q = CL x DVOUT + 10 mF 100 nF
-3 V
FIGURE 5. Charge Injection
Document Number: 70069 S-05734--Rev. G, 29-Jan-02 www.vishay.com
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DG534A/538A
Vishay Siliconix
TEST CIRCUITS
+5 V +15 V + 10 mF VL EN 8/4, 4/2 RS DA VIN SA1 I/O GND WR A0 to A2 50 W VO SA2 - SBn V+
100 nF
V-
+ 10 mF -3 V
100 nF
FIGURE 6. Bandwidth
8/4 or 4/2 = Logic "0" DA RIN SAn VOUT All Channels Off SA1 SAn VOUT SB1 SBn DB RL SB1 SBn DB RL 75 W DA
SA1
X TALK(AH) + 20 log10 Note: SA1 on or any other one channel on.
V OUT V X TALK(CD) + 20 log10 V OUT V
FIGURE 7. All Hostile Crosstalk
FIGURE 8. Chip Disabled Crosstalk
RIN 10 W VSn-1 Sn-1 VSn Sn VSn+1 RIN 10 W Sn+1 RL 10 kW SB1 SBn
V
Channels SA1 and SB1 On 4/2 = Logic "1" SA1 DA RIN SAn RL DB RL Signal Generator X TALK(DIFF) + 20 log 10 V OUT V VOUT
X TALK(AI) + 20 log10
V Sn - 1 V Sn
or 20 log 10
V Sn ) 1 V Sn
FIGURE 9. Adjacent Input Crosstalk
FIGURE 10. Differential Crosstalk
Document Number: 70069 S-05734--Rev. G, 29-Jan-02
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DG534A/538A
Vishay Siliconix
TEST CIRCUITS
+15 V +5 V V+ VL RS EN A0 A1 A2 8/4 or 4/2 GND I/O WR SA1 SAn SB1 SBn Meter HP4192A Impedance Analyzer or Equivalent DA DB +5 V V+ VL RS 8/4 or 4/2 SA1 SA2 DA DB SB1 SB2 Meter HP4192A Impedance Analyzer or Equivalent +15 V
V-
GND I/O WR
EN
V-
-3 V
-3 V
FIGURE 11. On State Input Capacitance
FIGURE 12. Off State Input/Output Capacitance
OPERATING VOLTAGE RANGE
22 21 20 19 18 17 16 15 Allowable Operating Voltage Area (Note b) 14 13 12 11 10 Positive Supply Voltage V+ (Volts)
-5.5 -5
-4
-3
-2
-1
0
Negative Supply Voltage V- (Volts) Notes: a. Both V+ and V- must have decoupling capacitors mounted as close as possible to the device pins. Typical decoupling capacitors would be 10-mF tantalum bead in parallel with 100-nF ceramic disc. b. Production tested with V+ = 15 V and V- = -3 V. a. For VL = 5 V "10%, 0.8- or 2-V TTL compatibility is maintained over the entire operating voltage range.
FIGURE 13.
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Vishay Siliconix
PIN DESCRIPTION
Pin Number Symbol
DA V+ SA1 SA2 SA3 SA4 4/2 8/4 RS WR A0, A1, A2 EN I/O VL SB4 SB3 SB2 SB1 V- DB GND
DG534ADJ
2 3 4 6 - - 7 - 8 9 11, 10, - 12 13 14 - - 15 17 18 19 1, 5, 16
DG538A
2 3 4 6 8 10 - 11 12 13 16, 15, 14 17 18 19 20 22 24 26 27 28 1, 5, 7, 9, 21, 23, 25 Analog Output/Input Positive Supply Voltage Analog Input/Output Analog Input/Output Analog Input/Output Analog Input/Output 4 x 1 or 2 x 2 Select 8 x 1 or 4 x 2 Select Reset Write command that latches A, EN
Description
Binary address inputs that determine which channel(s) is/are connected to the output(s) Enable. Input/Output, if EN = 0, all channels are open Input/Output control. Used to write to or read from the address latches Logic Supply Voltage, usually +5 V Analog Input/Output Analog Input/Output Analog Input/Output Analog Input/Output Negative Supply Voltage Analog Output/Input Analog and Digital Grounds. All grounds should be connected externally to optimize dynamic performance
APPLICATIONS
Device Description The DG534A/DG538A are improved pin-compatible replacements for the non-A versions. Improvements include: higher current readback drivers, readback of the EN bit, latchup protection
The DG534A/538A D/CMOS wideband multiplexers offer single-ended or differential functions. A 8/4 or 4/2 logic input pin selects the single-ended or differential mode.
Frequency Response To meet the high dynamic performance demands of video, high definition TV, digital data routing (in excess of 100 Mbps), etc., the DG534A/538A are fabricated with DMOS transistors configured in `T' arrangements with second level `L' configurations (see Functional Block Diagram).
Use of DMOS technology yields devices with very low capacitance and low rDS(on). This directly relates to improved high frequency signal handling and higher switching speeds, while maintaining low insertion loss figures. The `T' and `L' switch configurations further improve dynamic performance by greatly reducing crosstalk and output node capacitances.
A single multiplexer on-channel exhibits both resistance [rDS(on)] and capacitance [CS(on)]. This RC combination causes a frequency dependent attenuation of the analog signal. The -3-dB bandwidth of the DG534A/538A is typically 500 MHz (into 50 W). This figure of 500 MHz illustrates that the switch-channel cannot be represented by a simple RC combination. The on capacitance of the channel is distributed along the on-resistance, and hence becomes a more complex multi-stage network of R's and C's making up the total rDS(on) and CS(on).
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Document Number: 70069 S-05734--Rev. G, 29-Jan-02
DG534A/538A
Vishay Siliconix
APPLICATIONS (CONT'D)
Power Supplies and Decoupling A useful feature of the DG534A/538A is its power supply flexibility. It can be operated from unipolar supplies (V- connected to 0 V) if required. Allowable operating voltage ranges are shown in Figure 13. Note that the analog signal must not go below V- by more than 0.3 V (see absolute maximum ratings). However, the addition of a V- pin has a number of advantages: a. It allows flexibility in analog signal handling, i.e. with V- = -5 V and V+ = 15 V, up to "5 V ac signals can be accepted. The value of on capacitance (CS(on)) may be reduced by increasing the reverse bias across the internal FET body to source junction. V+ has no effect on CS(on). It is useful to note that tests indicate that optimum video differential phase and gain occur when V- is -3 V. c. V- eliminates the need to bias an ac analog signal using potential dividers and large decoupling capacitors.
SA1 SA2 SB1 SB2 GND V- C1 + C2 C2
a.
Use extensive ground planes on double sided PCB separating adjacent signal paths. Multilayer PCB is even better. Keep signal paths as short as practically possible with all channel paths of near equal length. Use strip-line layout techniques.
b. c.
Improvements in performance can be obtained by using PLCC parts instead of DIPs. The stray effects of the quad PLCC package are lower than those of the dual-in-line packages. Sockets for the PLCC packages usually increase crosstalk.
+5 V 51 W + C1 VL
+15 V 51 W + C1 V+
b.
C2
DA
It is established rf design practice to incorporate sufficient bypass capacitors in the circuit to decouple the power supplies to all active devices in the circuit. The dynamic performance of the DG534/538 is adversely affected by poor decoupling of power supply pins. Also, since the substrate of the device is connected to the negative supply, proper decoupling of this pin is essential. Rules: a. b. c. Decoupling capacitors should be incorporated on all power supply pins (V+, V-, VL). They should be mounted as close as possible to the device pins. Capacitors should have good frequency characteristics tantalum bead and/or ceramic disc types are suitable. Recommended decoupling capacitors are 1- to 10-mF tantalum bead, in parallel with 100-nF ceramic or polyester. Additional high frequency protection may be provided by 51-W carbon film resistors connected in series with the power supply pins (see Figure 14).
DG534A
DB
51 W C1 = 1 mF Tantalum C2 = 100 nF Polyester
-3 V
FIGURE 14. DG534A Power Supply Decoupling
Interfacing Logic interfacing is easily accomplished. Comprehensive addressing and control functions are incorporated in the design. The VL pin permits interface to various logic types. The device is primarily designed to be TTL or CMOS logic compatible with +5 V applied to VL. The actual logic threshold can be raised simply by increasing VL.
d.
Board Layout PCB layout rules for good high frequency performance must also be observed to achieve the performance boasted by the DG534A/538A. Some tips for minimizing stray effects are:
Document Number: 70069 S-05734--Rev. G, 29-Jan-02
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DG534A/538A
Vishay Siliconix
APPLICATIONS (CONT'D)
A typical switching threshold versus VL is shown in Figure 15. These devices feature an address readback (Tally) facility, whereby the last address written to the device may be output to the system. This allows improved status monitoring and hand shaking without additional external components. Channel address data can only be entered during WR low, when the address latches are transparent and I/O is low. Similarly, address readback is only operational when WR and I/O are high.
The Siliconix CLC410 Video amplifier is recommended as an output buffer to reduce insertion loss and to drive coaxial cables. For low power video routing applications or for unity gain input buffers CLC111/CLC114 are recommended.
This function is controlled by the I/O pin, which directly addresses the tri-state buffers connected to the EN and address pins. EN and address pins can be assigned to accept data (when I/O = 0; WR = 0; RS = 1), or output data (when I/O = 1; WR = 1; RS = 1), or to reflect a high impedance and latched state (when I/O = 0; WR = 1; RS = 1). When I/O is high, the address output can sink or source current. Note that VL is the logic high output condition. This point must be respected if VL is varied for input logic threshold shifting. Further control pins facilitate easy microprocessor interface. On chip address, data latches are activated by WR, which serves as a strobe type function eliminating the need for peripheral latch or memory I/O port devices. Also, for ease of interface, a direct reset function (RS) allows all latches to be cleared and switches opened. Reset should be used during power up, etc., to avoid spurious switch action. See Figure 16.
8 7 6 5 Vth (V) 4 3 2 1 0 0 2 4 6 8 10 VL (V) 12 14 16 18
FIGURE 15.
Switching Threshold Voltage vs. VL
DG534A
SA1 SB2 A0, A1 EN RS Data Bus Reset WR Address Bus WR DB 75 W CLC410 75 W DA AV = 2 CLC410
DG534A
SA1 SB2 A0, A1 EN RS WR CLC410 75 W DA
Address Decoder
I/O
CLC410 DB 75 W
Video Bus
Data Bus
FIGURE 16.
DG534A in a Video Matrix
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Document Number: 70069 S-05734--Rev. G, 29-Jan-02

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