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GALVANTECH, INC.
GVT7164D64 64K X 64 SYNCHRONOUS BURST SRAM
SYNCHRONOUS BURST SRAM PIPELINED OUTPUT
FEATURES
* * * * * * * * * * * * * * * * * * * * Fast access times: 5, 6, and 7ns Fast clock speed: 100, 83, and 66 MHz Provide high performance 3-1-1-1 access rate Fast OE# access times: 5, 6, and 7ns Optimal for depth expansion (one cycle chip deselect to eliminate bus contention) 3.3V -5% and +10% core power supply, 2.5V or 3.3V I/O supply 5V tolerant inputs except I/O's Clamp diodes to VSS at all inputs and outputs Common data inputs and data outputs BYTE WRITE ENABLE and GLOBAL WRITE control Four chip enables for depth expansion and one chip enable for address pipeline Address, control, input, and output pipeline registers Internally self-timed WRITE CYCLE Burst sequence control pins MODE (interleaved or linear burst sequence) Automatic power-down for portable applications ZZ pin for snooze control High density, high speed packages High 30pF output drive capability at rated access time
64K x 64 SRAM
+3.3V SUPPLY,FULLY REGISTERED INPUTS AND OUTPUTS, BURST COUNTER
GENERAL DESCRIPTION
The Galvantech Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. The GVT7164D64 SRAM integrates 65,536x64 SRAM cells with advanced synchronous peripheral circuitry and a 2bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edgetriggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE#), depth-expansion chip enables (CE2#, CE3#, CE2 and CE3), burst control inputs (ADSC#, ADSP#, and ADV#), write enables (BW1# to BW8#,and BWE#), and global write (GW#). Asynchronous inputs include the output enable (OE#) and burst mode control (MODE). The data outputs (Q), enabled by OE#, are also asynchronous. Addresses and chip enables are registered with either address status processor (ADSP#) or address status controller (ADSC#) input pins. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV#). Address, data inputs, and write controls are registered onchip to initiate self-timed WRITE cycle. WRITE cycles can be one to eight bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. BW1# controls DQ1-DQ8. BW2# controls DQ9DQ16. BW3# controls DQ17-DQ24. BW4# controls DQ25DQ32. BW5# controls DQ33-DQ40. BW6# controls DQ41DQ48. BW7# controls DQ49-DQ56. BW8# controls DQ57DQ64. BW1#, BW2#, BW3#, BW4#, BW5#, BW6#, BW7#, and BW8# can be active only with BWE# being LOW. GW# being LOW causes all bytes to be written. The GVT7164D64 operates from a +3.3V power supply. All inputs and outputs are TTL-compatible. The device is ideally suited for 486, PentiumTM, 680x0, and PowerPCTM systems and for systems that are benefited from a wide synchronous data bus.
OPTIONS
Timing 5ns access/10ns cycle 6ns access/12ns cycle 7ns access/15ns cycle Package 128-pin PQFP 128-pin TQFP
MARKING
-5 -6 -7 Q T
*
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051 Tel (408) 566-0688 Fax (408) 566-0699
Rev. 3/20/98
Pentium is a trademark of Intel Corporation. PowerPC is a trademark of IBM Corporation. Galvantech, Inc. reserves the right to change products or specifications without notice.
GALVANTECH, INC.
FUNCTIONAL BLOCK DIAGRAM
GVT7164D64 64K X 64 SYNCHRONOUS BURST SRAM
BYTE 1 WRITE
BW1# BWE# CLK
D
Q
BYTE 2 WRITE
BW2#
D
Q
BYTE 7 WRITE
BW7#
D
Q
BYTE 8 WRITE
BW8# GW# * CE3# * CE3 * CE2# * CE2 CE# * ZZ OE#
D
Q
byte 8 write byte 7 write byte 2 write byte 1 write DQ1-DQ64
ENABLE
D
Power Down Logic
Q
D
Q
ADSP# A15-A2 ADSC# CLR ADV# A1-A0 * MODE Binary Counter & Logic Address Register
Input Register
64K x 8 x 8 SRAM Array
D
Q
NOTE:
The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
March 20, 1998
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Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 3/20/98
Output Buffers
OUTPUT REGISTER
GALVANTECH, INC.
GVT7164D64 64K X 64 SYNCHRONOUS BURST SRAM
PIN ASSIGNMENT (Top View)
VCCQ CE3 CE2 CE3# CE2# VSS VCC CE# BW8# BW7# BW6# BW5# OE# CLK BWE# GW# BW4# BW3# VSS VCC BW2# BW1# ADSC# ADSP# ADV# VSSQ
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
VSSQ DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 VCCQ VSSQ DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 VCCQ VSSQ DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ64 VCCQ
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86
128-pin QFP
85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
VCCQ DQ32 DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 DQ23 DQ22 VSSQ VCCQ DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 DQ15 DQ14 DQ13 DQ12 VSSQ VCCQ DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 VSSQ
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
PIN DESCRIPTIONS
GVT7164D64 PINS
62, 61, 60, 57, 56, 55, 54, 53, 51, 50, 49, 48, 47, 44, 43, 42
SYMBOL
A0-A15
TYPE
InputSynchronous
107, 108, 111, BW1#, BW2#, 112, 117, 118, 119, BW3#, BW4#, 120 BW5#, BW6#, BW7#, BW8#
InputSynchronous
114 113
BWE# GW#
InputSynchronous
InputSynchronous
115
CLK
InputSynchronous
121
CE#
InputSynchronous
March 20, 1998
Rev. 3/20/98
VSSQ NC MODE A15 A14 A13 VCC VSS A12 A11 A10 A9 A8 NC A7 A6 A5 A4 A3 VCC VSS A2 A1 A0 ZZ VCCQ
DESCRIPTION
Addresses: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. The burst counter generates internal addresses associated with A0 and A1, during burst cycle and wait cycle. Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ cycle. BW1# controls DQ1-DQ8. BW2# controls DQ9-DQ16. BW3# controls DQ17-DQ24. BW4# controls DQ25-DQ32. BW5# controls DQ33-DQ40. BW6# controls DQ41-DQ48. BW7# controls DQ49-DQ56. BW8# controls DQ57-DQ64. Data I/O are high impedance if either of these inputs are LOW, conditioned by BWE# being LOW. Write Enable: This active LOW input gates byte write operations and must meet the setup and hold times around the rising edge of CLK. Global Write: This active LOW input allows a full 64-bit WRITE to occur independent of the BWE# and BWn# lines and must meet the setup and hold times around the rising edge of CLK. Clock: This signal registers the addresses, data, chip enables, write control and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. Chip Enable: This active LOW input is used to enable the device and to gate ADSP#.
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Galvantech, Inc. reserves the right to change products or specifications without notice.
GALVANTECH, INC.
PIN DESCRIPTIONS (continued)
GVT7164D64 PINS
124, 125 126, 127 116 104
GVT7164D64 64K X 64 SYNCHRONOUS BURST SRAM
SYMBOL
CE2#, CE3# CE2, CE3 OE# ADV#
TYPE
InputSynchronous
DESCRIPTION
Chip Enable: This active LOW input is used to enable the device. Chip enable: This active HIGH input is used to enable the device. Output Enable: This active LOW asynchronous input enables the data Address Advance: This active LOW input is used to control the internal burst counter. A HIGH on this pin generates wait cycle (no address advance). Address Status Processor: This active LOW input, along with CE# being LOW, causes a new external address to be registered and a READ cycle is initiated using the new address. Address Status Controller: This active LOW input causes device to be de-selected or selected along with new external address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs. Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR BURST. A NC or HIGH on this pin selects INTERLEAVED BURST. Snooze: This active HIGH input puts the device in low power either LOW or NC (No Connect).
InputSynchronous
InputInputSynchronous
Asynchronous output drivers.
105
ADSP#
InputSynchronous
106
ADSC#
InputSynchronous
41
MODE
InputStatic Input-
63
ZZ
Asynchronous consumption standby mode. For normal operation, this input has to be
66-76, 79-88, 91-101, 2-12, 15-24, 27-37
DQ1-DQ64
Input/ Output
Data Inputs/Outputs: First Byte is DQ1-DQ8. Second Byte is DQ9DQ16. Third Byte is DQ17-DQ24. Fourth Byte is DQ25-DQ32. Fifth Byte is DQ33-DQ40. Sixth Byte is DQ41-DQ48. Seventh Byte is DQ49DQ56. eighth Byte is DQ57-DQ64. Input data must meet setup and hold times around the rising edge of CLK. Power Supply: +3.3V -5% to +10%. Ground: GND Output Buffer Supply: +2.5V or 3.3V Output Buffer Ground: GND No Connect: These signals are not internally connected.
45, 58, 109, 122 46, 59, 110, 123 13, 25, 38, 64, 77, 89, 102 1, 14, 26, 39, 65, 78, 90, 103 40, 52
VCC VSS VCCQ VSSQ NC
Supply Ground I/O Supply I/O Ground -
BURST ADDRESS TABLE (MODE = NC/VCC)
First Address (external)
A...A00 A...A01 A...A10 A...A11
Second Address (internal)
A...A01 A...A00 A...A11 A...A10
Third Address (internal)
A...A10 A...A11 A...A00 A...A01
Fourth Address (internal)
A...A11 A...A10 A...A01 A...A00
BURST ADDRESS TABLE (MODE = GND)
First Address (external)
A...A00 A...A01 A...A10 A...A11
Second Address (internal)
A...A01 A...A10 A...A11 A...A00
Third Address (internal)
A...A10 A...A11 A...A00 A...A01
Fourth Address (internal)
A...A11 A...A00 A...A01 A...A10
March 20, 1998
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Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 3/20/98
GALVANTECH, INC.
TRUTH TABLE
OPERATION ADDRESS USED CE#
GVT7164D64 64K X 64 SYNCHRONOUS BURST SRAM
ADSP# ADSC#
ADV#
WRITE#
OE#
CLK
DQ
Deselected Cycle, Power Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst
None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current
H L L L L L X X H H X H X X H H X H
X L L H H H H H X X H X H H X X H X
L X X L L L H H H H H H H H H H H H
X X X X X X L L L L L L H H H H H H
X X X L H H H H H H L L H H H H L L
X L H X L H L H L H X X L H L H X X
L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H
High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D
Note:
1.
2.
3. 4. 5. 6. 7.
X means "don't care." H means logic HIGH. L means logic LOW. WRITE# = L means [BWE# + BW1#*BW2#*BW3#*BW4#*BW5#*BW6#*BW7#*BW8#]*GW# equals LOW. WRITE# = H means [BWE# + BW1#*BW2#*BW3#*BW4#*BW5#*BW6#*BW7#*BW8#]*GW# equals HIGH. BW1# enables write to DQ1-DQ8. BW2# enables write to DQ9-DQ16. BW3# enables write to DQ17-DQ24. BW4# enables write to DQ25-DQ32. BW5# enables write to DQ33-DQ40. BW6# enables write to DQ41-DQ48. BW7# enables write to DQ49-DQ56. BW8# enables write to DQ57-DQ64. All inputs except OE# must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. Suspending burst generates wait cycle. For a write operation following a read operation, OE# must be HIGH before the input data required setup time plus High-Z time for OE# and staying HIGH throughout the input data hold time. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. ADSP# LOW along with chip being selected always initiates an READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE# LOW for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.
PARTIAL TRUTH TABLE FOR READ/WRITE
FUNCTION READ READ WRITE one byte (Byte 1) WRITE one byte (Byte 8) WRITE two bytes (Byte 2 & 4) WRITE all bytes WRITE all bytes GW# H H H H H H L BWE# H X L L L L X BW1# X H L H H L X BW2# X H H H L L X BW3# X H H H H L X BW4# X H H H L L X BW5# X H H H H L X BW6# X H H H H L X BW7# X H H H H L X BW8# X H H L H L X
March 20, 1998
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Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 3/20/98
GALVANTECH, INC.
ABSOLUTE MAXIMUM RATINGS*
GVT7164D64 64K X 64 SYNCHRONOUS BURST SRAM
*Stresses greater than those listed uunder "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Voltage on VCC Supply Relative to VSS........-0.5V to +4.6V VIN .....................................................................-0.5V to +6V Storage Temperature (plastic) .......................-55oC to +150o Junction Temperature ....................................................+150o Power Dissipation ...........................................................1.6W Short Circuit Output Current ......................................100mA
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(0oC Ta
70C; VCC = 3.3V -5 to +10% unless otherwise noted)
CONDITIONS
Data Inputs (DQxx) All Other Inputs
DESCRIPTION
Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage I/O Supply Voltage
SYMBOL
VIHD VIH VIl ILI ILO VOH VOL VCC VCCQ
MIN
2.0 2.0 -0.3 -2 -2 2.4
MAX
VCCQ+0.3 4.6 0.8 2 2
UNITS
V V V uA uA V
NOTES
1,2 1,2 1, 2 14
0V < VIN < VCC Output(s) disabled, 0V < VOUT < VCC IOH = -4.0mA IOL = 8.0mA
1, 11 1, 11 1 1
0.4 3.1 2.375 3.6 VCC
V V V
DESCRIPTION
Power Supply Current: Operating CMOS Standby
CONDITIONS
Device selected; all inputs < VILor > VIH;cycle time > tKC MIN; VCC =MAX; outputs open Device deselected; VCC = MAX; all inputs < VSS +0.2 or >VCC -0.2; all inputs static; CLK frequency = 0 Device deselected; all inputs < VIL or > VIH ; all inputs static; VCC = MAX; CLK frequency = 0 Device deselected; all inputs < VIL or > VIH; VCC = MAX; CLK cycle time > tKC MIN
SYM
Icc
TYP
200
-5
320
-6
280
-7
240
UNITS NOTES
mA 3, 12, 13 12,13
ISB2
0.4
4
4
4
mA
TTL Standby
ISB3
8
18
18
18
mA
12,13
Clock Running
ISB4
50
95
85
75
mA
12,13
CAPACITANCE
DESCRIPTION
Input Capacitance Input/Output Capacitance (DQ)
CONDITIONS
TA = 25oC; f = 1 MHz VCC = 3.3V
SYMBOL
CI CO
TYP
3 6
MAX
4 7
UNITS
pF pF
NOTES
4 4
March 20, 1998
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Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 3/20/98
GALVANTECH, INC.
AC ELECTRICAL CHARACTERISTICS
(Note 5) (0oC
GVT7164D64 64K X 64 SYNCHRONOUS BURST SRAM
TA 70oC; VCC = 3.3V -5 to +10%)
-5*
SYM
tKC tKH tKL tKQ tKQX tKQLZ tKQHZ tOEQ tOELZ tOEHZ tS tH
DESCRIPTION
Clock Clock cycle time Clock HIGH time Clock LOW time Output Times Clock to output valid Clock to output invalid Clock to output in Low-Z Clock to output in High-Z OE to output valid OE to output in Low-Z OE to output in High-Z Setup Times Address, Controls and Data In Hold Times Address, Controls and Data In
-6
MAX MIN MAX MIN
-7
MAN UNITS NOTES
MIN
10 4 4 5 2 3 5 5 0 4 2.5 0.5
12 4 4 6 2 3 5 6 0 5 2.5 0.5
15 5 5 7 2 3 6 7 0 6 2.5 0.5
ns ns ns ns ns ns ns ns ns ns ns ns 6,7 6,7 9 6,7 6,7 10 10
CAPACITANCE DERATING
DESCRIPTION
Clock to output valid
SYMBOL
tKQ
TYP
0.016
MAX
UNITS
ns / pF
NOTES
15
THERMAL CONSIDERATION
DESCRIPTION
Thermal Resistance - Junction to Ambient Thermal Resistance - Junction to Case
CONDITIONS
Still air, soldered on 4.25 x 1.125 inch 4-layer PCB
SYMBOL
JA JC
TQFP TYP
20 1
UNITS
oC/W oC/W
NOTES
March 20, 1998
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Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 3/20/98
GALVANTECH, INC.
AC TEST CONDITIONS Input pulse levels Input rise and fall times Input timing reference levels Output reference levels Output load 0V to 3.0V 1.5ns 1.5V 1.5V See Figures 1 and 2
GVT7164D64 64K X 64 SYNCHRONOUS BURST SRAM
OUTPUT LOADS
DQ Z0 = 50 50 Vt = 1.5V Fig. 1 OUTPUT LOAD EQUIVALENT 3.3v 317 DQ 351 5 pF 30 pF
Fig. 2 OUTPUT LOAD EQUIVALENT
NOTES
1. 2. 3. 4. 5. 6. 7. 8. All voltages referenced to VSS (GND). Overshoot: Undershoot: VIH +6.0V for t tKC /2. VIL -2.0V for t tKC /2
15. Capacitance derating applies to capacitance different from the load capacitance shown in Fig. 1.
Icc is given with no output current. Icc increases with greater output loading and faster cycle times. This parameter is sampled. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. Output loading is specified with CL=5pF as in Fig. 2. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ. A READ cycle is defined by byte write enables all HIGH or ADSP# LOW along with chip enables being active for the required setup and hold times. A WRITE cycle is defined by at one byte or all byte WRITE per READ/WRITE TRUTH TABLE. OE# is a "don't care" when a byte write enable is sampled LOW.
9.
10. This is a synchronous device. All synchronous inputs must meet specified setup and hold time, except for "don't care" as defined in the truth table. 11. AC I/O curves are available upon request. 12. "Device Deselected" means the device is in POWER -DOWN mode as defined in the truth table. "Device Selected" means the device is active. 13. Typical values are measured at 3.3V, 25oC and 20ns cycle time. 14. MODE pin has an internal pull-up and ZZ pin has an internal pull-down. These two pins exhibit an input leakage current of +30 A.
March 20, 1998
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Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 3/20/98
GALVANTECH, INC.
t
GVT7164D64 64K X 64 SYNCHRONOUS BURST SRAM
READ TIMING
KC
t
KL
CLK
t
S
t
KH
ADSP#
t
H
ADSC#
t
S
ADDRESS BW1# to BW8#, BWE#, GW# CE# (See Note)
A1
t
A2
H
t
S
ADV#
t
H
OE#
tKQ t t
OEQ Q(A2)
t
KQ Q(A2+1) Q(A2+2) Q(A2+3) Q(A2) Q(A2+1)
KQLZ
DQ
OELZ Q(A1)
t
SINGLE READ
BURST READ
Note: CE# active in this timing diagram means that all chip enables CE#, CE2#, CE3#, CE2, and CE3 are active.
March 20, 1998
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Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 3/20/98
GALVANTECH, INC.
GVT7164D64 64K X 64 SYNCHRONOUS BURST SRAM
WRITE TIMING
CLK
t
S
ADSP#
t
H
ADSC#
t
S
ADDRESS BW1# to BW8#, BWE# GW# CE# (See Note)
A1
tH
A2
A3
tS
ADV#
t
H
OE#
tOEHZ t
KQX Q D(A1) D(A2) D(A2+1) D(A2+1) D(A2+2) D(A2+3) D(A3) D(A3+1) D(A3+2)
DQ
SINGLE WRITE
BURST WRITE
BURST WRITE
Note: CE# active in this timing diagram means that all chip enables CE#, CE2#, CE3#, CE2, and CE3 are active.
March 20, 1998
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Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 3/20/98
GALVANTECH, INC.
CLK
t
GVT7164D64 64K X 64 SYNCHRONOUS BURST SRAM
READ/WRITE TIMING
S
ADSP#
t
H
ADSC#
t
S
ADDRESS BW1# to BW8#, BWE#, GW# CE# (See Note) ADV#
A1
A2
t
A3
H
A4
A5
OE#
DQ
Q(A1) Single Reads
Q(A2)
D(A3) Single Write
Q(A3) Pass Through
Q(A4)
Q(A4+1) Burst Read
Q(A4+2)
D(A5)
D(A5+1)
Burst Write
Note: CE# active in this timing diagram means that all chip enables CE#, CE2#, CE3#, CE2, and CE3 are active.
March 20, 1998
11
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 3/20/98
GALVANTECH, INC.
GVT7164D64 64K X 64 SYNCHRONOUS BURST SRAM
100 Pin PQFP, 128 Pin PQFP, and 128 Pin TQFP Package Dimension
E E1
#1
D1
D
A2
A
e
b
L
Package No. of Leads Symbol
D D1 E E1 A A2 L b e
PQFP MIN
22.90 19.90 16.90 13.90 2.80 2.55 0.73 0.17
TQFP MAX
23.50 20.10 17.50 14.10 3.40 3.05 1.03 0.27
128 NOM
23.20 20.00 17.20 14.00 3.10 2.80 0.88 0.20 0.50 Basic
MIN
21.90 19.90 15.90 13.90 1.40 1.35 0.45 0.17
128 NOM
22.00 20.00 16.00 14.00 1.50 1.40 0.60 0.20 0.50 Basic
MAX
22.10 20.10 16.10 14.10 1.60 1.45 0.75 0.27
Note: All dimensions are in Millimeters.
March 20, 1998
12
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 3/20/98
GALVANTECH, INC.
Ordering Information
GVT7164D64 64K X 64 SYNCHRONOUS BURST SRAM
GVT 7164D64 X - X
Galvantech Prefix Part Number Speed (5 =5ns access/10ns cycle 6 = 6ns access/12ns cycle 7 = 7ns access/15ns cycle) Package (Q = 128 PIN PQFP, T = 128 PIN TQFP)
March 20, 1998
13
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 3/20/98

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