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256Mb F-die DDR2 SDRAM
DDR2 SDRAM
256Mb F-die DDR2 SDRAM Specification Version 1.5
February 2005
Page 1 of 27
Rev. 1.5 Feb. 2005
256Mb F-die DDR2 SDRAM Contents
DDR2 SDRAM
0. Ordering Information
1. Key Feature 2. Package Pinout/Mechnical Dimension & Addressing
2.1 Package Pintout & Mechnical Dimension 2.2 Input/Output Function Description 2.3 Addressing
3. Absolute Maximum Rating
4. AC & DC Operating Conditions & Specifications
Page 2 of 27
Rev. 1.5 Feb. 2005
256Mb F-die DDR2 SDRAM 0. Ordering Information
Organization 64Mx4 64Mx4 32Mx8 32Mx8 DDR2-667 5-5-5 K4T56083QF-GCE6 K4T56083QF-ZCE6 DDR2-533 4-4-4 K4T56043QF-GCD5 K4T56043QF-ZCD5 K4T56083QF-GCD5 K4T56083QF-ZCD5 DDR2-400 3-3-3 K4T56043QF-GCCC K4T56043QF-ZCCC K4T56083QF-GCCC K4T56083QF-ZCCC
DDR2 SDRAM
Package Leaded Lead-free Leaded Lead-free
Note: Speed bin is in order of CL-tRCD-tRP
1.Key Features
Speed CAS Latency tRCD(min) tRP(min) tRC(min) DDR2-667 5-5-5 5 15 15 54 DDR2-533 4-4-4 4 15 15 55 DDR2-400 3-3-3 3 15 15 55 Units tCK ns ns ns
* JEDEC standard 1.8V 0.1V Power Supply * VDDQ = 1.8V 0.1V * 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin, 333MHz fCK for 667Mb/sec/pin * 4 Banks * Posted CAS * Programmable CAS Latency: 3, 4, 5 * Programmable Additive Latency: 0, 1 , 2 , 3 and 4 * Write Latency(WL) = Read Latency(RL) -1 * Burst Length: 4 , 8(Interleave/nibble sequential) * Programmable Sequential / Interleave Burst Mode * Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature) * Off-Chip Driver(OCD) Impedance Adjustment * On Die Termination * Average Refesh Period 7.8us at lower then TCASE 85C, 3.9us at 85C < TCASE < 95 C * Package: 60ball FBGA - 64Mx4/32Mx8 * All of Lead-free products are compliant for RoHS
The 256Mb DDR2 SDRAM chip is organized as either 16Mbit x 4 I/Os x 4 banks or 8Mbit x 8 I/Os x 4banks device. This synchronous device achieves high speed double-data-rate transfer rates of up to 667Mb/sec/pin (DDR2667) for general applications. The chip is designed to comply with the following key DDR2 SDRAM features such as posted CAS with additive latency, write latency = read latency - 1, Off-Chip Driver(OCD) impedance adjustment and On Die Termination. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the crosspoint of differential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style. For example, 256Mb(x4) device receive 13/11/2 addressing. The 256Mb DDR2 device operates with a single 1.8V 0.1V power supply and 1.8V 0.1V VDDQ. The 256Mb DDR2 device is available in 60ball FBGAs(x4/x8). Note: The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in "Samsung's DDR2 SDRAM Device Operation & Timing Diagram"
Page 3 of 27
Rev. 1.5 Feb. 2005
256Mb F-die DDR2 SDRAM 2. Package Pinout/Mechnical Dimension & Addressing
2.1 Package Pinout x4 package pinout (Top View) : 60ball FBGA Package
1 2 3 7 8 9
DDR2 SDRAM
VDD NC VDDQ NC VDDL
NC VSSQ DQ1 VSSQ VREF CKE
VSS DM VDDQ DQ3 VSS WE BA1 A1 A5 A9 NC
A B C D E F G H J K L
VSSQ DQS VDDQ DQ2 VSSDL RAS CAS A2 A6 A11 NC
DQS VSSQ DQ0 VSSQ CK CK CS A0 A4 A8 NC
VDDQ NC VDDQ NC VDD ODT
NC
BA0 A10
VDD
VSS
A3 A7
VSS
VDD
A12
Notes: 1. Pin B3 has identical capacitance as pin B7. 2. VDDL and VSSDL are power and ground for the DLL.
Ball Locations (x4)
: Populated Ball + : Depopulated Ball Top View (See the balls through the Package)
1 A B C D E F G H J K L 2 3 4 5 6 7 8 9
+ + + +
+ + + + + + + + + + +
+ + + + + + + + + + +
+ + + + + + + + + + +
+ + +
Rev. 1.5 Feb. 2005
Page 4 of 27
256Mb F-die DDR2 SDRAM
DDR2 SDRAM
x8 package pinout (Top View) : 60ball FBGA Package
1 2 3 7 8 9
VDD DQ6 VDDQ DQ4 VDDL
NU/ RDQS VSSQ DQ1 VSSQ VREF CKE
VSS DM/ RDQS VDDQ DQ3 VSS WE BA1 A1 A5 A9 NC
A B C D E F G H J K L
VSSQ DQS VDDQ DQ2 VSSDL RAS CAS A2 A6 A11 NC
DQS VSSQ DQ0 VSSQ CK CK CS A0 A4 A8 NC
VDDQ DQ7 VDDQ DQ5 VDD ODT
NC
BA0 A10
VDD
VSS
A3 A7
VSS
VDD
A12
Notes: 1. Pins B3 and A2 have identical capacitance as pins B7 and A8. 2. For a read, when enabled, strobe pair RDQS & RDQS are identical in function and timing to strobe pair DQS & DQS and input masking function is disabled. 3. The function of DM or RDQS/RDQS are enabled by EMRS command. 4. VDDL and VSSDL are power and ground for the DLL.
Ball Locations (x8)
: Populated Ball + : Depopulated Ball Top View (See the balls through the Package)
1 2 3 4 5 6 7 8 9 A B C D E F G H J K L
+ + +
+ + + + + + + + + + +
+ + + + + + + + + + +
+ + + + + + + + + + +
+ + +
Rev. 1.5 Feb. 2005
Page 5 of 27
256Mb F-die DDR2 SDRAM
FBGA Package Dimension(x4/x8)
DDR2 SDRAM
11.00 0.10 6.40 0.80 1.60
# A1 INDEX MARK
9
8
7
6
5
4
3
2
1
A B C
E F
4.00
H J K L
3.20 60-0.450.05
0.2 M A B (0.90) (1.80)
(5.50)
1.60
0.80
G
13.00 0.10 0.10MAX
D
11.00 0.10 #A1
13.00 0.10
8.00
0.350.05 MAX.1.20
0.450.05
Page 6 of 27
Rev. 1.5 Feb. 2005
256Mb F-die DDR2 SDRAM
2.2 Input/Output Functional Description
Symbol CK, CK Type Input Function
DDR2 SDRAM
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. After VREF has become stable during the power on and initialization swquence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self refresh. Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on systems with multiple Ranks. CS is considered part of the command code. On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS, RDQS, RDQS, and DM signal for x4/x8 configurations. The ODT pin will be ignored if the Extended Mode Register Set(EMRS) is programmed to disable ODT. Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For x8 device, the function of DM or RDQS/RDQS is enabled by EMRS command. Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. Address Inputs: Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during Mode Register Set commands. Data Input/ Output: Bi-directional data bus. Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. For the x8, an RDQS option using DM pin can be enabled via the EMRS(1) to simplify read timing. The data strobes DQS and RDQS may be used in single ended mode or paired with optional complementary signals DQS and RDQS to provide differential pair signaling to the system during both reads and writes. An EMRS(1) control bit enables or disables all complementary data strobe signals. No Connect: No internal electrical connection is present.
CKE
Input
CS
Input
ODT RAS, CAS, WE DM
Input Input Input
BA0 - BA1
Input
A0 - A12
Input
DQ
Input/Output
DQS, (DQS) (RDQS), (RDQS)
Input/Output
NC VDD/VDDQ VSS/VSSQ VDDL VSSDL VREF Supply Supply Supply Supply Supply
Power Supply: 1.8V +/- 0.1V, DQ Power Supply: 1.8V +/- 0.1V Ground, DQ Ground DLL Power Supply: 1.8V +/- 0.1V DLL Ground Reference voltage
In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of EMRS(1) x4 DQS/DQS x8 DQS/DQS if EMRS(1)[A11] = 0 x8 DQS/DQS, RDQS/RDQS, if EMRS(1)[A11] = 1 "single-ended DQS signals" refers to any of the following with A10 = 1 of EMRS(1) x4 DQS x8 DQS if EMRS(1) [A11] = 0 x8 DQS, RDQS, if EMRS(1) [A11] = 1
Page 7 of 27
Rev. 1.5 Feb. 2005
256Mb F-die DDR2 SDRAM
2.3 256Mb Addressing
Configuration # of Bank Bank Address Auto precharge Row Address Column Address 64Mb x4 4 BA0,BA1 A10/AP A0 ~ A12 A0 ~ A9,A11 32Mb x 8 4 BA0,BA1 A10/AP A0 ~ A12 A0 ~ A9
DDR2 SDRAM
* Reference information: The following tables are address mapping information for other densities.
512Mb
Configuration # of Bank Bank Address Auto precharge Row Address Column Address 128Mb x4 4 BA0,BA1 A10/AP A0 ~ A13 A0 ~ A9,A11 64Mb x 8 4 BA0,BA1 A10/AP A0 ~ A13 A0 ~ A9 32Mb x16 4 BA0,BA1 A10/AP A0 ~ A12 A0 ~ A9
1Gb
Configuration # of Bank Bank Address Auto precharge Row Address Column Address 256Mb x4 8 BA0 ~ BA2 A10/AP A0 ~ A13 A0 ~ A9,A11 128Mb x 8 8 BA0 ~ BA2 A10/AP A0 ~ A13 A0 ~ A9 64Mb x16 8 BA0 ~ BA2 A10/AP A0 ~ A12 A0 ~ A9
2Gb
Configuration # of Bank Bank Address Auto precharge Row Address Column Address 512Mb x4 8 BA0 ~ BA2 A10/AP A0 ~ A14 A0 ~ A9,A11 256Mb x 8 8 BA0 ~ BA2 A10/AP A0 ~ A14 A0 ~ A9 128Mb x16 8 BA0 ~ BA2 A10/AP A0 ~ A13 A0 ~ A9
4Gb
Configuration # of Bank Bank Address Auto precharge Row Address Column Address/page size 1 Gb x4 8 BA0 ~ BA2 A10/AP A0 - A15 A0 - A9,A11 512Mb x 8 8 BA0 ~ BA2 A10/AP A0 - A15 A0 - A9 256Mb x16 8 BA0 ~ BA2 A10/AP A0 - A14 A0 - A9
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Rev. 1.5 Feb. 2005
256Mb F-die DDR2 SDRAM
3. Absolute Maximum DC Ratings
Symbol VDD VDDQ VDDL VIN, VOUT TSTG 1. Parameter Voltage on VDD pin relative to Vss Voltage on VDDQ pin relative to Vss Voltage on VDDL pin relative to Vss Voltage on any pin relative to Vss Storage Temperature Rating - 1.0 V ~ 2.3 V - 0.5 V ~ 2.3 V - 0.5 V ~ 2.3 V - 0.5 V ~ 2.3 V -55 to +100
DDR2 SDRAM
Units V V V V C
Notes 1 1 1 1 1, 2
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
4. AC & DC Operating Conditions Recommended DC Operating Conditions (SSTL - 1.8)
Symbol VDD VDDL VDDQ VREF VTT Parameter Supply Voltage Supply Voltage for DLL Supply Voltage for Output Input Reference Voltage Termination Voltage Rating Min. 1.7 1.7 1.7 0.49*VDDQ VREF-0.04 Typ. 1.8 1.8 1.8 0.50*VDDQ VREF Max. 1.9 1.9 1.9 0.51*VDDQ VREF+0.04 Units V V V mV V 4 4 1,2 3 Notes
There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must be less than or equal to VDD. 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC). 3. VTT of transmitting device must track VREF of receiving device. 4. AC parameters are measured with VDD, VDDQ and VDDDL tied together.
Page 9 of 27
Rev. 1.5 Feb. 2005
256Mb F-die DDR2 SDRAM
Operating Temperature Condition
Symbol TOPER Parameter Operating Temperature Rating 0 to 95 Units C
DDR2 SDRAM
Notes 1, 2
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard. 2. At 85 - 95 C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
Input DC Logic Level
Symbol VIH(DC) VIL(DC) Parameter DC input logic high DC input logic low Min. VREF + 0.125 - 0.3 Max. VDDQ + 0.3 VREF - 0.125 Units V V Notes
Input AC Logic Level
Symbol VIH (ac) VIL (ac) Parameter ac input logic high ac input logic low DDR2-400, DDR2-533 Min. VREF + 0.250 Max. VREF - 0.250 Min. VREF + 0.200 VREF - 0.200 DDR2-667 Max.
AC Input Test Conditions
Symbol VREF VSWING(MAX) SLEW Condition Input reference voltage Input signal maximum peak to peak swing Input signal minimum slew rate Value 0.5 * VDDQ 1.0 1.0 V V V/ns Units 1 1 2, 3 Notes
Notes: 1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising edges and the range from VREF to VIL(AC) max for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative transitions.
VDDQ VIH(AC) min VSWING(MAX) VIH(DC) min VREF VIL(DC) max VIL(AC) max delta TF Falling Slew = VREF - VIL(AC) max delta TF delta TR Rising Slew = VSS VIH(AC) min - VREF delta TR
< AC Input Test Signal Waveform >
Page 10 of 27
Rev. 1.5 Feb. 2005
256Mb F-die DDR2 SDRAM
Differential input AC logic Level
Symbol VID(AC) VIX(AC) Notes: Parameter AC differential input voltage AC differential cross point voltage Min. 0.5 0.5 * VDDQ - 0.175 Max. VDDQ + 0.6 0.5 * VDDQ + 0.175 Units V V
DDR2 SDRAM
Notes 1 2
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to VIH(AC) - VIL(AC). 2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ . VIX(AC) indicates the voltage at which differential input signals must cross.
VDDQ VTR VCP VSSQ
< Differential signal levels >
VID
Crossing point
VIX or VOX
Differential AC output parameters
Symbol VOX(AC) Parameter AC differential cross point voltage Min. 0.5 * VDDQ - 0.125 Max. 0.5 * VDDQ + 0.125 Units V Note 1
Note : 1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ . VOX(AC) indicates the voltage at which differential output signals must cross.
Page 11 of 27
Rev. 1.5 Feb. 2005
256Mb F-die DDR2 SDRAM
OCD default characteristics
Description Output impedance Output impedance step size for OCD calibration Pull-up and pull-down mismatch Output slew rate Sout Parameter Min 12.6 0 0 1.5 Nom 18 Max 23.4 1.5 4 5 Unit ohms ohms ohms V/ns
DDR2 SDRAM
Notes 1,2 6 1,2,3 1,4,5,6,7,8
Notes: 1. Absolute Specifications (0C TCASE +95C; VDD = +1.8V 0.1V, VDDQ = +1.8V 0.1V) 2. Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT-VDDQ)/Ioh must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ280mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol must be less than 23.4 ohms for values of VOUT between 0V and 280mV. 3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage. 4. Slew rate measured from VIL(AC) to VIH(AC). 5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaranteed by design and characterization. 6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process and represents only the DRAM uncertainty. Output slew rate load :
VTT
25 ohms Output (VOUT) Reference Point
7. DRAM output slew rate specification applies to 400Mb/sec/pin, 533Mb/sec/pin and 667Mb/sec/pin speed bins. 8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and tQHS specification.
Page 12 of 27
Rev. 1.5 Feb. 2005
256Mb F-die DDR2 SDRAM IDD Specification Parameters and Test Conditions
(IDD values are for full operating range of Voltage and Temperature, Notes 1 - 5) Symbol IDD0 Proposed Conditions
DDR2 SDRAM
Units mA
Notes
Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address businputs are SWITCHING; Data pattern is same as IDD4W Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0mA Slow PDN Exit MRS(12) = 1mA
IDD1
mA
IDD2P
mA
IDD2Q
mA
IDD2N
mA
IDD3P
mA
mA
IDD3N
Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Burst auto refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK\ at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Normal Low Power
mA
IDD4W
mA
IDD4R
mA
IDD5B
mA
IDD6
mA mA
IDD7
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the following page for detailed timing conditions
mA
Page 13 of 27
Rev. 1.5 Feb. 2005
256Mb F-die DDR2 SDRAM
DDR2 SDRAM
Notes: 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, DQS\, RDQS, RDQS\, LDQS, LDQS\, UDQS, and UDQS\. IDD values must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD LOW is defined as Vin VILAC(max) HIGH is defined as Vin VIHAC(min) STABLE is defined as inputs stable at a HIGH or LOW level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes.
For purposes of IDD testing, the following parameters are utilized
DDR2-667 Parameter CL(IDD) tRCD(IDD) tRC(IDD) tRRD(IDD)-x4/x8 tRRD(IDD)-x16 tCK(IDD) tRASmin(IDD) tRP(IDD) tRFC(IDD) 5-5-5 5 15 60 7.5 10 3 45 15 105 DDR2-533 4-4-4 4 15 60 7.5 10 3.75 45 15 105 DDR2-400 3-3-3 3 15 55 7.5 10 5 40 15 105 Units tCK ns ns ns ns ns ns ns ns
Detailed IDD7 The detailed timings are shown below for IDD7. Legend: A = Active; RA = Read with Autoprecharge; D = Deselect IDD7: Operating Current: All Bank Interleave Read operation All banks are being interleaved at minimum tRC(IDD) without violating tRRD(IDD) using a burst length of 4. Control and address bus inputs are STABLE during DESELECTs. IOUT = 0mA Timing Patterns for 4 bank devices x4/ x8/ x16 -DDR2-400 3/3/3 A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D -DDR2-533 4/4/4 A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D -DDR2-667 5/5/5 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D
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256Mb F-die DDR2 SDRAM
DDR2 SDRAM IDD Spec Table
Symbol
IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P-F IDD3P-S IDD3N IDD4W IDD4R IDD5B IDD6 Normal IDD7
DDR2 SDRAM
64Mx4(K4T56043QF)
-
D5(DDR2-533@CL=4) CC(DDR2-400@CL=3)
100 110 8 25 30 30 15 70 160 150 165 5 250 95 100 8 25 30 30 15 65 125 125 160 5 245
Unit
mA mA mA mA mA mA mA mA mA mA mA mA mA
Notes
Symbol
IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P-F IDD3P-S IDD3N IDD4W IDD4R IDD5B IDD6 Normal IDD7
32Mx8(K4T56083QF) E6(DDR2-667@CL=5)
105 115 8 30 35 35 15 75 210 185 170 5 265
D5(DDR2-533@CL=4) CC(DDR2-400@CL=3)
100 110 8 25 30 30 15 70 175 160 165 5 255 95 100 8 25 30 30 15 65 135 130 160 5 255
Unit
mA mA mA mA mA mA mA mA mA mA mA mA mA
Notes
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Rev. 1.5 Feb. 2005
256Mb F-die DDR2 SDRAM
Input/Output capacitance
Parameter Symbol DDR2-400 DDR2-533 Min Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS Input/output capacitance delta, DQ, DM, DQS, DQS CCK CDCK CI CDI CIO CDIO 1.0 x 1.0 x 2.5 x Max 2.0 0.25 2.0 0.25 4.0 0.5 DDR2-667 Min 1.0 x 1.0 x 2.5 x
DDR2 SDRAM
Max 2.0 0.25 2.0 0.25 3.5 0.5
Units pF pF pF pF pF pF
Electrical Characteristics & AC Timing for DDR2-667/533/400
(0 C < TCASE < 95 C; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V)
Refresh Parameters by Device Density
Parameter Refresh to active/Refresh command time tRFC 0 C TCASE 85C Average periodic refresh interval tREFI 85 C < TCASE 95C 3.9 3.9 3.9 3.9 3.9 s Symbol 256Mb 75 7.8 512Mb 105 7.8 1Gb 127.5 7.8 2Gb 195 7.8 4Gb 327.5 7.8 Units ns s
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed Bin (CL - tRCD - tRP) Parameter tCK, CL=3 tCK, CL=4 tCK, CL=5 tRCD tRP tRC tRAS min 5 3.75 3 15 15 54 39
70000
DDR2-667(E6) 5 - 5- 5 max 8 8 8
DDR2-533(D5) 4-4-4 min 5 3.75 15 15 55 40
70000
DDR2-400(CC) 3-3-3 min 5 5 15 15 55 40
70000
Units
max 8 8 -
max 8 8 ns ns ns ns ns ns ns
Page 16 of 27
Rev. 1.5 Feb. 2005
256Mb F-die DDR2 SDRAM
Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
Parameter Symbol DDR2-667 min
DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width CK half period tAC -450
DDR2 SDRAM
DDR2-533 min
-500
DDR2-400 min
-600
Units
Notes
max
+450
max
+500
max
+600 ps
tDQSCK
-400
+400
-450
+450
-500
+500
ps
tCH tCL tHP
0.45 0.45 min(tCL , tCH) 3000 175
0.55 0.55 x
0.45 0.45 min(tCL , tCH) 3750 225
0.55 0.55 x
0.45 0.45 min(tCL , tCH) 5000 275
0.55 0.55 x
tCK tCK ps 20,21
Clock cycle time, CL=x DQ and DM input hold time DQ and DM input setup time Control & Address input pulse width for each input DQ and DM input pulse width for each input Data-out highimpedance time from CK/CK DQS low-impedance time from CK/CK DQ low-impedance time from CK/CK DQS-DQ skew for DQS and associated DQ signals DQ hold skew factor DQ/DQS output hold time from DQS First DQS latching transition to associated clock edge DQS input high pulse width DQS input low pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK
tCK tDH(base)
8000 x
8000 x
8000 x
ps ps
24 15,16, 17,20 15,16, 17,21
tDS(base)
100
x
100
x
150
x
ps
tIPW
0.6
x
0.6
x
0.6
x
tCK
tDIPW
0.35
x
0.35
x
0.35
x
tCK
tHZ
x
tAC max
x
tAC max
x
tAC max
ps
tLZ(DQS)
tAC min 2*tAC min x
tAC max tAC max 240
tAC min 2* tAC min x
tAC max tAC max 300
tAC min 2* tAC min x
tAC max tAC max 350
ps
27
tLZ(DQ)
ps
27
tDQSQ
ps
22
tQHS tQH
x tHP tQHS -0.25
340 x
x tHP tQHS -0.25
400 x
x tHP tQHS -0.25
450 x
ps ps
21
tDQSS
0.25
0.25
0.25
tCK
tDQSH
0.35
x
0.35
x
0.35
x
tCK
tDQSL
0.35
x
0.35
x
0.35
x
tCK
tDSS
0.2
x
0.2
x
0.2
x
tCK
tDSH
0.2
x
0.2
x
0.2
x
tCK
Page 17 of 27
Rev. 1.5 Feb. 2005
256Mb F-die DDR2 SDRAM
Parameter Symbol DDR2-667 min
Mode register set command cycle time Write postamble Write preamble Address and control input hold time Address and control input setup time Read preamble Read postamble Active to active command period for 1KB page size products Active to active command period for 2KB page size products Four Activate Window for 1KB page size products Four Activate Window for 2KB page size products CAS to CAS command delay Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal read to precharge command delay Exit self refresh to a non-read command Exit self refresh to a read command Exit precharge power down to any non-read command Exit active power down to read command tMRD 2
DDR2 SDRAM
DDR2-533 min
2
DDR2-400 min
2
Units
Notes
max
x
max
x
max
x tCK
tWPST tWPRE tIH(base)
0.4 0.35 275
0.6 x x
0.4 0.35 375
0.6 x x
0.4 0.35 475
0.6 x x
tCK tCK ps
19
14,16, 18,23 14,16, 18,22 28 28 12
tIS(base)
200
x
250
x
350
x
ps
tRPRE tRPST tRRD
0.9 0.4 7.5
1.1 0.6 x
0.9 0.4 7.5
1.1 0.6 x
0.9 0.4 7.5
1.1 0.6 x
tCK tCK ns
tRRD
10
x
10
x
10
x
ns
12
tFAW
37.5
37.5
37.5
ns
tFAW
50
50
50
ns
tCCD
2
2
2
tCK
tWR tDAL
15 WR+tR P
x x
15 WR+tR P
x x
15 WR+tR P
x x
ns tCK 23
tWTR
7.5
x
7.5
x
10
x
ns
33
tRTP
7.5
7.5
7.5
ns
11
tXSNR
tRFC + 10 200
tRFC + 10 200
tRFC + 10 200
ns
tXSRD
tCK
tXP
2
x
2
x
2
x
tCK
tXARD
2
x
2
x
2
x
tCK
9
Page 18 of 27
Rev. 1.5 Feb. 2005
256Mb F-die DDR2 SDRAM
Parameter Symbol DDR2-667 min
Exit active power down to read command (slow exit, lower power) CKE minimum pulse width (high and low pulse width) ODT turn-on delay ODT turn-on tXARDS 7 - AL
DDR2 SDRAM
DDR2-533 min
6 - AL
DDR2-400 min
6 - AL
Units
Notes
max
max
max
tCK 9, 10
tCKE
3
3
3
tCK
36
tAOND tAON
2 tAC(mi n) tAC(mi n)+2
2 tAC(m ax)+0. 7 2tCK+t AC(ma x)+1 2.5 tAC(m ax)+ 0.6 2.5tCK +tAC( max)+ 1
2 tAC(mi n) tAC(mi n)+2
2 tAC(m ax)+1 2tCK+t AC(ma x)+1 2.5
tAC(ma x)+ 0.6
2 tAC(mi n) tAC(mi n)+2
2 tAC(ma x)+1 2tCK+t AC (max)+ 1 2.5
tAC(max )+ 0.6
tCK ns 13, 25
ODT turn-on(PowerDown mode)
tAONPD
ns
ODT turn-off delay ODT turn-off
tAOFD t
2.5 tAC(mi n) tAC(mi n)+2
2.5
tAC(min)
2.5 tAC(mi n) tAC(mi n)+2
tCK ns 26
AOF
ODT turn-off (PowerDown mode)
tAOFPD
tAC(mi n)+2
2.5tCK + tAC(m ax)+1
2.5tCK + tAC(ma x)+1
ns
ODT to power down entry latency ODT power down exit latency OCD drive mode output delay Minimum time clocks remains ON after CKE asynchronously drops LOW
tANPD tAXPD tOIT tDelay
3 8 0 tIS+tCK +tIH 12
3 8 0 tIS+tCK +tIH 12
3 8 0 tIS+tCK +tIH 12
tCK tCK ns ns 24
Page 19 of 27
Rev. 1.5 Feb. 2005
256Mb F-die DDR2 SDRAM
General notes, which may apply for all AC parameters
DDR2 SDRAM
1. Slew Rate Measurement Levels a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals. For differential signals (e.g. DQS - DQS) output slew rate is measured between DQS - DQS = -500 mV and DQS - DQS = +500mV. Output slew rate is guaranteed by design, but is not necessarily tested on each device. b. Input slew rate for single ended signals is measured from dc-level to ac-level: from VIL(dc) to VIH(ac) for rising edges and from VIH(dc) and VIL(ac) for falling edges. For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250 mV to CK - CK = +500 mV (250mV to -500 mV for falling edges). c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS for differential strobe. 2. DDR2 SDRAM AC timing reference load Following figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment or a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics).
VDDQ
DQ DQS DQS RDQS RDQS
DUT
Output Timing reference point 25
VTT = VDDQ/2

The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal. 3. DDR2 SDRAM output slew rate test load Output slew rate is characterized under the test conditions as shown in the following figure.
VDDQ DUT
DQ DQS, DQS RDQS, RDQS
Output Test point 25
VTT = VDDQ/2

Page 20 of 27
Rev. 1.5 Feb. 2005
256Mb F-die DDR2 SDRAM
DDR2 SDRAM
4. Differential data strobe DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS "Enable DQS" mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20 ohm to 10 K ohm resisor to insure proper operation.
DQS DQS tWPRE
VIH(ac) VIH(dc)
tDQSH
tDQSL
DQS/ DQS
tWPST
DQ
D
VIL(ac)
D
D
VIL(dc)
D tDH
VIH(dc)
tDS
VIH(ac)
tDS
tDH DMin
DM
DMin
DMin
VIL(ac)
DMin
VIL(dc)

tCH CK tCL
CK/CK
CK
DQS
DQS/DQS
DQS tRPRE tRPST Q tDQSQmax tQH Q Q tDQSQmax tQH Q
DQ

5. AC timings are for linear signal transitions. 6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 7. All voltages are referenced to VSS. 8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
Page 21 of 27
Rev. 1.5 Feb. 2005
256Mb F-die DDR2 SDRAM
Specific Notes for dedicated AC parameters
DDR2 SDRAM
9. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit timing. 10. AL = Additive Latency 11. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and tRAS(min) have been satisfied. 12. A minimum of two clocks (2 * tCK) is required irrespective of operating frequency 13. Timings are guaranteed with command/address input slew rate of 1.0 V/ns. 14. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 15. Timings are guaranteed with data, mask, and (DQS/RDQS in singled ended mode) input slew rate of 1.0 V/ns. 16. Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1V/ns in single ended mode. 17. tDS and tDH derating for DDR2-400 and DDR2-533
tDS, tDH Derating Values (ALL units in `ps', Note 1 applies to entire Table) DQS,DQS Differential Slew Rate 4.0 V/ns tD S 2.0 1.5 1.0 DQ Slew 0.8 rate V/ns 0.7 0.6 0.5 0.4 0.9 125 83 0 tD H 45 21 0 3.0 V/ns tD S 125 83 0 -11 tD H 45 21 0 -14 2.0 V/ns tD S 125 83 0 -11 -25 tD H 45 21 0 -14 -31 1.8 V/ns tD S 95 12 1 -13 -31 tD H 33 12 -2 -19 -42 1.6 V/ns tD S 24 13 -1 -19 -43 tD H 24 10 -7 -30 -59 1.4V/ns tD S 25 11 -7 -31 -74 tD H 22 5 -18 -47 -89 1.2V/ns tD S 23 5 -19 -62 tD H 17 -6 -35 -77 1.0V/ns tD S 17 -7 -50 tD H 6 -23 -65 0.8V/ns tD S 5 -38 tD H -11 -53
-127 -140 -115 -128 -103 -116
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the datasheet tDS(base) and tDH(base) value to the delta tDS and delta tDH derating value respectively. Example: tDS (total setup time) = tDS(base) + delta tDS.
Page 22 of 27
Rev. 1.5 Feb. 2005
256Mb F-die DDR2 SDRAM
18. tIS and tIH (input setup and hold) derating.
tIS, tIH Derating Values for DDR2-400, DDR2-533 CK,CK Differential Slew Rate 2.0 V/ns tIS 4.0 3.5 3.0 2.5 2.0 1.5 1.0 Command/Address Slew rate (V/ns) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.25 0.2 0.15 +187 +179 +167 +150 +125 +83 0 -11 -25 -43 -67 -110 -175 -285 -350 -525 -800 tIH +94 +89 +83 +75 +45 +21 0 -14 -31 -54 -83 -125 -188 -292 -375 -500 -708 tIS +217 +209 +197 +180 +155 +113 +30 +19 +5 -13 -37 -80 -145 -255 -320 -495 -770 1.5 V/ns tIH +124 +119 +113 +105 +75 +51 +30 +16 -1 -24 -53 -95 -158 -262 -345 -470 -678 tIS +247 +239 +227 +210 +185 +143 +60 +49 +35 +17 -7 -50 -115 -225 -290 -465 -740 1.0 V/ns tIH +154 +149 +143 +135 +105 +81 60 +46 +29 +6 -23 -65 -128 -232 -315 -440 -648
DDR2 SDRAM
Units ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Notes 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
tIS and tIH Derating Values for DDR2-667, DDR2-800 CK,CK Differential Slew Rate 2.0 V/ns tIS 4.0 3.5 3.0 2.5 2.0 1.5 1.0 Command/Address Slew rate (V/ns) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.25 0.2 0.15 0.1 +150 +143 +133 +120 +100 +67 0 -5 -13 -22 -34 -60 -100 -168 -200 -325 -517 -1000 tIH +94 +89 +83 +75 +45 +21 0 -14 -31 -54 -83 -125 -188 -292 -375 -500 -708 -1125 1.5 V/ns tIS +180 +173 +163 +150 +130 +97 +30 +25 +17 +8 -4 -30 -70 -138 -170 -295 -487 -970 tIH +124 +119 +113 +105 +75 +51 +30 +16 -1 -24 -53 -95 -158 -262 -345 -470 -678 -1095 1.0 V/ns tIS +210 +203 +193 +180 +160 +127 +60 +55 +47 +38 +26 0 -40 -108 -140 -265 -457 -940 tIH +154 +149 +143 +135 +105 +81 +60 +46 +29 +6 -23 -65 -128 -232 -315 -440 -648 -1065 Units ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps Notes 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Page 23 of 27
Rev. 1.5 Feb. 2005
256Mb F-die DDR2 SDRAM
DDR2 SDRAM
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the datasheet tIS(base) and tIH(base) value to the delta tIS and delta tIH derating value respectively. Example: tIS (total setup time) = tIS(base) + delta tIS 19. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 20. MIN ( tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). For example, tCL and tCH are = 50% of the period, less the half period jitter ( tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk ( tJIT(crosstalk)) into the clock traces. 21. tQH = tHP - tQHS, where: tHP = minimum half clock period for any given cycle and is defined by clock high or clock low ( tCH, tCL). tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and pchannel to n-channel variation of the output drivers. 22. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between DQS / DQS and associated DQ in any given cycle. 23. DAL = WR + RU{tRP(ns)/tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For DDR533 at tCK = 3.75ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 24. The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock frequency change during precharge power-down, a specific procedure is required as described in DDR2 device operation 25. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND. 26. ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. 27. tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ). Following figure shows a method to calculate the point when device is no longer driving (tHZ), or begins driving (tLZ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. 28. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). Following figure shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calPage 24 of 27
Rev. 1.5 Feb. 2005
256Mb F-die DDR2 SDRAM
DDR2 SDRAM
culation is consistent. These notes are referenced in the "Timing parameters by speed grade" tables for DDR2-400/533/667 and DDR2-800.
VOH + x mV VOH + 2x mV tHZ tRPST end point VOL + 2x mV VOL + x mV
VTT + 2x mV VTT + x mV tLZ tRPRE begin point VTT - x mV VTT - 2x mV
T2 T1
T1 T2
tHZ,tRPST end point = 2*T1-T2
tLZ,tRPRE begin point = 2*T1-T2

29. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIH(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL(ac) level to the differential data strobe crosspoint for a falling signal applied to the device under test. 30. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIH(dc) level to the differential data strobe crosspoint for a rising signal and VIL(dc) to the differential data strobe crosspoint for a falling signal applied to the device under test.
Differential Input waveform timing
DQS DQS
tDS
tDH
tDS
tDH
VDDQ VIH(ac) min VIH(dc) min
VREF(dc)
VIL(dc) max VIL(ac) max VSS
Page 25 of 27
Rev. 1.5 Feb. 2005
256Mb F-die DDR2 SDRAM
for a falling signal applied to the device under test.
DDR2 SDRAM
31. Input waveform timing is referenced from the input signal crossing at the VIH(ac) level for a rising signal and VIL(ac)
32. Input waveform timing is referenced from the input signal crossing at the VIH(dc) level for a rising signal and VIL(dc) for a falling signal applied to the device under test.
CK CK
tIS
tIH
tIS
tIH
VDDQ VIH(ac) min VIH(dc) min VREF(dc) VIL(dc) max VIL(ac) max VSS
33. tWTR is at lease two clocks (2 * tCK) independent of operation frequency. 34. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(ac) level to the single-ended data strobe crossing VIH/L(dc) at the start of its transition for a rising signal, and from the input signal crossing at the VIL(ac) level to the single-ended data strobe crossing VIH/L(dc) at the start of its transition for a falling signal applied to the device under test. The DQS signal must be monotonic between Vil(dc)max and Vih(dc)min. 35. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(dc) level to the single-ended data strobe crossing VIH/L(ac) at the end of its transition for a rising signal, and from the input signal crossing at the VIL(dc) level to the single-ended data strobe crossing VIH/L(ac) at the end of its transition for a falling signal applied to the device under test. The DQS signal must be monotonic between Vil(dc)max and Vih(dc)min. 36. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registeration. Thus, after any cKE transition, CKE may not transitioin from its valid level during the time period of tIS + 2*tCK + tIH.
Page 26 of 27
Rev. 1.5 Feb. 2005
256Mb F-die DDR2 SDRAM Revision History
Version 1.0 (Jan. 2004) - Initial Release Version 1.1 (Jun. 2004) - Added Lead-Free part number in ordering information. - Changed IDD2P - Corrected Typo Version 1.2 (Aug. 2004) - Corrected the part number in ordering information. Version 1.3 (Jan. 2005) - Revised current test AC spec condition - Added derating table Version 1.4 (Jan. 2005) - Corrected typo Version 1.5 (Feb. 2005) - Revised Input AC Logic Level for DDR2-667
DDR2 SDRAM
Page 27 of 27
Rev. 1.5 Feb. 2005

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