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INTEGRATED CIRCUITS
74LV574 Octal D-type flip-flop; positive edge-trigger (3-State)
Product specification Supersedes data of 1997 Feb 03 IC24 Data Handbook 1998 Jun 10
Philips Semiconductors
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger (3-State)
74LV574
FEATURES
* Wide operating voltage: 1.0 to 5.5V * Optimized for Low Voltage applications: 1.0 to 3.6V * Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V * Typical VOLP (output ground bounce) t 0.8V at VCC = 3.3V, * Typical VOHV (output VOH undershoot) u 2V at VCC = 3.3V, * Common 3-State output enable input * Output capability: bus driver * ICC category: MSI
QUICK REFERENCE DATA
GND = 0V; Tamb = 25C; tr =tf v2.5 ns SYMBOL tPHL/tPLH fmax CI CPD PARAMETER Propagation delay CP to Qn Maximum clock frequency Input capacitance Power dissipation capacitance per flip-flop Tamb = 25C Tamb = 25C
DESCRIPTION
The 74LV574 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT574. The 74LV574 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and non-inverting 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. The eight flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the eight flip-flops is available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.
CONDITIONS CL = 15pF VCC = 3.3V CL = 15pF, VCC = 3.3V
TYPICAL 13 77 3.5
UNIT ns MHz pF pF
Notes 1 and 2
25
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in W) VCC2 x fi )S (CL VCC2 fo) where: PD = CPD fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; VCC2 fo) = sum of the outputs. S (CL 2. The condition is VI = GND to VCC
ORDERING AND PACKAGE INFORMATION
PACKAGES 20-Pin Plastic DIL 20-Pin Plastic SO 20-Pin Plastic SSOP Type II 20-Pin Plastic TSSOP Type I TEMPERATURE RANGE -40C to +125C -40C to +125C -40C to +125C -40C to +125C OUTSIDE NORTH AMERICA 74LV574 N 74LV574 D 74LV574 DB 74LV574 PW NORTH AMERICA 74LV574 N 74LV574 D 74LV574 DB 74LV574PW DH PKG. DWG. # SOT146-1 SOT163-1 SOT339-1 SOT360-1
PIN DESCRIPTION
PIN NUMBER 1 2, 3, 4, 5, 6, 7, 8, 9 19, 18, 17, 16, 15, 14, 13, 12 10 11 20 SYMBOL OE D0-D7 Q0-Q7 GND CP VCC FUNCTION Output enabled input (active LOW) Data inputs 3-State flip-flop outputs Ground (0V) Clock input (LOW-to-HIGH, edge-triggered) Positive supply voltage
FUNCTION TABLE
OPERATING MODES Load and read register Load register and disable outputs H h L l Z INPUTS OE L L H H CP Dn l h l h INTERNAL FLIP-FLOPS L H L H OUTPUTS Q0 to Q7 L H Z Z
= HIGH voltage level = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition = LOW voltage level = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition = High impedance OFF-state = LOW-to-HIGH clock transition
1998 Jun 10
2
853-1990 19545
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger (3-State)
74LV574
PIN CONFIGURATION
OE D0 D1 D2 D3 D4 D5 D6 D7 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CP
LOGIC SYMBOL (IEEE/IEC)
11 1 C1 EN
2
1D
19
3 4 5 6 7 8 9
18 17 16 15 14 13 12
SV00714
SV00716
LOGIC SYMBOL
11
FUNCTIONAL DIAGRAM
2 3 D0 D1 D2 D3 D4 D5 D6 D7 FF1 to FF8 3-STATE OUTPUTS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 18 17 16 15 14 13 12
2 3 4 5 6 7 8 9
D0 D1 D2 D3 D4 D5 D6 D7
CP
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
19 18 17 16
4 5 6 7
15 14 13 12 8 9
OE
11 1
CP OE
1
SV00715
SV00717
1998 Jun 10
3
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger (3-State)
74LV574
LOGIC DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
FF1
FF2
FF3
FF4
FF5
FF6
FF7
FF8
CP OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
SV00342
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC IIK IOK IO IGND, ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC output diode current DC output source or sink current - bus driver outputs DC VCC or GND current for types with -bus driver outputs Storage temperature range Power dissipation per package -plastic DIL -plastic mini-pack (SO) -plastic shrink mini-pack (SSOP and TSSOP) for temperature range: -40 to +125C above +70C derate linearly with 12mW/K above +70C derate linearly with 8 mW/K above +60C derate linearly with 5.5 mW/K VI < -0.5 or VI > VCC + 0.5V VO < -0.5 or VO > VCC + 0.5V -0.5V < VO < VCC + 0.5V CONDITIONS RATING -0.5 to +7.0 20 50 35 70 -65 to +150 750 500 400 UNIT V mA mA mA mA C mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VI VO Tamb Input voltage Output voltage Operating ambient temperature range in free air Input rise and fall times See DC and AC characteristics VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V to 5.5V PARAMETER DC supply voltage CONDITIONS See Note1 MIN 1.0 0 0 -40 -40 - - - - - - - - TYP. 3.3 - - MAX 5.5 VCC VCC +85 +125 500 200 100 50 UNIT V V V C
tr, tf
ns/V
NOTES: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
1998 Jun 10
4
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger (3-State)
74LV574
DC CHARACTERISTICS FOR THE LV FAMILY
Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN VCC = 1.2V VIH HIGH level Input voltage VCC = 2.0V VCC = 2.7 to 3.6V VCC = 4.5 to 5.5V VCC = 1.2V VIL LOW level Input voltage VCC = 2.0V VCC = 2.7 to 3.6V VCC = 4.5 to 5.5 VCC = 1.2V; VI = VIH or VIL; -IO = 100A HIGH level output voltage all outputs out uts voltage; VOH HIGH level output voltage; BUS driver outputs VCC = 2.0V; VI = VIH or VIL; -IO = 100A VCC = 2.7V; VI = VIH or VIL; -IO = 100A VCC = 3.0V; VI = VIH or VIL; -IO = 100A VCC = 4.5V;VI = VIH or VIL; -IO = 100A VCC = 3.0V;VI = VIH or VIL; -IO = 8mA VCC = 4.5V;VI = VIH or VIL; -IO = 16mA VCC = 1.2V; VI = VIH or VIL; IO = 100A VCC = 2.0V; VI = VIH or VIL; IO = 100A VCC = 2.7V; VI = VIH or VIL; IO = 100A VCC = 3.0V;VI = VIH or VIL; IO = 100A VCC = 4.5V;VI = VIH or VIL; IO = 100A LOW level output voltage; BUS driver outputs II IOZ ICC ICC Input leakage current 3-State output OFF-state current Quiescent supply current; MSI Additional quiescent supply current per input VCC = 3.0V;VI = VIH or VIL; IO = 8mA VCC = 4.5V;VI = VIH or VIL; IO = 16mA VCC = 5.5V; VI = VCC or GND VCC = 5.5V; VI = VIH or VIL; VO = VCC or GND VCC = 5.5V; VI = VCC or GND; IO = 0 VCC = 2.7V to 3.6V; VI = VCC -0.6V 1.8 2.5 2.8 4.3 2.40 3.60 1.2 2.0 2.7 3.0 4.5 2.82 4.20 0 0 0 0 0 0.20 0.35 0.2 0.2 0.2 0.2 0.40 0.55 1.0 5 20.0 500 0.2 0.2 0.2 0.2 0.50 0.65 1.0 10 160 850 A A A A V 1.8 2.5 2.8 4.3 2.20 3.50 V 0.9 1.4 2.0 0.7*VCC 0.3 0.6 0.8 0.3*VCC -40C to +85C TYP1 MAX -40C to +125C MIN 0.9 1.4 2.0 0.7*VCC 0.3 0.6 0.8 0.3*VCC V V MAX UNIT
LOW level output voltage out uts voltage; all outputs VOL
NOTE: 1. All typical values are measured at Tamb = 25C.
1998 Jun 10
5
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger (3-State)
74LV574
AC CHARACTERISTICS
GND = 0V; tr = tf 2.5ns; CL = 50pF; RL = 1K SYMBOL PARAMETER WAVEFORM CONDITION VCC(V) 1.2 2.0 tPHL/tPLH Propagation delay CP to Qn Figure 1, 4 2.7 3.0 to 3.6 4.5 to 5.5 1.2 tPZH/tPZL 3-State output 3 State out ut enable time OE to Q t Qn 2.0 Figure 2, 4 2.7 3.0 to 3.6 4.5 to 5.5 1.2 tPHZ/tPLZ 3 State out ut 3-State output disable time OE to Q t Qn 2.0 Figure 2, 4 2.7 3.0 to 3.6 4.5 to 5.5 2.0 tW Clock pulse width HIGH or LOW Figure 1 2.7 3.0 to 3.6 1.2 tsu Set-up time Dn to CP Figure 3 2.0 2.7 3.0 to 3.6 1.2 th Hold time Dn to CP Figure 3 2.0 2.7 3.0 to 3.6 2.0 fmax Maximum clock ulse pulse frequency Figure 1 2.7 3.0 to 3.6 NOTE: 1. Unless otherwise stated, all typical values are at Tamb = 25C. 2. Typical value measured at VCC = 3.3V. MIN - - - - - - - - - - - - - - - 34 25 20 - 22 16 13 - 5 5 5 15 19 24 LIMITS -40 to +85 C TYP 80 27 20 152 - 70 24 18 132 - 75 27 21 162 - 9 6 52 10 4 3 22 -10 -4 -3 -22 40 58 702 MAX - 34 25 20 17 - 34 25 20 17 - 27 21 17 15 - - - - - - - - - - - - - - LIMITS -40 to +125 C MIN - - - - - - - - - - - - - - - 41 30 24 - 26 19 15 - 5 5 5 12 16 20 MAX - 43 31 25 21 - 43 31 25 21 - 34 26 21 18 - - - - - - - - - - - - - - MHz ns ns ns ns ns ns UNIT
1998 Jun 10
6
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger (3-State)
74LV574
AC WAVEFORMS
VM = 1.5V at VCC w 2.7V and v 3.6V VM = 0.5 * VCC at VCC t 2.7V and w 4.5V VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3V at VCC w 2.7V and v 3.6V VX = VOL + 0.1VCC at VCC < 2.7V and w 4.5V VY = VOH - 0.3V at VCC w 2.7V and v 3.6V VY = VOH - 0.1VCC at VCC < 2.7V and w 4.5V
VI CP INPUT GND VM(1)
t su
t su
th VI Dn INPUT
th
1/fmax VI CP INPUT GND VM tW tPHL VOH Qn OUTPUT VOL VM tPLH
GND
VOH
Qn OUTPUT VOL
NOTE: the shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 3.
SV00718
Figure 1. Clock (CP) to output (Qn) propagation delays, the clock pulse (CP) and the maximum clock pulse frequency
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
VI OE INPUT GND tPLZ VCC OUTPUT LOW-to-OFF OFF-to-LOW VOL tPHZ VOH OUTPUT HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled VY VM VX tPZH tPZL VM
TEST CIRCUIT
VCC 2 * VCC Open GND VO D.U.T. RT CL 50 pF RL = 1k RL = 1k
VM
PULSE GENERATOR
DEFINITIONS
RL = Load resistor CL = Load capacitance includes jig and probe capacitiance. RT = Termination resistance should be equal to ZOUT of pulse generators.
SWITCH POSITION
TEST S1 Open 2 * VCC GND VCC < 2.7V 2.7-3.6V w 4.5V VI VCC 2.7V VCC
SV00344
Figure 2. 3-state enable and disable times
tPLH/tPHL tPLZ/tPZL tPHZ/tPZH
1998 Jun 10
7
IIIIIIII IIII IIIIIIII IIII IIIIIIII IIII
VM VM
SV00345
Data set-up and hold times for the Dn input to the CP input
VI
Test Circuit for Outputs
SV00896
Figure 4.
Load circuitry for switching times
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger (3-State)
74LV574
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
1998 Jun 10
8
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger (3-State)
74LV574
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
1998 Jun 10
9
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger (3-State)
74LV574
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
1998 Jun 10
10
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger (3-State)
74LV574
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
1998 Jun 10
11
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger (3-State)
74LV574
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-04454
Philips Semiconductors
1998 Jun 10 12

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