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HUF75309T3ST
Data Sheet June 1999 File Number 4377.3
3A, 55V, 0.070 Ohm, N-Channel UltraFET Power MOSFET
This N-Channel power MOSFET is manufactured using the innovative UltraFETTM process. This advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in applications where power efficiency is important, such as switching regulators, switching converters, motor drivers, relay drivers, lowvoltage bus switches, and power management in portable and battery-operated products. Formerly developmental type TA75309.
Features
* 3A, 55V * Ultra Low On-Resistance, rDS(ON) = 0.070 * Diode Exhibits Both High Speed and Soft Recovery * Temperature Compensating PSPICETM Model * Thermal Impedance SPICE Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334, "Guidelines for Soldering Surface Mount Components to PC Boards"
Symbol
D
Ordering Information
PART NUMBER HUF75309T3ST PACKAGE SOT-223 5309
S
BRAND
G
NOTE: HUF75309T3ST is available only in tape and reel.
Packaging
SOT-223
DRAIN (FLANGE)
SOURCE DRAIN GATE
23
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. UltraFET is a trademark of Intersil Corporation. PSPICETM is a trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
HUF75309T3ST
Absolute Maximum Ratings
TA = 25oC, Unless Otherwise Specified HUF75309T3ST 55 55 20V 3 Figure 5 Figures 6, 14, 15 1.1 9.09 -55 to 150 300 260 UNITS V V V A
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (Note 2) (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
W mW/oC oC
oC oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 125oC.
Electrical Specifications
PARAMETER
TA = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V (Figure 11) VGS = VDS, ID = 250A (Figure 10) VDS = 50V, VGS = 0V VDS = 45V, VGS = 0V, TA = 150oC VGS = 20V ID = 3A, VGS = 10V (Figure 9) VDD = 30V, ID 3A, RL = 10, VGS = 10V, RGS = 28 MIN 55 2 VGS = 0V to 20V VGS = 0V to 10V VGS = 0V to 2V VDD = 30V, ID 3A, RL = 10 Ig(REF) = 1.0mA (Figure 13) Pad Area = 0.164 in2 (See note 2) Pad Area = 0.068 in2 (See TB337) Pad Area = 0.026 in2 (See TB337) TYP 0.057 8 20 12 28 19 10.7 0.71 352 146 30 MAX 4 1 250 100 0.070 45 65 23 13 0.85 110 126 143 UNITS V V A A nA ns ns ns ns ns ns nC nC nC pF pF pF
oC/W oC/W oC/W
Drain to Source Breakdown Voltage Gate to Source Threshold Voltage Zero Gate Voltage Drain Current
Gate to Source Leakage Current Drain to Source On Resistance Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 10V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Ambient
IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(10) Qg(TH) CISS COSS CRSS RJA
VDS = 25V, VGS = 0V, f = 1MHz (Figure 12)
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge NOTE: 2. 110oC/W measured using FR-4 board with 0.164 in2 footprint for 1000 seconds. SYMBOL VSD trr QRR ISD = 3A ISD = 3A, dISD/dt = 100A/s ISD = 3A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.25 41 59 UNITS V ns nC
24
HUF75309T3ST Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) 0 25 50 75 100 125 150 TA, AMBIENT TEMPERATURE (oC) 4 RJA = 110oC/W ID, DRAIN CURRENT (A) 1 THERMAL IMPEDANCE 0.1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 3
2
1
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE
ZJA, NORMALIZED
PDM 0.01 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 10-2 10-1 100 101 102 103
SINGLE PULSE 0.001 10-5 10-4 10-3
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
100 TJ = MAX RATED TA = 25oC RJA = 110oC/W 10 100s 1ms 1 10ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1
50
FOR TEMPERATURES TA = 25oC ABOVE 25oC DERATE PEAK RJA = 110oC/W CURRENT AS FOLLOWS: I = I25 150 - TA 125
ID, DRAIN CURRENT (A)
IDM, PEAK CURRENT (A)
10
0.1
VDSS(MAX) = 55V 200 1 10-3 10-2 10-1 100 101 t, PULSE WIDTH (s) 102 103
10 100 VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
25
HUF75309T3ST Typical Performance Curves
20 IAS, AVALANCHE CURRENT (A)
(Continued)
25 VGS = 20V VGS = 10V ID, DRAIN CURRENT (A) 20 VGS = 8V 15 VGS = 7V VGS = 6V VGS = 5V 5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TA = 25oC 0 1 2 3 4 5
If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
10
STARTING TJ = 25oC
10
STARTING TJ = 150oC
1 0.01
0 0.1 1 10 100 tAV, TIME IN AVALANCHE (ms)
VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
25 2.0 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 3A 1.5
FIGURE 7. SATURATION CHARACTERISTICS
ID, DRAIN CURRENT (A)
20
15
10 25oC 5 150oC -55oC 0 0 1.5 3.0 4.5 6.0 VGS, GATE TO SOURCE VOLTAGE (V) 7.5
1.0
0.5 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE
1.2 VGS = VDS, ID = 250A NORMALIZED GATE THRESHOLD VOLTAGE
ID = 250A 1.1
1.0
0.8
1.0
0.6
0.9
0.4 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
0.8 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
26
HUF75309T3ST Typical Performance Curves
600 500 C, CAPACITANCE (pF) 400 CISS 300 200 100 0 0 10 20 30 40 50 VDS , DRAIN TO SOURCE VOLTAGE (V) 60 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD
(Continued)
10
VGS , GATE TO SOURCE VOLTAGE (V)
8
WAVEFORMS IN DESCENDING ORDER: ID = 3A ID = 1A
VDD = 30V
6
4
COSS CRSS
2
0 0 2 4 6 8 Qg, GATE CHARGE (nC) 10 12
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS tP L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP 0 IAS 0.01 tAV RG IAS
+
BVDSS VDS VDD
VDD -
0V
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
VDS RL VDD VDS VGS = 20V VGS
+
Qg(TOT)
Qg(10) VDD VGS VGS = 2V 0 Qg(TH) Ig(REF) 0 VGS = 10V
DUT Ig(REF)
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORM
27
HUF75309T3ST Test Circuits and Waveforms
VDS
(Continued)
tON td(ON) RL VDS 90% tr
tOFF td(OFF) tf 90%
VGS
+
DUT RGS
VDD 0
10% 90%
10%
VGS 0 10%
50% PULSE WIDTH
50%
VGS
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJ(MAX), and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PD(MAX), in an application. Therefore the application's ambient temperature, TA (oC), and thermal impedance RJA (oC/W) must be reviewed to ensure that TJ(MAX) is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part.
( T J ( MAX ) - T A ) P D ( MAX ) = -------------------------------------------R JA
applications can be evaluated using the Intersill device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve.
200 RJA = 77.6 - 17.9 * ln(AREA) 143oC/W - 0.026in2 RJA (oC/W) 150 126oC/W - 0.068in2 110oC/W - 0.164in2 100
(EQ. 1)
In using surface mount devices such as the SOT-223 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of the PD(MAX) is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Intersil provides thermal information to assist the designer's preliminary application evaluation. Figure 20 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow.This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse
50 0.01
0.1 AREA, TOP COPPER AREA (in2)
1.0
FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD AREA
Displayed on the curve are the three RJA values listed in the Electrical Specifications table. The three points were chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power dissipation, PD(MAX). Thermal resistances corresponding to other component side copper areas can be obtained from Figure 20 or by calculation using Equation 2. The area, in square inches is the top copper area including the gate and source pads.
R JA = 77.6 - 17.9 x ln ( Area ) (EQ. 2)
28
HUF75309T3ST PSPICE Electrical Model
.SUBCKT HUF75309T3ST 2 1 3 ;
CA 12 8 5.0e-10 CB 15 14 5.0e-10 CIN 6 8 3.27e-10
DPLCAP 5 RLDRAIN DBREAK 11 + 17 EBREAK 18
REV December 97
LDRAIN 10 RSLC1 51 ESLC 50 DRAIN 2
DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 58.46 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 2.71e-9 LSOURCE 3 7 5.6e-10 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD
S1A LGATE GATE 1 RLGATE
RSLC2
5 51
ESG + EVTEMP RGATE + 18 22 9 20 6 8 EVTHRES + 19 8 6
MSTRO CIN LSOURCE 8 RSOURCE RLSOURCE S2A RBREAK 17 18 RVTEMP CB + 6 8 EDS 5 8 14 IT 19 7 SOURCE 3
RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 5e-3 RGATE 9 20 2.2 RLDRAIN 2 5 10 RLGATE 1 9 27.1 RLSOURCE 3 7 5.6 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 4.8e-2 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
12 S1B CA
13 8 13
14 13 S2B +
15
EGS
-
-
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*50),3))} .MODEL DBODYMOD D (IS = 3.4e-13 RS = 2.3e-2 TRS1 = 2.2e-3 TRS2 = 1.03e-6 CJO = 6.55e-10 TT = 3.6e-8 M = 0.57) .MODEL DBREAKMOD D (RS = 2.8e-1 TRS1 = 1e-4 TRS2 = 2.25e-5) .MODEL DPLCAPMOD D (CJO = 4e-10 IS = 1e-30 N = 10 M = 0.75) .MODEL MMEDMOD NMOS (VTO = 3.35 KP = 3 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.2) .MODEL MSTROMOD NMOS (VTO = 3.65 KP = 16 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 2.97 KP = 0.125 LAMBDA = 1e-3 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 22 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 1.07e-3 TC2 = -5.2e-7) .MODEL RDRAINMOD RES (TC1 = 5.25e-2 TC2 = 1.08e-4) .MODEL RSLCMOD RES (TC1 = 3.3e-3 TC2 = 1.03e-7) .MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0) .MODEL RVTHRESMOD RES (TC1 = -3.15e-3 TC2 = -9.41e-6) .MODEL RVTEMPMOD RES (TC1 = -1.61e-3 TC2 = 1.37e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -7.25 VOFF= -4.25) VON = -4.25 VOFF= -7.25) VON = 0 VOFF= 2.5) VON = 2.5 VOFF= 0)
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
29
+
-
RDRAIN 21 16
DBODY
MWEAK MMED
VBAT +
8 22 RVTHRES
HUF75309T3ST SPICE Thermal Model
REV December 97 HUF75309T3ST CTHERM1 7 6 7.5e-5 CTHERM2 6 5 4.0e-4 CTHERM3 5 4 1.7e-3 CTHERM4 4 3 1.5e-2 CTHERM5 3 2 7.1e-2 CTHERM6 2 1 5.9e-1 RTHERM1 7 6 7.0e-2 RTHERM2 6 5 2.7e-1 RTHERM3 5 4 2.0 RTHERM4 4 3 3.5 RTHERM5 3 2 30 RTHERM6 2 1 80
RTHERM1 CTHERM1 7 JUNCTION
6
RTHERM2
CTHERM2
5
RTHERM3
CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
1
CASE
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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30

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