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MOTOROLA
Order Number: MPC991/D Rev 0, 08/2001
SEMICONDUCTOR TECHNICAL DATA
Low Voltage PLL Clock Driver
The MPC991 is a 3.3 V compatible, PLL based ECL/PECL clock driver. The fully differential design ensures optimum skew and PLL jitter performance. The performance of the MPC991 makes the device ideal for Workstation, Mainframe Computer and Telecommunication applications. The MPC991 offers a differential ECL/PECL input for applications which need to lock to an existing clock signal. It also offers a secondary single-ended ECL clock for system test capabilities. * Fully Integrated PLL * Output Frequency up to 400 MHz * ECL/PECL Inputs and Outputs * Operates from a 3.3 V Supply * Output Frequency Configurable * TQFP Packaging * 50 ps Cycle-to-Cycle Jitter The MPC991 offers three banks of outputs which can each be programmed via the the four fsel pins of the device. There are 16 different output frequency configurations available in the device. The configurations include output ratios of 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 4:3:1 and 4:3:2. The programming table in this data sheet illustrates the various programming FA SUFFIX 52-LEAD TQFP PACKAGE options. The SYNC output monitors the relationship between the Qa and Qc CASE 848D-03 output banks. The output pulses per the timing diagrams in this data sheet signal the coincident edges of the two output banks. This feature is useful for non binary relationships between output frequencies (i.e., 3:2 or 4:3 relationships). The Sync_Sel input toggles the Qd outputs between sync signals and extensions to the Qc bank of outputs. The MPC991 provides a separate output for the feedback to the PLL. This allows for the feedback frequency to be programmed independently of the other outputs allowing for unique input vs output frequency relationships. The fselFB inputs provide 6 different feedback frequencies from the QFB differential output pair. The MPC991 features an external differential ECL/PECL feedback to the PLL. This external feedback feature allows the MPC991 to be used as a "zero" delay buffer. The propagation delay between the input reference and the output is dependent on the input reference frequency. The selection of higher reference frequencies will provide near zero delay through the device. The PLL_En, Ref_Sel and the Test_Clk input pins provide a means of bypassing the PLL and driving the output buffers directly. This allows the user to single step a design during system debug. Note that the Test_Clk input is routed through the dividers so that depending on the programming several edges on the Test_Clk input will be needed to get corresponding edge transitions on the outputs. The VCO_Sel input provides a means of recentering the VCO to provide a broader range of VCO frequencies for stable PLL operation. If the frequency select or the VCO_Sel pins are changed during operation, a master reset signal must be applied to ensure output synchronization and phase-lock. If the VCO is driven beyond its maximum frequency, the VCO can outrun the internal dividers when the VCO_Sel pin is low. This will also prevent the PLL from achieving lock. Again, a master reset signal will need to be applied to allow for phase-lock. The device employs a power-on reset circuit which will ensure output synchronization and PLL lock on initial power-up.
MPC991
LOW VOLTAGE PLL CLOCK DRIVER
Motorola, Inc. 2001
t
VCCO
fsel0
fsel1
fsel2
39 Qb3 Qb3 VCCO Qa0 Qa0 Qa1 Qa1 Qa2 Qa2 Qa3 Qa3 SYNC_Sel VCO_Sel 40 41 42 43 44 45 46 47 48 49 50 51 52 1
38
37
36
35
34
33
32
31
30
29
28
fsel3 27 26 25 24 23 22 21 Qc1 Qc1 Qc0 Qc0 VCCO Qd1 Qd1 Qd0 Qd0 VCCO QFB QFB VCCA 20 19 18 17 16 15 14 13 Ext_FB Qc /2 /4 /4 /6 /6 /6 /8 /8 /8 /8 /6 /6 /8 /8 /8 /8
Qb2
Qb2
Qb1
Qb1
Qb0
Qb0
Qc2 11 VCCI
MPC991
2
3
4
5
6
7
8
9
10
Test_Clk
PLL_En
Ref_Sel
fselFB2
fselFB1
fselFB0
ECL_CLK (991)
Figure 1. 52-Lead Pinout (Top View)
FUNCTION TABLE 1
INPUTS fsel3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 fsel2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 fsel1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 fsel0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Qa /2 /2 /2 /2 /2 /2 /2 /2 /2 /2 /4 /4 /4 /6 /6 /8 OUTPUTS Qb /2 /2 /4 /2 /6 /4 /4 /6 /2 /8 /4 /6 /6 /6 /8 /8
2
ECL_CLK (991)
Ext_FB
GNDI
MR
Qc2 12
MOTOROLA
FUNCTION TABLE 2
fselFB2 0 0 0 0 1 1 1 1 fselFB1 0 0 1 1 0 0 1 1 fselFB0 0 1 0 1 0 1 0 1 QFB /2 /4 /6 /8 /8 /16 /24 /32
FUNCTION TABLE 3
Control Pin PLL_En VCO_Sel Ref_Sel MR SYNC_Sel Logic `0' Enable PLL fVCO ECL/PECL -- SYNC Outputs Logic `1' Bypass PLL fVCO/2 Test_Clk Reset Outputs Match Qc Outputs
VCO_Sel PLL_En Ref_Sel Test_Clk ECL_Clk ECL_Clk
(Pulldown) (Pulldown) (Pulldown) (Pulldown)
Qa0 Qa0 Qa1 Qa1 PHASE DETECTOR LPF VCO Qa2 Qa2 Qa3 Qa3 Qb0 Qb0 Qb1 Qb1 Qb2 Qb2 Qb3 Qb3 Qc0 Qc0 Qc1 Qc1 Qc2 Qc2
Ext_FB Ext_FB MR
(Pulldown)
FREQUENCY GENERATOR fsela0:3
(Pulldown)
SYNC
fselFB0:2
(Pulldown)
SYNC_Sel
(Pulldown)
Qd0 Qd0 Qd1 Qd1 QFB QFB
NOTE: ECL_Clk, Ext_FB have internal pulldowns, while ECL_Clk, Ext_FB have external pullups to ensure stability under open input conditions. Figure 2. MPC991 Logic Diagram
MOTOROLA
3
1:1 Mode Qa
Qc Sync (Qd) 2:1 Mode Qa VCC
Qc
Sync (Qd)
3:1 Mode Qa
Qc
Sync (Qd)
3:2 Mode Qa
Qc
Sync (Qd)
4:3 Mode Qa
Qc
Sync (Qd)
Figure 3. Timing Diagrams
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MOTOROLA
ECL DC CHARACTERISTICS (TA = 0 to 70C, VCCA = VCCI = VCCO = 0 V, GNDI = -3.3 V 5%, Note 1.)
0C Symbol VOH VOL VIH VIL VPP VCMR IIH IGNDI Characteristic Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Minimum Input Swing Common Mode Range Input HIGH Current Power Supply Current 200 Min -1.3 -2.0 -1.1 -1.8 500 VCC -1.3V VCC -0.5V 150 240 200 Typ Max -0.7 -1.4 -0.9 -1.5 Min -1.3 -2.0 -1.1 -1.8 500 VCC -1.3V VCC -0.5V 150 240 200 25C Typ -1.0 -1.7 Max -0.7 -1.4 -0.9 -1.5 Min -1.3 -2.0 -1.1 -1.8 500 VCC -1.3V VCC -0.5V 150 240 70C Typ Max -0.7 -1.4 -0.9 -1.5 Unit V V V V mV V A mA
1. Refer to Motorola Application Note AN1545/D "Thermal Data for MPC Clock Drivers" for thermal management guidelines.
PECL DC CHARACTERISTICS (TA = 0 to 70C, VCCA = VCCI = VCCO = 3.3 V 5%, GNDI = 0 V, Note 2.)
0C Symbol VOH VOL VIH VIL VPP VCMR IIH IGNDI Characteristic Output HIGH Voltage (Note 3.) Output LOW Voltage (Note 3.) Input HIGH Voltage (Note 3.) Input LOW Voltage (Note 3.) Minimum Input Swing Common Mode Range Input HIGH Current Power Supply Current 200 Min 2.0 1.3 2.2 1.5 500 VCC -1.3V VCC -0.5V 150 240 200 Typ Max 2.6 1.9 2.4 1.8 Min 2.0 1.3 2.2 1.5 500 VCC -1.3V VCC -0.5V 150 240 200 25C Typ 2.3 1.6 Max 2.6 1.9 2.4 1.8 Min 2.3 1.3 2.2 1.5 500 VCC -1.3V VCC -0.5V 150 240 70C Typ Max 2.6 1.9 2.4 1.8 Unit V V V V mV V A mA
2. Refer to Motorola Application Note AN1545/D "Thermal Data for MPC Clock Drivers" for thermal management guidelines. 3. These values are for VCC = 3.3V. Level Specifications will vary 1:1 with VCC.
AC CHARACTERISTICS (TA = 0 to 70C, VCCA = VCCI = VCCO = 3.3 V 5%, Termination of 50 to VCC - 2.0 V)
Symbol tr, tf tpw tos fVCO tpd fmax Characteristic Output Rise/Fall Time Output Duty Cycle Output-to-Output Skew PLL VCO Lock Range Ref to Feedback Offset Maximum Output Frequency Qa,Qb,Qc (/2) Qa,Qb,Qc (/4) Qa,Qb,Qc (/6) Qa,Qb,Qc (/8) 50 10 Same Frequency Different Frequencies VCO_Sel = `0' VCO_Sel = `1' 400 200 75 250 Min 0.2 47.5 50 150 250 Typ Max 1.0 52.5 250 350 800 400 425 400 200 133 100 Unit ns % ps MHz ps MHz FB /8 to /32 (Note 4.) FB /4 to /32 fref = 50MHz (Note 5.) Condition 20% to 80%
tjitter tlock
Cycle-to-Cycle Jitter (Peak-to-Peak) Maximum PLL Lock Time
ps ms
4. With VCO_Sel = `0', the PLL will be unstable with a /2, /4 and some /6 feedback configurations. With VCO_Sel = `1', the PLL will be unstable with a /2 feedback ratio. 5. tpd is specified for 50MHz input reference FB / 8. The window will shrink/grow proportionally from the minimum limit with shorter/longer input reference periods. The tpd does not include jitter.
MOTOROLA
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PLL INPUT REFERENCE CHARACTERISTICS (TA = 0 to 70C)
Symbol tr, tf fref Characteristic TCLK Input Rise/Falls Reference Input Frequency VCO_SEL='0' Feedback divide 6 Feedback divide 8 Feedback divide 16 Feedback divide 24 Feedback divide 32 Feedback divide 4 Feedback divide 6 Feedback divide 8 Feedback divide 16 Feedback divide 24 Feedback divide 32 100 50 25 16.67 12.5 50 33.3 25 12.5 8.33 6.25 25 Min Max 3.0 125 100 50 33.33 25 100 66.67 50 25 16.67 12.5 75 % Unit ns MHz Condition
VCO_SEL='1'
frefDC
Reference Input Duty Cycle
APPLICATIONS INFORMATION
Power Supply Filtering The MPC991 provides a separate power supply for the internal PLL of the device. The purpose of this design technique is to allow the user to filter externally generated system noise from the internal, relatively sensitive analog PLL. Figure 4 illustrates a suggested power supply filter using an LC filter network. The inductor value should be choosen to maximize the AC filter impedance while maintaining a low DC resistance. An inductor with a maximum DC series resistance of 5 should be used. The parallel capacitor combination on the VCCA pin ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL.
3.3V
RS 5 VCCA 0.01F VCC 0.01F 22F
Figure 4. Power Supply Filter
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MOTOROLA
OUTLINE DIMENSIONS
FA SUFFIX TQFP PACKAGE CASE 848D-03 ISSUE D
4X 4X TIPS
-X- X=L, M, N C L AB AB G
0.20 (0.008) H L-M N
0.20 (0.008) T L-M N
52 1
40 39
VIEW Y
PLATING
3X VIEW
Y -M- B V
F
BASE METAL
-L-
J
B1
13 14 26 27
V1
0.13 (0.005)
SECTION AB-AB
ROTATED 90_ CLOCKWISE
A1 S1 A S
-N-
C -H- -T-
SEATING PLANE
4X
2 0.10 (0.004) T
4X
3
NOTES: 1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. 3 DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4 DATUMS -L-, -M- AND -N- TO BE DETERMINED AT DATUM PLANE -H-. 5 DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -T-. 6 DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H . 7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). MILLIMETERS MIN MAX 10.00 BSC 5.00 BSC 10.00 BSC 5.00 BSC --1.70 0.05 0.20 1.30 1.50 0.20 0.40 0.45 0.75 0.22 0.35 0.65 BSC 0.07 0.20 0.50 REF 0.08 0.20 12.00 BSC 6.00 BSC 0.09 0.16 12.00 BSC 6.00 BSC 0.20 REF 1.00 REF 0_ 7_ --0_ 12 _ REF 5_ 13 _ INCHES MIN MAX 0.394 BSC 0.197 BSC 0.394 BSC 0.197 BSC --0.067 0.002 0.008 0.051 0.059 0.008 0.016 0.018 0.030 0.009 0.014 0.026 BSC 0.003 0.008 0.020 REF 0.003 0.008 0.472 BSC 0.236 BSC 0.004 0.006 0.472 BSC 0.236 BSC 0.008 REF 0.039 REF 0_ 7_ --0_ 12 _ REF 13 _ 5_
VIEW AA
0.05 (0.002)
S
W 1 C2
2XR
R1
0.25 (0.010)
GAGE PLANE
K C1 E Z
VIEW AA
DIM A A1 B B1 C C1 C2 D E F G J K R1 S S1 U V V1 W Z 1 2 3
MOTOROLA
CCCC EEEE CCCC EEEE
M
U
D T L-M
S
N
S
7
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