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E2I0016-17-Y1
Semiconductor MSM52V1001LP
Semiconductor 131,072-Word 8-Bit CMOS STATIC RAM
This version: Jan. 1998 MSM52V1001LP Previous version: Aug. 1996
DESCRIPTION
The MSM52V1001LP is a 131,072-word by 8-bit CMOS static RAM featuring 3.0 V to 3.6 V power supply operation in the range of -40C to 85C and direct LVCMOS input/output compatibility. Since the circuitry is completely static, external clock and refreshing operations are unnecessary, making this device very easy to use. The MSM52V1001LP can be used in the high-speed operation of an access time 100 ns due to adopting a high-performance CMOS technology and in the low current consumption of a standby current max. 50 mA when there is no chip selection. In addition, the MSM52V1001LP is the most suitable memory for microcomputer systems or data terminals because it is provided with a chip enable signal (CE1) suited to the expansion of a memory capacity, a chip enable signal (CE2) suited to a battery back-up, and an output enable signal (OE) suited to the I/O bus line control.
FEATURES
* 131,072-word 8-bit configuration * Power supply voltage: 3.0 V to 3.6 V * Fully static operation * Operating temperature range: Ta = -40C to 85C * (Input/Output) LVCMOS compatible * 3-state output * Data retention available at power supply voltage 2 V * Package options: 32-pin 600 mil plastic DIP (DIP32-P-600-2.54) 32-pin 525 mil plastic SOP (SOP32-P-525-1.27-K) 32-pin plastic TSOP (Type I) (TSOPI32-P-820-0.50-K) (TSOPI32-P-820-0.50-L)
(Product : MSM52V1001LP-xxRS) (Product : MSM52V1001LP-xxGS-K) (Product : MSM52V1001LP-xxTS-K) (Product : MSM52V1001LP-xxTS-L) xx indicates speed rank.
PRODUCT FAMILY
Family MSM52V1001LP-10 MSM52V1001LP-12 Access Time (Max.) 100 ns 120 ns Power Dissipation Operating (Max.) 126 mW 108 mW Standby (Max.) 0.18 mW
1/11
Semiconductor
PIN CONFIGURATION (TOP VIEW)
NC A14 A7 A6 A5 A4 A3
1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4
A16 2
3
A12 4
5 6 7 8 9
A2 10 A1 11 A0 12 I/O1 13 I/O2 14 I/O3 15 VSS 16 32-Pin Plastic DIP

NC 1 A16 2 A14 3 A12 4 A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O1 13 I/O2 14 I/O3 15 VSS 16 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3 OE 32 A10 31 CE1 30 I/O8 29 I/O7 28 I/O6 27 I/O5 26 I/O4 25 VSS 24 I/O3 23 I/O2 22 I/O1 21 A0 20 A1 19 A2 18 A3 17
MSM52V1001LP
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4
32-Pin Plastic SOP

A11 1 A9 2 A8 3 A13 4 WE 5 CE2 6 A15 7 VCC 8 NC 9 A16 10 A14 11 A12 12 A7 13 A6 14 A5 15 A4 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
32-Pin Plastic TSOP (I) (K Type)
32-Pin Plastic TSOP (I) (L Type)
Pin Name A0 - A16 I/O1 - I/O8 CE1, CE2 OE WE VCC, VSS NC
Function Address Input Data Input/Output Chip Enable Output Enable Write Enable Power Supply No Connection
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4
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Semiconductor
MSM52V1001LP
BLOCK DIAGRAM
A4 A5 A6 A7 A12 A14 A16 A15 A13 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8
Row Select
Memory Array 512 Rows 128 Columns 16 Blocks
VCC VSS
Input Data Control
Column I/O Circuits Column Select
A8
A9
A11 A0 A2 A10 A1 A3
CE2 CE1 WE OE
FUNCTION TABLE
Operating Mode CE1 H Read Cycle * L L H Write Cycle * L CE2 * L H H * L H WE * * H H * * L OE * * H L * * * Data Read Output Floating Data Write Output Floating Operating Contents Power Mode Standby Standby Active Active Standby Standby Active
*Don't Care ("H" or "L")
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Semiconductor
MSM52V1001LP
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Power Supply Voltage Pin Voltage Power Dissipation Operating Temperature Storage Temperature Symbol VCC VT PD Topr Tstg Condition Ta = 25C, for VSS Ta = 25C -- -- Rating -0.5 to 4.6 -0.5* to VCC + 0.5 0.7 -40 to 85 -55 to 125 Unit V V W C C
* -1.2 V Min. for pulse width less than 30 ns. Recommended Operating Conditions
Parameter Power Supply Voltage Data Retention Voltage Input High Voltage Input Low Voltage Load Capacitance Fan Out Symbol VCC VSS VCCH VIH VIL CL N Condition -- -- VCC = 3.0 V to 3.6 V -- LVCMOS Min. 3.0 0 2 2.4 -0.3* -- -- Typ. -- 0 -- -- -- -- -- Max. 3.6 0 3.6 VCC + 0.3 0.4 100 1 Unit V V V V V pF --
* -1.2 V Min. for pulse width less than 30 ns. Capacitance
Parameter Input Capacitance Input/Output Capacitance Symbol CI CI/O Condition VI = 0 V VI/O = 0 V Min. -- -- (Ta = 25C, f = 1 MHz) Max. 10 10 Unit pF pF
Note:
This parameter is periodically sampled and not 100% tested.
4/11
Semiconductor DC Characteristics
Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Symbol ILI ILO VOH VOL Condition VIN = 0 to VCC CE1 = VIH or CE2 = VIL or OE = VIH or WE = VIL, VOUT = 0 to VCC IOH = -100 mA IOL = 100 mA CE1 VCC - 0.2 V, CE2 VCC - 0.2 V or 0 V CE2 0.2 V, VIN = 0 to VCC CE1 = VIH, CE2 = VIH or CE2 = VIL CE1 = VIL, CE2 = VIH, VIN = VIH / VIL, TCYC = Min. cycle, IOUT = 0 mA Operating Power Supply Current ICCA CE1 0.2 V, CE2 VCC - 0.2 V, VIH VCC - 0.2 V, VIL 0.2 V, TCYC = 1 ms, IOUT = 0 mA
MSM52V1001LP
(VCC = 3.0 V to 3.6 V, Ta = -40C to 85C) MSM52V1001LP Min. -1.0 -1.0 VCC - 0.2 -- Typ. -- -- -- -- Max. 1.0 1.0 -- 0.2 Unit mA mA V V
Standby Power Supply Current
ICCS
--
--
50
mA
ICCS1
--
--
0.3
mA
--
--
q
mA
--
--
10
mA
q 52V1001LP-10 35 mA 52V1001LP-12 30 mA
AC Characteristics Test Conditions
Parameter Input Pulse Level Input Rise and Fall Times Input/Output Timing Level Output Load Condition VIH = 2.4 V, VIL = 0.4 V 5 ns 1.4 V CL = 100 pF, 1 LVCMOS
5/11
Semiconductor Read Cycle
MSM52V1001LP
(VCC = 3.0 V to 3.6 V, Ta = -40C to 85C) Parameter Read Cycle Time Address Access Time CE1, CE2 Access Time OE Access Time CE1, CE2 to Output in Low-Z OE to Output in Low-Z Output Hold Time from Address Change Symbol tRC tAA tCO1 tCO2 tOE tCLZ1 tCLZ2 tOLZ tOH tCHZ1 tOHZ MSM52V1001LP-10 Min. 100 -- -- -- -- 10 10 5 10 -- -- -- Max. -- 100 100 100 50 -- -- -- -- 35 35 35 MSM52V1001LP-12 Min. 120 -- -- -- -- 10 10 5 10 -- -- -- Max. -- 120 120 120 60 -- -- -- -- 35 35 35 Unit ns ns ns ns ns ns ns
ADDRESS
Notes:
, , , ,
CE1, CE2 to Output in High-Z tCHZ2 ns OE to Output in High-Z ns
tRC
tAA
tCHZ1
CE1
tCO1
tCLZ1
CE2
tCO2
tCLZ2
tCHZ2
OE
tOE
tOHZ
DOUT
Valid Data-out
tOLZ
tOH
1. 2. 3. 4.
A read cycle occurs during the overlap of CE1 = "L", CE2 = "H", OE = "L" and WE = "H". tCLZ1 and tCLZ2 are specified from CE1 = "L" or CE2 = "H", whichever occurs last. tCHZ1 and tCHZ2 are specified from CE1 = "H" or CE2 = "L", whichever occurs first. tOHZ, tCHZ1 and tCHZ2 are specified by the time when DATA is floating, not defined by the output level.
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Semiconductor Write Cycle
Parameter Write Cycle Time Address Setup Time Write Pulse Width Write Recovery Time Data Setup Time Data Hold Time WE to Output in High-Z CE1, CE2 to End of Write Symbol tWC tAS tWP tWR tDS tDH tWHZ tCW1 tAW tCW2
MSM52V1001LP
(VCC = 3.0 V to 3.6 V, Ta = -40C to 85C) MSM52V1001LP-10 Min. 100 0 75 5 40 0 -- 90 90 90 5 Max. -- -- -- -- -- -- 35 -- -- -- -- MSM52V1001LP-12 Min. 120 0 90 5 50 0 -- 100 100 100 5 Max. -- -- -- -- -- -- 35 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns
, , ,
Address Valid to End of Write Output Active from End of Write tWLZ
tWC ADDRESS tCW1 CE1 CE2 tCW2 tAW WE tAS tWR tWP tWLZ DOUT tWHZ tDS tDH DIN Data-in
Notes:
1. 2. 3. 4. 5.
A write cycle occurs during the overlap of CE1 = "L", CE2 = "H" and WE = "L". OE may be either of "H" or "L" in the write cycle. tAS is specified from CE1 = "L", CE2 = "H" or WE = "L", whichever occurs last. tWP is an overlap time of CE1 = "L", CE2 = "H" and WE = "L". tWR, tDS and tDH are specified from CE1 = "H", CE2 = "L" or WE = "H", whichever occurs first. 6. tWHZ is specified by the time when DATA output is floating, not defined by the output level. 7. When I/O pins are in the output mode, don't apply the inverted input signal to the output pins.
7/11
Semiconductor Data Retention Characteristics
Parameter Symbol Condition CE1 VCC - 0.2 V, CE2 VCC - 0.2 V or 0 V CE2 0.2 V, VIN = 0 to VCC VCC = 3 V, VIN = 0 to VCC, CE1 VCC - 0.2 V, CE2 VCC - 0.2 V or 0 V CE2 0.2 V -- -- Min. Typ.
MSM52V1001LP
(Ta = -40C to 85C) Max. Unit
Data Retention Power Supply Voltage
VCCH
2.0
--
--
V
Data Retention Power Supply Current
ICCH
--
--
40*
mA
Chip Deselect to Data Retention Time Operation Recovery Time
tCDR tR
0 50
-- --
-- --
ns ms
* 5 mA Max. when Ta = 0C to 40C. CE1 Control
tCDR VCC 3.0 V VIH VCCH CE1 0V CE1 VCC - 0.2 V Data Retention Mode tR
CE2 Control
Data Retention Mode VCC 3.0 V tCDR CE2 VCCH VIL 0V CE2 0.2 V tR
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Semiconductor
MSM52V1001LP
PACKAGE DIMENSIONS
(Unit : mm)
DIP32-P-600-2.54
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 4.70 TYP.
9/11
Semiconductor
MSM52V1001LP
(Unit : mm)
SOP32-P-525-1.27-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.32 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
10/11
Semiconductor
MSM52V1001LP
(Unit : mm)
TSOPI32-P-820-0.50-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.40 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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