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PI7C7100 3-Port PCI Bridge
Rev 1.1
Pericom Semiconductor Corporation
The Complete Interface Solution
2380 Bering Drive, San Jose, California 95131 Telephone: 1-877-PERICOM, (1-877-737-4266) Fax: (408) 435-1100, E-mail: nolimits@pericom.com Internet: http://www.pericom.com
(c) 2000 Pericom Semiconductor Corporation
09/18/00
Rev 1.1
ADVANCE INFORMATION
65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
LIFE SUPPORT POLICY
Pericom Semiconductor Corporation's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of PSC. 1.Life support devices or systems are devices or systems which: a) are intended for surgical implant into the body or b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.Pericom Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a Pericom Semiconductor product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Pericom Semiconductor Corporation. All other trademarks are of their respective companies.
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765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
Table of Contents
1. 2. 3. 3.1 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.3 4. 4.1 4.2 4.3 4.4 4.5 4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.5.6 4.6 4.6.1 4.6.2 4.6.3 4.6.4 4.6.5 4.6.6 4.7 4.7.1 4.7.2 4.7.3 4.7.4 4.8 4.8.1 4.8.2 4.8.3 4.8.3.1 4.8.3.2 4.8.3.3 4.8.4 4.8.4.1 4.8.4.2 Introduction/Product Features ............................................................................................................................... 1 PI7C7100 Block Diagram ...................................................................................................................................... 3 Signal Definitions ................................................................................................................................................... 4 Signal Types ............................................................................................................................................................ 4 Signals ...................................................................................................................................................................... 4 Primary Bus Interface Signals .................................................................................................................................. 4 Secondary Bus Interface Signals ............................................................................................................................. 6 Clock Signals ............................................................................................................................................................ 8 Miscellaneous Signals ............................................................................................................................................. 8 JTAG Boundary Scan Signals .................................................................................................................................. 9 Power and Ground .................................................................................................................................................... 9 PI7C7100 PBGA Pin Listing ..................................................................................................................................... 9 PCI Bus Operation ................................................................................................................................................ 13 Types of Transactions ........................................................................................................................................... 13 Single Address Phase ............................................................................................................................................ 14 Device Select (DEVSEL#) Generation .................................................................................................................... 14 Data Phase ............................................................................................................................................................. 14 Write Transactions ................................................................................................................................................ 14 Posted Write Transactions .................................................................................................................................... 14 Memory Write and Invalidate Transactions .......................................................................................................... 15 Delayed Write Transactions .................................................................................................................................. 15 Write Transaction Address Boundaries ................................................................................................................ 16 Buffering Multiple Write Transactions .................................................................................................................. 16 Fast Back-to-Back Write Transactions .................................................................................................................. 16 Read Transactions ................................................................................................................................................. 17 Prefetchable Read Transactions ............................................................................................................................ 17 Non-prefetchable Read Transactions .................................................................................................................... 17 Read Pre-fetch Address Boundaries ...................................................................................................................... 17 Delayed Read Requests ......................................................................................................................................... 18 Delayed Read Completion with Target .................................................................................................................. 18 Delayed Read Completion on Initiator Bus ........................................................................................................... 18 Configuration Transactions ................................................................................................................................... 19 Type 0 Access to PI7C7100 ................................................................................................................................... 19 Type 1 to Type 0 Conversion ................................................................................................................................ 20 Type 1 to Type 1 Forwarding ................................................................................................................................ 21 Special Cycles ........................................................................................................................................................ 22 Transaction Termination ........................................................................................................................................ 22 Master Termination Initiated by PI7C7100 ............................................................................................................ 23 Master Abort Received by PI7C7100 ..................................................................................................................... 23 Target Termination Received by PI7C7100 ............................................................................................................ 24 Delayed Write Target Termination Response ....................................................................................................... 24 Posted Write Target Termination Response ......................................................................................................... 24 Delayed Read Target Termination Response ........................................................................................................ 25 Target Termination Initiated by PI7C7100 ............................................................................................................. 26 Target Retry ........................................................................................................................................................... 26 Target Disconnect .................................................................................................................................................. 27
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65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
4.8.4.3 4.9 5. 5.1 5.2 5.2.1 5.2.2 5.3 5.3.1 5.3.2 5.4 5.4.1 5.4.2 6. 6.1 6.2 6.3 6.4 7. 7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.3 7.4 8. 8.1 8.2 8.3 9. 9.1 9.2 9.2.1 9.2.2 9.2.3 10. 10.1 10.2 11. 11.1 11.2 11.3 12. 12.1 12.2 13.
Target Abort .......................................................................................................................................................... 27 Concurrent Mode Operation .................................................................................................................................. 27 Address Decoding .................................................................................................................................................. 28 Address Ranges ..................................................................................................................................................... 28 I/O Address Decoding ........................................................................................................................................... 28 I/O Base and Limit Address Registers ................................................................................................................... 28 ISA Mode ............................................................................................................................................................... 29 Memory Address Decoding ................................................................................................................................... 29 Memory-Mapped I/O Base and Limit Address Registers ...................................................................................... 30 Prefetchable Memory Base and Limit Address Registers ...................................................................................... 30 VGA Support .......................................................................................................................................................... 31 VGA Mode ............................................................................................................................................................. 31 VGA Snoop Mode .................................................................................................................................................. 31 Transaction Ordering ........................................................................................................................................... 32 Transactions Governed by Ordering Rules ........................................................................................................... 32 General Ordering Guidelines .................................................................................................................................. 32 Ordering Rules ....................................................................................................................................................... 33 Data Synchronization ............................................................................................................................................. 34 Error Handling ...................................................................................................................................................... 35 Address Parity Errors ............................................................................................................................................. 35 Data Parity Errors ................................................................................................................................................... 35 Configuration Write Transactions to Configuration Space ................................................................................... 35 Read Transactions ................................................................................................................................................. 36 Delayed Write Transactions .................................................................................................................................. 36 Posted Write Transactions .................................................................................................................................... 38 Data Parity Error Reporting Summary .................................................................................................................... 39 System Error (SERR#) Reporting ........................................................................................................................... 45 Exclusive Access ................................................................................................................................................... 46 Concurrent Locks ................................................................................................................................................... 46 Acquiring Exclusive Access across PI7C7100 ....................................................................................................... 46 Ending Exclusive Access ....................................................................................................................................... 47 PCI Bus Arbitration .............................................................................................................................................. 48 Primary PCI Bus Arbitration ................................................................................................................................... 48 Secondary PCI Bus Arbitration ............................................................................................................................. 48 Secondary Bus Arbitration Using the Internal Arbiter .......................................................................................... 48 Secondary Bus Arbitration Using an External Arbiter ........................................................................................... 49 Bus Parking ............................................................................................................................................................ 49 Clocks .................................................................................................................................................................... 50 Primary Clock Inputs .............................................................................................................................................. 50 Secondary Clock Outputs ...................................................................................................................................... 50 Reset ...................................................................................................................................................................... 51 Primary Interface Reset .......................................................................................................................................... 51 Secondary Interface Reset ..................................................................................................................................... 51 Chip Reset .............................................................................................................................................................. 51 Supported Commands ............................................................................................................................................ 52 Primary Interface .................................................................................................................................................... 52 Secondary Interface ............................................................................................................................................... 54 Configuration Registers ....................................................................................................................................... 55
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765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
13.1 13.2 13.2.1 13.2.2 13.2.3 13.2.4 13.2.5 13.2.6 13.2.7 13.2.8 13.2.9 13.2.10 13.2.11 13.2.12 13.2.13 13.2.14 13.2.15 13.2.16 13.2.17 13.2.18 13.2.19 13.2.20 13.2.21 13.2.22 13.2.23 13.2.24 13.2.25 13.2.26 13.2.27 13.2.28 13.2.29 13.2.30 13.2.31 13.2.32 13.2.33 13.2.34 13.2.35 13.2.36 13.2.37 13.2.38 13.2.39 13.2.40 13.2.41 13.2.42 13.2.43 13.2.44 13.2.45 13.2.46 13.2.47 13.2.48
Config Register 1 .................................................................................................................................................... 55 Config Register 2 .................................................................................................................................................... 56 Config Register 1 or 2:Vendor ID Register (read only, bit 15-0; offset 00h) .......................................................... 57 Config Register 1: Device ID Register (read only, bit 31-16; offset 00h) ............................................................... 57 Config Register 2: Device ID Register (read only, bit 31-16; offset 00h) ............................................................... 57 Config Register 1: Command Register (bit 15-0; offset 04h) .................................................................................. 57 Config Register 2: Command Register (bit 15-0; offset 04h) .................................................................................. 58 Config Register 1 or 2: Status Register (for primary bus, bit 31-16; offset 04h) ..................................................... 59 Config Register 1 or 2: Revision ID Register (read only, bit 7-0; offset 08h) ......................................................... 60 Config Register 1 or 2: Class Code Register (read only, bit 31-8; offset 08h) ........................................................ 60 Config Register 1 or 2: Cache Line Size Register (read/write, bit 7-0; offset 0Ch) ................................................. 60 Config Register 1: Primary Latency Timer Register (read/write, bit 15-8; offset 0Ch) ............................................ 60 Config Register 2: Primary Latency Timer Register (read/write, bit 15-8; offset 0Ch) ............................................ 60 Config Register 1: Header Type Register (read only, bit 23-16; offset 0Ch) .......................................................... 60 Config Register 2: Header Type Register (read only, bit 23-16; offset 0Ch) .......................................................... 60 Config Register 1: Primary Bus Number Register (read/write, bit 7-0; offset 18h) ................................................. 60 Config Register 2: Primary Bus Number Register (read/write, bit 7-0; offset 18h) ................................................. 60 Config Register 1 or 2: Secondary Bus Number Register (read/write, bit 15-8; offset 18h) ................................... 60 Config Register 1 or 2: Subordinate Bus Number Register (read/write, bit 23-16; offset 18h) ............................... 60 Config Register 1 or 2: Secondary Latency Timer (read/write, bit 31-24; offset 18h) ............................................ 60 Config Register 1 or 2: I/O Base Register (read/write, bit 7-0; offset 1Ch) ............................................................ 60 Config Register 1 or 2: I/O Limit Register (read/write, bit 15-8; offset 1Ch) ........................................................... 60 Config Register 1 or 2: Secondary Status Register (bit 31-16; offset 1Ch) ............................................................ 61 Config Register 1 or 2: Memory Base Register (read/write, bit 15-0; offset 20h) ................................................... 62 Config Register 1 or 2: Memory Limit Register (read/write, bit 31:16; offset 20h) ................................................. 62 Config Register 1 or 2: Prefetchable Memory Base Register (read/write, bit 15-0;offset 24h) ............................... 62 Config Register 1 or 2: Prefetchable Memory Limit Register (read/write, bit 31-16; offset 24h) ............................ 62 Config Register 1 or 2: I/O Base Address Upper 16 Bits Register (read/write, bit 15-0; offset 30h) ...................... 62 Config Register 1 or 2: I/O Limit Address Upper 16 Bits Register (read/write, bit 31-16; offset 30h) .................... 62 Config Register 1 or 2: Subsystem Vendor ID (read/write, bit 15-0; offset 34h) .................................................... 62 Config Register 1 or 2: Subsystem ID (read/write, bit 31-16; offset 34h) ............................................................... 62 Config Register 1 or 2: Interrupt Pin Register (read only, bit 15-8; offset 3Ch) ..................................................... 62 Config Register 1 or 2: Bridge Control Register (bit 31-16; offset 3Ch) ................................................................. 63 Config Register 1 or 2: Diagnostic/Chip Control Register (bit 15-0; offset 40h) .................................................... 64 Config Register 1 or 2: Arbiter Control Register (bit 31-16; offset 40h) ................................................................. 64 Config Register 1: Primary Prefetchable Memory Base Register (Read/Write, bit 15-0; offset 44h) ..................... 65 Config Register 2: Primary Prefetchable Memory Base Register (Read/Write, bit 15-0; offset 44h) ..................... 65 Config Register 1: Primary Prefetchable Memory Limit Register (Read/Write, bit 31-16; offset 44h) .................... 65 Config Register 2: Primary Prefetchable Memory Limit Register (Read/Write, bit 31-16; offset 44h) .................... 65 Config Register 1 or 2: P_SERR# Event Disable Register (bit 7-0; offset 64h) ...................................................... 65 Config Register 1: Secondary Clock Control Register (bit 15-0; offset 68h) .......................................................... 66 Config Register 2: Secondary Clock Control Register (bit 15-0; offset 68h) .......................................................... 66 Config Register 1 or 2: Non-Posted Memory Base Register (read/write, bit 15-0; offset 70h) .............................. 67 Config Register 1 or 2: Non-Posted Memory Limit Register (read/write, bit 31-16; offset 70h) ............................. 67 Config Register 1: Port Option Register (bit 15-0; offset 74h) ............................................................................... 67 Config Register 2: Port Option Register (bit 15-0; offset 74h) ............................................................................... 68 Config Register 1 or 2: Master Timeout Counter Register (read/write, bit 31-16; offset 74h) ................................ 69 Config Register 1 or 2: Retry Counter Register (read/write, bit 31-0; offset 78h) .................................................. 69 Config Register 1 or 2: Sampling Timer Register (read/write, bit 31-0; offset 7Ch) ................................................ 69 Config Register 1 or 2: Successful I/O Read Count Register (read/write, bit 31-0; offset 80h) ............................. 69
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ADVANCE INFORMATION
65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
13.2.49 13.2.50 13.2.51 13.2.52 13.2.53 13.2.54 13.2.55 14. 14.1 14.2 14.3 14.3.1 14.3.2 14.3.3 14.3.4 15. 15.1 15.1.1 15.1.2 15.2 15.3 15.4 15.5 15.6 16. 16.1 16.2 16.3 16.4 16.5 17. 17.1
Config Register 1 or 2: Successful I/O Write Count Register (read/write, bit 31-0; offset 84h) ............................. 69 Config Register 1 or 2: Successful Memory Read Count Register (read/write, bit 31-0; offset 88h) ..................... 69 Config Register 1 or 2: Successful Memory Write Count Register (read/write, bit 31-0; offset 8Ch) .................... 69 Config Register 1: Primary Successful I/O Read Count Register (read/write, bit 31-0; offset 90h) ....................... 69 Config Register 1: Primary Successful I/O Write Count Register (read/write, bit 31-0; offset 94h) ....................... 69 Config Register 1: Primary Successful Memory Read Count Register (read/write, bit 31-0; offset 98h) ............... 69 Config Register 1: Primary Successful Memory Write Count Register (read/write, bit 31-0; offset 9Ch) .............. 69 Bridge Behavior .................................................................................................................................................... 70 Bridge Actions for Various Cycle Types ............................................................................................................... 70 Transaction Ordering ............................................................................................................................................. 70 Abnormal Termination (Initiated by Bridge Master) ............................................................................................. 71 Master Abort ......................................................................................................................................................... 71 Parity and Error Reporting ..................................................................................................................................... 71 Reporting Parity Errors ........................................................................................................................................... 71 Secondary IDSEL mapping .................................................................................................................................... 71 IEEE 1149.1 Compatible JTAG Controller ........................................................................................................... 72 Boundary Scan Architecture ................................................................................................................................. 72 TAP Pins ................................................................................................................................................................ 72 Instruction Register ............................................................................................................................................... 72 Boundary Scan Instruction Set .............................................................................................................................. 73 TAP Test Data Registers ....................................................................................................................................... 74 Bypass Register ..................................................................................................................................................... 74 Boundary-Scan Register ......................................................................................................................................... 74 TAP Controller ....................................................................................................................................................... 74 Electrical and Timing Specifications .................................................................................................................... 79 Maximum Ratings ................................................................................................................................................... 79 3.3V DC Specifications ........................................................................................................................................... 79 3.3V AC Specifications ........................................................................................................................................... 80 Primary and Secondary buses at 33 MHz clock timing .......................................................................................... 80 Power Consumption ............................................................................................................................................... 80 256-Pin PBGA Package ........................................................................................................................................... 81 Part Number Ordering Information ........................................................................................................................ 81
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765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
List of Figures
1-1. 1-2. 1-3. 2-1. 9-1. 15-1. 16-1. 17-1. PI7C7100 on the System Board .................................................................................................................................... 2 PI7C7100 in Redundant Applications .......................................................................................................................... 2 PI7C7100 on Network Switching Hub .......................................................................................................................... 2 PI7C7100 Block Diagram .............................................................................................................................................. 3 Secondary Arbiter Example ....................................................................................................................................... 48 Test Access Port Block Diagram ............................................................................................................................... 72 PCI Signal Timing Measurement Conditions ............................................................................................................ 80 256-Pin PBGA Package Drawing ................................................................................................................................ 81
List of Tables
4-1. 4-2. 4-3. 4-4. 4-5. 4-6. 4-7. 4-8. 4-9. 6-1. 7-1. 7-2. 7-3. 7-4. 7-5. 7-6. 7-7. 15-1. 15-2. PCI Transaction ......................................................................................................................................................... 13 Write Transaction Forwarding .................................................................................................................................. 14 Write Transaction Disconnect Address Boundaries ................................................................................................ 16 Read Pre-fetch Address Boundaries ......................................................................................................................... 17 Read Transaction Pre-fetching .................................................................................................................................. 18 Device Number to IDSEL S1_AD or S2_AD Pin Mapping ....................................................................................... 21 Delayed Write Target Termination Response ........................................................................................................... 24 Responses to Posted Write Target Termination ....................................................................................................... 25 Responses to Delayed Read Target Termination ...................................................................................................... 25 Summary of Tranaction Ordering .............................................................................................................................. 33 Setting the Primary Interface Detected Parity Error Bit ............................................................................................. 39 Setting the Secondary Interface Detected Parity Error Bit ........................................................................................ 40 Setting the Primary Interface Data Parity Detected Bit .............................................................................................. 40 Setting the Secondary InterfaceData Parity Detected Bit ......................................................................................... 41 Assertion of P_PERR# ............................................................................................................................................... 42 Assertion of S_PERR# ............................................................................................................................................... 43 Assertion of P_SERR# for Data Parity Errors ........................................................................................................... 44 TAP Pins .................................................................................................................................................................... 73 JTAG Boundary Register Order ................................................................................................................................ 75
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PI7C7100 3-Port PCI Bridge
Appendix A - Timing Diagrams
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. Configuration Read Transaction ................................................................................................................................. A-3 Configuration Write Transaction ................................................................................................................................A-3 Type 1 to Type 0 Configuration Read Transaction (P S) ......................................................................................A-3 Type 1 to Type 0 Configuration Write Transaction (P S) .....................................................................................A-4 Upstream Type 1 to Special Cycle Transaction (S P) ............................................................................................. A-4 Downstream Type 1 to Special Cycle Transaction (P S) ........................................................................................ A-5 Downstream Type 1 to Type 1 Configuration Read Transaction (P S) ..................................................................A-5 Downstream Type 1 to Type 1 Configuration Write Transaction (P S) .................................................................A-6 Upstream Delayed Burst Memory Read Transaction (S P) ...................................................................................A-6 Downstream Delayed Burst Memory Read Transaction (P S) ..............................................................................A-7 Downstream Delayed Memory Read Transaction (P/33MHz S/33MHz) ............................................................... A-7 Downstream Delayed Memory Read Transaction (S2/33MHz S1/33MHz) ...........................................................A-8 Downstream Delayed Memory Read Transaction (S1/33MHz S2/33MHz) ...........................................................A-8 Upstream Delayed Memory Read Transaction (S/33MHz P/33MHz) ...................................................................A-9 Downstream Posted Memory Write Transaction (P/33MHz S/33MHz) ................................................................ A-9 Downstream Posted Memory Write Transaction (S2/33MHz S1/33MHz) ........................................................... A-10 Downstream Posted Memory Write Transaction (S1/33MHz S2/33MHz) ........................................................... A-10 Upstream Posted Memory Write Transaction (S/33MHz P/33MHz) ................................................................... A-11 Downstream Flow-Through Posted Memory Write Transaction (P/33MHz S/33MHz) ........................................ A-11 Downstream Flow-Through Posted Memory Write Transaction (S2/33MHz S1/33MHz) .................................... A-12 Downstream Flow-Through Posted Memory Write Transaction (S1/33MHz S2/33MHz) .................................... A-12 Upstream Flow-Through Posted Memory Write Transaction (S/33MHz P/33MHz) ............................................ A-13 Downstream Delayed I/O Read Transaction (P S) ............................................................................................... A-13 Downstream Delayed I/O Read Transaction (S2/33MHz S1/33MHz) .................................................................. A-14 Downstream Delayed I/O Read Transaction (S1/33MHz S2/33MHz) .................................................................. A-14 Downstream Delayed I/O Read Transaction (S/33MHz P/33MHz) ...................................................................... A-15 Downstream Delayed I/O Write Transaction (P S) .............................................................................................. A-15 Downstream Delayed I/O Write Transaction (S2/33MHz S1/33MHz) ................................................................. A-16 Downstream Delayed I/O Write Transaction (S1/33MHz S2/33MHz) ................................................................. A-16 Upstream Delayed I/O Write Transaction (S P) ................................................................................................... A-17
Appendix B - Evaluation Board User's Manual
General Information ........................................................................................................................................................... B-3 Frequently Asked Questions ............................................................................................................................................ B-5
Appendix C - Three-Port PCI Bridge Evaluation Board Schematics
PCI Chip ............................................................................................................................................................................. C-3 PCI Edge Connector .......................................................................................................................................................... C-4 Secondary 1 PCI Bus ......................................................................................................................................................... C-5 Secondary 2 PCI Bus ......................................................................................................................................................... C-6 Top View ............................................................................................................................................................................ C-7
Appendix D - Representatives and Distributors
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PI7C7100 3-Port PCI Bridge
1. Introduction Product Description
PI7C7100 is the first triple port PCI-to-PCI Bridge device designed to be fully compliant with the 32-bit, 33 MHz implementation of the PCI Local Bus Specification, Revision 2.1. PI7C7100 supports only synchronous bus transactions between devices on the primary 33 MHz bus and the secondary buses operating at 33 MHz. The primary and the secondary buses can also operate in concurrent mode, resulting in added increase in system performance. Concurrent bus operation off-loads and isolates unnecessary traffic from the primary bus; thereby enabling a master and a target device on the same secondary PCI bus to communicate even while the primary bus is busy.
Product Features
* 32-bit Primary & two Secondary Ports run up to 33 MHz * All three ports compliant with the PCI Local Bus Specification, Revision 2.1 * Compliant with PCI-to-PCI Bridge Architecture Specification, Revision 1.0. - All I/O and memory commands - Type 1 to Type 0 configuration conversion - Type 1 to Type 1 configuration forwarding - Type 1 configuration-write to special cycle conversion * Concurrent primary to secondary bus operation and independent intra-secondary port channel to reduce traffic on the primary port * Provides internal arbitration for two sets of eight secondary bus masters - Programmable 2-level priority arbiter - Disable control for use of external arbiter * Supports posted write buffers on all directions * Three 128 byte FIFOs for delay transactions * Three 128 byte FIFOs for posted memory transactions * Enhanced address decoding - 32-bit I/O address range - 32-bit memory-mapped I/O address range - VGA addressing and VGA palette snooping - ISA-aware mode for legacy support in the first 64KB of I/O address range * Interrupt Handling - PCI interrupts are routed through an external interrupt concentrator * Supports system transaction ordering rules * Hot-plug support on secondary buses - 3-State control of output buffers * IEEE 1149.1 JTAG interface support * 3.3V core; 3.3V PCI I/O interface with 5V I/O Tolerant * 256-pin plastic BGA package
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65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
CPU System Memory NB S1 PCI Bus PI7C7100 PCI Device PCI Device
PI7C7100 3-Port PCI Bridge
Figure 1-1. PI7C7100 on the System Board
Master Controller
System Primary PCI Bus
Figure 1-2. PI7C7100 in Redundant Application
Slot
Slot
S2 PCI Bus
Redundant Controller
System Primary PCI Bus
PI7C7100
PI7C7100
S2 S1
S1 S2
S1 PCI Bus
S2 PCI Bus
CPU
Core Logic
PCI Bus 32/33
Fast Ethernet Internal Slot
L2 Cache
PCI Bus 32/33
PI7C7100
PI7C7100
PI7C7100
I/O Daughter Board to Isolate Traffic
Figure 1-3. PI7C7100 on Network Switching Hub
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765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
2. PI7C7100 Block Diagram
Configuration Register #1 Arbiter
Transaction Queue #1 Primary PCI Bus Primary Interface
Secondary Interface A
Secondary PCI Bus A
Transaction Queue #2 Secondary PCI Bus B
Transaction Queue #3
Secondary Interface B
Configuration Register #2
Arbiter
Figure 2-1. PI7C7100 Block Diagram
3
09/18/00 Rev 1.1
ADVANCE INFORMATION
65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
3. Signal Definitions
3.1 Signal Types
Signal Type PI PIU PB PO PSTS PTS POD CI CIU CID CTO Description PCI Input (3.3V, 5V tolerant) PCI Input (3.3V, 5V tolerant) with weak pull-up PCI 3-state bidirectional (3.3V, 5V tolerant) PCI Output (3.3V) PCI Sustained 3-state bidirectional (Active LOW signal which must be driven inactive for one cycle before being 3-stated to ensure HIGH performance on a shared signal line) PCI 3-state Output PCI Output which either drives LOW (active state) or 3-stated CMOS Input CMOS Input with weak pull-up CMOS Input with weak pull-down CMOS 3-state Output
3.2 Signals (Note: Signal name that ends with character `#' is active LOW.)
3.2.1 Primary Bus Interface Signals
Name P_AD[31:0] Pin # Type Description P rimary Address/D ata. Multi plexed address and data bus. A ddress i s indicated by P_FRAME# assertion. Write data is stable and valid when P_IRDY# is asserted and read data is stable and valid when P_TRDY# is asserted. Data is transferred on rising clock edges when both P_IRDY# and P_TRDY# are asserted. During bus idle, PI7C7100 drives P_AD to a valid logic level when P_GNT# is asserted. Y7, W7, Y8, W8, V8, PB U8, Y9, W9, W10, V10, Y11, V11, U11, Y12, W12, V12, V16, W16, Y16, W17, Y17, U18, W18, Y18, U19, W19, Y19, U20, V20, Y20, T17, R17 V9, U12, U16, V19 PB
P_CBE[3:0]
Primary Command/Byte Enables. Multiplexed command field and byte enable field. During address phase, the initiator drives the transaction type on these pins. After that the initiator drives the byte enables during data phases. During bus idle, PI7C7100 drives P_CBE[3:0] to a valid logic level when P_GNT# is asserted. P rima ry P a rity. P a ri ty i s e ve n a c ro s s P _ A D [3 1 :0 ], P _ C B E [3 :0 ], a nd P_PAR (i.e. an even number of '1's). P_PAR is an input and is valid and s ta b le o ne c yc le a fte r the a d d re s s p ha s e (i nd i c a te d b y a s s e rti o n o f P_FRAME#) for address parity. For write data phases, P_PAR is an input and i s vali d one clock after P_IRD Y# i s asserted. For read data phase, P _PA R i s an output and i s vali d one clock after P _TRD Y# i s asserted. Signal P_PAR is tri-stated one cycle after the PAD lines are 3-stated. During bus i dle, PI7C 7100 dri ves PPAR to a vali d logi c level when P_GNT# i s asserted.
P_PAR
U15
PB
P_FRAME#
W13
PSTS Primary FRAME (Active LOW). Driven by the initiator of a transaction to i ndi cate the begi nni ng and durati on of an access. The de-asserti on of P_FRAME# indicates the final data phase requested by the initiator. Before being 3-stated, it is driven to a de-asserted state for one cycle.
4
09/18/00 Rev 1.1
ADVANCE INFORMATION
765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
3.2.1 Primary Bus Interface Signals (continued)
Name P_IRDY# Pin # V 13 Type PSTS Description Primary IRDY (Active LOW). Driven by the initiator of a transaction to indicate its ability to complete current data phase on the primary side. Once asserted in a data phase, it is not de-asserted until end of data phase. Before being 3-stated, it is driven to a de-asserted state for one cycle. Primary TRDY (Active LOW). Driven by the target of a transaction to indicate its ability to complete current data phase on the primary side. Once asserted in a data phase, it is not de-asserted until end of data phase. Before being 3-stated, it is driven to a de-asserted state for one cycle. Primary Device Select (Active LOW). Asserted by the target indicating that the device is accepting the transaction. As a master, PI7C7100 waits for the assertion of this signal within 5 cycles of P_FRAME# assertion; otherwise, terminate with master abort. Before being 3-stated, it is driven to a de-asserted state for one cycle. Primary STOP (Active LOW). Asserted by the target indicating that the target is requesting the initiator to stop the current transaction. Before being 3-stated, it is driven to a de-asserted state for one cycle. Primary LOCK (Active LOW). Asserted by master for multiple transactions to complete. Primary ID Select. Used as chip select line for Type 0 configuration access to PI7C7100 configuration space. Primary Parity Error (Active LOW). Asserted when a data parity error is detected for data received on the primary interface. Before being 3-stated, it is driven to a deasserted state for one cycle. Primary System Error (Active LOW). Can be driven LOW by any device to indicate a system error condition, PI7C7100 drives this pin on: * Address parity error * Posted write data parity error on target bus * Secondary S1_SERR# or S2_SERR# asserted * Master abort during posted write transaction * Target abort during posted write transaction * Posted write transaction discarded * Delayed write request discarded * Delayed read request discarded * Delayed transaction master timeout This signal requires an external pull-up resistor for proper operation. Primary Request (Active LOW). This is asserted by PI7C7100 to indicate that it wants to start a transaction on the primary bus. PI7C7100 de-asserts this pin for at least 2 PCI clock cycles before asserting it again. Primary Grant (Active LOW). When asserted, PI7C7100 can access the primary bus. During idle and P_GNT# asserted, PI7C7100 will drive P_AD, P_CBE and P_PAR to valid logic levels. Primary RESET (Active LOW). When P_RESET# is active, all PCI signals should be asynchronously 3-stated. Primary FIFO FLUSH (Active LOW). When P_FLUSH# is active, all primary FIFO(s) are cleared (invalidate all primary transactions). This signal should be pulled to a static "high." Reserved for Future Use. Must be tied to ground.
P_TRDY#
U13
PSTS
P _D E V S E L#
Y14
PSTS
P_STOP#
W14
PSTS
P_LOCK# P_IDSEL P_PERR#
V 14 Y10 Y15
PSTS PI PSTS
P_SERR#
W15
POD
P_REQ#
W6
PTS
P_GNT#
U7
PI
P_RESET# P_FLUSH#
Y5 W5
PI PI
P_M66EN
V 18
-
5
09/18/00 Rev 1.1
ADVANCE INFORMATION
65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
3.2.2 Secondary Bus Interface Signals
Name S1_AD[31:0], Pin # B 20, B 19, C 20, C 19, C 18, D 20, D 19, D 17, E 19, E 18, E 17, F 20, F19, F17, G20, G19, L20, L19, L18, M20, M19, M17, N20, N19, N18, N17, P17, R20, R19, R18, T20, T19 J4, H1, H2, H3, H4, G1, G3, G4, F2, F3, F4, E1, E 4, D 1, C 1, B 1, C 5, B 5, D 6, C 6, B 6, A 6, C 7, B 7, D 8, C 8, D 9, C 9, B 9, A 9, D 10, C 10 E20, G18, K17, P20 F 1, A 1, A 4, A 7 Type PB Description Secondary Address/Data. Multiplexed address and data bus. Address is indicated by S1_FRAME# or S2_FRAME# assertion. Write data is stable and valid when S1_IRDY# or S2_IRDY# is asserted and read data is stable and valid when S1_TRDY# or S2_TRDY# is asserted. Data is transferred on rising clock edges when both S1_IRDY# and S1_TRDY# or S2_IRDY# and S2_TRDY# are asserted. During bus idle, PI7C7100 drives S1_AD or S2_AD to a valid logic level when the S1_GNT# or S2_GNT# is asserted respectively.
S2_AD[31:0]
S1_CBE[3:0], S2_CBE[3:0]
PB
Secondary Command/Byte Enables. Multiplexed command field and byte enable field. During the address phase, the initiator drives the transaction type on these pins. After that the initiator drives the byte enables during data phases. During bus idle, PI7C7100 drives S1_CBE[3:0] or S2_CBE[3:0] to a valid logic level when the internal grant is asserted. Secondary Parity. Parity is even across S1_AD[31:0], S1_CBE[3:0], and S1_PAR or S2_AD[31:0], S2_CBE[3:0], and S2_PAR (i.e. an even number of '1's). S1_PAR or S2_PAR is an input and is valid and stable one cycle after the address phase (indicated by assertion of S1_FRAME# or S2_FRAME#) for address parity. For write data phases, S1_PAR or S2_PAR is an input and is valid one clock after S1_IRDY# or S2_IRDY# is asserted. For read data phase, S1_PAR or S2_PAR is an output and is valid one clock after S1_TRDY# or S2_TRDY# is asserted. Signal S1_PAR or S2_PAR is 3-stated one cycle after the S1_AD or S2_AD lines are tri-stated. During bus idle, PI7C7100 drives S1_PAR or S2_PAR to a valid logic level when the internal grant is asserted. Secondary FRAME (Active LOW). Driven by the initiator of a transaction to indicate the beginning and duration of an access. De-assertion of S1_FRAME# or S2_FRAME# indicates the final data phase requested by initiator. Before being 3-stated, it is driven to a de-asserted state for one cycle. Secondary IRDY (Active LOW). Driven by the initiator of a transaction to indicate its ability to complete the current data phase on the primary side. Once asserted in a data phase, it is not de-asserted until end of the data phase. Before being 3-stated, it is driven to a de-asserted state for one cycle. Secondary TRDY (Active LOW). Driven by the target of a transaction to indicate its ability to complete the current data phase on the primary side. Once asserted in a data phase, it is not de-asserted until end of the data phase. Before being 3-stated, it is driven to a de-asserted state for one cycle. Secondary Device Select (Active LOW). Asserted by the target indicating that the device is accepting the transaction. As a master, PI7C7100 waits for the assertion of this signal within 5 cycles of S1_FRAME# or S2_FRAME# assertion; otherwise, terminate with master abort. Before being 3-stated, it is driven to a de-asserted state for one cycle.
S1_PAR, S2_PAR
K 18, B4
PB
S1_FRAME#, S2_FRAME#
H20, D2
PSTS
S1_IRDY#, S2_IRDY#
H19, B2
PSTS
S1_TRDY#, S2_TRDY#
H18, A2
PSTS
S 1_D E V S E L#, S 2_D E V S E L#
J2 0 , D3
PSTS
6
09/18/00 Rev 1.1
ADVANCE INFORMATION
765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
3.2.2 Secondary Bus Interface Signals (continued)
Name S1_STOP#, S2_STOP# Pin # J1 9 , C3 Type PSTS Description Secondary STOP (Active LOW). Asserted by the target indicating that the target is requesting the initiator to stop the current transaction. Before being 3-stated, it is driven to a de-asserted state for one cycle. Secondary LOCK (Active LOW). Asserted by master for multiple transactions to complete. Secondary Parity Error (Active LOW). Asserted when a data parity error is detected for data received on the secondary interface. Before being 3-stated, it is driven to a de-asserted state for one cycle. Secondary System Error (Active LOW). Can be driven LOW by any device to indicate a system error condition. Secondary Request (Active LOW). This is asserted by an external device to indicate that it wants to start a transaction on the Secondary bus. The input is externally pulled up through a resistor to VDD.
S1_LOCK#, S2_LOCK# S1_PERR#, S2_PERR# S1_SERR#, S2_SERR# S1_REQ#[7:0],
J1 8 , B3 J1 7 , D4 K 20, C4 B11, A12, D 13, C 13, C 15, A 16, C 17, B 17 T2, R3, P2, P1, M2, M1, K 1, K 3 C11, B12, B 13, A 14, D 14, B 16, D 16, B 18 U1, P4, R1, N4, M3, L4, L1, K 2 B 10, T4
PSTS PSTS
PI PIU
S2_REQ#[7:0]
S1_GNT#[7:0],
PO
S2_GNT#[7:0]
Secondary Grant (Active LOW). PI7C7100 asserts this pin to access the secondary bus. PI7C7100 de-asserts this pin for at least 2 PCI clock cycles before asserting it again. During idle and S1_GNT# or S2_GNT# asserted, PI7C7100 will drive S1_AD, S1_CBE and S1_PAR or S2_AD, S2_CBE and S2_PAR to valid logic levels.
S1_RESET#, S2_RESET#
PO
Secondary RESET (Active LOW). Asserted when any of the following conditions are met: 1. Signal P_RESET# is asserted. 2. Secondary reset bit in bridge control register in configuration space is set. When asserted, all control signals are 3-stated and zeros are driven on S1_AD, S1_CBE, and S1_PAR or S2_AD, S2_CBE, and S2_PAR. Secondary Enable (Active HIGH). When S1_EN or S2_EN is inactive, secondary PCI S1 or S2 bus will be asynchronously 3-stated. Reserved for Future Use. Must be tied to ground. Secondary Bus Central Function Control Pin. When tied LOW, it enables the internal arbiter. When tied HIGH, an external arbiter must be used. S1_REQ0# or S2_REQ0# is reconfigured to be the secondary bus grant input, and S1_GNT0# or S2_GNT0# is reconfigured to be the secondary bus request output.
S1_EN, S 2_E N S_M66EN S_CFN#
W3, W4 D7 Y2
PIU - CIU
7
09/18/00 Rev 1.1
ADVANCE INFORMATION
65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
3.2.3 Clock Signals
Name P _C LK Pin # V6 Type PI Description Primary Clock Input. Provides timing for all transaction on primary interface. Secondary Clock Output. Provides secondary clocks phase synchronous with the P_CLK.
S_CLKOUT T3, T1, P3, PTS [15:0] N3,M4, L3, L2, J1,A11, C12, A 13, B 14, B 15, C 16, A 18, A 19
3.2.4 Miscellaneous Signals
Name BYPASS PLL_TM S_CLKIN Pin # Y4 Y3 V5 Type - - PI Description Reserved for Future Use. Must be tied HIGH. Reserved for Future Use. Must be tied LOW. Secondary Test Clock Input. It should be tied to LOW in normal mode. It also may be a secondary clock input for the secondary buses if both SCAN_TM# and SCAN_EN are connected to logic "1". Full-scan Test Mode enable (Active LOW). When SCAN_TM# is active, the twelve scan chains will be enabled. The scan clock is P_CLK. The scan inputs and outputs are as follows: S1_REQ[7], S1_REQ[6], S1_REQ[5], S1_REQ[4], S1_REQ[3], S1_REQ[2], S2_REQ[7], S2_REQ[6], S2_REQ[5], S2_REQ[4], S2_REQ[3], S2_REQ[2] and S1_GNT[7], S1_GNT[6], S1_GNT[5], S1_GNT[4], S1_GNT[3], S1_GNT[2], S2_GNT[7], S2_GNT[6], S2_GNT[5], S2_GNT[4], S2_GNT[3], S2_GNT[2] respectively Full-scan Enable Control. When SCAN_EN is LOW, full-scan is in shift operation if SCAN_TM# is active. When SCAN_EN is HIGH, full-scan is in parallel operation if SCAN_TM# is active. SCAN_EN should be tied LOW in normal mode. If SCAN_TM# and SCAN_EN are connected to logic "1", S_CLKIN is the clock source for the internal secondary clock. If SCAN_TM# is connected to logic "1" and SCAN_EN is connected to logic "0", P_CLK is the clock source for the internal secondary clock. Note: During power-up, SCAN_EN is the reset signal for the on-chip PLL. Reserved for Future Use. Reserved
SCAN_TM#
V4
CI
SCAN_EN
U5
CIU
CMPO1 Reserved
U6 R4
-
3.2.5 JTAG Boundary Scan Signals
Name TCK TMS TDO TDI TRST# Pin # V2 W1 V3 W2 U3 Type CIU CIU CTO CIU CIU Description Test Clock. Used to clock state information and data into and out of the PI7C7100 during boundary scan. Test Mode Select. Used to control the state of the Test Access Port controller. Test Data Output. When SCANEN is HIGH it is used (in conjunction with TCK) to shift data out of the Test Access Port (TAP) in a serial bit stream. Test Data Input. When SCANEN is HIGH it is used (in conjunction with TCK) to shift data and instructions into the Test Access Port (TAP) a serial bit stream. Test Reset. Active LOW signal to reset the Test Access Port (TAP) controller into an initialized state.
8
09/18/00 Rev 1.1
ADVANCE INFORMATION
765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
3.2.6 Power and Ground
Name VD D VSS Pin # B8, C14, D5, D11, D15, E2, F18, J3, L17, N2, P19, U10, V1, V7, V15, W20 A 3, A 5, A 8, A 10, A 15, A 17, A 20, C 2, D 12, D 18, E3, G2, G17, H17, J2, K4, K19, M18, N1, P18, R2, T18, U2, U9, U14, U17 V17 W11 Y6 Y13 Y1 U4 Type Description +3.3V Digital Pow er Digital Ground
AVCC AGND
Analog 3.3V for PLL Analog Ground for PLL
3.3 PI7C7100 PBGA Pin List
Pin No. A1 A3 A5 A7 A9 A11 A13 A15 A17 A19 B1 B3 B5 B7 B9 B11 B13 B15 B17 B19 C1 C3 C5 C7 C9 C11 C13 C15 Name S2_CBE[2] VSS VSS S2_CBE[0] S2_AD[2] S_CLKOUT[7] S_CLKOUT[5] VSS VSS S_CLKOUT[0] S2_AD[16] S2_LOCK# S2_AD[14] S2_AD[8] S2_AD[3] S1_REQ#[7] S1_GNT#[7] S_CLKOUT[3] S1_REQ#[0] S1_AD[30] S2_AD[17] S2_STOP# S2_AD[15] S2_AD[9] S2_AD[4] S1_GNT#[7] S1_REQ#[4] S1_REQ#[3] Type PB - - PB PB PTS PTS - - PTS PB PSTS PB PB PB PIU PO PTS PIU PB PB PSTS PB PB PB PO PIU PIU Pin No. A2 A4 A6 A8 A10 A12 A14 A16 A18 A20 B2 B4 B6 B8 B10 B12 B14 B16 B18 B20 C2 C4 C6 C8 C10 C12 C14 C16 Name S2_TRDY# S2_CBE[1] S2_AD[10] VSS VSS S1_REQ#[6] S1_GNT#[6] S1_REQ#[2] S_CLKOUT[1] VSS S2_IRDY# S2_PAR S2_AD[11] VDD S1_RESET# S1_GNT#[6] S_CLKOUT[4] S1_GNT#[2] S1_GNT#[0] S1_AD[31] VSS S2_SER# S2_AD[12] S2_AD[6] S2_AD[0] S_CLKOUT[6] VDD S_CLKOUT[2] Type PSTS PB PB - - PIU PO PIU PTS - PSTS PB PB - PO PO PTS PO PO PB - PI PB PB PB PTS - PTS
9
09/18/00 Rev 1.1
ADVANCE INFORMATION
65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
3.3 PI7C7100 PBGA Pin List (continued)
Pin No. C17 C19 D1 D3 D5 D7 D9 D11 D13 D15 D17 D19 E1 E3 E17 E19 F1 F3 F17 F19 G1 G3 G17 G19 H1 H3 H17 H19 J1 J3 J17 J19 Name S1_REQ#[1] S1_AD[28] S2_AD[18] S2_DEVSEL# VDD S_M66EN S2_AD[5] VDD S1_REQ#[5] VDD S1_AD[24] S1_AD[25] S2_AD[20] VSS S1_AD[21] S1_AD[23] S2_CBE[3] S2_AD[22] S1_AD[18] S1_AD[19] S2_AD[26] S2_AD[25] VSS S1_AD[16] S2_AD[30] S2_AD[28] VSS S1_IRDY# S_CLKOUT[8] VDD S1_PERR# S1_STOP# Type PIU PB PB PSTS - - PB - PIU - PB PB PB - PB PB PB PB PB PB PB PB - PB PB PB - PSTS PTS - PSTS PSTS Pin No. C18 C20 D2 D4 D6 D8 D10 D12 D14 D16 D18 D20 E2 E4 E18 E20 F2 F4 F18 F20 G2 G4 G18 G20 H2 H4 H18 H20 J2 J4 J18 J20 Name S1_AD[27] S1_AD[29] S2_FRAME# S2_PERR# S2_AD[13] S2_AD[7] S2_AD[1] VSS S1_GNT#[3] S1_GNT#[1] VSS S1_AD[26] VDD S2_AD[19] S1_AD[22] S1_CBE[3] S2_AD[23] S2_AD[21] VDD S1_AD[20] VSS S2_AD[24] S1_CBE[2] S1_AD[17] S2_AD[29] S2_AD[27] S1_TRDY# S1_FRAME# VSS S2_AD[31] S1_LOCK# S1_DEVSEL# Type PB PB PSTS PSTS PB PB PB - PO PO - PB - PB PB PB PB PB - PB - PB PB PB PB PB PSTS PSTS - PB PSTS PSTS
10
09/18/00 Rev 1.1
ADVANCE INFORMATION
765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
3.3 PI7C7100 PBGA Pin List (continued)
Pin No. K1 K3 K17 K19 L1 L3 L17 L19 M1 M3 M17 M19 N1 N3 N17 N19 P1 P3 P17 P19 R1 R3 R17 R19 T1 T3 T17 T19 U1 U3 U5 U7 Name S2_REQ#[1] S2_REQ#[0] S1_CBE[1] VSS S2_GNT#[1] S_CLKOUT[10] VDD S1_AD[14] S2_REQ#[2] S2_GNT#[3] S1_AD[10] S1_AD[11] VSS S_CLKOUT[12] S1_AD[6] S1_AD[8] S2_REQ#[4] S_CLKOUT[13] S1_AD[5] VDD S2_GNT#[5] S2_REQ#[6] P_AD[0] S1_AD[3] S_CLKOUT[14] S_CLKOUT[15] P_AD[1] S1_AD[0] S2_GNT#[7] TRST# SCAN_EN P_GNT# Type PIU PIU PB - PO PTS - PB PIU PO PB PB - PTS PB PB PIU PTS PB - PO PIU PB PB PTS PTS PB PB PO CIU CIU PI Pin No. K2 K4 K18 K20 L2 L4 L18 L20 M2 M4 M18 M20 N2 N4 N18 N20 P2 P4 P18 P20 R2 R4 R18 R20 T2 T4 T18 T20 U2 U4 U6 U8 Name S2_GNT#[0] VSS S1_PAR S1_SERR# S_CLKOUT[9] S2_GNT#[2] S1_AD[13] S1_AD[15] S2_REQ#[3] S_CLKOUT[11] VSS S1_AD[12] VDD S2_GNT#[4] S1_AD[7] S1_AD[9] S2_REQ#[5] S2_GNT#[6] VSS S1_CBE[0] VSS Reserved S1_AD[2] S1_AD[4] S2_REQ#[7] S2_RESET# VSS S1_AD[1] VSS AGND CMPO1 P_AD[26] Type PO - PB PI PTS PO PB PB PIU PTS - PB - PO PB PB PIU PO - PB - - PB PB PIU PO - PB - - - PB
11
09/18/00 Rev 1.1
ADVANCE INFORMATION
65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
3.3 PI7C7100 PBGA Pin List (continued)
Pin No. U9 U11 U13 U15 U17 U19 V1 V3 V5 V7 V9 V11 V13 V15 V17 V19 W1 W3 W5 W7 W9 W11 W13 W15 W17 W19 Y1 Y3 Y5 Y7 Y9 Y11 Y13 Y15 Y17 Y19 Name VSS P_AD[19] P_TRDY# P_PAR VSS P_AD[7] VDD TDO S_CLKIN VDD P_CBE[3] P_AD[20] P_IRDY# VDD VSS P_CBE[0] TMS S1_EN P_FLUSH# P_AD[30] P_AD[24] VSS P_FRAME# P_SERR# P_AD[12] P_AD[6] AVCC PLL_TM P_RESET# P_AD[31] P_AD[25] P_AD[21] VSS P_PERR# P_AD[11] P_AD[5] Type - PB PB PB - PB - CTO PI - PB PB PB - - PB CIU PIU PI PB PB - PB POD PB PB - - PI PB PB PB - PSTS PB PB Pin No. U10 U12 U14 U16 U18 U20 V2 V4 V6 V8 V10 V12 V14 V16 V18 V20 W2 W4 W6 W8 W10 W12 W14 W16 W18 W20 Y2 Y4 Y6 Y8 Y10 Y12 Y14 Y16 Y18 Y20 Name VDD P_CBE[2] VSS P_CBE[1] P_AD[10] P_AD[4] TCK SCAN_TM# P_CLK P_AD[27] P_AD[22] P_AD[16] P_LOCK# P_AD[15] P_M66EN P_AD[3] TDI S2_EN P_REQ# P_AD[28] P_AD[23] P_AD[17] P_STOP# P_AD[14] P_AD[9] VDD S_CFN# BYPASS VSS P_AD[29] P_IDSEL P_AD[18] P_DEVSEL# P_AD[13] P_AD[8] P_AD[2] - PB PB PB CIU CI PI PB PB PB PSTS PB - PB CIU PIU PTS PB PB PB PSTS PB PB - CIU - - PB PI PB PSTS PB PB PB Type -
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4. PCI Bus Operation
This chapter offers information about PCI transactions, transaction forwarding across PI7C7100, and transaction termination. The PI7C7100 has three 128-byte buffers for buffering of upstream and downstream transactions. These hold addresses, data, commands, and byte enables and are used for both read and write transactions.
4.1 Types of Transactions
This section provides a summary of PCI transactions performed by PI7C7100. Table 4-1 lists the command code and name of each PCI transaction. The Master and Target columns indicate support for each transaction when PI7C7100 initiates transactions as a master, on the primary (P) and secondary (S1, S2) buses, and when PI7C7100 responds to transactions as a target, on the primary (P) and secondary (S1, S2) buses.
Table 4-1. PCI Transactions
Type of Transactions Initiates as Master Primary 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Interrupt acknowledge Special cycle I/O read I/O write Reserved Reserved Memory read Memory write Reserved Reserved Configuration read Configuration write Memory read multiple Dual address cycle Memory read line Memory write and invalidate N Y Y Y N N Y Y N N N Y (Type 1 only) Y N Y N Secondary N Y Y Y N N Y Y N N Y Y Y N Y N Responds as Target Primary N N Y Y N N Y Y N N Y Y Y N Y Y Secondary N N Y Y N N Y Y N N N Y (Type 1 only) Y N Y Y
As indicated in Table 4-1, the following PCI commands are not supported by PI7C7100: * PI7C7100 never initiates a PCI transaction with a reserved command code and, as a target, PI7C7100 ignores reserved command codes. * PI7C7100 does not generate interrupt acknowledge transactions. PI7C7100 ignores interrupt acknowledge transactions as a target. * PI7C7100 does not respond to special cycle transactions. PI7C7100 cannot guarantee delivery of a special cycle transaction to downstream buses because of the broadcast nature of the special cycle command and the inability to control the transaction as a target. To generate special cycle transactions on other PCI buses, either upstream or downstream, Type 1 configuration write must be used. * PI7C7100 neither generates Type 0 configuration transactions on the primary PCI bus nor responds to Type 0 configuration transactions on the secondary PCI buses. * PI7C7100 does not support DAC (Dual Address Cycle) transactions.
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4.2 Single Address Phase
A 32-bit address uses a single address phase. This address is driven on P_AD[31:0], and the bus command is driven on P_CBE[3:0]. PI7C7100 supports the linear increment address mode only, which is indicated when the lowest two address bits are equal to zero. If either of the lowest two address bits is nonzero, PI7C7100 automatically disconnects the transaction after the first data transfer.
4.3 Device Select (DEVSEL#) Generation
PI7C7100 always performs positive address decoding (medium decode) when accepting transactions on either the primary or secondary buses. PI7C7100 never does subtractive decode.
4.4 Data Phase
The address phase of a PCI transaction is followed by one or more data phases. A data phase is completed when IRDY# and either TRDY# or STOP# are asserted. A transfer of data occurs only when both IRDY# and TRDY# are asserted during the same PCI clock cycle. The last data phase of a transaction is indicated when FRAME# is de-asserted and both TRDY# and IRDY# are asserted, or when IRDY# and STOP# are asserted. See Section 4.8 for further discussion of transaction termination. Depending on the command type, PI7C7100 can support multiple data phase PCI transactions. For a detailed description of how PI7C7100 imposes disconnect boundaries, see Section 4.5.4 for write address boundaries and Section 4.6.3 read address boundaries.
4.5 Write Transactions
Write transactions are treated as either posted write or delayed write transactions. Table 4-2 shows the method of forwarding used for each type of write operation.
Table 4-2. Write Transaction Forwarding
Type of Transaction Memory write Memory write and invalidate I/O write Type 1 configuration write Type of Forwarding Posted (except VGA memory) Posted Delayed Delayed
For timing diagrams, see Figures 15-22 and 27-30 in Appendix A
4.5.1 Posted Write Transactions
Posted write forwarding is used for "Memory Write" and "Memory Write and Invalidate" transactions. When PI7C7100 determines that a memory write transaction is to be forwarded across the bridge, PI7C7100 asserts DEVSEL# with medium timing and TRDY# in the next cycle, provided that enough buffer space is available in the posted memory write queue for the address and at least one DWORD of data. Under this condition, PI7C7100 accepts write data without obtaining access to the target bus. The PI7C7100 can accept one DWORD of write data every PCI clock cycle. That is, no target wait state is inserted. The write data is stored in an internal posted write buffers and is subsequently delivered to the target. The PI7C7100 continues to accept write data until one of the following events occurs: * The initiator terminates the transaction by de-asserting FRAME# and IRDY#. * An internal write address boundary is reached, such as a cache line boundary or an aligned 4KB boundary, depending on the transaction type. * The posted write data buffer fills up.
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When one of the last two events occurs, the PI7C7100 returns a target disconnect to the requesting initiator on this data phase to terminate the transaction. Once the posted write data moves to the head of the posted data queue, PI7C7100 asserts its request on the target bus. This can occur while PI7C7100 is still receiving data on the initiator bus. When the grant for the target bus is received and the target bus is detected in the idle condition, PI7C7100 asserts FRAME# and drives the stored write address out on the target bus. On the following cycle, PI7C7100 drives the first DWORD of write data and continues to transfer write data until all write data corresponding to that transaction is delivered, or until a target termination is received. As long as write data exists in the queue, PI7C7100 can drive one DWORD of write data each PCI clock cycle; that is, no master wait states are inserted. If write data is flowing through PI7C7100 and the initiator stalls, PI7C7100 will signal the last data phase for the current transaction at the target bus if the queue empties. PI7C7100 will restart the follow-on transactions if the queue has new data. PI7C7100 ends the transaction on the target bus when one of the following conditions is met: * All posted write data has been delivered to the target. * The target returns a target disconnect or target retry (PI7C7100 starts another transaction to deliver the rest of write data). * The target returns a target abort (PI7C7100 discards remaining write data). * The master latency timer expires, and PI7C7100 no longer has the target bus grant (PI7C7100 starts another transaction to deliver remaining write data). Section 4.8.3.2 provides detailed information about how PI7C7100 responds to target termination during posted write transactions.
4.5.2 Memory Write and Invalidate Transactions
Posted write forwarding is used for Memory Write and Invalidate transactions. PI7C7100 always converts Memory Write and Invalidate transactions to Memory Write transactions. The PI7C7100 disconnects Memory Write and Invalidate commands at aligned cache line boundaries. The cache line size value in the cache line size register gives the number of DWORD in a cache line. If the value in the cache line size register does meet the memory write and invalidate conditions, the PI7C7100 returns a target disconnect to the initiator either on a cache line boundary or when the posted write buffer fills. When the Memory Write and Invalidate transaction is disconnected before a cache line boundary is reached, typically because the posted write buffer fills, the transaction is converted to Memory Write transaction.
4.5.3 Delayed Write Transactions
Delayed write forwarding is used for I/O write transactions and Type 1 configuration write transactions. A delayed write transaction guarantees that the actual target response is returned back to the initiator without holding the initiating bus in wait states. A delayed write transaction is limited to a single DWORD data transfer. When a write transaction is first detected on the initiator bus, and PI7C7100 forwards it as a delayed transaction, PI7C7100 claims the access by asserting DEVSEL# and returns a target retry to the initiator. During the address phase, PI7C7100 samples the bus command, address, and address parity one cycle later. After IRDY# is asserted, PI7C7100 also samples the first data DWORD, byte enable bits, and data parity. This information is placed into the delayed transaction queue. The transaction is queued only if no other existing delayed transactions have the same address and command, and if the delayed transaction queue is not full. When the delayed write transaction moves to the head of the delayed transaction queue and all ordering constraints with posted data are satisfied. The PI7C7100 initiates the transaction on the target bus. PI7C7100 transfers the write data to the target. If PI7C7100 receives a target retry in response to the write transaction on the target bus, it continues to repeat the write transaction until the data transfer is completed, or until an error condition is encountered. If PI7C7100 is unable to deliver write data after 224(default) or 232(maximum) attempts, PI7C7100 will report a system error. PI7C7100 also asserts P_SERR# if the primary SERR# enable bit is set in the command register. See Section 7.4 for information on the assertion of P_SERR#. When the initiator repeats the same write transaction (same command, address, byte enable bits, and data), and the completed delayed transaction is at the head of the queue, the PI7C7100
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claims the access by asserting DEVSEL# and returns TRDY# to the initiator, to indicate that the write data was transferred. If the initiator requests multiple DWORD, PI7C7100 also asserts STOP# in conjunction with TRDY# to signal a target disconnect. Note that only those bytes of write data with valid byte enable bits are compared. If any of the byte enable bits are turned off (driven HIGH), the corresponding byte of write data is not compared. If the initiator repeats the write transaction before the data has been transferred to the target, PI7C7100 returns a target retry to the initiator. PI7C7100 continues to return a target retry to the initiator until write data is delivered to the target, or until an error condition is encountered. When the write transaction is repeated, PI7C7100 does not make a new entry into the delayed transaction queue. Section 4.8.3.1 provides detailed information about how PI7C7100 responds to target termination during delayed write transactions. PI7C7100 implements a discard timer that starts counting when the delayed write completion is at the head of the delayed transaction queue. The initial value of this timer can be set to the retry counter register offset 78h. If the initiator does not repeat the delayed write transaction before the discard timer expires, PI7C7100 discards the delayed write completion from the delayed transaction queue. PI7C7100 also conditionally asserts P_SERR# (see Section 7.4).
4.5.4 Write Transaction Address Boundaries
PI7C7100 imposes internal address boundaries when accepting write data. The aligned address boundaries are used to prevent PI7C7100 from continuing a transaction over a device address boundary and to provide an upper limit on maximum latency. PI7C7100 returns a target disconnect to the initiator when it reaches the aligned address boundaries under conditions shown in Table 4-3. Table 4-3. Write Transaction Disconnect Address Boundaries
Type of Transaction Delayed write Posted memory write Posted memory write Posted memory write and invalidate Posted memory write and invalidate Condition All Cache line size not equal to 1, 2, 4, 8, 16 Cache line size = 1, 2, 4, 8, 16 Cache line size not equal to 1, 2, 4, 8, 16 Cache line size = 1, 2, 4, 8, 16 Aligned Address Boundary Disconnects after one data transfer 4KB aligned address boundary Disconnects at cache line boundary 4KB aligned address boundary Cache line boundary,
Note 1. Memory-write-disconnect-control bit is bit 1 of the chip control register at offset 40h in configuration space.
4.5.5 Buffering Multiple Write Transactions
PI7C7100 continues to accept posted memory write transactions as long as space for at least one DWORD of data in the posted write data buffer remains. If the posted write data buffer fills before the initiator terminates the write transaction, PI7C7100 returns a target disconnect to the initiator. Delayed write transactions are posted as long as at least one open entry in the delayed transaction queue exists. Therefore, several posted and delayed write transactions can exist in data buffers at the same time. See Chapter 6 for information about how multiple posted and delayed write transactions are ordered.
4.5.6 Fast Back-to-Back Write Transactions
PI7C7100 can recognize and post fast back-to-back write transactions. When PI7C7100 cannot accept the second transaction because of buffer space limitations, it returns a target retry to the initiator.
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4.6 Read Transactions
Delayed read forwarding is used for all read transactions crossing PI7C7100. Delayed read transactions are treated as either prefetchable or non-prefetchable. Table 4-4 shows the read behavior, prefetchable or non-prefetchable, for each type of read operation. For Timing diagrams, see Figures 11-14 and 23-26 in Appendix A
4.6.1 Prefetchable Read Transactions
A prefetchable read transaction is a read transaction where PI7C7100 performs speculative DWORD reads, transferring data from the target before it is requested from the initiator. This behavior allows a prefetchable read transaction to consist of multiple data transfers. However, byte enable bits cannot be forwarded for all data phases as is done for the single data phase of the non-prefetchable read transaction. For prefetchable read transactions, PI7C7100 forces all byte enable bits to be turned on for all data phases. Prefetchable behavior is used for memory read line and memory read multiple transactions, as well as for memory read transactions that fall into prefetchable memory space. The amount of data that is pre-fetched depends on the type of transaction. The amount of pre-fetching may also be affected by the amount of free buffer space available in PI7C7100, and by any read address boundaries encountered. Pre-fetching should not be used for those read transactions that have side effects in the target device, that is, control and status registers, FIFOs, and so on. The target device's base address register or registers indicate if a memory address region is prefetchable.
4.6.2 Non-prefetchable Read Transactions
A non-prefetchable read transaction is a read transaction where PI7C7100 requests one and only one DWORD from the target and disconnects the initiator after delivery of the first DWORD of read data. Unlike prefetchable read transactions, PI7C7100 forwards the read byte enable information for the data phase. Non-prefetchable behavior is used for I/O and configuration read transactions, as well as for memory read transactions that fall into non-prefetchable memory space. If extra read transactions could have side effects, for example, when accessing a FIFO, use non-prefetchable read transactions to those locations. Accordingly, if it is important to retain the value of the byte enable bits during the data phase, use non-prefetchable read transactions. If these locations are mapped in memory space, use the memory read command and map the target into non-prefetchable (memory-mapped I/O) memory space to use non-prefetching behavior.
4.6.3 Read Pre-fetch Address Boundaries
PI7C7100 imposes internal read address boundaries on read pre-fetched data. When a read transaction reaches one of these aligned address boundaries, the PI7C7100 stops pre-fetched data, unless the target signals a target disconnect before the read pre-fetched boundary is reached. When PI7C7100 finishes transferring this read data to the initiator, it returns a target disconnect with the last data transfer, unless the initiator completes the transaction before all pre-fetched read data is delivered. Any leftover pre-fetched data is discarded. Prefetchable read transactions in flow-through mode pre-fetch to the nearest aligned 4KB address boundary, or until the initiator de-asserts FRAME#. Section 4.6.6 describes flow-through mode during read operations. Table 4-5 shows the read pre-fetch address boundaries for read transactions during non-flow-through mode. Table 4-4. Read Pre-fetch Address Boundaries
Type of Transaction Config read I/O read Memory read Memory read Memory read Memory read line Memory read line Memory read multiple Memory read multiple Address Space Non-prefetchable Prefetchable Prefetchable Cache Line Siz e (CLS) CLS not equal to 1, 2, 4, 8 C LS = 1, 2, 4, 8 CLS not equal to 1, 2, 4, 8 C LS = 1, 2, 4, 8 CLS not equal to 1, 2, 4, 8 C LS = 1, 2, 4, 8
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Pre-fetch Aligned Address Boundary One DWORD (no pre-fetch) One DWORD (no pre-fetch) One DWORD (no pre-fetch) 16-DWORD aligned address boundary Cache line address boundary 16-DWORD aligned address boundary Cache line boundary 32-DWORD aligned address boundary 2 times of cache line boundary
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Table 4-5. Read Transaction Pre-Fetching
Type of Transaction I/O read Configuration read Memory read Read Behavior Pre-fetching never done Pre-fetching never done Downstream: pre-fetching used if address in prefetchable space Upstream: pre-fetching used Memory read line Memory read multiple Pre-fetching always used Pre-fetching always used
See Section 5.3 for detailed information about prefetchable and non-prefetchable address spaces.
4.6.4 Delayed Read Requests
PI7C7100 treats all read transactions as delayed read transactions, which means that the read request from the initiator is posted into a delayed transaction queue. Read data from the target is placed in the read data queue directed toward the initiator bus interface and is transferred to the initiator when the initiator repeats the read transaction. When PI7C7100 accepts a delayed read request, it first samples the read address, read bus command, and address parity. When IRDY# is asserted, PI7C7100 then samples the byte enable bits for the first data phase. This information is entered into the delayed transaction queue. PI7C7100 terminates the transaction by signaling a target retry to the initiator. Upon reception of the target retry, the initiator is required to continue to repeat the same read transaction until at least one data transfer is completed, or until a target response (target abort or master abort) other than a target retry is received.
4.6.5 Delayed Read Completion with Target
When delayed read request reaches the head of the delayed transaction queue, PI7C7100 arbitrates for the target bus and initiates the read transaction only if all previously queued posted write transactions have been delivered. PI7C7100 uses the exact read address and read command captured from the initiator during the initial delayed read request to initiate the read transaction. If the read transaction is a non-prefetchable read, PI7C7100 drives the captured byte enable bits during the next cycle. If the transaction is a prefetchable read transaction, it drives all byte enable bits to zero for all data phases. If PI7C7100 receives a target retry in response to the read transaction on the target bus, it continues to repeat the read transaction until at least one data transfer is completed, or until an error condition is encountered. If the transaction is terminated via normal master termination or target disconnect after at least one data transfer has been completed, PI7C7100 does not initiate any further attempts to read more data. If PI7C7100 is unable to obtain read data from the target after 224(default) or 232(maximum) attempts, PI7C7100 will report system error. The number of attempts is programmable. PI7C7100 also asserts P_SERR# if the primary SERR# enable bit is set in the command register. See Section 7.4 for information on the assertion of P_SERR#. Once PI7C7100 receives DEVSEL# and TRDY# from the target, it transfers the data read to the opposite direction read data queue, pointing toward the opposite interface, before terminating the transaction. For example, read data in response to a downstream read transaction initiated on the primary bus is placed in the upstream read data queue. The PI7C7100 can accept one DWORD of read data each PCI clock cycle; that is, no master wait states are inserted. The number of DWORD transferred during a delayed read transaction depends on the conditions given in Table 4-5 (assuming no disconnect is received from the target).
4.6.6 Delayed Read Completion on Initiator Bus
When the transaction has been completed on the target bus, and the delayed read data is at the head of the read data queue, and all ordering constraints with posted write transactions have been satisfied, the PI7C7100 transfers the data to the initiator when the initiator repeats the transaction. For memory read transactions, PI7C7100 aliases the memory read, memory read line, and memory read multiple bus commands when matching the bus command of the transaction to the bus command in the delayed transaction queue. PI7C7100 returns a target disconnect along with the transfer of the last DWORD of read data to the initiator. If PI7C7100 initiator terminates the transaction before all read data has been transferred, the remaining read data left in data buffers is discarded.
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When the master repeats the transaction and starts transferring prefetchable read data from data buffers while the read transaction on the target bus is still in progress and before a read boundary is reached on the target bus, the read transaction starts operating in flow-through mode. Because data is flowing through the data buffers from the target to the initiator, long read bursts can then be sustained. In this case, the read transaction is allowed to continue until the initiator terminates the transaction, or until an aligned 4KB address boundary is reached, or until the buffer fills, whichever comes first. When the buffer empties, PI7C7100 reflects the stalled condition to the initiator by de-asserting TRDY# until more read data is available; otherwise, PI7C7100 does not insert any target wait states. When the initiator terminates the transaction, PI7C7100 de-assertion of FRAME# on the initiator bus is forwarded to the target bus. Any remaining read data is discarded. PI7C7100 implements a discard timer that starts counting when the delayed read completion is at the head of the delayed transaction queue, and the read data is at the head of the read data queue. The initial value of this timer is programmable through configuration register. If the initiator does not repeat the read transaction and before the discard timer expires (215 default), PI7C7100 discards the read transaction and read data from its queues. PI7C7100 also conditionally asserts P_SERR# (see Section 7.4). PI7C7100 has the capability to post multiple delayed read requests, up to a maximum of four in each direction. If an initiator starts a read transaction that matches the address and read command of a read transaction that is already queued, the current read command is not posted as it is already contained in the delayed transaction queue. See Section 6 for a discussion of how delayed read transactions are ordered when crossing PI7C7100.
4.7 Configuration Transactions
Configuration transactions are used to initialize a PCI system. Every PCI device has a configuration space that is accessed by configuration commands. All registers are accessible in configuration space only. In addition to accepting configuration transactions for initialization of its own configuration space, the PI7C7100 also forwards configuration transactions for device initialization in hierarchical PCI systems, as well as for special cycle generation. To support hierarchical PCI bus systems, two types of configuration transactions are specified: Type 0 and Type 1. Type 0 configuration transactions are issued when the intended target resides on the same PCI bus as the initiator. A Type 0 configuration transaction is identified by the configuration command and the lowest two bits of the address set to 00b. Type 1 configuration transactions are issued when the intended target resides on another PCI bus, or when a special cycle is to be generated on another PCI bus. A Type 1 configuration command is identified by the configuration command and the lowest two address bits set to 01b. The register number is found in both Type 0 and Type 1 formats and gives the DWORD address of the configuration register to be accessed. The function number is also included in both Type 0 and Type 1 formats and indicates which function of a multifunction device is to be accessed. For single-function devices, this value is not decoded. The addresses of Type 1 configuration transaction include a 5-bit field designating the device number that identifies the device on the target PCI bus that is to be accessed. In addition, the bus number in Type 1 transactions specifies the PCI bus to which the transaction is targeted. For timing diagrams, see Figures 1-8 in Appendix A.
4.7.1 Type 0 Access to PI7C7100
The configuration space is accessed by a Type 0 configuration transaction on the primary interface. The configuration space cannot be accessed from the secondary bus. The PI7C7100 responds to a Type 0 configuration transaction by asserting P_DEVSEL# when the following conditions are met during the address phase: * The bus command is a configuration read or configuration write transaction. * Lowest two address bits P_AD[1:0] must be 00b. * Signal P_IDSEL must be asserted. Function code is either 0 for configuration space of S1, or 1 for configuration space of S2 as PI7C7100 is a multi-function device. PI7C7100 limits all configuration access to a single DWORD data transfer and returns target-disconnect with the first data transfer if additional data phases are requested. Because read transactions to configuration space do not have side effects, all bytes in the requested DWORD are returned, regardless of the value of the byte enable bits.
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Type 0 configuration write and read transactions do not use data buffers; that is, these transactions are completed immediately, regardless of the state of the data buffers. The PI7C7100 ignores all Type 0 transactions initiated on the secondary interface.
4.7.2 Type 1 to Type 0 Conversion
Type 1 configuration transactions are used specifically for device configuration in a hierarchical PCI bus system. A PCIto-PCI bridge is the only type of device that should respond to a Type 1 configuration command. Type 1 configuration commands are used when the configuration access is intended for a PCI device that resides on a PCI bus other than the one where the Type 1 transaction is generated. PI7C7100 performs a Type 1 to Type 0 translation when the Type 1 transaction is generated on the primary bus and is intended for a device attached directly to the secondary bus. PI7C7100 must convert the configuration command to a Type 0 format so that the secondary bus device can respond to it. Type 1 to Type 0 translations are performed only in the downstream direction; that is, PI7C7100 generates a Type 0 transaction only on the secondary bus, and never on the primary bus. PI7C7100 responds to a Type 1 configuration transaction and translates it into a Type 0 transaction on the secondary bus when the following conditions are met during the address phase: The lowest two address bits on P_AD[1:0] are 01b. The bus number in address field P_AD[23:16] is equal to the value in the secondary bus number register in configuration space. * The bus command on P_CBE[3:0] is a configuration read or configuration write transaction. * When PI7C7100 translates the Type 1 transaction to a Type 0 transaction on the secondary interface, it performs the following translations to the address: * Sets the lowest two address bits on S1_AD[1:0] or S2_AD[1:0] to 00b. * Decodes the device number and drives the bit pattern specified in Table 4-6 on S1_AD[31:16] or S2_AD[31:16] for the purpose of asserting the device's IDSEL signal. * Sets S1_AD[15:11] or S2_AD[15:11] to 0. * Leaves unchanged the function number and register number fields. PI7C7100 asserts a unique address line based on the device number. These address lines may be used as secondary bus IDSEL signals. The mapping of the address lines depends on the device number in the Type 1 address bits P_AD[15:11]. Table 4-6 presents the mapping that PI7C7100 uses * *
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PI7C7100 3-Port PCI Bridge
Table 4-6. Device Number to IDSEL S1_AD or S2_AD Pin Mapping
Device Number 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 10h-1Eh 1F h P_AD<15: 11> 00000 00001 00010 00011 00100 00101 0110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000-11110 11111 Secondary IDSEL S1_AD[31: 16] or S2_AD[31: 16] 0000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 Generate special cycle (P_AD[7:2] = 00h) 0000 0000 0000 0000 (P_AD[7:2] = 00h) S1_AD or S2_AD Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -
PI7C7100 can assert up to 16 unique address lines to be used as IDSEL signals for up to 16 devices on the secondary bus, for device numbers ranging from 0 through 15. Because of electrical loading constraints of the PCI bus, more than 16 IDSEL signals should not be necessary. However, if device numbers greater than 15 are desired, some external method of generating IDSEL lines must be used, and no upper address bits are then asserted. The configuration transaction is still translated and passed from the primary bus to the secondary bus. If no IDSEL pin is asserted to a secondary device, the transaction ends in a master abort. PI7C7100 forwards Type 1 to Type 0 configuration read or write transactions as delayed transactions. Type 1 to Type 0 configuration read or write transactions are limited to a single 32-bit data transfer.
4.7.3 Type 1 to Type 1 Forwarding
Type 1 to Type 1 transaction forwarding provides a hierarchical configuration mechanism when two or more levels of PCIto-PCI bridges are used. When PI7C7100 detects a Type 1 configuration transaction intended for a PCI bus downstream from the secondary bus, PI7C7100 forwards the transaction unchanged to the secondary bus. Ultimately, this transaction is translated to a Type 0 configuration command or to a special cycle transaction by a downstream PCI-to-PCI bridge. Downstream Type 1 to Type 1 forwarding occurs when the following conditions are met during the address phase: * The lowest two address bits are equal to 01b. * The bus number falls in the range defined by the lower limit (exclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register. * The bus command is a configuration read or write transaction.
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PI7C7100 3-Port PCI Bridge
PI7C7100 also supports Type 1 to Type 1 forwarding of configuration write transactions upstream to support upstream special cycle generation. A Type 1 configuration command is forwarded upstream when the following conditions are met: * The lowest two address bits are equal to 01b. * The bus number falls outside the range defined by the lower limit (inclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register. * The device number in address bits AD[15:11] is equal to 11111b. * The function number in address bits AD[10:8] is equal to 111b. * The bus command is a configuration write transaction. The PI7C7100 forwards Type 1 to Type 1 configuration write transactions as delayed transactions. Type 1 to Type 1 configuration write transactions are limited to a single data transfer.
4.7.4 Special Cycles
The Type 1 configuration mechanism is used to generate special cycle transactions in hierarchical PCI systems. Special cycle transactions are ignored by acting as a target and are not forwarded across the bridge. Special cycle transactions can be generated from Type 1 configuration write transactions in either the upstream or the downstream direction. PI7C7100 initiates a special cycle on the target bus when a Type 1 configuration write transaction is being detected on the initiating bus and the following conditions are met during the address phase: * The lowest two address bits on AD[1:0] are equal to 01b. * The device number in address bits AD[15:11] is equal to 11111b. * The function number in address bits AD[10:8] is equal to 111b. * The register number in address bits AD[7:2] is equal to 000000b. * The bus number is equal to the value in the secondary bus number register in configuration space for downstream forwarding or equal to the value in the primary bus number register in configuration space for upstream forwarding. * The bus command on CBE# is a configuration write command. When PI7C7100 initiates the transaction on the target interface, the bus command is changed from configuration write to special cycle. The address and data are forwarded unchanged. Devices that use special cycles ignore the address and decode only the bus command. The data phase contains the special cycle message. The transaction is forwarded as a delayed transaction, but in this case the target response is not forwarded back (because special cycles result in a master abort). Once the transaction is completed on the target bus, through detection of the master abort condition, PI7C7100 responds with TRDY# to the next attempt of the configuration transaction from the initiator. If more than one data transfer is requested, PI7C7100 responds with a target disconnect operation during the first data phase.
4.8 Transaction Termination
This section describes how PI7C7100 returns transaction termination conditions back to the initiator. The initiator can terminate transactions with one of the following types of termination: * Normal termination Normal termination occurs when the initiator de-asserts FRAME# at the beginning of the last data phase, and deasserts IRDY# at the end of the last data phase in conjunction with either TRDY# or STOP# assertion from the target. * Master abort A master abort occurs when no target response is detected. When the initiator does not detect a DEVSEL# from the target within five clock cycles after asserting FRAME#, the initiator terminates the transaction with a master abort. If FRAME# is still asserted, the initiator de-asserts FRAME# on the next cycle, and then de-asserts IRDY# on the following cycle. IRDY# must be asserted in the same cycle in which FRAME# de-asserts. If FRAME# is already de-asserted, IRDY# can be de-asserted on the next clock cycle following detection of the master abort condition.
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PI7C7100 3-Port PCI Bridge
The target can terminate transactions with one of the following types of termination: * Normal termination--TRDY# and DEVSEL# asserted in conjunction with FRAME# de-asserted and IRDY# asserted. * Target retry--STOP# and DEVSEL# asserted with TRDY# de-asserted during the first data phase. No data transfers occur during the transaction. This transaction must be repeated. * Target disconnect with data transfer--STOP#, DEVSEL# and TRDY# asserted. It signals that this is the last data transfer of the transaction. * Target disconnect without data transfer--STOP# and DEVSEL# asserted with TRDY# de-asserted after previous data transfers have been made. Indicates that no more data transfers will be made during this transaction. * Target abort--STOP# asserted with DEVSEL# and TRDY# de-asserted. Indicates that target will never be able to complete this transaction. DEVSEL# must be asserted for at least one cycle during the transaction before the target abort is signaled.
4.8.1 Master Termination Initiated by PI7C7100
PI7C7100, as an initiator, uses normal termination if DEVSEL# is returned by target within five clock cycles of PI7C7100's assertion of FRAME# on the target bus. As an initiator, PI7C7100 terminates a transaction when the following conditions are met: * During a delayed write transaction, a single DWORD is delivered. * During a non-prefetchable read transaction, a single DWORD is transferred from the target. * During a prefetchable read transaction, a pre-fetch boundary is reached. * For a posted write transaction, all write data for the transaction is transferred from data buffers to the target. * For burst transfer, with the exception of "Memory Write and Invalidate" transactions, the master latency timer expires and the PI7C7100's bus grant is de-asserted. * The target terminates the transaction with a retry, disconnect, or target abort. If PI7C7100 is delivering posted write data when it terminates the transaction because the master latency timer expires, it initiates another transaction to deliver the remaining write data. The address of the transaction is updated to reflect the address of the current DWORD to be delivered. If PI7C7100 is pre-fetching read data when it terminates the transaction because the master latency timer expires, it does not repeat the transaction to obtain more data.
4.8.2 Master Abort Received by PI7C7100
If the initiator initiates a transaction on the target bus and does not detect DEVSEL# returned by the target within five clock cycles of the assertion of FRAME#, PI7C7100 terminates the transaction with a master abort. This sets the receivedmaster-abort bit in the status register corresponding to the target bus. For delayed read and write transactions, PI7C7100 is able to reflect the master abort condition back to the initiator. When PI7C7100 detects a master abort in response to a delayed transaction, and when the initiator repeats the transaction, PI7C7100 does not respond to the transaction with DEVSEL# which induces the master abort condition back to the initiator. The transaction is then removed from the delayed transaction queue. When a master abort is received in response to a posted write transaction, PI7C7100 discards the posted write data and makes no more attempt to deliver the data. PI7C7100 sets the received-master-abort bit in the status register when the master abort is received on the primary bus, or it sets the received master abort bit in the secondary status register when the master abort is received on the secondary interface. When master abort is detected in posted write transaction with both master-abort-mode bit (bit 5 of bridge control register) and the SERR# enable bit (bit 8 of command register for secondary bus S1 or S2) are set, PI7C7100 asserts P_SERR# if the master-abort-on-posted-write is not set. The master-abort-on-posted-write bit is bit 4 of the P_SERR# event disable register (offset 64h). Note: When PI7C7100 performs a Type 1 to special cycle conversion, a master abort is the expected termination for the special cycle on the target bus. In this case, the master abort received bit is not set, and the Type 1 configuration transaction is disconnected after the first data phase.
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PI7C7100 3-Port PCI Bridge
4.8.3 Target Termination Received by PI7C7100
When PI7C7100 initiates a transaction on the target bus and the target responds with DEVSEL#, the target can end the transaction with one of the following types of termination: * Normal termination (upon de-assertion of FRAME#) * Target retry * Target disconnect * Target abort PI7C7100 handles these terminations in different ways, depending on the type of transaction being performed. 4.8.3.1 Delayed Write Target Termination Response When PI7C7100 initiates a delayed write transaction, the type of target termination received from the target can be passed back to the initiator. Table 4-7 shows the response to each type of target termination that occurs during a delayed write transaction. PI7C7100 repeats a delayed write transaction until one of the following conditions is met: * PI7C7100 completes at least one data transfer. * PI7C7100 receives a master abort. * PI7C7100 receives a target abort. PI7C7100 makes 224(default) or 232(maximum) write attempts resulting in a response of target retry.
Table 4-7. Delayed Write Target Termination Response
Target Termination Normal Target retry Target disconnect Target abort R esp o n se Returning disconnect to initiator with first data transfer only if multiple data phases requested. Returning target retry to initiator. Continue write attempts to target. Returning disconnect to initiator with first data transfer only if multiple data phases requested. Returning target abort to initiator.Set received target abort bit in target interface status register.Set signaled target abort bit in initiator interface status register.
After the PI7C7100 makes 224(default) attempts of the same delayed write transaction on the target bus, PI7C7100 asserts P_SERR# if the SERR# enable bit (bit 8 of command register for secondary bus S1 or S2) is set and the delayed-writenon-delivery bit is not set. The delayed-write-non-delivery bit is bit 5 of P_SERR# event disable register (offset 64h). PI7C7100 will report system error. See Section 7.4 for a description of system error conditions. 4.8.3.2 Posted Write Target Termination Response When PI7C7100 initiates a posted write transaction, the target termination cannot be passed back to the initiator. Table 4-8 shows the response to each type of target termination that occurs during a posted write transaction.
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PI7C7100 3-Port PCI Bridge
Table 4-8. Responses to Posted Write Target Termination
Target Termination Normal Target retry Target disconnect Target abort No additional action. Repeating write transaction to target. Initiate write transaction for delivering remaining posted write data. Set received-target-abort bit in the target interface status register. Assert P_SERR# if enabled, and set the signaled-system-error bit in primary status register. R esp o n se
Note that when a target retry or target disconnect is returned and posted write data associated with that transaction remains in the write buffers, PI7C7100 initiates another write transaction to attempt to deliver the rest of the write data. If there is a target retry, the exact same address will be driven as for the initial write transaction attempt. If a target disconnect is received, the address that is driven on a subsequent write transaction attempt will be updated to reflect the address of the current DWORD. If the initial write transaction is Memory-Write-and-Invalidate transaction, and a partial delivery of write data to the target is performed before a target disconnect is received, PI7C7100 will use the memory write command to deliver the rest of the write data. It is because an incomplete cache line will be transferred in the subsequent write transaction attempt. After the PI7C7100 makes 224(default) write transaction attempts and fails to deliver all posted write data associated with that transaction, PI7C7100 asserts P_SERR# if the primary SERR# enable bit is set (bit 8 of command register for secondary bus S1 or S2) and posted-write-non-delivery bit is not set. The posted-write-non-delivery bit is the bit 2 of P_SERR# event disable register (offset 64h). PI7C7100 will report system error. See Section 7.4 for a discussion of system error conditions. 4.8.3.3 Delayed Read Target Termination Response When PI7C7100 initiates a delayed read transaction, the abnormal target responses can be passed back to the initiator. Other target responses depend on how much data the initiator requests. Table 4-9 shows the response to each type of target termination that occurs during a delayed read transaction. PI7C7100 repeats a delayed read transaction until one of the following conditions is met: * * * * PI7C7100 completes at least one data transfer. PI7C7100 receives a master abort. PI7C7100 receives a target abort. PI7C7100 makes 224(default) read attempts resulting in a response of target retry. Table 4-9. Responses to Delayed Read Target Termination
Target Termination Normal Target retry Target disconnect Target abort R esp o n se If prefetchable, target disconnect only if initiator requests more data than read from target. If non-prefetchable, target disconnect on first data phase. Reinitiate read transaction to target. If initiator requests more data than read from target, return target disconnect to initiator. Return target abort to initiator. Set received target abort bit in the target interface status register. Set signaled target abort bit in the initiator interface status register.
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PI7C7100 3-Port PCI Bridge
After PI7C7100 makes 224(default) attempts of the same delayed read transaction on the target bus, PI7C7100 asserts P_SERR# if the primary SERR# enable bit is set (bit 8 of command register for secondary bus S1 or S2) and the delayedwrite-non-delivery bit is not set. The delayed-write-non-delivery bit is bit 5 of P_SERR# event disable register (offset 64h). PI7C7100 will report system error. See Section 7.4 for a description of system error conditions.
4.8.4 Target Termination Initiated by PI7C7100
PI7C7100 can return a target retry, target disconnect, or target abort to an initiator for reasons other than detection of that condition at the target interface. 4.8.4.1 Target Retry PI7C7100 returns a target retry to the initiator when it cannot accept write data or return read data as a result of internal conditions. PI7C7100 returns a target retry to an initiator when any of the following conditions is met: For delayed write transactions: * The transaction is being entered into the delayed transaction queue. * Transaction has already been entered into delayed transaction queue, but target response has not yet been received. * Target response has been received but has not progressed to the head of the return queue. * The delayed transaction queue is full, and the transaction cannot be queued. * A transaction with the same address and command has been queued. * A locked sequence is being propagated across PI7C7100, and the write transaction is not a locked transaction. * The target bus is locked and the write transaction is a locked transaction. * Use more than 16 clocks to accept this transaction. For delayed read transactions: * The transaction is being entered into the delayed transaction queue. * The read request has already been queued, but read data is not yet available. * Data has been read from target, but it is not yet at head of the read data queue, or a posted write transaction precedes it. * The delayed transaction queue is full, and the transaction cannot be queued. * A delayed read request with the same address and bus command has already been queued. * A locked sequence is being propagated across PI7C7100, and the read transaction is not a locked transaction. * PI7C7100 is currently discarding previously pre-fetched read data. * The target bus is locked and the write transaction is a locked transaction. * Use more than 16 clocks to accept this transaction. For posted write transactions: * The posted write data buffer does not have enough space for address and at least one DWORD of write data. * A locked sequence is being propagated across PI7C7100, and the write transaction is not a locked transaction. When a target retry is returned to the initiator of a delayed transaction, the initiator must repeat the transaction with the same address and bus command as well as the data if it is a write transaction, within the time frame specified by the master timeout value. Otherwise, the transaction is discarded from the buffers.
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PI7C7100 3-Port PCI Bridge
4.8.4.2 Target Disconnect PI7C7100 returns a target disconnect to an initiator when one of the following conditions is met: * PI7C7100 hits an internal address boundary. * PI7C7100 cannot accept any more write data. * PI7C7100 has no more read data to deliver. See Section 4.5.4 for a description of write address boundaries, and Section 4.6.3 for a description of read address boundaries. 4.8.4.3 Target Abort PI7C7100 returns a target abort to an initiator when one of the following conditions is met: * PI7C7100 is returning a target abort from the intended target. When PI7C7100 returns a target abort to the initiator, it sets the signaled target abort bit in the status register corresponding to the initiator interface.
4.9 Concurrent Mode Operation
The Bridge can be configured to run in concurrent operation. Concurrent operation is defined as cycles going from one device on one secondary bus to another device on the same or other secondary bus. This off-loads traffic from the primary bus, allowing other traffic to run on the primary bus concurrently. The Bridge is already configured to handle concurrent operation. However, the devices themselves need to be configured to do so. Meaning, device drivers for the specific device used will have to be configured to perform the operation. Please contact Pericom for more information.
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PI7C7100 3-Port PCI Bridge
5. Address Decoding
PI7C7100 uses three address ranges that control I/O and memory transaction forwarding. These address ranges are defined by base and limit address registers in the configuration space. This chapter describes these address ranges, as well as ISA-mode and VGA-addressing support.
5.1 Address Ranges
PI7C7100 uses the following address ranges that determine which I/O and memory transactions are forwarded from the primary PCI bus to the secondary PCI bus, and from the secondary bus to the primary bus: * Two 32-bit I/O address ranges * Two 32-bit memory-mapped I/O (non-prefetchable memory) ranges * Two 32-bit prefetchable memory address ranges Transactions falling within these ranges are forwarded downstream from the primary PCI bus to the two secondary PCI buses. Transactions falling outside these ranges are forwarded upstream from the two secondary PCI buses to the primary PCI bus. No address translation is required in PI7C7100. The addresses that are not marked for downstream are always forwarded upstream. However, if an address of a transaction initiated from S1 bus is located in the marked address range for downstream in S2 bus and not in the marked address range for downstream in S1 bus, the transaction will be forwarded to S2 bus instead of primary bus. By the same token, if an address of a transaction initiated from S2 bus is located in the marked address range for downstream in S1 bus and not in the marked address range for downstream in S2 bus, the transaction will be forwarded to S1 bus instead of primary bus.
5.2 I/O Address Decoding
PI7C7100 uses the following mechanisms that are defined in the configuration space to specify the I/O address space for downstream and upstream forwarding: * I/O base and limit address registers * The ISA enable bit * The VGA mode bit * The VGA snoop bit This section provides information on the I/O address registers and ISA mode. Section 5.4 provides information on the VGA modes. To enable downstream forwarding of I/O transactions, the I/O enable bit must be set in the command register in configuration space. All I/O transactions initiated on the primary bus will be ignored if the I/O enable bit is not set. To enable upstream forwarding of I/O transactions, the master enable bit must be set in the command register. If the masterenable bit is not set, PI7C7100 ignores all I/O and memory transactions initiated on the secondary bus. The masterenable bit also allows upstream forwarding of memory transactions if it is set. CAUTION
If any configuration state affecting I/O transaction forwarding is changed by a configuration write operation on the primary bus at the same time that I/O transactions are ongoing on the secondary bus, PI7C7100 response to the secondary bus I/O transactions is not predictable. Configure the I/O base and limit address registers, ISA enable bit, VGA mode bit, and VGA snoop bit before setting I/O enable and master enable bits, and change them subsequently only when the primary and secondary PCI buses are idle.
5.2.1 I/O Base and Limit Address Registers
PI7C7100 implements one set of I/O base and limit address registers in configuration space that define an I/O address range per port downstream forwarding. PI7C7100 supports 32-bit I/O addressing, which allows I/O addresses downstream of PI7C7100 to be mapped anywhere in a 4GB I/O address space.
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PI7C7100 3-Port PCI Bridge
I/O transactions with addresses that fall inside the range defined by the I/O base and limit registers are forwarded downstream from the primary PCI bus to the secondary PCI bus. I/O transactions with addresses that fall outside this range are forwarded upstream from the secondary PCI bus to the primary PCI bus. The I/O range can be turned off by setting the I/O base address to a value greater than that of the I/O limit address. When the I/O range is turned off, all I/O transactions are forwarded upstream, and no I/O transactions are forwarded downstream. The I/O range has a minimum granularity of 4KB and is aligned on a 4KB boundary. The maximum I/O range is 4GB in size. The I/O base register consists of an 8-bit field at configuration address 1Ch, and a 16-bit field at address 30h. The top 4 bits of the 8-bit field define bits [15:12] of the I/O base address. The bottom 4 bits read only as 1h to indicate that PI7C7100 supports 32-bit I/O addressing. Bits [11:0] of the base address are assumed to be 0, which naturally aligns the base address to a 4KB boundary. The 16 bits contained in the I/O base upper 16 bits register at configuration offset 30h define AD[31:16] of the I/O base address. All 16 bits are read/write. After primary bus reset or chip reset, the value of the I/O base address is initialized to 0000 0000h. The I/O limit register consists of an 8-bit field at configuration offset 1Dh and a 16-bit field at offset 32h. The top 4 bits of the 8-bit field define bits [15:12] of the I/O limit address. The bottom 4 bits read only as 1h to indicate that 32-bit I/O addressing is supported. Bits [11:0] of the limit address are assumed to be FFFh, which naturally aligns the limit address to the top of a 4KB I/O address block. The 16 bits contained in the I/O limit upper 16 bits register at configuration offset 32h define AD[31:16] of the I/O limit address. All 16 bits are read/write. After primary bus reset or chip reset, the value of the I/O limit address is reset to 0000 0FFFh. Note: The initial states of the I/O base and I/O limit address registers define an I/O range of 0000 0000h to 0000 0FFFh, which is the bottom 4KB of I/O space. Write these registers with their appropriate values before setting either the I/O enable bit or the master enable bit in the command register in configuration space.
5.2.2 ISA Mode
PI7C7100 supports ISA mode by providing an ISA enable bit in the bridge control register in configuration space. ISA mode modifies the response of PI7C7100 inside the I/O address range in order to support mapping of I/O space in the presence of an ISA bus in the system. This bit only affects the response of PI7C7100 when the transaction falls inside the address range defined by the I/O base and limit address registers, and only when this address also falls inside the first 64KB of I/O space (address bits [31:16] are 0000h). When the ISA enable bit is set, PI7C7100 does not forward downstream any I/O transactions addressing the top 768 bytes of each aligned 1KB block. Only those transactions addressing the bottom 256 bytes of an aligned 1KB block inside the base and limit I/O address range are forwarded downstream. Transactions above the 64KB I/O address boundary are forwarded as defined by the address range defined by the I/O base and limit registers. Accordingly, if the ISA enable bit is set, PI7C7100 forwards upstream those I/O transactions addressing the top 768 bytes of each aligned 1KB block within the first 64KB of I/O space. The master enable bit in the command configuration register must also be set to enable upstream forwarding. All other I/O transactions initiated on the secondary bus are forwarded upstream only if they fall outside the I/O address range. When the ISA enable bit is set, devices downstream of PI7C7100 can have I/O space mapped into the first 256 bytes of each 1KB chunk below the 64KB boundary, or anywhere in I/O space above the 64KB boundary.
5.3 Memory Address Decoding
PI7C7100 has three mechanisms for defining memory address ranges for forwarding of memory transactions: * Memory-mapped I/O base and limit address registers * Prefetchable memory base and limit address registers * VGA mode This section describes the first two mechanisms. Section 5.4.1 describes VGA mode. To enable downstream forwarding of memory transactions, the memory enable bit must be set in the command register in configuration space. To enable upstream forwarding of memory transactions, the master-enable bit must be set in the command register. The master-enable bit also allows upstream forwarding of I/O transactions if it is set.
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PI7C7100 3-Port PCI Bridge
CAUTION If any configuration state affecting memory transaction forwarding is changed by a configuration write operation on the primary bus at the same time that memory transactions are ongoing on the secondary bus, response to the secondary bus memory transactions is not predictable. Configure the memory-mapped I/ O base and limit address registers, prefetchable memory base and limit address registers, and VGA mode bit before setting the memory enable and master enable bits, and change them subsequently only when the primary and secondary PCI buses are idle.
5.3.1 Memory-Mapped I/O Base and Limit Address Registers
Memory-mapped I/O is also referred to as non-prefetchable memory. Memory addresses that cannot automatically be prefetched but that can be conditionally pre-fetched based on command type should be mapped into this space. Read transactions to non-prefetchable space may exhibit side effects; this space may have non-memory-like behavior. PI7C7100 pre-fetches in this space only if the memory read line or memory read multiple commands are used; transactions using the memory read command are limited to a single data transfer. The memory-mapped I/O base address and memory-mapped I/O limit address registers define an address range that PI7C7100 uses to determine when to forward memory commands. PI7C7100 forwards a memory transaction from the primary to the secondary interface if the transaction address falls within the memory-mapped I/O address range. PI7C7100 ignores memory transactions initiated on the secondary interface that fall into this address range. Any transactions that fall outside this address range are ignored on the primary interface and are forwarded upstream from the secondary interface (provided that they do not fall into the prefetchable memory range or are not forwarded downstream by the VGA mechanism). The memory-mapped I/O range supports 32-bit addressing only. The PCI-to-PCI Bridge Architecture Specification does not provide for 64-bit addressing in the memory-mapped I/O space. The memory-mapped I/O address range has a granularity and alignment of 1MB. The maximum memory-mapped I/O address range is 4GB. The memory-mapped I/O address range is defined by a 16-bit memory-mapped I/O base address register at configuration offset 20h and by a 16-bit memory-mapped I/O limit address register at offset 22h. The top 12 bits of each of these registers correspond to bits [31:20] of the memory address. The low 4 bits are hardwired to 0. The lowest 20 bits of the memorymapped I/O base address are assumed to be 0 0000h, which results in a natural alignment to a 1MB boundary. The lowest 20 bits of the memory-mapped I/O limit address are assumed to be F FFFFh, which results in an alignment to the top of a 1MB block. Note: The initial state of the memory-mapped I/O base address register is 0000 0000h. The initial state of the memorymapped I/O limit address register is 000F FFFFh. Note that the initial states of these registers define a memory-mapped I/O range at the bottom 1MB block of memory. Write these registers with their appropriate values before setting either the memory enable bit or the master enable bit in the command register in configuration space. To turn off the memory-mapped I/O address range, write the memory-mapped I/O base address register with a value greater than that of the memory-mapped I/O limit address register.
5.3.2 Prefetchable Memory Base and Limit Address Registers
Locations accessed in the prefetchable memory address range must have true memory-like behavior and must not exhibit side effects when read. This means that extra reads to a prefetchable memory location must have no side effects. PI7C7100 pre-fetches for all types of memory read commands in this address space. The prefetchable memory base address and prefetchable memory limit address registers define an address range that PI7C7100 uses to determine when to forward memory commands. PI7C7100 forwards a memory transaction from the primary to the secondary interface if the transaction address falls within the prefetchable memory address range. PI7C7100 ignores memory transactions initiated on the secondary interface that fall into this address range. PI7C7100 does not respond to any transactions that fall outside this address range on the primary interface and forwards those transactions upstream from the secondary interface (provided that they do not fall into the memory-mapped I/O range or are not forwarded by the VGA mechanism). The prefetchable memory range supports 64-bit addressing and provides additional registers to define the upper 32 bits of the memory address range, the prefetchable memory base address upper 32 bits register, and the prefetchable memory limit address upper 32 bits register. For address comparison, a single address cycle (32-bit address) prefetchable memory transaction is treated like a 64-bit address transaction where the upper 32 bits of the address are equal to 0. This upper
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PI7C7100 3-Port PCI Bridge
32-bit value of 0 is compared to the prefetchable memory base address upper 32 bits register and the prefetchable memory limit address upper 32 bits register. The prefetchable memory base address upper 32 bits register must be 0 to pass any single address cycle transactions downstream. Prefetchable memory address range has a granularity and alignment of 1MB. Maximum memory address range is 4GB when 32-bit addressing is being used. Prefetchable memory address range is defined by a 16-bit prefetchable memory base address register at configuration offset 24h and by a 16-bit prefetchable memory limit address register at offset 26h. The top 12 bits of each of these registers correspond to bits [31:20] of the memory address. The lowest 4 bits are hardwired to 1h. The lowest 20 bits of the prefetchable memory base address are assumed to be 0 0000h, which results in a natural alignment to a 1MB boundary. The lowest 20 bits of the prefetchable memory limit address are assumed to be FFFFFh, which results in an alignment to the top of a 1MB block. Note: The initial state of the prefetchable memory base address register is 0000 0000h. The initial state of the prefetchable memory limit address register is 000F FFFFh. Note that the initial states of these registers define a prefetchable memory range at the bottom 1MB block of memory. Write these registers with their appropriate values before setting either the memory enable bit or the master enable bit in the command register in configuration space. To turn off the prefetchable memory address range, write the prefetchable memory base address register with a value greater than that of the prefetchable memory limit address register. The entire base value must be greater than the entire limit value, meaning that the upper 32 bits must be considered. Therefore, to disable the address range, the upper 32 bits registers can both be set to the same value, while the lower base register is set greater than the lower limit register. Otherwise, the upper 32-bit base must be greater than the upper 32-bit limit.
5.4 VGA Support
PI7C7100 provides two modes for VGA support: * VGA mode, supporting VGA-compatible addressing * VGA snoop mode, supporting VGA palette forwarding
5.4.1 VGA Mode
When a VGA-compatible device exists downstream from PI7C7100, set the VGA mode bit in the bridge control register in configuration space to enable VGA mode. When PI7C7100 is operating in VGA mode, it forwards downstream those transactions addressing the VGA frame buffer memory and VGA I/O registers, regardless of the values of the base and limit address registers. PI7C7100 ignores transactions initiated on the secondary interface addressing these locations. The VGA frame buffer consists of the following memory address range: 000A 0000h-000B FFFFh Read transactions to frame buffer memory are treated as non-prefetchable. PI7C7100 requests only a single data transfer from the target, and read byte enable bits are forwarded to the target bus. The VGA I/O addresses are in the range of 3B0h-3BBh and 3C0h-3DFh I/O. These I/O addresses are aliases every 1KB throughout the first 64KB of I/O space. This means that address bits <15:10> are not decoded and can be any value, while address bits [31:16] must be all 0s. VGA BIOS addresses starting at C0000h are not decoded in VGA mode.
5.4.2 VGA Snoop Mode
PI7C7100 provides VGA snoop mode, allowing for VGA palette write transactions to be forwarded downstream. This mode is used when a graphics device downstream from PI7C7100 needs to snoop or respond to VGA palette write transactions. To enable the mode, set the VGA snoop bit in the command register in configuration space. Note that PI7C7100 claims VGA palette write transactions by asserting DEVSEL# in VGA snoop mode. When VGA snoop bit is set, PI7C7100 forwards downstream transactions within the 3C6h, 3C8h and 3C9h I/O addresses space. Note that these addresses are also forwarded as part of the VGA compatibility mode previously described. Again, address bits <15:10> are not decoded, while address bits <31:16> must be equal to 0, which means that these addresses are aliases every 1KB throughout the first 64KB of I/O space. Note: If both the VGA mode bit and the VGA snoop bit are set, PI7C7100 behaves in the same way as if only the VGA mode bit were set.
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PI7C7100 3-Port PCI Bridge
6. Transaction Ordering
To maintain data coherency and consistency, PI7C7100 complies with the ordering rules set forth in the PCI Local Bus Specification, Revision 2.1, for transactions crossing the bridge. This chapter describes the ordering rules that control transaction forwarding across PI7C7100.
6.1 Transactions Governed by Ordering Rules
Ordering relationships are established for the following classes of transactions crossing PI7C7100: * Posted write transactions, comprised of memory write and memory write and invalidate transactions. Posted write transactions complete at the source before they complete at the destination; that is, data is written into intermediate data buffers before it reaches the target. * Delayed write request transactions, comprised of I/O write and configuration write transactions. Delayed write requests are terminated by target retry on the initiator bus and are queued in the delayed transaction queue. A delayed write transaction must complete on the target bus before it completes on the initiator bus. * Delayed write completion transactions, comprised of I/O write and configuration write transactions. Delayed write completion transactions complete on the target bus, and the target response is queued in the buffers. A delayed write completion transaction proceeds in the direction opposite that of the original delayed write request; that is, a delayed write completion transaction proceeds from the target bus to the initiator bus. * Delayed read request transactions, comprised of all memory read, I/O read, and configuration read transactions. Delayed read requests are terminated by target retry on the initiator bus and are queued in the delayed transaction queue. * Delayed read completion transactions, comprised of all memory read, I/O read, & configuration read transactions. Delayed read completion transactions complete on the target bus, and the read data is queued in the read data buffers. A delayed read completion transaction proceeds in the direction opposite that of the original delayed read request; that is, a delayed read completion transaction proceeds from the target bus to the initiator bus. PI7C7100 does not combine or merge write transactions: * PI7C7100 does not combine separate write transactions into a single write transaction--this optimization is best implemented in the originating master. * PI7C7100 does not merge bytes on separate masked write transactions to the same DWORD address--this optimization is also best implemented in the originating master. * PI7C7100 does not collapse sequential write transactions to the same address into a single write transaction--the PCI Local Bus Specification does not permit this combining of transactions.
6.2 General Ordering Guidelines
Independent transactions on primary and secondary buses have a relationship only when those transactions cross PI7C7100. The following general ordering guidelines govern transactions crossing PI7C7100: * The ordering relationship of a transaction with respect to other transactions is determined when the transaction completes, that is, when a transaction ends with a termination other than target retry. * Requests terminated with target retry can be accepted and completed in any order with respect to other transactions that have been terminated with target retry. If the order of completion of delayed requests is important, the initiator should not start a second delayed transaction until the first one has been completed. If more than one delayed transaction is initiated, the initiator should repeat all delayed transaction requests, using some fairness algorithm. Repeating a delayed transaction cannot be contingent on completion of another delayed transaction. Otherwise, a deadlock can occur.
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* Write transactions flowing in one direction have no ordering requirements with respect to write transactions flowing in the other direction. PI7C7100 can accept posted write transactions on both interfaces at the same time, as well as initiate posted write transactions on both interfaces at the same time. * The acceptance of a posted memory write transaction as a target can never be contingent on the completion of a non-locked, non-posted transaction as a master. This is true for PI7C7100 and must also be true for other bus agents. Otherwise, a deadlock can occur. * PI7C7100 accepts posted write transactions, regardless of the state of completion of any delayed transactions being forwarded across PI7C7100.
6.3 Ordering Rules
Table 6-1 shows the ordering relationships of all the transactions and refers by number to the ordering rules that follow. Table 6-1. Summary of Transaction Ordering
P ass Posted write Delayed read request Delayed write request Delayed read completion Delayed write completion Posted Write N1 N2 N4 N3 Y Delayed Read R eq u est Y5 N N Y Y Delayed Write R eq u est Y5 N N Y Y Delayed Read Completion Y5 Y Y N N Delayed Write Completion Y5 Y Y N N
Note: The superscript accompanying some of the table entries refers to any applicable ordering rule listed in this section. Many entries are not governed by these ordering rules; therefore, the implementation can choose whether or not the transactions pass each other. The entries without superscripts reflect the PI7C7100's implementation choices. The following ordering rules describe the transaction relationships. Each ordering rule is followed by an explanation, and the ordering rules are referred to by number in Table 6-1. These ordering rules apply to posted write transactions, delayed write and read requests, and delayed write and read completion transactions crossing PI7C7100 in the same direction. Note that delayed completion transactions cross PI7C7100 in the direction opposite that of the corresponding delayed requests. 1. Posted write transactions must complete on the target bus in the order in which they were received on the initiator bus. The subsequent posted write transaction can be setting a flag that covers the data in the first posted write transaction; if the second transaction were to complete before the first transaction, a device checking the flag could subsequently consume stale data. 2. A delayed read request traveling in the same direction as a previously queued posted write transaction must push the posted write data ahead of it. The posted write transaction must complete on the target bus before the delayed read request can be attempted on the target bus. The read transaction can be to the same location as the write data, so if the read transaction were to pass the write transaction, it would return stale data. 3. A delayed read completion must ``pull'' ahead of previously queued posted write data traveling in the same direction. In this case, the read data is traveling in the same direction as the write data, and the initiator of the read transaction is on the same side of PI7C7100 as the target of the write transaction. The posted write transaction must complete to the target before the read data is returned to the initiator. The read transaction can be a reading to a status register of the initiator of the posted write data and therefore should not complete until the write transaction is complete. 4. Delayed write requests cannot pass previously queued posted write data. For posted memory write transactions, the delayed write transaction can set a flag that covers the data in the posted write transaction. If the delayed write request were to complete before the earlier posted write transaction, a device checking the flag could subsequently consume stale data.
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PI7C7100 3-Port PCI Bridge
5. Posted write transactions must be given opportunities to pass delayed read and write requests and completions. Otherwise, deadlocks may occur when some bridges which support delayed transactions and other bridges which do not support delayed transactions are being used in the same system. A fairness algorithm is used to arbitrate between the posted write queue and the delayed transaction queue.
6.4 Data Synchronization
Data synchronization refers to the relationship between interrupt signaling and data delivery. The PCI Local Bus Specification, Revision 2.1, provides the following alternative methods for synchronizing data and interrupts: * The device signaling the interrupt performs a read of the data just written (software). * The device driver performs a read operation to any register in the interrupting device before accessing data written by the device (software). * System hardware guarantees that write buffers are flushed before interrupts are forwarded. PI7C7100 does not have a hardware mechanism to guarantee data synchronization for posted write transactions. Therefore, all posted write transactions must be followed by a read operation, either from the device to the location just written (or some other location along the same path), or from the device driver to one of the device registers.
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PI7C7100 3-Port PCI Bridge
7. Error Handling
PI7C7100 checks, forwards, and generates parity on both the primary and secondary interfaces. To maintain transparency, PI7C7100 always tries to forward the existing parity condition on one bus to the other bus, along with address and data. PI7C100 always attempts to be transparent when reporting errors, but this is not always possible, given the presence of posted data and delayed transactions. To support error reporting on the PCI bus, PI7C7100 implements the following: * PERR# and SERR# signals on both the primary and secondary interfaces * Primary status and secondary status registers * The device-specific P_SERR# event disable register This chapter provides detailed information about how PI7C7100 handles errors. It also describes error status reporting and error operation disabling.
7.1 Address Parity Errors
PI7C7100 checks address parity for all transactions on both buses, for all address and all bus commands. When PI7C7100 detects an address parity error on the primary interface, the following events occur: * If the parity error response bit is set in the command register, PI7C7100 does not claim the transaction with P_DEVSEL#; this may allow the transaction to terminate in a master abort. If parity error response bit is not set, PI7C7100 proceeds normally and accepts the transaction if it is directed to or across PI7C7100. * PI7C7100 sets the detected parity error bit in the status register. * PI7C7100 asserts P_SERR# and sets signaled system error bit in the status register, if both the following conditions are met: - The SERR# enable bit is set in the command register. - The parity error response bit is set in the command register. When PI7C7100 detects an address parity error on the secondary interface, the following events occur: * If the parity error response bit is set in the bridge control register, PI7C7100 does not claim the transaction with S1_DEVSEL# or S2_DEVSEL#; this may allow the transaction to terminate in a master abort. If parity error response bit is not set, PI7C7100 proceeds normally and accepts transaction if it is directed to or across PI7C7100. * PI7C7100 sets the detected parity error bit in the secondary status register. * PI7C7100 asserts P_SERR# and sets signaled system error bit in status register, if both of the following conditions are met: - The SERR# enable bit is set in the command register. - The parity error response bit is set in the bridge control register.
7.2 Data Parity Errors
When forwarding transactions, PI7C7100 attempts to pass the data parity condition from one interface to the other unchanged, whenever possible, to allow the master and target devices to handle the error condition. The following sections describe, for each type of transaction, the sequence of events that occurs when a parity error is detected and the way in which the parity condition is forwarded across PI7C7100.
7.2.1 Configuration Write Transactions to Configuration Space
When PI7C7100 detects a data parity error during a Type 0 configuration write transaction to PI7C7100 configuration space, the following events occur: * If the parity error response bit is set in the command register, PI7C7100 asserts P_TRDY# and writes the data to the configuration register. PI7C7100 also asserts P_PERR#. If the parity error response bit is not set, PI7C7100 does not assert P_PERR#. * PI7C7100 sets the detected parity error bit in the status register, regardless of the state of the parity error response bit.
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PI7C7100 3-Port PCI Bridge
7.2.2 Read Transactions
When PI7C7100 detects a parity error during a read transaction, the target drives data and data parity, and the initiator checks parity and conditionally asserts PERR#. For downstream transactions, when PI7C7100 detects a read data parity error on the secondary bus, the following events occur: * * * * PI7C7100 asserts S_PERR# two cycles following the data transfer, if the secondary interface parity error response bit is set in the bridge control register. PI7C7100 sets the detected parity error bit in the secondary status register. PI7C7100 sets the data parity detected bit in the secondary status register, if the secondary interface parity error response bit is set in the bridge control register. PI7C7100 forwards the bad parity with the data back to the initiator on the primary bus. If the data with the bad parity is pre-fetched and is not read by the initiator on the primary bus, the data is discarded and the data with bad parity is not returned to the initiator. PI7C7100 completes the transaction normally. PI7C7100 asserts P_PERR# two cycles following the data transfer, if the primary interface parity error response bit is set in the command register. PI7C7100 sets the detected parity error bit in the primary status register. PI7C7100 sets the data parity detected bit in the primary status register, if the primary interface parity-errorresponse bit is set in the command register. PI7C7100 forwards the bad parity with the data back to the initiator on the secondary bus. If the data with the bad parity is pre-fetched and is not read by the initiator on the secondary bus, the data is discarded and the data with bad parity is not returned to the initiator. PI7C7100 completes the transaction normally. PI7C7100 returns to the initiator the data and parity that was received from the target. When the initiator detects a parity error on this read data and is enabled to report it, the initiator asserts PERR# two cycles after the data transfer occurs. It is assumed that the initiator takes responsibility for handling a parity error condition; therefore, when PI7C7100 detects PERR# asserted while returning read data to the initiator, PI7C7100 does not take any further action and completes the transaction normally.
* * * * *
For upstream transactions, when PI7C7100 detects a read data parity error on the primary bus, the following events occur:
*
7.2.3 Delayed Write Transactions
When PI7C7100 detects a data parity error during a delayed write transaction, the initiator drives data and data parity, and the target checks parity and conditionally asserts PERR#. For delayed write transactions, a parity error can occur at the following times: * * * During the original delayed write request transaction When the initiator repeats the delayed write request transaction When PI7C7100 completes the delayed write transaction to the target
When a delayed write transaction is normally queued, the address, command, address parity, data, byte enable bits, and data parity are all captured and a target retry is returned to the initiator. When PI7C7100 detects a parity error on the write data for the initial delayed write request transaction, the following events occur: * If the parity-error-response bit corresponding to the initiator bus is set, PI7C7100 asserts TRDY# to the initiator and the transaction is not queued. If multiple data phases are requested, STOP# is also asserted to cause a target disconnect. Two cycles after the data transfer, PI7C7100 also asserts PERR#. If the parity-error-response bit is not set, PI7C7100 returns a target retry. It queues the transaction as usual. PI7C7100 does not assert PERR#. In this case, the initiator repeats the transaction. * PI7C7100 sets the detected-parity-error bit in the status register corresponding to the initiator bus, regardless of the state of the parity-error-response bit.
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PI7C7100 3-Port PCI Bridge
Note: If parity checking is turned off and data parity errors have occurred for queued or subsequent delayed write transactions on the initiator bus, it is possible that the initiator's re-attempts of the write transaction may not match the original queued delayed write information contained in the delayed transaction queue. In this case, a master timeout condition may occur, possibly resulting in a system error (P_SERR# assertion). For downstream transactions, when PI7C7100 is delivering data to the target on the secondary bus and S_PERR# is asserted by the target, the following events occur: * * PI7C7100 sets the secondary interface data parity detected bit in the secondary status register, if the secondary parity error response bit is set in the bridge control register. PI7C7100 captures the parity error condition to forward it back to the initiator on the primary bus.
Similarly, for upstream transactions, when PI7C7100 is delivering data to the target on the primary bus and P_PERR# is asserted by the target, the following events occur: * * PI7C7100 sets the primary interface data-parity-detected bit in the status register, if the primary parity-errorresponse bit is set in the command register. PI7C7100 captures the parity error condition to forward it back to the initiator on the secondary bus.
A delayed write transaction is completed on the initiator bus when the initiator repeats the write transaction with the same address, command, data, and byte enable bits as the delayed write command that is at the head of the posted data queue. Note that the parity bit is not compared when determining whether the transaction matches those in the delayed transaction queues. Two cases must be considered: * * When parity error is detected on the initiator bus on a subsequent re-attempt of the transaction and was not detected on the target bus When parity error is forwarded back from the target bus
For downstream delayed write transactions, when the parity error is detected on the initiator bus and PI7C7100 has write status to return, the following events occur: * * * PI7C7100 first asserts P_TRDY# and then asserts P_PERR# two cycles later, if the primary interface parityerror-response bit is set in the command register. PI7C7100 sets the primary interface parity-error-detected bit in the status register. Because there was not an exact data and parity match, the write status is not returned and the transaction remains in the queue.
Similarly, for upstream delayed write transactions, when the parity error is detected on the initiator bus and PI7C7100 has write status to return, the following events occur: * * * PI7C7100 first asserts S1_TRDY# or S2_TRDY# and then asserts S_PERR# two cycles later, if the secondary interface parity-error-response bit is set in the bridge control register (offset 3Ch). PI7C7100 sets the secondary interface parity-error-detected bit in the secondary status register. Because there was not an exact data and parity match, the write status is not returned and the transaction remains in the queue.
For downstream transactions, where the parity error is being passed back from the target bus and the parity error condition was not originally detected on the initiator bus, the following events occur: * PI7C7100 asserts P_PERR# two cycles after the data transfer, if the following are both true: - The parity-error-response bit is set in the command register of the primary interface. - The parity-error-response bit is set in the bridge control register of the secondary interface. * PI7C7100 completes the transaction normally.
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PI7C7100 3-Port PCI Bridge
For upstream transactions, when the parity error is being passed back from the target bus and the parity error condition was not originally detected on the initiator bus, the following events occur: * PI7C7100 asserts S_PERR# two cycles after the data transfer, if the following are both true: - The parity error response bit is set in the command register of the primary interface. - The parity error response bit is set in the bridge control register of the secondary interface. * PI7C7100 completes the transaction normally.
7.2.4 Posted Write Transactions
During downstream posted write transactions, when PI7C7100 responds as a target, it detects a data parity error on the initiator (primary) bus, the following events occur: * * * * PI7C7100 asserts P_PERR# two cycles after the data transfer, if the parity error response bit is set in the command register of primary interface. PI7C7100 sets the parity error detected bit in the status register of the primary interface. PI7C7100 captures and forwards the bad parity condition to the secondary bus. PI7C7100 completes the transaction normally.
Similarly, during upstream posted write transactions, when PI7C7100 responds as a target, it detects a data parity error on the initiator (secondary) bus, the following events occur: * * * * PI7C7100 asserts S_PERR# two cycles after the data transfer, if the parity error response bit is set in the bridge control register of the secondary interface. PI7C7100 sets the parity error detected bit in the status register of the secondary interface. PI7C7100 captures and forwards the bad parity condition to the primary bus. PI7C7100 completes the transaction normally.
During downstream write transactions, when a data parity error is reported on the target (secondary) bus by the target's assertion of S_PERR#, the following events occur: * * PI7C7100 sets the data parity detected bit in the status register of secondary interface, if the parity error response bit is set in the bridge control register of the secondary interface. PI7C7100 asserts P_SERR# and sets the signaled system error bit in the status register, if all the following conditions are met: - The SERR# enable bit is set in the command register. - The posted write parity error bit of P_SERR# event disable register is not set. - The parity error response bit is set in the bridge control register of the secondary interface. - The parity error response bit is set in the command register of the primary interface. - PI7C7100 has not detected the parity error on the primary (initiator) bus which the parity error is not forwarded from the primary bus to the secondary bus. During upstream write transactions, when a data parity error is reported on the target (primary) bus by the target's assertion of P_PERR#, the following events occur: * * PI7C7100 sets the data parity detected bit in the status register, if the parity error response bit is set in the command register of the primary interface. PI7C7100 asserts P_SERR# and sets the signaled system error bit in the status register, if all the following conditions are met: - The SERR# enable bit is set in the command register. - The parity error response bit is set in the bridge control register of the secondary interface. - The parity error response bit is set in the command register of the primary interface. - PI7C7100 has not detected the parity error on the secondary (initiator) bus which the parity error is not forwarded from the secondary bus to the primary bus. Assertion of P_SERR# is used to signal the parity error condition when the initiator does not know that the error occurred.
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PI7C7100 3-Port PCI Bridge
Because the data has already been delivered with no errors, there is no other way to signal this information back to the initiator. If the parity error has forwarded from the initiating bus to the target bus, P_SERR# will not be asserted.
7.3 Data Parity Error Reporting Summary
In the previous sections, the responses of PI7C7100 to data parity errors are presented according to the type of transaction in progress. This section organizes the responses of PI7C7100 to data parity errors according to the status bits that PI7C7100 sets and the signals that it asserts. Table 7-1 shows setting the detected parity error bit in the status register, corresponding to the primary interface. This bit is set when PI7C7100 detects a parity error on the primary interface. Table 7-1 Setting the Primary Interface Detected Parity Error Bit
Primary detected parity error bit 0 0 1 0 1 0 0 0 1 0 0 0
1
Transaction Type Read Read Read Read Posted write Posted write Posted write Posted write Delayed write Delayed write Delayed write Delayed write
Direction Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream
Bus w here error w as detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary
Primary/Secondary parity error response bits x/x1 x/x x/x x/x x/x x/x x/x x/x x/x x/x x/x x/x
x =don't care
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PI7C7100 3-Port PCI Bridge
Table 7-2 shows setting the detected parity error bit in the secondary status register, corresponding to the secondary interface. This bit is set when PI7C7100 detects a parity error on the secondary interface. Table 7-2. Setting Secondary Interface Detected Parity Error Bit
Secondary detected parity error bit 0 1 0 0 0 0 0 1 0 0 0 1 Transaction Type Read Read Read Read Posted write Posted write Posted write Posted write Delayed write Delayed write Delayed write Delayed write Direction Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Bus w here error w as detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary/Secondary parity error response bits x/x1 x/x x/x x/x x/x x/x x/x x/x x/x x/x x/x x/x
Table 7-3 shows setting data parity detected bit in the primary interface's status register. This bit is set under the following conditions: * PI7C7100 must be a master on the primary bus. * The parity error response bit in the command register, corresponding to the primary interface, must be set. * The P_PERR# signal is detected asserted or a parity error is detected on the primary bus. Table 7-3. Setting Primary Interface Data Parity Detected Bit
Primary data parity bit 0 0 1 0 0 0 1 0 0 0 1 0
1
Transaction Type Read Read Read Read Posted write Posted write Posted write Posted write Delayed write Delayed write Delayed write Delayed write
Direction Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream
Bus w here error w as detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary
Primary/Secondary parity error response bits x/x1 x/x 1/x x/x x/x x/x 1/x x/x x/x x/x 1/x x/x
x =don't care
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PI7C7100 3-Port PCI Bridge
Table 7-4 shows setting the data parity detected bit in the status register of secondary interface. This bit is set under the following conditions: * The PI7C7100 must be a master on the secondary bus. * The parity error response bit must be set in the bridge control register of secondary interface. * The S_PERR# signal is detected asserted or a parity error is detected on the secondary bus. Table 7-4. Setting Secondary Interface Data Parity Detected Bit
Secondary data parity detected bit 0 1 0 0 0 1 0 0 0 1 0 0
1
Transaction Type Read Read Read Read Posted write Posted write Posted write Posted write Delayed write Delayed write Delayed write Delayed write
Direction Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream
Bus w here error w as detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary
Primary/Secondary parity error response bits x/x1 x/1 x/x x/x x/x x/1 x/x x/x x/x x/1 x/x x/x
x =don't care
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PI7C7100 3-Port PCI Bridge
Table 7-5 shows assertion of P_PERR#. This signal is set under the following conditions: * PI7C7100 is either the target of a write transaction or the initiator of a read transaction on the primary bus. * The parity-error-response bit must be set in the command register of primary interface. * PI7C7100 detects a data parity error on the primary bus or detects S_PERR# asserted during the completion phase of a downstream delayed write transaction on the target (secondary) bus. Table 7-5. Assertion of P_PERR#
P _P E R R # 1 (de-asserted) 1 0 (asserted) 1 0 1 1 1 0 02 1 1
1 2
Transaction Type Read Read Read Read Posted write Posted write Posted write Posted write Delayed write Delayed write Delayed write Delayed write
Direction Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream
Bus w here error w as detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary
Primary/Secondary parity error response bits x/x1 x/x 1/x x/x 1/x x/x x/x x/x 1/x 1/1 x/x x/x
x =don't care The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
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PI7C7100 3-Port PCI Bridge
Table 7-6 shows assertion of S_PERR# that is set under the following conditions: * PI7C7100 is either the target of a write transaction or the initiator of a read transaction on the secondary bus. * The parity error response bit must be set in the bridge control register of secondary interface. * PI7C7100 detects a data parity error on the secondary bus or detects P_PERR# asserted during the completion phase of an upstream delayed write transaction on the target (primary) bus. Table 7-6. Assertion of S_PERR#
S _P E R R # 1 (de-asserted) 0 (asserted) 1 1 1 1 1 0 1 1 02 0
1 2
Transaction Type Read Read Read Read Posted write Posted write Posted write Posted write Delayed write Delayed write Delayed write Delayed write
Direction Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream
Bus w here error w as detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary
Primary/Secondary parity error response bits x/x1 x/1 x/x x/x x/x x/x x/x x/1 x/x x/x 1/1 x/1
x =don't care The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
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PI7C7100 3-Port PCI Bridge
Table 7-7 shows assertion of P_SERR#. This signal is set under the following conditions: * PI7C7100 has detected P_PERR# asserted on an upstream posted write transaction or S_PERR# asserted on a downstream posted write transaction. * PI7C7100 did not detect the parity error as a target of the posted write transaction. * The parity error response bit on the command register and the parity error response bit on the bridge control register must both be set. * The SERR# enable bit must be set in the command register.
Table 7-7. Assertion of P_SERR# for Data Parity Errors
P _S E R R # 1 (de-asserted) 1 1 1 1 02 (asserted) 03 1 1 1 1 1
1 2
Transaction Type Read Read Read Read Posted write Posted write Posted write Posted write Delayed write Delayed write Delayed write Delayed write
Direction Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream
Bus w here error w as detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary
Primary/Secondary parity error response bits x/x1 x/x x/x x/x x/x 1/1 1/1 x/x x/x x/x x/x x/x
x =don't care The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus. 3 The parity error was detected on the target (primary) bus but not on the initiator (secondary) bus.
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PI7C7100 3-Port PCI Bridge
7.4 System Error (SERR#) Reporting
PI7C7100 uses the P_SERR# signal to report conditionally a number of system error conditions in addition to the special case parity error conditions described in Section 7.2.3. Whenever assertion of P_SERR# is discussed in this document, it is assumed that the following conditions apply: * For PI7C7100 to assert P_SERR# for any reason, the SERR# enable bit must be set in the command register. * Whenever PI7C7100 asserts P_SERR#, PI7C7100 must also set the signaled system error bit in the status register. In compliance with the PCI-to-PCI Bridge Architecture Specification, PI7C7100 asserts P_SERR# when it detects the secondary SERR# input, S_SERR#, asserted and the SERR# forward enable bit is set in the bridge control register. In addition, PI7C7100 also sets the received system error bit in the secondary status register. PI7C7100 also conditionally asserts P_SERR# for any of the following reasons: * Target abort detected during posted write transaction * Master abort detected during posted write transaction * Posted write data discarded after 224(default) attempts to deliver (224 target retries received) * Parity error reported on target bus during posted write transaction (see previous section) * Delayed write data discarded after 224(default) attempts to deliver (224 target retries received) * Delayed read data cannot be transferred from target after 224(default) attempts (224 target retries received) * Master timeout on delayed transaction The device-specific P_SERR# status register reports the reason for the assertion of P_SERR#. Most of these events have additional device-specific disable bits in the P_SERR# event disable register that make it possible to mask out P_SERR# assertion for specific events. The master timeout condition has a SERR# enable bit for that event in the bridge control register and therefore does not have a device-specific disable bit.
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PI7C7100 3-Port PCI Bridge
8. Exclusive Access
This chapter describes the use of the LOCK# signal to implement exclusive access to a target for transactions that cross PI7C7100.
8.1 Concurrent Locks
The primary and secondary bus lock mechanisms operate concurrently except when a locked transaction crosses PI7C7100. A primary master can lock a primary target without affecting the status of the lock on the secondary bus, and vice versa. This means that a primary master can lock a primary target at the same time that a secondary master locks a secondary target.
8.2 Acquiring Exclusive Access across PI7C7100
For any PCI bus, before acquiring access to the LOCK# signal and starting a series of locked transactions, the initiator must first check that both of the following conditions are met: * The PCI bus must be idle. * The LOCK# signal must be de-asserted. The initiator leaves the LOCK# signal de-asserted during the address phase and asserts LOCK# one clock cycle later. Once a data transfer is completed from the target, the target lock has been achieved. Locked transactions can cross PI7C7100 in the downstream and upstream directions, from the primary bus to the secondary bus and vice versa. When the target resides on another PCI bus, the master must acquire not only the lock on its own PCI bus but also the lock on every bus between its bus and the target's bus. When PI7C7100 detects on the primary bus, an initial locked transaction intended for a target on the secondary bus, PI7C7100 samples the address, transaction type, byte enable bits, and parity, as described in Section 4.6.4. It also samples the lock signal. If there is a lock established between 2 ports or the target bus is already locked by another master, then the current lock cycle is retried without forward. Because a target retry is signaled to the initiator, the initiator must relinquish the lock on the primary bus, and therefore the lock is not yet established. The first locked transaction must be a read transaction. Subsequent locked transactions can be read or write transactions. Posted memory write transactions that are a part of the locked transaction sequence are still posted. Memory read transactions that are a part of the locked transaction sequence are not pre-fetched. When the locked delayed read request is queued, PI7C7100 does not queue any more transactions until the locked sequence is finished. PI7C7100 signals a target retry to all transactions initiated subsequent to the locked read transaction that are intended for targets on the other side of PI7C7100. PI7C7100 allows any transactions queued before the locked transaction to complete before initiating the locked transaction. When the locked delayed read request transaction moves to the head of the delayed transaction queue, PI7C7100 initiates the transaction as a locked read transaction by de-asserting LOCK# on the target bus during the first address phase, and by asserting LOCK# one cycle later. If LOCK# is already asserted (used by another initiator), PI7C7100 waits to request access to the secondary bus until LOCK# is de-asserted when the target bus is idle. Note that the existing lock on the target bus could not have crossed PI7C7100. Otherwise, the pending queued locked transaction would not have been queued. When PI7C7100 is able to complete a data transfer with the locked read transaction, the lock is established on the secondary bus. When the initiator repeats the locked read transaction on the primary bus with the same address, transaction type, and byte enable bits, PI7C7100 transfers the read data back to the initiator, and the lock is then also established on the primary bus. For PI7C7100 to recognize and respond to the initiator, the initiator's subsequent attempts of the read transaction must use the locked transaction sequence (de-assert LOCK# during address phase, and assert LOCK# one cycle later). If the LOCK# sequence is not used in subsequent attempts, a master timeout condition may result. When a master timeout condition occurs, SERR# is conditionally asserted (see Section 7.4), the read data and queued read transaction are discarded, and the LOCK# signal is de-asserted on the target bus.
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PI7C7100 3-Port PCI Bridge
Once the intended target has been locked, any subsequent locked transactions initiated on the initiator bus that are forwarded by PI7C7100 are driven as locked transactions on the target bus. When PI7C7100 receives a target abort or a master abort in response to the delayed locked read transaction, this status is passed back to the initiator, and no locks are established on either the target or the initiator bus. PI7C7100 resumes forwarding unlocked transactions in both directions.
8.3 Ending Exclusive Access
After the lock has been acquired on both initiator and target buses, PI7C7100 must maintain the lock on the target bus for any subsequent locked transactions until the initiator relinquishes the lock. The only time a target-retry causes the lock to be relinquished is on the first transaction of a locked sequence. On subsequent transactions in the sequence, the target retry has no effect on the status of the lock signal. An established target lock is maintained until the initiator relinquishes the lock. PI7C7100 does not know whether the current transaction is the last one in a sequence of locked transactions until the initiator de-asserts the LOCK# signal at end of the transaction. When the last locked transaction is a delayed transaction, PI7C7100 has already completed the transaction on the secondary bus. In this example, as soon as PI7C7100 detects that the initiator has relinquished the LOCK# signal by sampling it in the de-asserted state while FRAME# is de-asserted, PI7C7100 de-asserts the LOCK# signal on the target bus as soon as possible. Because of this behavior, LOCK# may not be de-asserted until several cycles after the last locked transaction has been completed on the target bus. As soon as PI7C7100 has de-asserted LOCK# to indicate the end of a sequence of locked transactions, it resumes forwarding unlocked transactions. When the last locked transaction is a posted write transaction, PI7C7100 de-asserts LOCK# on the target bus at the end of the transaction because the lock was relinquished at the end of the write transaction on the initiator bus. When PI7C7100 receives a target abort or a master abort in response to a locked delayed transaction, PI7C7100 returns a target abort or a master abort when the initiator repeats the locked transaction. The initiator must then de-assert LOCK# at the end of the transaction. PI7C7100 sets the appropriate status bits, flagging the abnormal target termination condition (see Section 4.8). Normal forwarding of unlocked posted and delayed transactions is resumed. When PI7C7100 receives a target abort or a master abort in response to a locked posted write transaction, PI7C7100 cannot pass back that status to the initiator. PI7C7100 asserts SERR# on the initiator bus when a target abort or a master abort is received during a locked posted write transaction, if the SERR# enable bit is set in the command register. Signal SERR# is asserted for the master abort condition if the master abort mode bit is set in the bridge control register (see Section 7.4).
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PI7C7100 3-Port PCI Bridge
9. PCI Bus Arbitration
PI7C7100 must arbitrate for use of the primary bus when forwarding upstream transactions. Also, it must arbitrate for use of the secondary bus when forwarding downstream transactions. The arbiter for the primary bus resides external to PI7C7100, typically on the motherboard. For the secondary PCI bus, PI7C7100 implements an internal arbiter. This arbiter can be disabled, and an external arbiter can be used instead. This chapter describes primary and secondary bus arbitration.
9.1 Primary PCI Bus Arbitration
PI7C7100 implements a request output pin, P_REQ#, and a grant input pin, P_GNT#, for primary PCI bus arbitration. PI7C7100 asserts P_REQ# when forwarding transactions upstream; that is, it acts as initiator on the primary PCI bus. As long as at least one pending transaction resides in the queues in the upstream direction, either posted write data or delayed transaction requests, PI7C7100 keeps P_REQ# asserted. However, if a target retry, target disconnect, or a target abort is received in response to a transaction initiated by PI7C7100 on the primary PCI bus, PI7C7100 de-asserts P_REQ# for two PCI clock cycles. For all cycles through the bridge, P_REQ# is not asserted until the transaction request has been completely queued. When P_GNT# is asserted LOW by the primary bus arbiter after PI7C7100 has asserted P_REQ#, PI7C7100 initiates a transaction on the primary bus during the next PCI clock cycle. When P_GNT# is asserted to PI7C7100 when P_REQ# is not asserted, PI7C7100 parks P_AD, P_CBE, and P_PAR by driving them to valid logic levels. When the primary bus is parked at PI7C7100 and PI7C7100 has a transaction to initiate on the primary bus, PI7C7100 starts the transaction if P_GNT# was asserted during the previous cycle.
9.2 Secondary PCI Bus Arbitration
PI7C7100 implements an internal secondary PCI bus arbiter. This arbiter supports two sets of eight external masters in addition to PI7C7100. The internal arbiter can be disabled, and an external arbiter can be used instead for secondary bus arbitration.
9.2.1 Secondary Bus Arbitration Using the Internal Arbiter
To use the internal arbiter, the secondary bus arbiter enable pin, S_CFN#, must be tied LOW. PI7C7100 has two sets of eight secondary bus request input pins, S1_REQ#[7:0], S2_REQ#[7:0], and two sets of eight secondary bus output grant pins, S1_GNT#[7:0], S2_GNT#[7:0], to support external secondary bus masters. The secondary bus request and grant signals are connected internally to the arbiter and are not brought out to external pins when S_CFN# is HIGH. The secondary arbiter supports a 2-sets programmable 2-level rotating algorithm with each set taking care of 8 requests/ grants. Each set of masters can be assigned to a high priority group and a low priority group. The low priority group as a whole represents one entry in the high priority group; that is, if the high priority group consists of n masters, then in at least every n+1 transactions the highest priority is assigned to the low priority group. Priority rotates evenly among the low priority group. Therefore, members of the high priority group can be serviced n transactions out of n+1, while one member of the low priority group is serviced once every n+1 transactions. Figure 9-1 shows an example of an internal arbiter where four masters, including PI7C7100, are in the high priority group, and five masters are in the low priority group. Using this example, if all requests are always asserted, the highest priority rotates among the masters in the following fashion (high priority members are given in italics, low priority members, in boldface type): B, m0, m1, m2, m3, B, m0, m1, m2, m4, B, m0, m1, m2, m5, B, m0, m1, m2, m6, B, m0, m1, m2, m7 and so on.
m2
m1
lpg m4 m3 m0 B m5 m7 m6
Figure 9-1. Secondary Arbiter Example
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PI7C7100 3-Port PCI Bridge
Each bus master, including PI7C7100, can be configured to be in either the low priority group or the high priority group by setting the corresponding priority bit in the arbiter-control register. The arbiter-control register is located at offset 40h. Each master has a corresponding bit. If the bit is set to 1, the master is assigned to the high priority group. If the bit is set to 0, the master is assigned to the low priority group. If all the masters are assigned to one group, the algorithm defaults to a straight rotating priority among all the masters. After reset, all external masters are assigned to the low priority group, and PI7C7100 is assigned to the high priority group. PI7C7100 receives highest priority on the target bus every other transaction, and priority rotates evenly among the other masters. Priorities are re-evaluated every time S1_FRAME# or S2_FRAME# is asserted at the start of each new transaction on the secondary PCI bus. From this point until the time that the next transaction starts, the arbiter asserts the grant signal corresponding to the highest priority request that is asserted. If a grant for a particular request is asserted, and a higher priority request subsequently asserts, the arbiter de-asserts the asserted grant signal and asserts the grant corresponding to the new higher priority request on the next PCI clock cycle. When priorities are re-evaluated, the highest priority is assigned to the next highest priority master relative to the master that initiated the previous transaction. The master that initiated the last transaction now has the lowest priority in its group. If PI7C7100 detects that an initiator has failed to assert S1_FRAME# or S2_FRAME# after 16 cycles of both grant assertion and a secondary idle bus condition, the arbiter de-asserts the grant. That master does not receive any more grants until it de-asserts its request for at least one PCI clock cycle. To prevent bus contention, if the secondary PCI bus is idle, the arbiter never asserts one grant signal in the same PCI cycle in which it de-asserts another. It de-asserts one grant and asserts the next grant, no earlier than one PCI clock cycle later. If the secondary PCI bus is busy, that is, either S1_FRAME# (S2_FRAME#) or S1_IRDY# (S2_IRDY#) is asserted, the arbiter can de-assert one grant and assert another grant during the same PCI clock cycle.
9.2.2 Secondary Bus Arbitration Using an External Arbiter
The internal arbiter is disabled when the secondary bus central function control pin, S_CFN#, is tied high. An external arbiter must then be used. When S_CFN# is tied high, PI7C7100 reconfigures four pins (two per port) to be external request and grant pins. The S1_GNT#[0] and S2_GNT#[0] pins are reconfigured to be the external request pins because they are output. The S1_REQ#[0] and S2_REQ#[0] pins are reconfigured to be the external grant pins because they are input. When an external arbiter is used, PI7C7100 uses the S1_GNT#[0] or S2_GNT#[0] pin to request the secondary bus. When the reconfigured S1_REQ#[0] or S2_REQ#[0] pin is asserted low after PI7C7100 has asserted S1_GNT#[0] or S2_GNT#[0]. PI7C7100 initiates a transaction on the secondary bus one cycle later. If grant is asserted and PI7C7100 has not asserted the request, PI7C7100 parks AD, CBE and PAR pins by driving them to valid logic levels. The unused secondary bus grant outputs, S1_GNT#[7:1] and S2_GNT#[7:1] are driven high. The unused secondary bus request inputs, S1_REQ#[7:1] and S2_REQ#[7:1], should be pulled high.
9.2.3 Bus Parking
Bus parking refers to driving the AD[31:0], CBE[3:0]#, and PAR lines to a known value while the bus is idle. In general, the device implementing the bus arbiter is responsible for parking the bus or assigning another device to park the bus. A device parks the bus when the bus is idle, its bus grant is asserted, and the device's request is not asserted. The AD and CBE signals should be driven first, with the PAR signal driven one cycle later. PI7C7100 parks the primary bus only when P_GNT# is asserted, P_REQ# is de-asserted, and the primary PCI bus is idle. When P_GNT# is de-asserted, PI7C7100 3-states the P_AD, P_CBE, and P_PAR signals on the next PCI clock cycle. If PI7C7100 is parking the primary PCI bus and wants to initiate a transaction on that bus, then PI7C7100 can start the transaction on the next PCI clock cycle by asserting P_FRAME# if P_GNT# is still asserted. If the internal secondary bus arbiter is enabled, the secondary bus is always parked at the last master that used the PCI bus. That is, PI7C7100 keeps the secondary bus grant asserted to a particular master until a new secondary bus request comes along. After reset, PI7C7100 parks the secondary bus at itself until transactions start occurring on the secondary bus. If the internal arbiter is disabled, PI7C7100 parks the secondary bus only when the reconfigured grant signal, S_REQ#<0>, is asserted and the secondary bus is idle.
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PI7C7100 3-Port PCI Bridge
10. Clocks
This chapter provides information about the clocks.
10.1 Primary Clock Inputs
PI7C7100 implements a primary clock input for the PCI interface. The primary interface is synchronized to the primary clock input, P_CLK, and the secondary interface is synchronized to the secondary clock. The secondary clock is derived internally from the primary clock, P_CLK, through an internal PLL. PI7C7100 operates at a maximum frequency of 33 MHz.
10.2 Secondary Clock Outputs
PI7C7100 has 16 secondary clock outputs, S_CLKOUT[15:0] that can be used as clock inputs for up to sixteen external secondary bus devices. The S_CLKOUT[15:0] outputs are derived from P_CLK. The secondary clock edges are delayed from P_CLK edges by a minimum of 0ns. This is the rule for using secondary clocks: * Each secondary clock output is limited to no more than one load.
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PI7C7100 3-Port PCI Bridge
11. Reset
This chapter describes the primary interface, secondary interface, and chip reset mechanisms.
11.1 Primary Interface Reset
PI7C7100 has a reset input, P_RESET#. When P_RESET# is asserted, the following events occur: * PI7C7100 immediately 3-states all primary and secondary PCI interface signals. * PI7C7100 performs a chip reset. * Registers that have default values are reset. P_RESET# asserting and de-asserting edges can be asynchronous to P_CLK and S_CLK.
11.2 Secondary Interface Reset
PI7C7100 is responsible for driving the secondary bus reset signals, S1_RESET# and S2_RESET#. PI7C7100 asserts S1_RESET# or S2_RESET# when any of the following conditions is met: * Signal P_RESET# is asserted. Signal S1_RESET# or S2_RESET# remains asserted as long as P_RESET# is asserted and does not de-assert until P_RESET# is de-asserted. * The secondary reset bit in the bridge control register is set. Signal S1_RESET# or S2_RESET# remains asserted until a configuration write operation clears the secondary reset bit. * S1_RESET# or S2_RESET# pin is asserted. When S1_RESET# or S2_RESET# is asserted, the following events occur: PI7C7100 immediately 3-states all the secondary PCI interface signals associated with the Secondary S1 or S2 port. The S1_RESET# or S2_RESET# in asserting and de-asserting edges can be asynchronous to P_CLK. * The chip reset bit in the diagnostic control register is set. Signal S1_RESET# or S2_RESET# remains asserted until a configuration write operation clears the secondary reset bit and the secondary clock serial mask has been shifted in. When S1_RESET# or S2_RESET# is asserted, all secondary PCI interface control signals, including the secondary grant outputs, are immediately 3-stated. Signals S1_AD, S1_CBE[3:0]#, S1_PAR (S2_AD, S2_CBE[3:0]#, S2_PAR) are driven low for the duration of S1_RESET# (S2_RESET#) assertion. All posted write and delayed transaction data buffers are reset. Therefore, any transactions residing inside the buffers at the time of secondary reset are discarded. When S1_RESET# or S2_RESET# is asserted by means of the secondary reset bit, PI7C7100 remains accessible during secondary interface reset and continues to respond to accesses to its configuration space from the primary interface.
11.3 Chip Reset
The chip reset bit in the diagnostic control register can be used to reset PI7C7100 and the secondary buses. All registers, and chip state machines are reset and all signals are 3-stated when the chip reset is set. In addition, S1_RESET# or S2_RESET# is asserted, and the secondary reset bit is automatically set. Signal S1_RESET# or S2_RESET# remains asserted until a configuration write operation clears the secondary reset bit. As soon as chip reset completes, within 20 PCI clock cycles after completion of the configuration write operation that sets the chip reset bit, the chip reset bit automatically clears and the chip is ready for configuration. During chip reset, PI7C7100 is inaccessible.
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PI7C7100 3-Port PCI Bridge
12. Supported Commands
The PCI command set is given below for the primary and secondary interfaces.
12.1 Primary Interface
P_CBE[3: 0]# 0000 0001 0010 Command Interrupt Acknowledge Special Cycle I/O Read Ignore. Do not claim. Ignore. 1. If address is within pass through I/O range: claim and pass through. 2. If address points to I/O mapped bridge internal register: claim and permit access to register, do not pass through. 3. Otherwise, do not pass through and do not claim for internal access. Same as I/O read. --------1. If address is within pass through memory range: claim and pass through. 2. If address is within pass through memory mapped I/O range: claim and pass through. 3. If address points to memory mapped bridge internal register: claim and permit access to register, do not pass through. 4. Otherwise, do not pass through and do not claim for internal access. Same as Memory Read --------I. Type 0 configuration read: If the bridge's IDSEL line is asserted, perform function decode and claim if target function is implemented, otherwise, ignore. If claimed, permit access to target function's configuration registers. Do not pass through under any circumstances. II. Type 1 configuration read: 1. If the target bus is the bridge's secondary bus: claim and pass through as a type 0 configuration read. 2. If the target bus is a subordinate bus that exists behind the bridge (but not equal to the secondary bus): claim and pass through as a type 1 configuration read. 3. Otherwise, ignore. Action
0011 0100 0101 0110
I/O Write Reserved Reserved Memory Read
0111 1000 1001 1010
Memory Write Reserved Reserved Configuration Read
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PI7C7100 3-Port PCI Bridge
12.1 Primary Interface (continued)
P_CBE[3: 0]# 1011 Command Configuration Write Action I. Type 0 configuration w rite: same as configuration read. II. Type 1 configuration w rite(not special cycle request): 1. If the target bus is the bridge's secondary bus: claim and pass through as a type 0 configuration write 2. If the target bus is a subordinate bus that exists behind the bridge (but not equal to the secondary bus): claim and pass through unchanged as a type 1 configuration write. 3. Otherwise, ignore. III. Configuration w rite as special cycle request (device = 1Fh, function = 7h): 1. If the target bus is the bridge's secondary bus: claim and pass through as a special cycle 2. If the target bus is a subordinate bus that exists behind the bridge (but not equal to the secondary bus): claim and pass through unchanged as a type 1 configuration write. 3. Otherwise, ignore Same as Memory Read Not Supported Same as Memory Read Same as Memory Read
1100 1101 1110 1111
Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write & Invalidate
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PI7C7100 3-Port PCI Bridge
12.2 Secondary Interface
S1_CBE[3: 0]# S2_CBE[3: 0]# 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 Command Interrupt Acknowledge Special Cycle I/O Read I/O Write Reserved Reserved Memory Read Memory Write Reserved Reserved Configuration Read Configuration Write Ignore. Do not claim. Ignore. Same as primary interface. Same as I/O read. --------Same as primary interface. Same as Memory Read. --------Ignore. I. Type 0 configuration w rite: Ignore. II. Type 1 configuration w rite (not special cycle request): Ignore. III. Configuration w rite as special cycle request (device = 1Fh, function = 7h): 1. If the target bus is the bridge's primary bus: claim and pass through as a special cycle. 2. If the target bus is neither the primary bus nor is it in range of buses defined by the bridge's secondary and subordinate bus registers: claim and pass through unchanged as a type 1 configuration write. 3. If the target bus is not the bridge's primary bus: but is in range of buses defined by the bridge's secondary and subordinate bus registers: Ignore. Same as Memory Read Not Supported Same as Memory Read Same as Memory Read Action
1100 1101 1110 1111
Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write & Invalidate
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PI7C7100 3-Port PCI Bridge
13. Configuration Registers
As PI7C7100 supports two secondary interfaces, it has two sets of configuration registers which are almost identical and accessed through different function numbers. The description below is for one set only. PCI configuration defines a 64-byte space (configuration header) to define various attributes of the PCI-to-PCI Bridge as shown below. All of the registers in bold type are required by the PCI specification and are implemented in this bridge. The others are available for use as control registers for the device. There are two configuration registers: Configuration Register 1 and Configuration Register 2 corresponding to Secondary bus 1 and Secondary bus 2 interfaces respectively. Also, the configuration for the primary interface is implemented through the Configuration Register 1.
13.1 Configuration Register 1
31-24 Device ID Status Class Code Reserved Secondary Latency Timer Header Type Subordinate Bus Number Primary Latency Timer Reserved Secondary Bus Number I/O Limit Memory Base Prefetchable Memory Base Reserved I/O Limit Upper 16 Bits Subsystem ID Reserved Bridge Control Arbiter Control Primary Prefetchable Memory Limit Reserved Reserved Reserved Reserved Reserved Non-Posted Memory Limit Master Timeout Counter Retry Counter Sampling Timer Secondary Successful I/O read count Secondary Successful I/O write count Secondary Successful memory read count Secondary Successful memory write count Primary Successful I/O read count Primary Successful I/O write count Primary Successful memory read count Primary Successful memory write count Reserved
55
23-16
15-8 Vendor ID Command
7-0 00h 04h Revision ID Cache Line Siz e Primary Bus Number I/O Base 08h 0C h
Address
10h-14h 18h 1C h 20h 24h 28h-2Ch I/O Base Upper 16 Bits Subsystem Vendor ID Interrupt Pin Reserved Chip Control 30h 34h 38h 3C h 40h 44h 48h-60h P_SERR# Event Disable Secondary Clock Control Non-Posted Memory Base Port Option 64h 68h 6C h 70h 74h 78h 7C h 80h 84h 88h 8C h 90h 94h 98h 9C h A0h-FFh
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Secondary Status Memory Limit Prefetchable Memory Limit
Diagnostic Control
Primary Prefetchable Memory Base
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PI7C7100 3-Port PCI Bridge
13.2 Configuration Register 2
31-24 Device ID Status Class Code Reserved Header Type Primary Latency Timer Reserved Secondary Latency Timer Subordinate Bus Number Secondary Bus Number I/O Limit Memory Base Prefetchable Memory Base Reserved I/O Limit Upper 16 Bits Subsystem ID Reserved Bridge Control Arbiter Control Primary Prefetchable Memory Limit Reserved Reserved Reserved Reserved Reserved Non-Posted Memory Limit Reserved Reserved Sampling Timer Secondary Successful I/O read count Secondary Successful I/O write count Secondary Successful memory read count Secondary Successful memory write count Reserved Reserved Reserved Reserved Reserved Non-Posted Memory Base Reserved Secondary Clock Control Interrupt Pin Diagnostic Control Reserved Chip Control I/O Base Upper 16 Bits Subsystem Vendor ID Primary Bus Number I/O Base 23-16 15-8 Vendor ID Command Revision ID Cache Line Siz e 7-0 00h 04h 08h 0C h 10h-14h 18h 1C h 20h 24h 28h-2Ch 30h 34h 38h 3C h 40h 44h 48h-60h 64h 68h 6C h 70h 74h 78h 7C h 80h 84h 88h 8C h 90h 94h 98h 9C h A0h-FFh Address
Secondary Status Memory Limit Prefetchable Memory Limit
Primary Prefetchable Memory Base
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PI7C7100 3-Port PCI Bridge
13.2.1 Config Register 1 or 2: Vendor ID Register (read only, bit 15-0; offset 00h)
Pericom ID is 12D8h.
13.2.2 Config Register 1: Device ID Register (read only, bit 31-16; offset 00h)
Hardwired to 1B59h (S1)
13.2.3 Config Register 2: Device ID Register (read only, bit 31-16; offset 00h)
Hardwired to 1B5Ah (S2)
13.2.4 Configuration Register 1: Command Register (bit 15-0; offset 04h)
Bit 15-10 Function Reserved Fast Back to Back Enable 9 Type R/O R/W Reset to '000000' Controls bridge's ability to generate fast back-to-back transactions to different devices on the primary interface. 0 = no fast back to back transaction 1 = enable fast back to back transaction Reset to 0 Controls the enable for the P_SERR# pin. 0=disable the P_SERR# driver 1 = enable the P_SERR# driver Reset to 0 No data stepping supported. Reset to 0 Controls bridge's response to parity errors. 0 = ignore any parity errors 1 = normal parity checking performed Reset to 0 Controls bridge's response to VGA compatible palette accesses. 0 = ignore VGA palette accesses on the primary interface 1 = enable response to VGA palette writes on the primary interface (I/O address AD[9:0] = 3C6h, 3C8h and 3C9h) Reset to 0 Memory Write and Invalidate not supported Reset to 0 No special cycle implementation Reset to 0 Controls bridge's ability to operate as a master on the primary interface. 0 = do not initiate transaction on the primary interface and disable response to memory or I/O transactions on secondary interface 1 = enable the bridge to operate as a master on the primary interface Reset to 0 Controls bridge's response to memory accesses on the primary interface. 0 = ignore all memory transaction 1 = enable response to memory transaction Reset to 0 Controls bridge's response to I/O accesses on the primary interface. 0 = ignore I/O transaction 1 = enable response to I/O transaction Reset to 0 Description
SERR# Enable 8 Wait Cycle Control Parity Error Enable 6 VGA Palette Snoop Enable 5
R/W
7
R/O R/W
R/W
4 3
Memory Write and Invalidate Enable Special Cycle Enable Bus Master Enable
R/O R/O R/W
2
Memory Space Enable 1
R/W
I/O Space Enable 0
R/W
Note: R/W - Read/Write, R/O - Read Only, R/WC - Read/ Write 1 to clear
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PI7C7100 3-Port PCI Bridge
13.2.5 Configuration Register 2: Command Register (bit 15-0; offset 04h)
Bit 15-10 9 8 7 6 Function Reserved Reserved Reserved Wait Cycle Control Reserved VGA Palette Snoop Enable 5 Type R/O R/W R/W R/O R/W R/W Reset to '000000' Reset to 0 Reset to 0 No data stepping supported. Reset to 0 Reset to 0 Controls bridge's response to VGA compatible palette accesses. 0 = ignore VGA palette accesses on the primary interface 1 = enable response to VGA palette writes on the primary interface (I/O address AD[9:0] = 3C6h, 3C8h and 3C9h) Reset to 0 Memory Write and Invalidate not supported. Reset to 0 No special cycle implementation. Reset to 0 Controls bridge's ability to operate as a master on the primary interface. 0 = do not initiate transaction on the primary interface and disable response to memory or I/O transactions on secondary interface 1 = enable the bridge to operate as a master on the primary interface Reset to 0 Controls bridge's response to memory accesses on the primary interface. 0 = ignore all memory transaction 1 = enable response to memory transaction Reset to 0 Controls bridge's response to I/O accesses on the primary interface. 0 = ignore I/O transaction 1 = enable response to I/O transaction Reset to 0 Description
4 3
Memory Write and Invalidate Enable Special Cycle Enable Bus Master Enable
R/O R/O R/W
2
Memory Space Enable R/W 1
I/O Space Enable 0
R/W
Note: R/W - Read/Write, R/O - Read Only, R/WC - Read/ Write 1 to clear
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PI7C7100 3-Port PCI Bridge
13.2.6 Configuration Register 1 or 2: Status Register (for primary bus, bits 31-16; offset 04h)
Bit 31 Function Detected Parity Error Type Description R/WC Should be set whenever a parity error is detected regardless of the state of bit 6 of the command register. Reset to 0 R/WC Should be set whenever P_SERR# is asserted. Reset to 0 R/WC Set to '1' (by a master) when transactions are terminated with Master Abort. Reset to 0 R/WC Set to '1' (by a master device) when transactions are terminated with Target Abort. Reset to 0 R/WC Should be set (by a target device) whenever a Target Abort cycle occurs. Reset to 0 R/O Medium DEVSEL# timing. Reset to '01'
30 29
Signaled System Error Received Master Abort
28
Received Target Abort
27
Signaled Target Abort
26-25 24
DEVSEL Timing Data Parity Error Detected
R/WC It is set when the following conditions are met: 1. P_PERR# is asserted 2. Bit 6 of Command Register is set Reset to 0 R/O R/O R/O R/O R/O Fast back-to-back write capable on primary side. Reset to 1 Reset to 0 Reset to 1 Capabilities List is not supported. Reset to 0 Reset to 0
23 22 21 20 19-16
Fast Back to Back Capable Reserved Reserved Capabilities List Reserved
Note: R/W - Read/Write; R/O - Read Only; R/WC - Read/Write1 to clear.
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PI7C7100 3-Port PCI Bridge
13.2.7 Config Register 1 or 2: Revision ID Register (read only, bit 7-0; offset 08h)
Hardwired to 01h
13.2.8 Config Register 1 or 2: Class Code Register (read only, bit 31-8; offset 08h)
Hardwired to 060400h
13.2.9 Config Register 1 or 2: Cache Line Size Register (read/write, bit 7-0; offset 0Ch)
This register is used when terminating memory write and invalidate transactions and when pre-fetching. Only cache line sizes (in units of 4-byte) which are power of two are valid (only one bit can be set in this register; only 00h, 01h, 02h, 04h, 08h, 10h are valid values). Reset to 00h
13.2.10 Config Register 1: Primary Latency Timer Register (read/write, bit 15-8; offset 0Ch)
This register sets the value for Master Latency Timer which starts counting when master asserts FRAME#. Reset to 00h
13.2.11 Config Register 2: Primary Latency Timer Register (read/write, bit 15-8; offset 0Ch)
This register is implemented but not being used internally. Reset to 00h
13.2.12 Config Register 1: Header Type Register (read only, bit 23-16; offset 0Ch)
Hardwired to 81h for function 0 (multiple function PCI-to-PCI bridge, for secondary bus S1)
13.2.13 Config Register 2: Header Type Register (read only, bit 23-16; offset 0Ch)
Hardwired to 01h for function 1 (single function PCI-to-PCI bridge, for secondary bus S2)
13.2.14 Config Register 1: Primary Bus Number Register (read/write, bit 7-0; offset 18h)
Programmed with the number of the PCI bus to which the primary bridge interface is connected. This value is set by software during configuration. Reset to 00h
13.2.15 Config Register 2: Primary Bus Number Register (read/write, bit 7-0; offset 18h)
This register is implemented but not being used internally. Reset to 00h
13.2.16 Config Register 1 or 2: Secondary Bus Number Register (read/write, bit 15-8; offset 18h)
Programmed with the number of the PCI bridge secondary bus interface. This value is set by software during configuration. Reset to 00h
13.2.17 Config Register 1 or 2: Subordinate Bus Number Register (read/write, bit 23-16; offset 18h)
Programmed with the number of the PCI bus with the highest number that is subordinate to the bridge. This value is set by software during configuration. Reset to 00h
13.2.18 Config Register 1 or 2: Secondary Latency Timer (read/write, bit 31-24; offset 18h)
This register is programmed in units of PCI bus clocks.The latency timer checks for master accesses on the secondary bus interfaces that remain unclaimed by any target. Reset to 00h
13.2.19 Config Register 1 or 2: I/O Base Register (read/write, bit 7-0; offset 1Ch)
This register defines the bottom address of the I/O address range for the bridge. The upper four bits define the bottom address range used by the chip to determine when to forward I/O transactions from one interface to the other. These 4 bits correspond to address bits [15:12] and are write-able. The upper 16 bits corresponding to address bits [31:16] are defined in the I/O base upper 16 bits address register. The address bits [11:0] are assumed to be 000h. The lower four bits (3:0) of this register set to `0001' (read-only) to indicate 32-bit I/O addressing. Reset to 00h
13.2.20 Config Register 1 or 2: I/O Limit Register (read/write, bit 15-8; offset 1Ch)
This register defines the top address of the I/O address range for the bridge. The upper four bits define the top address range used by the chip to determine when to forward I/O transactions from one interface to the other. These 4 bits correspond to address bits [15:12] and are write-able. The upper 16 bits corresponding to address bits [31:16] are defined in the I/O limit upper 16 bits address register. The address bits [11:0] are assumed to be FFFh. The lower four bits (3:0) of this register set to `0001' (read-only) to indicate 32-bit I/O addressing. Reset to 00h.
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PI7C7100 3-Port PCI Bridge
13.2.21 Configuration Register 1 or 2: Secondary Status Register (bits 31-16; offset 1Ch)
Bit 31 Function Detected Parity Error Type Description R/WC Should be set whenever a parity error is detected regardless of the state of bit 6 of the command register. Reset to 0 R/WC Should be set whenever S1_SERR# or S2_SERR# is detected. Should be a '0' after reset. Reset to 0 R/WC Set to '1' (by a master) when transactions are terminated with Master Abort. Reset to 0 R/WC Set to '1' (by a master device) when transactions are terminated with Target Abort. Reset to 0 R/WC Should be set (by a target device) whenever a Target Abort cycle occurs. Should be '0' after reset. Reset to 0 R/O Medium DEVSEL# timing. Reset to '01'
30
Signaled System Error
29
Received Master Abort
28
Received Target Abort
27
Signaled Target Abort
26-25 DEVSEL timing 24 Data Parity Error Detected
R/WC It is set when the following conditions are met: 1. S1_PERR# or S2_PERR# is asserted 2. Bit 6 of Command Register is set Reset to 0 R/O R/O R/O R/O Fast back-to-back write capable on secondary buses. Reset to 1 Reset to 0 Reset to 0 Reset to '00000'
23 22 21
Fast Back-to-Back Capable Reserved Reserved
20-16 Reserved
Note: R/W - Read/Write, R/O - Read Only, R/WC - Read/ Write 1 to clear
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PI7C7100 3-Port PCI Bridge
13.2.22 Config Register 1 or 2: Memory Base Register (read/write, bit 15-0; offset 20h)
This register defines the base address of the memory-mapped address range for forwarding the cycle through the bridge. The upper twelve bits corresponding to address bits [31:20] are read/write. The twelve bits are reset to 000h. The lower 20 address bits (19:0) are assumed to be 00000h.
13.2.23 Config Register 1 or 2: Memory Limit Register (read/write, bit 31:16; offset 20h)
This register defines the upper limit address of the memory-mapped address range for forwarding the cycle through the bridge. Upper twelve bits corresponding to address bit [31:20] are read/write. Upper twelve bits are reset to 0000h. Lower 20 address bits (19:0) are assumed to be FFFFFh.
13.2.24 Config Register 1 or 2: Prefetchable Memory Base Register (read/write, bit 15-0;offset 24h)
This register defines the base address of the prefetchable memory-mapped address range for forwarding the cycle through the bridge. The upper twelve bits corresponding to address bits [31:20] are read/write. The upper twelve bits are reset to 000h. The lower four bits are read only and are set to 0. The lower 20 address bits (19:0) are assumed to be 00000h.
13.2.25 Config Register 1 or 2: Prefetchable Memory Limit Register (read/write, bit 31-16; offset 24h)
This register defines the upper limit address of the memory-mapped address range for forwarding the cycle through the bridge. The upper twelve bits correspond to address bit [31:20] are read/write. The upper twelve bits are reset to 000h. The lower four bits are read only and are set to 0. The lower 20 address bits (19:0) are assumed to be FFFFFh.
13.2.26 Config Register 1 or 2: I/O Base Address Upper 16 Bits Register (read/write, bit 15-0; offset 30h)
This register defines the upper 16 bits of a 32-bit base I/O address range used for forwarding the cycle through the bridge. Reset to 0000h.
13.2.27 Config Register 1 or 2: I/O Limit Address Upper 16 Bits Register (read/write, bit 31-16; offset 30h)
This register defines the upper 16 bits of a 32-bit limit I/O address range used for forwarding the cycle through the bridge. Reset to 0000h.
13.2.28 Config Register 1 or 2: Subsystem Vendor ID (read/write, bit 15-0; offset 34h)
A 16-bit register for add-on cards to distinguish from one another. Reset to 0000h.
13.2.29 Config Register 1 or 2: Subsystem ID (read/write, bit 31-16; offset 34h)
A 16-bit register for add-on cards to distinguish from one another. Reset to 0000h.
13.2.30 Config Register 1 or 2: Interrupt Pin Register (read only, bit 15-8; offset 3Ch)
The register reads as 00h to indicate that PI7C7100 does not use any interrupt pins.
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09/18/00 Rev 1.1
ADVANCE INFORMATION
765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
13.2.31 Configuration Register 1 or 2: Bridge Control Register (bits 31-16; offset 3Ch)
Bit Function Type R/O R/W R/WC R/W R/W R/W Reset to '0000' Reset to 0 Set to '1' when either primary master or secondary master timeout. Reset to 0 Reset to 0 Reset to 0 Controls bridge's ability to generate fast back-to-back transactions to different devices on the secondary interface. 0 = no fast back-to-back transaction 1 = enable fast back-to-back transacton Reset to 0 Forces the assertion of S1_RESET# or S2_RESET# signal pin on the secondary interface. 0 = do not force the assertion of S1_RESET# or S2_RESET# pin 1 = force the assertion of S1_RESET# or S2_RESET# pin Reset to 0 Controls bridge's behavior responding to master aborts on secondary interface. 0 = do not report master aborts (return FFFF_FFFFh on read and discard data on w rite) 1 = report master aborts by signaling target abort if possible by the assertion of P_SERR# if enabled Reset to 0 Reset to 0 Controls the bridge's response to VGA compatible addresses. 0 = do not forw ard VGA compatible memory and I/O addresses from primary to secondary 1 = forward VGA compatible memory and I/O address from primary to secondary regardless of other settings Reset to 0 Controls bridge's response to ISA I/O address which is limited to the first 64K. 0 = forw ard all I/O addresses in the range defined by the I/O Base and I/O Limit registers, 1 = block forwarding of ISA I/O addresses in the range defined by the I/O Base and I/O Limit registers that are in the first 64K of I/O space that address the last 768 bytes in each 1 Kbytes block. Secondary I/O transactions are forwarded upstream if the address falls within the last 768 bytes in each 1 Kbyte block Reset to 0 Controls the forwarding of S1_SERR# or S2_SERR# to the primary interface. 0 = disable the forw arding S1_SERR# or S2_SERR# to primary 1 = enable the forwarding of S1_SERR# or S2_SERR# to primary interface. Reset to 0 Controls the bridge's response to parity errors on the secondary interface. 0 = ignore address and data parity errors on the secondary interface. 1 = enable parity error reporting and detection on the secondary interface. Reset to 0 Description 31-28 Reserved 27 26 25 24 23 Reserved Master Timeout Status Reserved Reserved Fast Back-to-Back Enable
22
Secondary Interface Reset
R/W
21
Master Abort Mode
R/W
20 19
Reserved VGA Enable
R/O R/W
18
ISA Enable
R/W
17
S1_SERR# or S2_SERR# Enable Parity Error Response Enable
16
Note: R/W - Read/Write, R/O - Read Only, R/WC - Read/ Write 1 to clear.
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09/18/00 Rev 1.1
ADVANCE INFORMATION
65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
13.2.32 Configuration Register 1 or 2: Diagnostic/Chip Control Register (bit 15-0, offset 40h)
Bit 15-11 10-9 Function Reserved Test Mode Type R/O R/W Reset to '00000' Controls testability of chip's internal counters. When 00, all bits of counter are exercised. When 01, byte 1 of counter is exercised. When 10, byte 2 of counter is exercised. When 11, byte 3 of counter is exercised. Reset to 0 Reset to '0000' Reset to 0 Reset to '00' Reset to 0 Reset to 0 Description
8-5 4 3-2 1 0
Reserved Reserved Reserved Reserved Reserved
R/O R/W R/O R/W R/O
13.2.33 Configuration Register 1 or 2: Arbiter Control Register (bit 31-16, offset 40h)
Bit 31:28 27 Function Reserved Hybrid Type R/O R/W Reset to '0000' Mixed arbitration for masters from secondary bus 1 and 2. 0 = separate arbitration for S1_REQ[7:0]# and S2_REQ[7:0]# 1 = S1_REQ[3:0]# are mixed with S2_REQ[3:0]# for arbitration. Only one arbiter is used. Reset to 0 Reset to 0 Defines whether the secondary port of PI7C7100 is in high priority group or the low priority group. 0 = low priority group 1 = high priority group Reset to 1 Reset to 0 Each bit controls whether a secondary-bus master is assigned to the high priority group or the low priority group. Bit [7:0] correspond to request inputs S1_REQ[7:0]# or S2_REQ[7:0]#. Reset to '00000000' Description
26 25
Reserved Priority of Secondary Port
R/W R/W
24 23-16
Reserved Arbiter Control
R/O R/W
Note: R/W - Read/Write, R/O - Read Only, R/WC - Read/ Write 1 to clear.
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09/18/00 Rev 1.1
ADVANCE INFORMATION
765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
13.2.34 Config Register 1: Primary Prefetchable Memory Base Register (Read/Write, bit 15-0; offset 44h)
This register is implemented but not being used internally.This register defines the base address of the primary prefetchable memory-mapped address range for forwarding the cycle through the bridge. The upper twelve bits corresponding to address bits [31:20] are read/write. The upper twelve bits are reset to 0000h. The lower four bits are read only and are set to 0h. The lower 20 address bits (19:0) are assumed to be 00000h.
13.2.35 Config Register 2: Primary Prefetchable Memory Base Register (Read/Write, bit 15-0; offset 44h)
This register is implemented but not being used internally. The upper twelve bits corresponding to address bits [31:20] are read/write. The upper twelve bits are reset to 0000h. The lower four bits are read only and are set to 0h.
13.2.36 Config Register 1: Primary Prefetchable Memory Limit Register (Read/Write, bit 31-16; offset 44h)
This register is implemented but not being used internally.This register defines the upper limit address of the primary prefetchable memory-mapped address range for forwarding the cycle through the bridge. The upper twelve bits corresponding to address bits [31:20] are read/write. The upper twelve bits are reset to 0000h. The lower four bits are read only and are set to 0h. The lower 20 address bits (19:0) are assumed to be FFFFFh.
13.2.37 Config Register 2: Primary Prefetchable Memory Limit Register (Read/Write, bit 31-16; offset 44h)
This register is implemented but not being used internally. The upper twelve bits corresponding to address bits [31:20] are read/write. The upper twelve bits are reset to 0000h. The lower four bits are read only and are set to 0h.
13.2.38 Config Register 1 or 2: P_SERR# Event Disable Register (bit 7-0; offset 64h)
Bit 7 6 Function Reserved Delayed read no data from target Delayed write nondeliver Type R/O R/W Reset to 0 Controls ability of PI7C7100 to assert P_SERR# when it is unable to transfer any read data from the target after 224 attempts. P_SERR# is asserted if this event occurs when this bit is 0 and SERR# enable bit in the command register is set. Reset to 0 Controls ability of PI7C7100 to assert P_SERR# when it is unable to transfer delayed write data after 224 attempts. P_SERR# is asserted if this event occurs when this bit is 0 and SERR# enable bit in the command register is set. Reset to 0 Controls ability of PI7C7100 to assert P_SERR# when it receives a master abort when attempting to deliver posted write data. P_SERR# is asserted if this event occurs when this bit is 0 and SERR# enable bit in the command register is set. Reset to 0 Controls ability of PI7C7100 to assert P_SERR# when it receives a target abort when attempting to deliver posted write data. P_SERR# is asserted if this event occurs when this bit is 0 and SERR# enable bit in the command register is set. Reset to 0 Controls ability of PI7C7100 to assert P_SERR# when it is unable to deliver posted write data after 224 attempts. P_SERR# is asserted if this event occurs when this bit is 0 and SERR# enable bit in the command register is set. Reset to 0 Controls ability of PI7C7100 to assert P_SERR# when a parity error is detected on the target bus during a posted write transaction. P_SERR# is asserted if this event occurs when this bit is 0 and SERR# enable bit in the command register is set. Reset to 0 Reset to 0 Description
5
R/W
4
Master abort on posted write Target abort during posted write Posted write non-delivery
R/W
3
R/W
2
R/W
1
Posted write parity error
R/W
0
Reserved
R/O
Note: R/W - Read/Write, R/O - Read Only, R/WC - Read/ Write 1 to clear.
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ADVANCE INFORMATION
65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
13.2.39 Configuration Register 1: Secondary Clock Control Register (bit 15-0; offset 68h)
Bit 15-14 13-12 11-10 9-8 7-6 5-4 3-2 1-0 Function Clock 7 Disable Clock 6 Disable Clock 5 Disable Clock 4 Disable R/W Clock 3 Disable Clock 2 Disable Clock 1 Disable Clock 0 Disable If either bit is 0, S_CLKOUT[3] is enabled When both bits are 1, S_CLKOUT[3] is disabled If either bit is 0, S_CLKOUT[2] is enabled When both bits are 1, S_CLKOUT[2] is disabled If either bit is 0, S_CLKOUT[1] is enabled When both bits are 1, S_CLKOUT[1] is disabled If either bit is 0, S_CLKOUT[0] is enabled When both bits are 1, S_CLKOUT[0] is disabled Type Description If either bit is 0, S_CLKOUT[7] is enabled When both bits are 1, S_CLKOUT[7] is disabled If either bit is 0, S_CLKOUT[6] is enabled When both bits are 1, S_CLKOUT[6] is disabled If either bit is 0, S_CLKOUT[5] is enabled When both bits are 1, S_CLKOUT[5] is disabled If either bit is 0, S_CLKOUT[4] is enabled When both bits are 1, S_CLKOUT[4] is disabled
13.2.40 Configuration Register 2: Secondary Clock Control Register (bit 15-0; offset 68h)
Bit 15-14 13-12 11-10 9-8 7-6 5-4 3-2 1-0 Function Clock 7 Disable Clock 6 Disable Clock 5 Disable Clock 4 Disable R/W Clock 3 Disable Clock 2 Disable Clock 1 Disable Clock 0 Disable If either bit is 0, S_CLKOUT[11] is enabled When both bits are 1, S_CLKOUT[11] is disabled If either bit is 0, S_CLKOUT[10] is enabled When both bits are 1, S_CLKOUT[10] is disabled If either bit is 0, S_CLKOUT[9] is enabled When both bits are 1, S_CLKOUT[9] is disabled If either bit is 0, S_CLKOUT[8] is enabled When both bits are 1, S_CLKOUT[8] is disabled Type Description If either bit is 0, S_CLKOUT[15] is enabled When both bits are 1, S_CLKOUT[15] is disabled If either bit is 0, S_CLKOUT[14] is enabled When both bits are 1, S_CLKOUT[14] is disabled If either bit is 0, S_CLKOUT[13] is enabled When both bits are 1, S_CLKOUT[13] is disabled If either bit is 0, S_CLKOUT[12] is enabled When both bits are 1, S_CLKOUT[12] is disabled
Note: R/W - Read/Write.
66
09/18/00 Rev 1.1
ADVANCE INFORMATION
765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
13.2.41 Config Register 1 or 2: Non-Posted Memory Base Register (read/write, bit 15-0; offset 70h)
This register defines the base address of the non-posted memory-mapped address range for forwarding the cycle through the bridge. Upper twelve bits corresponding to address bits [31:20] are read/write. Lower 20 bits (19:0) are assumed to be 00000h.
13.2.42 Config Register 1 or 2: Non-Posted Memory Limit Register (read/write, bit 31-16; offset 70h)
This register defines the upper limit address of the non-posted memory-mapped address range for forwarding the cycle through the bridge. Upper twelve bits corresponding to address bits [31:20] are read/write. Lower 20 bits (19:0) are assumed to be FFFFFh.
13.2.43 Configuration Register 1: Port Option Register (bit 15-0; offset74h)
Bit 15-13 12 11-10 9 Reset DTQUEUE 8 7-6 5 Reserved ID Write Enable R/W R/O R/W Reserved Enable Long Request R/W Function Reserved Primary Pre Read R/W R/O Type R/O Reset to '000' Enable 1 more read for MEMR command on primary 1 = Enable 0 = N o ch an g e Reset to '00' Enable Long request for lock cycle 0 = N o ch an g e 1 = Enable Reset Secondary Delayed Transaction Queue 0 = N o ch an g e 1 = R eset Reset to '00' Allow write to Vendor ID, Device ID, Subsystem Vendor ID and Subsystem ID in the configuration space. 0 = Write protect 1 = Write enable Reset to 0 Controls the bridge's detection mechanism for matching non-posted memory write retry cycle from initiator on secondary interface. 0 = Command has to be exact 1 = MEMW is equivalent to MEMWI Reset to 0 Controls the bridge's detection mechanism for matching memory read retry cycle from initiator on secondary interface. 0=Command has to be exact 1=MEMR is equivalent to MEMRL or MEMRM Reset to 0 Controls the bridge's detection mechanism for matching non-posted memory write retry cycle from initiator on primary interface. 0 = Command has to be exact 1 = MEMW is equivalent to MEMWI Reset to 0 Controls the bridge's detection mechanism for matching memory read retry cycle from initiator on primary interface. 0 = Command has to be exact 1 = MEMR is equivalent to MEMRL or MEMRM Reset to 0 Enable 1 more read for MEMR command on secondary. 0 = disable 1 = enable Reset to 0
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Description
4
Secondary MEMW Command Alias Enable
R/W
3
Secondary MEMR Command Alias Enable
R/W
2
Primary MEMW Command Alias Enable
R/W
1
Primary MEMR Command Alias Enable
R/W
0
Secondary Pre Read
R/W
ADVANCE INFORMATION
65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
13.2.44 Configuration Register 2: Port Option Register (bit 15-0; offset74h)
Bit 15-13 12 11-10 9-8 7-6 5 Function Reserved Reserved Reserved Reserved Reserved ID Write Enable Type R/O R/W R/O R/W R/O R/W Reset to '000' Reset to 0 Reset to '00' Reset to '00' Reset to '00' Allow write to Vendor ID, Device ID, Subsystem Vendor ID, and Subsystem ID in the configuration space. 0 = Write protect 1 = Write enable Reset to 0 Controls the bridge's detection mechanism for matching non-posted memory write retry cycle from initiator on secondary interface. 0 = Command has to be exact 1 = MEMW is equivalent to MEMWI Reset to 0 Controls the bridge's detection mechanism for matching memory read retry cycle from initiator on secondary interface. 0=Command has to be exact 1=MEMR is equivalent to MEMRL or MEMRM Reset to 0 Reset to 0 Reset to 0 Enable 1 more read for MEMR command on secondary. 0 = disable 1 = enable Reset to 0 Description
4
Secondary MEMW Command Alias Enable
R/W
3
Secondary MEMR Command Alias Enable
R/W
2 1 0
Reserved Reserved Secondary Pre Read
R/W R/W R/W
68
09/18/00 Rev 1.1
ADVANCE INFORMATION
765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
13.2.45 Config Register 1 or 2: Master Timeout Counter Register (read/write, bit 31-16; offset 74h)
This register holds the maximum number of PCI clocks that PI7C7100 will wait for initiator to retry the same cycle before reporting timeout. Default is 8000h.
13.2.46 Config Register 1 or 2: Retry Counter Register (read/write, bit 31-0; offset 78h)
This register holds the maximum number of attempts that PI7C7100 will try before reporting retry timeout. Default is 0100_0000h.
13.2.47 Config Register 1 or 2: Sampling Timer Register (read/write, bit 31-0; offset 7Ch)
This register set the duration (in PCI clocks) during which PI7C7100 will record the number of successful transactions for performance evaluation. The recording will start right after this register is programmed and will be cleared after the timer expires. The maximum period is 128 seconds. Reset to 0000_0000h.
13.2.48 Config Register 1 or 2: Successful I/O Read Count Register (read/write, bit 31-0; offset 80h)
This register stores the successful I/O read count on the secondary interface which will be updated when the sampling timer is active. Reset to 0000_0000h.
13.2.49 Config Register 1 or 2: Successful I/O Write Count Register (read/write, bit 31-0; offset 84h)
This register stores the successful I/O write count on the secondary interface which will be updated when the sampling timer is active. Reset to 0000_0000h.
13.2.50 Config Register 1 or 2: Successful Memory Read Count Register (read/write, bit 31-0; offset 88h)
This register stores the successful memory read count on the secondary interface which will be updated when the sampling timer is active. Reset to 0000_0000h.
13.2.51 Config Register 1 or 2: Successful Memory Write Count Register (read/write, bit 31-0; offset 8Ch)
This register stores the successful memory write count on the secondary interface which will be updated when the sampling timer is active. Reset to 0000_0000h.
13.2.52 Config Register 1: Primary Successful I/O Read Count Register (read/write, bit 31-0; offset 90h)
This register stores the successful I/O read count on the primary interface which will be updated when the sampling timer is active. Reset to 0000_0000h.
13.2.53 Config Register 1: Primary Successful I/O Write Count Register (read/write, bit 31-0; offset 94h)
This register stores the successful I/O write count on the primary interface which will be updated when the sampling timer is active. Reset to 0000_0000h.
13.2.54 Config Register 1: Primary Successful Memory Read Count Register (read/write, bit 31-0; offset 98h)
This register stores the successful memory read count on the primary interface which will be updated when the sampling timer is active. Reset to 0000_0000h.
13.2.55 Config Register 1: Primary Successful Memory Write Count Register (read/write, bit 31-0; offset 9Ch)
This register stores the successful memory write count on the primary interface which will be updated when the sampling timer is active. Reset to 0000_0000h.
69
09/18/00 Rev 1.1
ADVANCE INFORMATION
65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
14. Bridge Behavior
A PCI cycle is initiated by asserting the FRAME# signal. In a bridge, there are a number of possibilities. Those possibilities are summarized in the table below:
14.1 Bridge Actions for Various Cycle Types
Initiator Master on primary Target Target on Primary R esp o n se PI7C7100 does not respond. It detects this situation by decoding the address as well as monitoring the P_DEVSEL# for other fast and medium devices on the primary port. PI7C7100 asserts P_DEVSEL#, terminates the cycle normally if it is able to be posted, otherwise returns with a retry. It then passes the cycle to the appropriate port. When the cycle is complete on the target port, it will wait for the initiator to repeat the same cycle and end with normal termination. PI7C7100 does not respond and the cycle will terminate as master abort. PI7C7100 does not respond. PI7C7100 asserts S1_DEVSEL# or S2_DEVSEL#, terminates the cycle normally if it is able to be posted, otherwise returns with a retry. It then passes the cycle to the appropriate port. When cycle is complete on the target port, it will wait for the initiator to repeat the same cycle and end with normal termination. PI7C7100 does not respond.
Master on primary
Target on secondary
Master on primary Master on secondary Master on secondary
Target not on primary nor secondary port Target on the same secondary port Target on primary or the other secondary port
Master on secondary
Target not on primary nor the other secondary
A target then has up to three cycles to respond before subtractive decoding is initiated. If the target detects an address hit, it should assert its DEVSEL# signal in the cycle corresponding to the values of bits 9 and 10 in the Configuration Status Register. Termination of a PCI cycle can occur in a number of ways. Normal termination begins by the initiator (master) de-asserting FRAME# with IRDY# being asserted (or remaining asserted) on the same cycle. The cycle completes when TRDY# and IRDY# are both asserted simultaneously. The target should de-assert TRDY# for one cycle following final assertion (sustained 3-state signal).
14.2 Transaction Ordering
To maintain data coherency and consistency, PI7C7100 complies with the ordering rules put forth in the PCI Local Bus Specification, Rev 2.1. The following table summarizes the ordering relationship of all the transactions through the bridge. PMW - Posted write (either memory write or memory write & invalidate) DRR - Delayed read request (all memory read, I/O read & configuration read) DWR - Delayed write request (I/O write & configuration write) DRC - Delayed read completion (all memory read, I/O read & configuration read) DWC - Delayed write completion (I/O write & configuration write )
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ADVANCE INFORMATION
765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
Cycle type shown on each row is the subsequent cycle after the previous shown on the column.
Can Row pass Column? PMW (Row 1) DRR (Row 2) DWR (Row 3) DRC (Row 4) DWC (Row 5) PMW Column 1 No No No No Yes DRR Column 2 Yes No No Yes Yes DWR Column 3 Yes No No Yes Yes DRC Column 4 Yes Yes Yes No No DWC Column 5 Yes Yes Yes No No
In Row 1 Column 1, PMW cannot pass the previous PMW and that means they must complete on the target bus in the order in which they were received in the initiator bus. In Row 2 Column 1, DRR cannot pass the previous PMW and that means the previous PMW heading to the same direction must be completed before the DRR can be attempted on the target bus. In Row 1 Column 2, PMW can pass the previous DRR as long as the DRR reaches the head of the delayed transaction queue.
14.3 Abnormal Termination (Initiated by Bridge Master)
14.3.1 Master Abort
Master abort indicates that when PI7C7100 acts as a master and receives no response (i.e., no target asserts P_DEVSEL# or S1_DEVSEL# or S2_DEVSEL#) from a target, the bridge de-asserts FRAME# and then de-asserts IRDY#.
14.3.2 Parity and Error Reporting
Parity must be checked for all addresses and write data. Parity is defined on the P_PAR, S1_PAR, and S2_PAR signals. Parity should be even (i.e. an even number of `1's) across AD, CBE, and PAR. Parity information on PAR is valid the cycle after AD and CBE are valid. For reads, even parity must be generated using the initiators CBE signals combined with the read data. Again, the PAR signal corresponds to read data from the previous data phase cycle.
14.3.3 Reporting Parity Errors
For all address phases, if a parity error is detected, the error should be reported on the P_SERR# signal by asserting P_SERR# for one cycle and then 3-stating two cycles after the bad address. P_SERR# can only be asserted if bit 6 and 8 in the Command Register are both set to 1. For write data phases, a parity error should be reported by asserting the P_PERR# signal two cycles after the data phase and should remain asserted for one cycle when bit 8 in the Command register is set to a 1. The target reports any type of data parity errors during write cycles, while the master reports data parity errors during read cycles. Detection of an address parity error will cause the PCI-to-PCI Bridge target to not claim the bus (P_DEVSEL# remains inactive) and the cycle will then terminate with a Master Abort. When the bridge is acting as master, a data parity error during a read cycle results in the bridge master initiating a Master Abort.
14.3.4 Secondary IDSEL mapping
When PI7C7100 detects a Type 1 configuration transaction for a device connected to the secondary, it translates the Type 1 transaction to Type 0 transaction on the downstream interface. Type 1 configuration format uses a 5-bit field at P_AD[15:11] as a device number. This is translated to S1_AD[31:16] or S2_AD[31:16] by PI7C7100.
71
09/18/00 Rev 1.1
ADVANCE INFORMATION
65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
15. IEEE 1149.1 Compatible JTAG Controller
An IEEE 1149.1 compatible Test Access Port (TAP) controller and associated TAP pins are provided to support boundary scan in PI7C7100 for board-level continuity test and diagnostics. The TAP pins assigned are TCK, TDI, TDO, TMS and TRST#. All digital input, output, input/output pins are tested except TAP pins and clock pin. The IEEE 1149.1 Test Logic consists of a TAP controller, an instruction register, and a group of test data registers including Bypass, Device Identification and Boundary Scan registers. The TAP controller is a synchronous 16 state machine driven by the Test Clock (TCK) and the Test Mode Select (TMS) pins. An independent power on reset circuit is provided to ensure the machine is in TEST_LOGIC_RESET state at power-up. The JTAG signal lines are not active when the PCI resource is operating PCI bus cycles. PI7C7100 implements 3 basic instructions: BYPASS, SAMPLE/PRELOAD, EXTEST.
15.1 Boundary Scan Architecture
Boundary-scan test logic consists of a boundary-scan register and support logic. These are accessed through a Test Access Port (TAP). The TAP provides a simple serial interface that allows all processor signal pins to be driven and/or sampled, thereby providing direct control and monitoring of processor pins at the system level. This mode of operation is valuable for design debugging and fault diagnosis since it permits examination of connections not normally accessible to the test system. The following subsections describe the boundary-scan test logic elements: TAP pins, instruction register, test data registers and TAP controller. Figure 15-1 illustrates how these pieces fit together to form the JTAG unit.
TAP Pins TDI Instruction Register Boundary-Scan Register Bypass Register TMS TCK TDO PI7C7100 System Pins
TAP Controller
Control and Clock Signals
TRST#
Figure 15-1. Test Access Port Block Diagram
15.1.1 TAP Pins
The PI7C7100's TAP pins form a serial port composed of four input connections (TMS, TCK, TRST# and TDI) and one output connection (TDO). These pins are described in Table 15-1. The TAP pins provide access to the instruction register and the test data registers.
15.1.2 Instruction Register
The Instruction Register (IR) holds instruction codes. These codes are shifted in through the Test Data Input (TDI) pin. The instruction codes are used to select the specific test operation to be performed and the test data register to be accessed. The instruction register is a parallel-loadable, master/slave-configured 2-bit wide, serial-shift register with latched outputs. Data is shifted into and out of the IR serially through the TDI pin clocked by the rising edge of TCK. The shifted-in instruction becomes active upon latching from the master stage to the slave stage. At that time the IR outputs along with the TAP finite state machine outputs are decoded to select and control the test data register selected by that instruction. Upon latching, all actions caused by any previous instructions terminate.
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765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
The instruction determines the test to be performed, the test data register to be accessed, or both. The IR is two bits wide. When the IR is selected, the most significant bit is connected to TDI, and the least significant bit is connected to TDO. The value presented on the TDI pin is shifted into the IR on each rising edge of TCK. The TAP controller captures fixed parallel data (01 binary ). When a new instruction is shifted in through TDI, the value 01 (binary) is always shifted out through TDO, least significant bit first. This helps identify instructions in a long chain of serial data from several devices. Upon activation of the TRST# reset pin, the latched instruction asynchronously changes to the idcode instruction. When the TAP controller moves into the test state other than by reset activation, the opcode changes as TDI shifts, and becomes active on the falling edge of TCK.
15.2 Boundary-Scan Instruction Set
The PI7C7100 supports three mandatory boundary-scan instructions (bypass, sample/preload and extest). The table shown below lists the PI7C7100's boundary-scan instruction codes. The "reserved" code should not be used.
Instruction Code (binary) 00 01
Instruction Name extest sample/preload
Instruction Code (binary) 10 11
Instruction Name reserved bypass
Table 15-1. TAP Pins
Instruction / Requisite extest IEEE 1149.1 Required
Opcode (binary) 00
Description Extest initiates testing of external circuitry, typically board-level interconnects and off chip circuitry. extest connects the boundary-scan register between TDI and TDO. When Extest is selected, all output signal pin values are driven by values shifted into the boundary-scan register and may change only on the falling edge of TCK. Also, when extest is selected, all system input pin states must be loaded into the boundary-scan register on the rising-edge of TCK. Sample/preload performs two functions: A snapshot of the sample instruction is captured on the rising edge of TCK without interfering with normal operation. The instruction causes boundary-scan register cells associated with outputs to sample the value being driven. * On the falling edge of TCK the data held in the boundary-scan cells is transferred to the slave register cells. Typically the slave latched data is applied to the system outputs via the extest instruction. Reserved
sample/ preload IEEE 1149.1 Required
01
i d co d e IEEE 1149.1 Optional bypass IEEE 1149.1 Required
10
11
Bypass instruction selects the one-bit bypass register between TDI and TDO pins. 0 (binary) is the only instruction that accesses the bypass register. While this instruction is in effect, all other test data registers have no effect on system operation. Test data registers with both test and system functionality perform their system functions when this instruction is selected.
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65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
15.3 TAP Test Data Registers
The PI7C7100 contains two test data registers (bypass and boundary-scan). Each test data register selected by the TAP controller is connected serially between TDI and TDO. TDI is connected to the test data register's most significant bit. TDO is connected to the least significant bit. Data is shifted one bit position within the register towards TDO on each rising edge of TCK. While any register is selected, data is transferred from TDI to TDO without inversion. The following sections describe each of the test data registers.
15.4 Bypass Register
The required bypass register, a one-bit shift register, provides the shortest path between TDI and TDO when a bypass instruction is in effect. This allows rapid movement of test data to and from other components on the board. This path can be selected when no test operation is being performed on the PI7C7100.
15.5 Boundary-Scan Register
The boundary-scan register contains a cell for each pin as well as control cells for I/O and the high-impedance pin. Table 15-2 shows the bit order of the PI7C7100 boundary-scan register. All table cells that contain "Control" select the direction of bidirectional pins or high-impedance output pins. When a "0" is loaded into the control cell, the associated pin(s) are high-impedance or selected as input. The boundary-scan register is a required set of serial-shiftable register cells, configured in master/slave stages and connected between each of the PI7C7100's pins and on-chip system logic. The VDD, GND, PLL, AGND, AVDD and JTAG pins are NOT in the boundary-scan chain. The boundary-scan register cells are dedicated logic and do not have any system function. Data may be loaded into the boundary-scan register master cells from the device input pins and output pin-drivers in parallel by the mandatory sample/ preload and extest instructions. Parallel loading takes place on the rising edge of TCK. Data may be scanned into the boundary-scan register serially via the TDI serial input pin, clocked by the rising edge of TCK. When the required data has been loaded into the master-cell stages, it can be driven into the system logic at input pins or onto the output pins on the falling edge of TCK state. Data may also be shifted out of the boundary-scan register by means of the TDO serial output pin at the falling edge of TCK.
15.6 TAP Controller
The TAP (Test Access Port) controller is a 4-state synchronous finite state machine that controls the sequence of test logic operations. The TAP can be controlled via a bus master. The bus master can be either automatic test equipment or a component (i.e., PLD) that interfaces to the TAP. The TAP controller changes state only in response to a rising edge of TCK. The value of the test mode state (TMS) input signal at a rising edge of TCK controls the sequence of state changes. The TAP controller is initialized after power-up by applying a low to the TRST# pin. In addition, the TAP controller can be initialized by applying a high signal level on the TMS input for a minimum of five TCK periods. For greater detail on the behavior of the TAP controller, test logic in each controller state and the state machine and public instructions, refer to the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture document (available from the IEEE).
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765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
Table 15-2. JTAG Boundary Register Order
Order 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Pin Names S2_AD[20-31] S2_AD[21] S2_AD[21] S2_PERR# S2_PERR# S2_PERR# S2_AD[8-19] S2_AD[16] S2_AD[16] S2_FRAME# S2_FRAME# S2_FRAME# S2_DEVSEL# /S2_TRDY# S2_DEVSEL# S2_DEVSEL# S2_AD[19] S2_AD[19] S2_AD[17] S2_AD[17] S2_AD[18] S2_AD[18] S2_AD[20] S2_AD[20] S2_AD[22] S2_AD[22] S2_AD[24] S2_AD[24] S2_AD[23] S2_AD[23] S2_CBE[0-3] S2_CBE[3] S2_CBE[3] S2_AD[25] S2_AD[25] S2_AD[26] Type co ntro l e nab le o utp ut inp ut co ntro l e nab le o utp ut inp ut co ntro l e nab le o utp ut inp ut co ntro l e nab le o utp ut inp ut co ntro l e nab le o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut co ntro l e nab le o utp ut inp ut o utp ut inp ut o utp ut
Order 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
Pin Names S2_AD[26] S2_AD[28] S2_AD[28] S2_AD[27] S2_AD[27] S2_AD[29] S2_AD[29] S2_AD[30] S2_AD[30] S2_AD[31] S2_AD[31] S2_GNT[0]# S2_GNT[0]# S2_REQ[0]# S2_REQ[1]# S2_GNT[1]# S2_GNT[2]# S2_REQ[2]# S2_REQ[3]# S2_GNT[3]# S2_GNT[4]# S2_REQ[4]# S2_REQ[5]# S2_GNT[5]# S2_GNT[6]# S2_REQ[6]# S2_REQ[7]# S2_GNT[7]# S2_RESET# S_CFN# S1_EN# S2_EN# SCAN_TM# SCAN_EN PLL_TM inp ut
Type
Order 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
Pin Names BYPASS FLUSH# P_RESET# P_GNT# P_REQ# P_REQ# P_AD[20-31] P_AD[30] P_AD[30] P_AD[31] P_AD[31] P_AD[27] P_AD[27] P_AD[26] P_AD[26] P_AD[28] P_AD[28] P_AD[29] P_AD[29] P_CBE[0-3] P_CBE[3] P_CBE[3] P_AD[24] P_AD[24] P_AD[25] P_AD[25] P_AD[23] P_AD[23] P_AD[22] P_AD[22] P_IDSEL P_AD[21] P_AD[21] P_AD[20] P_AD[20] inp ut inp ut inp ut inp ut
Type
o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut co ntro l e nab le o utp ut inp ut inp ut o utp ut o utp ut inp ut inp ut o utp ut o utp ut inp ut inp ut o utp ut o utp ut inp ut inp ut o utp ut o utp ut inp ut inp ut inp ut inp ut inp ut inp ut
co ntro l e nab le o utp ut co ntro l e nab le o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut co ntro l e nab le o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut inp ut o utp ut inp ut o utp ut inp ut
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65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
Table 15-2. JTAG Boundary Register Order
Order 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Pin Names P_AD[8-19] P_AD[19] P_AD[19] P_AD[18] P_AD[18] P_AD[17] P_AD[17] P_AD[16] P_AD[16] P_CBE[2] P_CBE[2] P_FRAME# P_FRAME# P_FRAME# P_IRDY# P_IRDY# P_IRDY# P_DEVSEL/P_TRDY# P_TRDY# P_TRDY# P_DEVSEL# P_DEVSEL# P_STOP# P_STOP# P_STOP# P_PERR# P_PERR# P_PERR# P_LOCK# P_LOCK# P_LOCK# P_SERR# P_SERR# P_AD[13] P_AD[13] Type co ntro l e nab le o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut co ntro l e nab le o utp ut inp ut co ntro l e nab le o utp ut inp ut co ntro l e nab le o utp ut inp ut o utp ut inp ut co ntro l e nab le o utp ut inp ut co ntro l e nab le o utp ut inp ut co ntro l e nab le o utp ut inp ut co ntro l e nab le o utp ut o utp ut inp ut Order 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 Pin Names P_AD[14] P_AD[14] P_AD[11] P_AD[11] P_AD[15] P_AD[15] P_AD[12] P_AD[12] P_AD[8] P_AD[8] P_CBE[1] P_CBE[1] P_AD[9] P_AD[9] P_AD[0-7] P_AD[5] P_AD[5] P_M66EN P_AD[6] P_AD[6] P_AD[2] P_AD[2] P_PAR P_PAR P_PAR P_AD[0] P_AD[0] P_CBE[0] P_CBE[0] P_AD[7] P_AD[7] P_AD[10] P_AD[10] P_AD[1] P_AD[1] Type o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut co ntro l e nab le o utp ut inp ut inp ut o utp ut inp ut o utp ut inp ut co ntro l e nab le o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut
(continued)
Order 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 Pin Names P_AD[3] P_AD[3] P_AD[4] P_AD[4] S1_AD[0-7] S1_AD[0] S1_AD[0] S1_AD[1] S1_AD[1] S1_AD[2] S1_AD[2] S1_AD[5] S1_AD[5] S1_AD[3] S1_AD[3] S1_AD[4] S1_AD[4] S1_CBE[0-3] S1_CBE[0] S1_CBE[0] S1_AD[7] S1_AD[7] S1_AD[6] S1_AD[6] S1_AD[8-19] S1_AD[8] S1_AD[8] S1_AD[9] S1_AD[9] S1_AD[10] S1_AD[10] S1_AD[11] S1_AD[11] S1_AD[12] S1_AD[12] Type o utp ut inp ut o utp ut inp ut co ntro l e nab le o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut co ntro l e nab le o utp ut inp ut o utp ut inp ut o utp ut inp ut co ntro l e nab le o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut
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765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
Table 15-2. JTAG Boundary Register Order
Order 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 Pin Names S1_AD[14] S1_AD[14] S1_AD[13] S1_AD[13] S1_AD[15] S1_AD[15] S1_SERR# S1_PAR S1_PAR S1_PAR S1_CBE[1] S1_CBE[1] S1_DEVSEL# /S1_TRDY# S1_DEVSEL# S1_DEVSEL# S1_STOP# S1_STOP# S1_STOP# S1_LOCK# S1_LOCK# S1_LOCK# S1_PERR# S1_PERR# S1_PERR# S1_FRAME# S1_FRAME# S1_FRAME# S1_IRDY# S1_IRDY# S1_IRDY# S1_TRDY# S1_TRDY# S1_AD[17]# S1_AD[17]# S1_AD[16]# Type o utp ut inp ut o utp ut inp ut o utp ut inp ut inp ut co ntro l e nab le o utp ut inp ut o utp ut inp ut co ntro l e nab le o utp ut inp ut co ntro l e nab le o utp ut inp ut co ntro l e nab le o utp ut inp ut co ntro l e nab le o utp ut inp ut co ntro l e nab le o utp ut inp ut co ntro l e nab le o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut Order 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 Pin Names S1_AD[16]# S1_AD[20-31] S1_AD[20] S1_AD[20] S1_CBE[2] S1_CBE[2] S1_AD[19] S1_AD[19] S1_CBE[3] S1_CBE[3] S1_AD[23] S1_AD[23] S1_AD[26] S1_AD[26] S1_AD[22] S1_AD[22] S1_AD[25] S1_AD[25] S1_AD[29] S1_AD[29] S1_AD[21] S1_AD[21] S1_AD[28] S1_AD[28] S1_AD[30] S1_AD[30] S1_AD[31] S1_AD[31] S1_AD[27] S1_AD[27] S1_AD[24] S1_AD[24] S1_AD[18] S1_AD[18] S1_GNT[0]# inp ut co ntro l e nab le o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut co ntro l e nab le Type
(continued)
Order 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 Pin Names S1_GNT[0]# S1_REQ[0]# S1_REQ[1]# S1_GNT[1]# S1_GNT[2]# S1_REQ[2]# S1_REQ[3]# S1_GNT[3]# S1_GNT[4]# S1_REQ[4]# S1_REQ[5]# S1_GNT[5]# S1_GNT[6]# S1_REQ[6]# S1_REQ[7]# S1_GNT[7]# S1_RESET# S2_AD[0-7] S2_AD[0] S2_AD[0] S2_AD[1] S2_AD[1] S2_AD[2] S2_AD[2] S2_AD[3] S2_AD[3] S2_AD[4] S2_AD[4] S2_AD[5] S2_AD[5] S2_AD[6] S2_AD[6] S2_AD[7] S2_AD[7] S2_CBE[0] Type o utp ut inp ut inp ut o utp ut o utp ut inp ut inp ut o utp ut o utp ut inp ut inp ut o utp ut o utp ut inp ut inp ut o utp ut o utp ut co ntro l e nab le o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut
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65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
Table 15-2. JTAG Boundary Register Order
Order 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 Pin Names S2_CBE[0] S2_AD[8] S2_AD[8] S2_AD[10] S2_AD[10] S2_AD[9] S2_AD[9] S2_AD[11] S2_AD[11] S_M66EN S2_AD[12] S2_AD[12] S2_AD[14] S2_AD[14] S2_CBE[1] S2_CBE[1] S2_AD[15] S2_AD[15] S2_PAR inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut o utp ut inp ut co ntro l e nab le Type
Order 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 Pin Names S2_PAR S2_PAR S2_SERR# S2_LOCK# S2_LOCK# S2_LOCK# S2_TRDY# S2_TRDY# S2_STOP# S2_STOP# S2_STOP# S2_IRDY# S2_IRDY# S2_IRDY# S2_CBE[2] S2_CBE[2] S2_AD[13] S2_AD[13] Type o utp ut inp ut inp ut co ntro l e nab le o utp ut inp ut o utp ut inp ut co ntro l e nab le o utp ut inp ut co ntro l e nab le o utp ut inp ut o utp ut inp ut o utp ut inp ut
(continued)
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765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
16. Electrical and Timing Specifications
16.1 Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested).
Storage Temperature Ambient Temperature with Power applied Supply Voltage to Ground Potentials (Inputs & AVC C , VD D only) DC Input Voltage -65C to +150C 0C to +70C -0.3V to +3.6V -0.5V to +3.6V
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
16.2 3.3V DC Specifications
Symbol VDD, AVCC Vih Vil Vih Vil Vipu Iil Voh Vol Voh Vol Cin Cclk CIDSEL Lpin
Notes: 1. CMOS Input pins: S_CFN#, TCK, TMS, TDI, TRST#, SCAN_EN, SCAN_TM# 2. CMOS Output pin: TDO 3. PCI pins: P_AD[31:0], P_CBE[3:0], P_PAR, P_FRAME#, P_IRDY#, P_TRDY#, P_DEVSEL#, P_STOP#, P_LOCK#, PIDSEL#, P_PERR#, P_SERR#, P_REQ#, P_GNT#, P_RESET#, S1_AD[31:0], S2_AD[31:0], S1_CBE[3:0], S2_CBE[3:0], S1_PAR, S2_PAR, S1_FRAME#, S2_FRAME#, S1_IRDY#, S2_IRDY#, S1_TRDY#, S2_TRDY#, S1_DEVSEL#, S2_DEVSEL#, S1_STOP#, S2_STOP#, S1_LOCK#, S2_LOCK#, S1_PERR#, S2_PERR#, S1_SERR#, S2_SERR#, S1_REQ[7:0]#, S2_REQ[7:0]#, S1_GNT[7:0]#, S2_GNT[7:0], S1_RESET#, S2_RESET#, S1_EN, S2_EN, P_FLUSH#.
Parameter Supply Voltage Input HIGH Voltage Input LOW Voltage CMOS Input HIGH Voltage CMOS Input LOW Voltage Input Pull-up Voltage Input Leakage Current Output HIGH Voltage Output LOW Voltage CMOS Output HIGH Voltage CMOS Output LOW Voltage Input Pin Capacitance CLK Pin Capacitance IDSEL Pin Capacitance Pin Inductance
Condition
Min. 3 0.5 VDD -0.5 0.7 VDD -0.5 0.7 VDD
Max. 3.6 VDD + 0.5 0.3 VDD VDD + 0.5 0.3 VDD
Units
Notes
3 V 1
0 < Vin < VDD Iout = -500A Iout = 1500A Iout = -500A Iout = 1500A VDD-0.5 0.9 VDD
10
A 3
0.1 VDD
V 2
0.5 10 5 12 8 20 nH pF
3
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09/18/00 Rev 1.1
ADVANCE INFORMATION
65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
16.3 3.3V AC Specifications
CLK Output Ton Input Tsu Th Note: Vtest - 1.5V for 5V signals: 0.4 VCC for 3.3V signals
Figure 16-1. PCI Signal Timing Measurement Conditions
Valid
Vtest Tval
Valid
Tinval Toff
Symbol Tsu Tsu(ptp) Th Tval Tval(ptp) Ton Toff
Parameter Input setup time to CLK - bused signals1,2,3 Input setup time to CLK - point-to-point1,2,3 Input signal hold time from CLK1,2 CLK to signal valid delay - bused signals1,2,3 CLK to signal valid delay - point-to-point1,2,3 Float to active delay1,2 Active to float delay1,2
Min. 7 10, 12 0 2 2 2 -
Max. - - - 11 12 - 28
Units
ns
1. See Figure 16-1 PCI Signal Timing Measurement Conditions. 2. All primary interface signals are synchronized to P_CLK. All secondary interface signals are synchronized to S_CLKOUT. 3. Point-to-point signals are p_req#, s1_req#<7:0>, s2_req#<7:0>, p_gnt#, s1_gnt#<7:0>, and s2_gnt#<7:0>. Bused signals are p_ad, p_cbe#, p_par, p_perr#, p_serr#, p_frame#, p_irdy#, p_trdy#, p_lock#, p_devsel#, p_stop#, p_idsel, s1_ad, s1_cbe#, s1_par, s1_perr#, s1_serr#, s1_frame#, s1_irdy#, s1_trdy#, s1_lock#, s1_devsel#, s1_stop#, s2_ad, s2_cbe#, s3_par, s2_perr#, s2_serr#, s2_frame#, s2_irdy#, s2_trdy#, s2_lock#, s2_devsel#, and s2_stop#.
16.4 Primary and Secondary Buses at 33 MHz Clock Timing
Symbol TS K E W TD E LAY TC Y C L E TH I G H TL O W Parameter SKEW among S_CLKOUT[15:0] DELAY between PCLK and S_CLKOUT[15:0] PCLK, S_CLKOUT[15:0] cycle time PCLK, S_CLKOUT[15:0] HIGH time PCLK, S_CLKOUT[15:0] LOW time 20pF load Condition Min. 0 7 30 11 11 Max. 1.0 10 ns Units
16.5 Power Consumption
Parameter Power Consumption Supply Current, ICC Typical 600 182 Units mW mA
80
09/18/00 Rev 1.1
ADVANCE INFORMATION
30
2
PIN #1 CORNER
27.00 0.15
SEATING PLANE 0.15 C
27.00 0.15
24.00 0.1
4 x 45 CHAMFER (4X) 8.00
1.44
1.27 BSC
765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
17. 256-Pin PBGA Package
A
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y 256 x o0.75 0.15 0.30 S C A S B S 0.10 S C
o1.0 (3X)
C 0.60 0.1
B
0.56 0.05 1.17 0.1 2.33 Min. / 3.50Max.
TOP
Figure 17-1. 256-Pin PBGA Package
BOTTOM
17.1 Part Number Ordering Information
Part PI7C7100CNA Pin - Package 256 - PBGA Temperature 0C to +70C
81
09/18/00 Rev 1.1
65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
ADVANCE INFORMATION
82
PI7C7100 3-Port PCI Bridge
09/18/00 Rev 1.1
PI7C7100 3-Port PCI Bridge
Appendix A
Timing Diagrams
432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
ADVANCE INFORMATION
A-2
Appendix A PI7C7100 3-Port PCI Bridge
04/18/00
ADVANCE INFORMATION
Appendix A PI7C7100 3-Port PCI Bridge
32121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 32121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Figure 1. Configuration Read Transaction
0 1 Addr 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_IDSEL
A
Data Byte Enables
Figure 2. Configuration Write Transaction
0 1 Addr 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_IDSEL
B
Data Byte Enables
Figure 3. Type 1 to Type 0 Configuration Read Transaction ( P --> S )
0 1 Addr 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_IDSEL P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L
A
Byte Enables
Addr A
Data Byte Enables
Addr Data A Byte Enables
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A-3
04/18/00
ADVANCE INFORMATION
432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Appendix A PI7C7100 3-Port PCI Bridge
Figure 4. Type 1 to Type 0 Configuration Write Transaction ( P --> S )
0 1 Addr 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_IDSEL P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L
B
Data Byte Enables
Addr B
Data Byte Enables
Addr Data B Byte Enables
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Figure 5. Upstream Type 1 to Special Cycle Transaction ( S --> P )
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L
0 1 2 3 4
Data Addr 1 Byte Enables
Addr
B
Data Byte Enables
Addr Data B Byte Enables
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
04/18/00
A-4
ADVANCE INFORMATION
Appendix A PI7C7100 3-Port PCI Bridge
32121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 32121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Figure 6. Downstream Type 1 to Special Cycle Transaction ( P --> S )
0 1 Addr 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L
B
Data Byte Enables
Addr B
Data Byte Enables
Addr Data 1 Byte Enables
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Figure 7. Downstream Type1 to Type1 Configuration Read Transaction ( P --> S )
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_IDSEL P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L
Addr B BytesEnables
Addr B Byte Enables
Addr B Byte Enables
Addr B Byte Enables
Addr Data B Byte Enables
Addr B Byte Enables
Addr B Byte Enables
Addr Data B Byte Enables
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
04/18/00
A-5
ADVANCE INFORMATION
432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Appendix A PI7C7100 3-Port PCI Bridge
Figure 8. Downstream Type1 to Type1 Configuration Write Transaction ( P --> S )
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_IDSEL P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L
Addr Data B Byte Enables
Addr Data B Byte Enables
Addr Data B Byte Enables
Addr Data B Byte Enables
Addr Data B Byte Enables
Addr Data B Byte Enables
Addr Data B Byte Enables
Addr Data B Byte Enables
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
Figure 9. Upstream Delayed Burst Memory Read Transaction ( S --> P )
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L
Addr
6
Data Data Data Data Data Data Data Data
Byte Enables
Addr 6 Byte Enables
Addr 6 Byte Enables
Addr 6 Byte Enables
Addr 6
Data Data Data Data Data Data Data Data
Byte Enables
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
04/18/00
A-6
ADVANCE INFORMATION
Appendix A PI7C7100 3-Port PCI Bridge
32121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 32121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Figure 10. Downstream Delayed Burst Memory Read Transaction ( P --> S )
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L
Addr 6 Byte Enables
Addr 6 Byte Enables
Addr 6 Byte Enables
Addr
6
Data Data Data Data Data Data Data Data
Byte Enables
Addr
6
Data Data Data Data Data Data Data Data
Byte Enables
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
Figure 11. Downstream Delayed Memory Read Transaction (P/33MHz-->S/33MHz)
0 1 Addr 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L
6
Byte Enables
Addr 6
Data Byte Enables
Addr Data 6 Byte Enables
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A-7
04/18/00
ADVANCE INFORMATION
432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Appendix A PI7C7100 3-Port PCI Bridge
Figure 12. Downstream Delayed Memory Read Transaction (S2/33MHz-->S1/33MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
S_CLKOUT[0] S1_AD [31:0] S1_CBE [3:0] S1_FRAME_L S1_IRDY_L S1_TRDY_L S1_STOP_L S1_DEVSEL_L S1_GNT_L S1_REQ_L S_CLKOUT[0] S2_AD[31:0] S2_CBE[3:0] S2_FRAME_L S2_IRDY_L S2_TRDY_L S2_STOP_L S2_DEVSEL_L S2_GNT_L S2_REQ_L
0 1 2 3 4
Addr Data 6 Byte Enables
Addr
6
Byte Enables
Data Addr 6 Byte Enables
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Figure 13. Downstream Delayed Memory Read Transaction (S1/33MHz-->S2/33MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
S_CLKOUT[0] S2_AD [31:0] S2_CBE [3:0] S2_FRAME_L S2_IRDY_L S2_TRDY_L S2_STOP_L S2_DEVSEL_L S2_GNT_L S2_REQ_L S_CLKOUT[0] S1_AD[31:0] S1_CBE[3:0] S1_FRAME_L S1_IRDY_L S1_TRDY_L S1_STOP_L S1_DEVSEL_L S1_GNT_L S1_REQ_L
0 1 2 3 4
Addr Data 6 Byte Enables
Addr
6
Byte Enables
Data Addr 6 Byte Enables
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
A-8
04/18/00
ADVANCE INFORMATION
Appendix A PI7C7100 3-Port PCI Bridge
32121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 32121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Figure 14. Upstream Delayed Memory Read Transaction (S/33MHz-->P/33MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L
0 1 2 3 4
Addr Data 6 Byte Enables
Addr
6
Byte Enables
Addr Data 6 Byte Enables
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Figure 15. Downstream Posted Memory Write Transaction (P/33MHz-->S/33MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L
Data Addr 7 Byte Enables
Data Addr 7 Byte Enables
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A-9
04/18/00
ADVANCE INFORMATION
432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Appendix A PI7C7100 3-Port PCI Bridge
Figure 16. Downstream Posted Memory Write Transaction (S2/33MHz-->S1/33MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
S_CLKOUT[0] S1_AD [31:0] S1_CBE [3:0] S1_FRAME_L S1_IRDY_L S1_TRDY_L S1_STOP_L S1_DEVSEL_L S1_GNT_L S1_REQ_L S_CLKOUT[0] S2_AD[31:0] S2_CBE[3:0] S2_FRAME_L S2_IRDY_L S2_TRDY_L S2_STOP_L S2_DEVSEL_L S2_GNT_L S2_REQ_L
Addr Data 7 Byte Enables
Addr Data 7 Byte Enables
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Figure 17. Downstream Posted Memory Write Transaction (S1/33MHz-->S2/33MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
S_CLKOUT[0] S2_AD [31:0] S2_CBE [3:0] S2_FRAME_L S2_IRDY_L S2_TRDY_L S2_STOP_L S2_DEVSEL_L S2_GNT_L S2_REQ_L S_CLKOUT[0] S1_AD[31:0] S1_CBE[3:0] S1_FRAME_L S1_IRDY_L S1_TRDY_L S1_STOP_L S1_DEVSEL_L S1_GNT_L S1_REQ_L
Addr Data 7 Byte Enables
Addr Data 7 Byte Enables
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
04/18/00
A-10
ADVANCE INFORMATION
Appendix A PI7C7100 3-Port PCI Bridge
32121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 32121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Figure 18. Upstream Posted Memory Write Transaction (S/33MHz-->P/33MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L
Addr Data 7 Byte Enables
Addr Data 7 Byte Enables
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Figure 19. Downstream Flow-Through Posted Memory Write Transaction (P/33MHz-->S/33MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L
Addr 7
Data
Data Data Data Data Data Data Data Data Data Byte Enables
Addr 7
Data
Data Data Data Data Data Data Data Data Data Byte Enables
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
04/18/00
A-11
ADVANCE INFORMATION
432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Appendix A PI7C7100 3-Port PCI Bridge
Figure 20. Downstream Flow-Through Posted Memory Write Transaction (S2/33MHz-->S1/33MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
S_CLKOUT[0] S1_AD [31:0] S1_CBE [3:0] S1_FRAME_L S1_IRDY_L S1_TRDY_L S1_STOP_L S1_DEVSEL_L S1_GNT_L S1_REQ_L S_CLKOUT[0] S2_AD[31:0] S2_CBE[3:0] S2_FRAME_L S2_IRDY_L S2_TRDY_L S2_STOP_L S2_DEVSEL_L S2_GNT_L S2_REQ_L
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Addr 7
Data
Data Data Data Data Data Data Data Data Data Byte Enables
Addr 7
Data
Data Data Data Data Data Data Data Data Data Byte Enables
Figure 21. Downstream Flow-Through Posted Memory Write Transaction (S1/33MHz-->S2/33MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
S_CLKOUT[0] S2_AD [31:0] S2_CBE [3:0] S2_FRAME_L S2_IRDY_L S2_TRDY_L S2_STOP_L S2_DEVSEL_L S2_GNT_L S2_REQ_L S_CLKOUT[0] S1_AD[31:0] S1_CBE[3:0] S1_FRAME_L S1_IRDY_L S1_TRDY_L S1_STOP_L S1_DEVSEL_L S1_GNT_L S1_REQ_L
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Addr 7
Data
Data Data Data Data Data Data Data Data Data Byte Enables
Addr 7
Data
Data Data Data Data Data Data Data Data Data Byte Enables
A-12
04/18/00
ADVANCE INFORMATION
Appendix A PI7C7100 3-Port PCI Bridge
32121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 32121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Figure 22. Upstream Flow-Through Posted Memory Write Transaction (S/33MHz-->P/33MHz)
! " # $ % & ' ! " # $ % & ' ! " # $ % &
P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L
! " # $ % & ' ! " # $ % & ' ! " # $ % &
Addr 7
Data
Data Data Data Data Data Data Data Data Data Byte Enables
Addr 7
Data
Data Data Data Data Data Data Data Data Data Byte Enables
Figure 23. Downstream Delayed I/O Read Transaction ( P --> S )
0 1 Addr 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L
2
Byte Enables
Addr 2
Data Byte Enables
Addr Data 2 Byte Enables
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
A-13
04/18/00
ADVANCE INFORMATION
432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Appendix A PI7C7100 3-Port PCI Bridge
Figure 24. Downstream Delayed I/O Read Transaction (S2/33MHz-->S1/33MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
S_CLKOUT[0] S1_AD [31:0] S1_CBE [3:0] S1_FRAME_L S1_IRDY_L S1_TRDY_L S1_STOP_L S1_DEVSEL_L S1_GNT_L S1_REQ_L S_CLKOUT[0] S2_AD[31:0] S2_CBE[3:0] S2_FRAME_L S2_IRDY_L S2_TRDY_L S2_STOP_L S2_DEVSEL_L S2_GNT_L S2_REQ_L
0 1 2 3 4
Addr Data 2 Byte Enables
Addr
2
Byte Enables
Data Addr 2 Byte Enables
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Figure 25. Downstream Delayed I/O Read Transaction (S1/33MHz-->S2/33MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
S_CLKOUT[0] S2_AD [31:0] S2_CBE [3:0] S2_FRAME_L S2_IRDY_L S2_TRDY_L S2_STOP_L S2_DEVSEL_L S2_GNT_L S2_REQ_L S_CLKOUT[0] S1_AD[31:0] S1_CBE[3:0] S1_FRAME_L S1_IRDY_L S1_TRDY_L S1_STOP_L S1_DEVSEL_L S1_GNT_L S1_REQ_L
0 1 2 3 4
Addr Data 2 Byte Enables
Addr
2
Byte Enables
Data Addr 2 Byte Enables
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
A-14
04/18/00
ADVANCE INFORMATION
Appendix A PI7C7100 3-Port PCI Bridge
32121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 32121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Figure 26. Upstream Delayed I/O Read Transaction (S/33MHz-->P/33MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L
0 1 2 3 4
Addr Data 2 Byte Enables
Addr
2
Byte Enables
Addr Data 2 Byte Enables
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Figure 27. Downstream Delayed I/O Write Transaction ( P --> S )
0 1 Addr 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L
3
Data Byte Enables
Addr 3
Data Byte Enables
Addr Data 3 Byte Enables
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A-15
04/18/00
ADVANCE INFORMATION
432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Appendix A PI7C7100 3-Port PCI Bridge
Figure 28. Downstream Delayed I/O Write Transaction (S2/33MHz-->S1/33MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
S_CLKOUT[0] S1_AD [31:0] S1_CBE [3:0] S1_FRAME_L S1_IRDY_L S1_TRDY_L S1_STOP_L S1_DEVSEL_L S1_GNT_L S1_REQ_L S_CLKOUT[0] S2_AD[31:0] S2_CBE[3:0] S2_FRAME_L S2_IRDY_L S2_TRDY_L S2_STOP_L S2_DEVSEL_L S2_GNT_L S2_REQ_L
0 1 2 3 4
Data Addr 3 Byte Enables
Addr
3
Data Byte Enables
Addr Data 3 Byte Enables
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Figure 29. Downstream Delayed I/O Write Transaction (S1/33MHz-->S2/33MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
S_CLKOUT[0] S2_AD [31:0] S2_CBE [3:0] S2_FRAME_L S2_IRDY_L S2_TRDY_L S2_STOP_L S2_DEVSEL_L S2_GNT_L S2_REQ_L S_CLKOUT[0] S1_AD[31:0] S1_CBE[3:0] S1_FRAME_L S1_IRDY_L S1_TRDY_L S1_STOP_L S1_DEVSEL_L S1_GNT_L S1_REQ_L
0 1 2 3 4
Data Addr 3 Byte Enables
Addr
3
Data Byte Enables
Addr Data Byte Enables 3
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
A-16
04/18/00
ADVANCE INFORMATION
Appendix A PI7C7100 3-Port PCI Bridge
32121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 32121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Figure 30. Upstream Delayed I/O Write Transaction ( S --> P )
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
P_CLK P_AD [31:0] P_CBE [3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_STOP_L P_DEVSEL_L P_GNT_L P_REQ_L S_CLKOUT[0] S_AD[31:0] S_CBE[3:0] S_FRAME_L S_IRDY_L S_TRDY_L S_STOP_L S_DEVSEL_L S_GNT_L S_REQ_L
0 1 2 3 4
Data Addr 3 Byte Enables
Addr
3
Data Byte Enables
Addr Data 3 Byte Enables
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
A-17
04/18/00
432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
ADVANCE INFORMATION
A-18
Appendix A PI7C7100 3-Port PCI Bridge
04/18/00
PI7C7100 3-Port PCI Bridge
Appendix B
Evaluation Board User's Manual
65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
ADVANCE INFORMATION
B-2
Appendix B PI7C7100 3-Port PCI Bridge
04/18/00
ADVANCE INFORMATION
765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Appendix B PI7C7100 3-Port PCI Bridge
PI7C7100 Evaluation Board User's Manual
General Information
1. Please make sure you have included with your PI7C7100 evaluation board, the five-page schematic and the preliminary specification for the PI7C7100. 2. Check all jumpers for proper settings:
Pin Name S_CFN# S 1_E N S 2_E N SCAN_EN SCAN_EN PLL_TM BYPASS P_FLUSH# Jumper JP 4 JP 5 JP 6 JP 7 JP 7 JP 8 JP 9 JP 1 0 Function Internal arbiter enable S1 bus enable S2 bus enable SCAN control SCLK_IN as clock input PLL test mode disable PLL disable Primary FIFO flush disable Position 1-2 (0) 2-3 (1) 2-3 (1) 1-2 (0) 2-3 (1) 1-2 (0) 2-3 (1) 2-3 (1)
3. Check and make sure there are no shorts between power (3.3V, 5V, 12V, and -12V) and ground. 4. Plug evaluation board in any PCI slot on your system. Make sure your system is powered off before doing so. 5. Connect any PCI devices on the secondary slots of the evaluation board. Be careful that the orientation of the card is correct (see Diagram A).
PCI Add-In Card
Pericom Semiconductor Three-Port PCI Bridge Board
Diagram A
B-3
04/18/00
ADVANCE INFORMATION
65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Appendix B PI7C7100 3-Port PCI Bridge
General Information (continued)
6. Turn on the power for the system. Your OS should already have drivers for the PI7C7100 evaluation board. In Win9X, Plug and Play should detect the device as a PCI-to-PCI bridge. The system may prompt you for the Win9X CD for the drivers. The OS will detect two PCI-to-PCI bridges as the PI7C7100 has two secondary PCI buses. In Win NT, you should not have to install drivers. 7. Install drivers for any PCI devices you have attached to the evaluation board. 8. If any of the steps are unclear or were unsuccessful, please contact your Pericom support person at 408-435-0800. 9. Thank you for evaluating Pericom Semiconductor Corporation's products.
B-4
04/18/00
ADVANCE INFORMATION
765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Appendix B PI7C7100 3-Port PCI Bridge
Frequently Asked Questions
1. What is the function of SCAN_EN? SCAN_EN is for a full scan test or S_CLKIN select. During SCAN mode, SCAN_EN will be driven to logic "0" or "logic "1" depending on functionality. During normal mode, if SCAN_EN is connected to logic "0" (JP7 in the 1-2 position), S_CLKIN will be used for PLL test only when PL_TM is active. If SCAN_EN is connected to logic "1" (JP7 in the 2-3 position), S_CLKIN will be the clock input for the secondary buses. All secondary clock outputs, S_CLKOUT [15:0], are still derived from P_CLK with 0-10ns delay. The S_CLKOUT [15:0] should be disabled by programming the bits [15:0] in both configuration registers 1 and 2 at offset 68h. 2. What is the function of SCAN_TM#? SCAN_TM# is for full scan test and power on reset for the PLL. SCAN_TM# should be connected to logic "1" or to an RC path (R1 and C13) during normal operation. 3. How do you use the external arbiter? a) Disable the on chip arbiter by connecting S_CFN to logic "1" (JP4 in the 2-3 position). b) Use S1_REQ0# as GRANT and S1_GNT0# as REQUEST on the S1 bus. c) Use S2_REQ0# as GRANT and S2_GNT0# as REQUEST on the S2 bus. 4. What is the purpose of having JP1, JP2, and JP3? JP1, JP2, and JP3 are designed for easy access to the primary bus signals. You may connect any of these pins to an oscilloscope or a logic analyzer for observation. No connection is required for normal operation. The following table indicates which bus signals correspond to which pins.
1 JP 2 JP 3 JP 1 REQ A D 31 GNT 2 A D 29 A D 28 A D 30 3 A D 26 A D 25 A D 27 4 C BE3 A D 23 A D 24 5 A D 21 A D 20 A D 22 6 A D 18 A D 17 A D 19 7 C BE2 FRAME A D 16 8 IRDY D VSEL IRDY 9 LOCK PERR STOP 10 PAR C BE1 SERR 11 A D 14 A D 13 A D 15 12 AD11 A D 10 A D 12 13 C BE0 AD 8 AD 9 14 AD 6 AD 4 AD 7 15 AD 5 AD 2 AD 3 16 AD 0 GND AD 1
5. What is the purpose for having U17, U19, and U20? U17, U19, and U20 are designed for easy access to the digital ground planes for observation. 6. How is the evaluation board constructed? The evaluation board is a six-layer PCB. The top and bottom layers (1 and 6) are for signals, power, and ground routing. Layer 2 and layer 5 are ground planes. Layer 3 is a digital 3.3V power plane. Layer 4 is a digital 5V power plane with an island of analog 3.3V power. 7. What is the function of S_CLKIN? The S_CLKIN pin is a test pin for the on chip PLL when PLL_TM is set to logic "1". During normal operation, if PLL_TM is set to logic "0", SCAN_TM# is set to logic "1", and SCAN_EN is set to logic "1", then S_CLKIN will be the clock input for both the secondary buses. However, the S_CLKOUT [15:0] are still derived by programming bits [15:0] in both configuration registers 1 and 2 at offset 68h. 8. What clock frequency combinations does the PI7C7100 support? Primary Bus 33MHz Secondary (1 and 2) Buses 33MHz
9. How are the JTAG signals being connected? The JTAG signals consist of TRST#, TCK, TMS, TDI, and TDO. All the mentioned signals have weak internal pull-up connections. Therefore, no connection is needed if you want the JTAG circuit to be disabled. If you want to activate the JTAG circuit, you need to connect all five signals according to the JTAG specification (IEEE 1149).
B-5
04/18/00
65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
ADVANCE INFORMATION
B-6
Appendix B PI7C7100 3-Port PCI Bridge
04/18/00
PI7C7100 3-Port PCI Bridge
Appendix C
Schematics
65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
ADVANCE INFORMATION
C-2
Appendix C PI7C7100 3-Port PCI Bridge
04/18/00
A
B
C
D
E
t1 P_AD[31:0] P_AD[31:0] U1 S1_AD[31:0] S1_AD[31:0]
Name 1-2 2-3 2-3
+3.3V +3.3V +3.3V R1 3.3k R2 5.1K JP5 JP4 JP6 3 2 1 HEADER 3 HEADER 3 C13 0.1uF R7 5.1k R6 5.1k R8 5.1K HEADER 3 3 2 1 3 2 1 R3 5.1K R4 5.1k +3.3V
JP Select
Position
S_CFNn
JP4
Function Internal Arbiter
S1_EN
JP5
S1_Enable
S2_EN 1-2 1-2 1-2 2-3
JP6
SCAN_EN
JP7
4
4
PLL_TM
JP8
ByPass_L
JP9
P_Flush_L
JP10
S2_Enable SCAN Disable PLL_TM Disable PLL Enable P_Flush Disable
Table1
+3.3V P_CBE[3:0] S1_CBE[3:0]
+3.3V
P_AD0 P_AD1 P_AD2 P_AD3 P_AD4 P_AD5 P_AD6 P_AD7 P_AD8 P_AD9 P_AD10 P_AD11 P_AD12 P_AD13 P_AD14 P_AD15 P_AD16 P_AD17 P_AD18 P_AD19 P_AD20 P_AD21 P_AD22 P_AD23 P_AD24 P_AD25 P_AD26 P_AD27 P_AD28 P_AD29 P_AD30 P_AD31 P_CBE0 P_CBE1 P_CBE2 P_CBE3 P_AD[0] P_AD[1] P_AD[2] P_AD[3] P_AD[4] P_AD[5] P_AD[6] P_AD[7] P_AD[8] P_AD[9] P_AD[10] P_AD[11] P_AD[12] P_AD[13] P_AD[14] P_AD[15] P_AD[16] P_AD[17] P_AD[18] P_AD[19] P_AD[20] P_AD[21] P_AD[22] P_AD[23] P_AD[24] P_AD[25] P_AD[26] P_AD[27] P_AD[28] P_AD[29] P_AD[30] P_AD[31] P_CBE[0] P_CBE[1] P_CBE[2] P_CBE[3] S_CFN_L S1_DEVSELN S1_FRAMEN S1_GNTN[7:0] S1_AD[0] S1_AD[1] S1_AD[2] S1_AD[3] S1_AD[4] S1_AD[5] S1_AD[6] S1_AD[7] S1_AD[8] S1_AD[9] S1_AD[10] S1_AD[11] S1_AD[12] S1_AD[13] S1_AD[14] S1_AD[15] S1_AD[16] S1_AD[17] S1_AD[18] S1_AD[19] S1_AD[20] S1_AD[21] S1_AD[22] S1_AD[23] S1_AD[24] S1_AD[25] S1_AD[26] S1_AD[27] S1_AD[28] S1_AD[29] S1_AD[30] S1_AD[31] S1_CBE[0] S1_CBE[1] S1_CBE[2] S1_CBE[3] Y2
R17 T17 Y20 V20 U20 Y19 W19 U19 Y18 W18 U18 Y17 W17 Y16 W16 V16 V12 W12 Y12 U11 V11 Y11 V10 W10 W9 Y9 U8 V8 W8 Y8 W7 Y7 V19 U16 U12 V9 S1_AD0 S1_AD1 S1_AD2 S1_AD3 S1_AD4 S1_AD5 S1_AD6 S1_AD7 S1_AD8 S1_AD9 S1_AD10 S1_AD11 S1_AD12 S1_AD13 S1_AD14 S1_AD15 S1_AD16 S1_AD17 S1_AD18 S1_AD19 S1_AD20 S1_AD21 S1_AD22 S1_AD23 S1_AD24 S1_AD25 S1_AD26 S1_AD27 S1_AD28 S1_AD29 S1_AD30 S1_AD31 S1_CBE0 S1_CBE1 S1_CBE2 S1_CBE3
T19 T20 R18 R19 R20 P17 N17 N18 N19 N20 M17 M19 M20 L18 L19 L20 G19 G20 F17 F19 F20 E17 E18 E19 D17 D19 D20 C18 C19 C20 B19 B20 P20 K17 G18 E20
JP8 3 2 1 HEADER 3 R12 5.1K R11 5.1K HEADER 3 R13 5.1k PLL_CAP1 PLL_CAP2 ByPass P_M66EN S_M66EN R14 5.1K PLL_PCLK P_M66EN PLL_SCLK S_M66EN 3 2 1
R10 5.1k
JP7
R9 5.1k
+3.3V
TRST_L TCK TMS TDO TDI
W3 W4 U3 V2 W1 V3 W2 S1_EN S2_EN TRST_L JTAG_TCK JTAG_TMS JTAG_TD0 JTAG_TDI
S1_DEVSELN S1_FRAMEN S1_GNTN0 S1_GNTN1 S1_GNTN2 S1_GNTN3 S1_GNTN4 S1_GNTN5 S1_GNTN6 S1_GNTN7 S1_IRDYN S1_LOCKN S1_PAR S1_IRDYN S1_LOCKN S1_PAR S1_PERRN
JP9
3
S1_REQN[7:0]
3
+3.3V
3 2 1
HEADER 3
V4 U5 Y3 U6 R4 Y4 V18 V5 D7 V6 SCAN_TM_L SCAN_EN_H PLL_TM_H CMPO1 RESERVED ByPass P_M66EN PLL_SCLK S_M66EN PLL_PCLK S1_REQN0 S1_REQN1 S1_REQN2 S1_REQN3 S1_REQN4 S1_REQN5 S1_REQN6 S1_REQN7
JP10
R15 5.1K
S1_RESETN S1_SERRN S1_STOPN S1_TRDYN
3 2 1 +3.3V AVCC
S2_AD[31:0]
S2_AD[31:0]
HEADER 3 1 F3A C57 0.1uF C19 0.001uF C22 0.01uF C23 0.1uF C40 0.01uF C41 0.1uF C42 0.001uF C58 0.01uF C59 0.1uF C60 0.001uF P_LOCKN P_PERRN P_SERRN 2
R16 5.1k
ADVANCE INFORMATION
765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
P_RESETN P_GNTN P_IDSEL P_REQN P_FRAMEN P_IRDYN P_TRDYN P_DEVSELN P_STOPN P_LOCKN P_PERRN P_SERRN P_PAR +3.3V W5 Y5 U7 Y10 W6 W13 V13 U13 Y14 W14 V14 Y15 W15 U15 P_FLUSH_L P_RESET_L P_GNT P_IDSEL P_REQ P_FRAME_L P_IRDY_L P_TRDY_L P_DEVSEL_L P_STOP_ L P_LOCK_L P_PERR_L P_SERR_L P_PAR C51 0.1uF + C8 10uF E2 J3 N2 V1 V7 U10 V15 W20 P19 L17 F18 D15 C14 D11 B8 D5 Y1 U4 AVCC +D3.3V +D3.3V +D3.3V +D3.3V +D3.3V +D3.3V +D3.3V +D3.3V +D3.3V +D3.3V +D3.3V +D3.3V +D3.3V +D3.3V +D3.3V +D3.3V AVCC AGND
2
C-3
C48 0.001uF C49 0.001uF C50 0.01uF AVCC +3.3V AVCC + C11 0.01uF C12 0.1uF C353 0.001uF C370 0.01uF C371 0.1uF C372 0.001uF C373 0.01uF C9 10uF + C10 10uF + C374 10uF C2 E3 G2 J2 K4 N1 R2 U2 DGND DGND DGND DGND DGND DGND DGND DGND C354 100uF C17 0.1uF +3.3V +3.3V +3.3V C360 0.01uF C361 0.001uF C362 0.1uF C363 0.01uF C364 0.001uF C365 0.1uF C366 0.01uF C367 0.001uF C368 0.1uF Y6 U9 W11 Y13 U14 V17 U17 T18 P18 M18 K19 H17 G17 D18 A20 A17 A15 D12 A10 A8 A5 A3 DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND C20 0.001uF C21 0.001uF C38 0.001uF C39 0.001uF C30 0.001uF C31 0.001uF C32 0.1uF C33 0.1uF C34 0.1uF C35 0.1uF C36 0.1uF C37 0.1uF PI7C7100
B C
C55 0.001uF
C56 0.01uF
+3.3V
AVCC
1
2
F3A
2
C43 0.001uF
C44 0.01uF
C45 0.1uF
C46 0.01uF
C47 0.1uF
S2_CBE[3:0]
+5V
U0
S1_DEVSEL_L S1_FRAME_L S1_GNTN[0] S1_GNTN[1] S1_GNTN[2] S1_GNTN[3] S1_GNTN[4] S1_GNTN[5] S1_GNTN[6] S1_GNTN[7] S1_IRDY_L S1_LOCK_L S1_PAR_L S1_PERR_L S1_REQ[0] S1_REQ[1] S1_REQ[2] S1_REQ[3] S1_REQ[4] S1_REQ[5] S1_REQ[6] S1_REQ[7] S1_RESET_L S1_SERR_L S1_STOP_L S1_TRDY_L S2_AD[0] S2_AD[1] S2_AD[2] S2_AD[3] S2_AD[4] S2_AD[5] S2_AD[6] S2_AD[7] S2_AD[8] S2_AD[9] S2_AD[10] S2_AD[11] S2_AD[12] S2_AD[13] S2_AD[14] S2_AD[15] S2_AD[16] S2_AD[17] S2_AD[18] S2_AD[19] S2_AD[20] S2_AD[21] S2_AD[22] S2_AD[23] S2_AD[24] S2_AD[25] S2_AD[26] S2_AD[27] S2_AD[28] S2_AD[29] S2_AD[30] S2_AD[31] S2_CBE[0] S2_CBE[1] S2_CBE[2] S2_CBE[3] S2_AD0 S2_AD1 S2_AD2 S2_AD3 S2_AD4 S2_AD5 S2_AD6 S2_AD7 S2_AD8 S2_AD9 S2_AD10 S2_AD11 S2_AD12 S2_AD13 S2_AD14 S2_AD15 S2_AD16 S2_AD17 S2_AD18 S2_AD19 S2_AD20 S2_AD21 S2_AD22 S2_AD23 S2_AD24 S2_AD25 S2_AD26 S2_AD27 S2_AD28 S2_AD29 S2_AD30 S2_AD31 S2_CBE0 S2_CBE1 S2_CBE2 S2_CBE3 S2_DEVSELN S2_FRAMEN
J20 H20 B18 D16 B16 D14 A14 B13 B12 C11 H19 J18 K18 J17 B17 C17 A16 C15 C13 D13 A12 B11 B10 K20 J19 H18 C10 D10 A9 B9 C9 D9 C8 D8 B7 C7 A6 B6 C6 D6 B5 C5 B1 C1 D1 E4 E1 F4 F3 F2 G4 G3 G1 H4 H3 H2 H1 J4 A7 A4 A1 F1
3
VI
VO
2
+
C16 0.1uF
C7 10uF
1
GNDTAB
4
S2_GNTN[7:0]
LT1117
R5
R25
121
S2_GNTN0 S2_GNTN1 S2_GNTN2 S2_GNTN3 S2_GNTN4 S2_GNTN5 S2_GNTN6 S2_GNTN7
226
R17
0
S2_IRDYN S2_LOCKN S2_PAR S2_PERRN S2_REQN[7:0]
R18
150
+3.3V
S2_DEVSEL_L S2_FRAME_L S2_GNTN[0] S2_GNTN[1] S2_GNTN[2] S2_GNTN[3] S2_GNTN[4] S2_GNTN[5] S2_GNTN[6] S2_GNTN[7] S2_IRDY_L S2_LOCK_L S2_PAR_L S2_PERR_L S2_REQ[0] S2_REQ[1] S2_REQ[2] S2_REQ[3] S2_REQ[4] S2_REQ[5] S2_REQ[6] S2_REQ[7] S2_RESET_L S2_SERR_L S2_STOP_L S2_TRDY_L
D3 D2 K2 L1 L4 M3 N4 R1 P4 U1 B2 B3 B4 D4 K3 K1 M1 M2 P1 P2 R3 T2 T4 C4 C3 A2
S2_REQN0 S2_REQN1 S2_REQN2 S2_REQN3 S2_REQN4 S2_REQN5 S2_REQN6 S2_REQN7
S2_RESETN S2_SERRN S2_STOPN S2_TRDYN
1
1
SCLKOUT[15:0]
C24 0.01uF
C25 0.01uF
C26 0.01uF
C27 0.01uF
C28 0.01uF
C29 0.01uF
2380 Bering Dr., San Jose, CA
Title
Three Port PCI Bridge Evaluation Board
Size C Date:
D
SCLKOUT[15] SCLKOUT[14] SCLKOUT[13] SCLKOUT[12] SCLKOUT[11] SCLKOUT[10] SCLKOUT[9] SCLKOUT[8] SCLKOUT[7] SCLKOUT[6] SCLKOUT[5] SCLKOUT[4] SCLKOUT[3] SCLKOUT[2] SCLKOUT[1] SCLKOUT[0]
T3 T1 P3 N3 M4 L3 L2 J1 A11 C12 A13 B14 B15 C16 A18 A19
SCLKOUT15 SCLKOUT14 SCLKOUT13 SCLKOUT12 SCLKOUT11 SCLKOUT10 SCLKOUT9 SCLKOUT8 SCLKOUT7 SCLKOUT6 SCLKOUT5 SCLKOUT4 SCLKOUT3 SCLKOUT2 SCLKOUT1 SCLKOUT0
Document Number PI7C7100
PCI Chip
Friday, March 17, 2000
E
Rev 1.3 Sheet 1 of 5
Appendix C PI7C7100 3-Port PCI Bridge
04/18/00
A
A
B
C
D
E
4
4
U44 U43 T 1header U42 T TRST_L R28 0 R30 0 TMS TDI INTA 1header INTB U40 1header INTC RESET_L 1 INTD 1header U39 1header
3
T
1header 1 U5 1 AD[31:0] 1 U45 T C/BE[3:0] 1header
TCK TDO 1 1 T T R29 0
1
AD[31:0]
C/BE[3:0]
1 1header
U46 T
U38 1 T 1 1header 1 U48 T U47 T
1header
3
T
JP1
JP2
JP3
R31 5.1k
+3.3V
ADVANCE INFORMATION
65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
R32 5.1k P_GNT_L AD30 AD27 AD24 AD22 AD19 AD16 P_IRDY_L P_STOP_ L P_SERR_L AD15 AD12 AD9 AD7 AD3 AD1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 HEADER 16 P_REQ_L AD29 AD26 C/BE3 AD21 AD18 C/BE2 P_TRDY_L P_LOCK_L P_PAR AD14 AD11 C/BE0 AD6 AD5 AD0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 HEADER 16 AD31 AD28 AD25 AD23 AD20 AD17 P_FRAME_L P_DVSEL_L P_PERR_L C/BE1 AD13 AD10 AD8 AD4 AD2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 HEADER 16 B1 R27 0 B2 B3 B4 B5 B6 B7 INTB INTB_L B8 INTD INTD_L U41 B9 B10 1header B11 B12 B13 B14 B15 B16 P_CLK CLK B17 B18 P_REQ_L REQ_L B19 AD31 B20 AD29 B21 B22 AD27 B23 B24 AD25 B25 C/BE3 B26 B27 AD23 B28 B29 AD21 B30 AD19 B31 B32 AD17 B33 C/BE2 B34 B35 P_IRDY_L IRDY_L B36 B37 P_DVSEL_L DVSEL_L B38 B39 P_LOCK_L LOCK_L P_PERR_L B40 PERR_L B41 B42 P_SERR_L SERR_L B43 B44 C/BE1 AD14 B45 B46 B47 AD12 B48 AD10 B49 M66EN B50 B51 B52 AD8 B53 AD7 B54 B55 AD5 B56 AD3 B57 B58 AD1 B59 B60 B61 B62 -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# NC PRSNT2# NC NC NC GND CLK GND REQ# +5VIO1 AD31 AD29 GND AD27 AD25 +3.3V C/BE3# AD23 GND AD21 AD19 +3.3V AD17 C/BE2# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 GND AD12 AD10 M66EN NC NC AD08 AD07 +3.3V AD05 AD03 GND AD01 +5VIO2 ACK64# +5V +5V PCIEDGE T2 TRST# +12V TMS TDI +5V INTA# INTC# +5V NC +5VIO1 NC NC NC NC RST# +5VIO1 GNT# GND NC AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3V AD22 AD20 GND AD18 AD16 +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD15 +3.3V AD13 AD11 GND AD09 NC NC C/BE0# +3.3V AD06 AD04 GND AD02 AD00 +5VIO2 REQ64# +5V +5V R26 0 A1 A2 A3 A4 A5 A6 INTA INTA_L A7 INTC INTC_L A8 A9 A10 A11 A12 A13 A14 A15 P_RESET_L A16 A17 P_GNT_L GNT_L A18 A19 A20 AD30 A21 AD28 A22 A23 AD26 A24 A25 AD24 A26 P_IDSEL_L IDSEL_L A27 A28 AD22 A29 AD20 A30 A31 AD18 A32 AD16 A33 A34 P_FRAME_L FRAME_L A35 A36 P_TRDY_L TRDY_L A37 A38 P_STOP_ L STOP_ L A39 A40 A41 A42 A43 P_PAR PAR A44 AD15 A45 AD13 A46 A47 AD11 A48 A49 AD9 A50 A51 A52 C/BE0 A53 A54 AD6 A55 AD4 A56 A57 AD2 A58 AD0 A59 A60 A61 A62
2
C-4
+5V +12V -12V +5VIO2 +5VIO1 + C103 0.01uF C104 0.01uF C101 10uF + C102 10uF C1 0.1uF C110 0.01uF C111 0.1uF C112 0.01uF +3.3V +3.3V + C121 0.001uF + C2 0.01uF C106 0.1uF C97 10uF C119 0.001uF C108 0.01uF C5 0.1uF C105 0.01uF C3 0.1uF C120 0.001uF C109 10uF C107 0.01uF C4 0.1uF C118 0.001uF +5V C113 0.1uF C114 0.1uF C115 0.01uF C116 0.01uF C6 0.001uF C14 0.001uF C15 0.001uF
B C
2
1 2 3 4 5 6 7 8 9 10 11 12 13 JP1 GNT AD30 AD27 AD24 AD22 AD19 AD16 IRDY STOP SERR AD15 AD12 AD9 JP2 REQ AD29 AD26 CBE3 AD21 AD18 CBE2 TRDY LOCK PAR AD14 AD11 CBE0 JP3 AD31 AD28 AD25 AD23 AD20 AD17 Frame DVSEL PERR CBE1 AD13 AD10 AD8
Table2 M66EN
14 AD7 AD6 AD4
15 AD3 AD5 AD2
16 AD1 AD0 GND
C117 0.01uF
1
1
2380 Bering Dr., San Jose, CA
C18 0.001uF Title
Three Port PCI Bridge Evaluation Board
Size C Date:
D
Document Number PI7C7100
PCI Edge Connector
Friday, March 17, 2000
E
Rev 1.3 Sheet 2 of 5
Appendix C PI7C7100 3-Port PCI Bridge
A
04/18/00
A
B
C
D
E
+12V
-12V
+3.3V
+5V
C129 0.01uF
C130 0.01uF
C131 0.1uF
C132 0.1uF
C133 0.1uF
C134 0.1uF
C135 0.1uF
C138 0.1uF
C139 0.1uF
C140 0.1uF
C69 0.1uF
C70 0.1uF
U9 2 1 TCK1 2 2 INTB_L INTD_L INTD_L INTB_L INTA_L INTC_L INTC_L INTA_L INTD_L INTB_L 5.1K 2 2 2 2 TCK2 TCK3 2 2 INTA_L INTC_L INTC_L INTA_L 5.1K R38 2 1 2 5.1K R42 TMS2 1 R45 TDI2 1 5.1K 5.1K 2 1 R33 5.1K R39 +3.3V 2 1 TRST2_L 2 2 +3.3V R36 +3.3V +3.3V
U10
U11
U8
1
R37
2
TCK0
5.1K
4
4
INTB_L INTD_L
RESET_L CLK1 GNT0_L REQ1_L AD30 AD28 AD26 AD24 IDSEL2_L AD22 AD20 AD18 AD16 FRAME_L IRDY_L TRDY_L DEVSEL_L STOP_L SDONE2 SBO2_ L SERR_L AD15 AD13 AD11 AD9 C/BE0 AD6 AD4 AD2 AD0 REQ64#2 C216 0.01uF PAR LOCK_L PERR_L REQ2_L REQ3_L GNT1_L GNT2_L CLK2 CLK3
RESET_L
RESET_L
RESET_L GNT3_L
CLK0
REQ0_L
IDSEL0_L
IDSEL1_L
IDSEL3_L
FRAME_L IRDY_L TRDY_L DEVSEL_L STOP_ L LOCK_L PERR_L SERR_L PAR PAR SERR_L LOCK_L PERR_L STOP_ L DEVSEL_L TRDY_L IRDY_L
FRAME_L
FRAME_L TRDY_L STOP_ L
IRDY_L
DEVSEL_L
LOCK_L PERR_L
3
SERR_L
PAR
3
C153 0.01uF
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C147 B11 0.01uF B12 C150 B13 0.01uFB14 B15 B16 B17 B18 B19 B20 AD31 B21 AD29 B22 B23 AD27 B24 AD25 B25 B26 C/BE3 B27 AD23 B28 B29 AD21 B30 AD19 B31 B32 AD17 B33 C/BE2 B34 B35 B36 B37 B38 B39 B40 B41 B42 SERR_L B43 B44 C/BE1 B45 AD14 B46 B47 AD12 B48 AD10 B49 M66EN B50 B51 B52 AD8 B53 AD7 B54 B55 AD5 B56 AD3 B57 B58 AD1 B59 B60 ACK64#0 B61 B62 C154 0.01uF -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# NC PRSNT2# GND GND NC GND CLK GND REQ# +5V AD31 AD29 GND AD27 AD25 +3.3V C/BE3# AD23 GND AD21 AD19 +3.3V AD17 C/BE2# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 GND AD12 AD10 M66EN NC NC AD08 AD07 +3.3V AD05 AD03 GND AD01 +5V ACK64# +5V +5V C155 0.01uF PCISLOT PCISLOT PCISLOT TRST# +12V TMS TDI +5V INTA# INTC# +5V NC +5V NC GND GND NC RST# +5V GNT# GND NC AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3V AD22 AD20 GND AD18 AD16 +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD15 +3.3V AD13 AD11 GND AD09 NC NC C/BE0# +3.3V AD06 AD04 GND AD02 AD00 +5V REQ64# +5V +5V -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# NC PRSNT2# GND GND NC GND CLK GND REQ# +5V AD31 AD29 GND AD27 AD25 +3.3V C/BE3# AD23 GND AD21 AD19 +3.3V AD17 C/BE2# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 GND AD12 AD10 M66EN NC NC AD08 AD07 +3.3V AD05 AD03 GND AD01 +5V ACK64# +5V +5V TRST# +12V TMS TDI +5V INTA# INTC# +5V NC +5V NC GND GND NC RST# +5V GNT# GND NC AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3V AD22 AD20 GND AD18 AD16 +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD15 +3.3V AD13 AD11 GND AD09 NC NC C/BE0# +3.3V AD06 AD04 GND AD02 AD00 +5V REQ64# +5V +5V -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# NC PRSNT2# GND GND NC GND CLK GND REQ# +5V AD31 AD29 GND AD27 AD25 +3.3V C/BE3# AD23 GND AD21 AD19 +3.3V AD17 C/BE2# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 GND AD12 AD10 M66EN NC NC AD08 AD07 +3.3V AD05 AD03 GND AD01 +5V ACK64# +5V +5V TRST# +12V TMS TDI +5V INTA# INTC# +5V NC +5V NC GND GND NC RST# +5V GNT# GND NC AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3V AD22 AD20 GND AD18 AD16 +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD15 +3.3V AD13 AD11 GND AD09 NC NC C/BE0# +3.3V AD06 AD04 GND AD02 AD00 +5V REQ64# +5V +5V
-12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# NC PRSNT2# GND GND NC GND CLK GND REQ# +5V AD31 AD29 GND AD27 AD25 +3.3V C/BE3# AD23 GND AD21 AD19 +3.3V AD17 C/BE2# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 GND AD12 AD10 M66EN NC NC AD08 AD07 +3.3V AD05 AD03 GND AD01 +5V ACK64# +5V +5V
TRST# +12V TMS TDI +5V INTA# INTC# +5V NC +5V NC GND GND NC RST# +5V GNT# GND NC AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3V AD22 AD20 GND AD18 AD16 +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD15 +3.3V AD13 AD11 GND AD09 NC NC C/BE0# +3.3V AD06 AD04 GND AD02 AD00 +5V REQ64# +5V +5V
R34 A1 1 TRST0_L 5.1K A2 R40 A3 TMS0 1 R43 1 5.1K A4 TDI0 5.1K A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 AD30 A21 A22 AD28 A23 AD26 A24 A25 AD24 A26 A27 A28 AD22 A29 AD20 A30 A31 AD18 A32 AD16 A33 A34 A35 A36 A37 A38 A39 A40 SDONE0 A41 SBO0_ L A42 A43 A44 AD15 A45 A46 AD13 A47 AD11 A48 A49 AD9 A50 A51 A52 C/BE0 A53 A54 AD6 A55 AD4 A56 A57 AD2 A58 AD0 A59 A60 REQ64#0 A61 A62 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C148 B11 0.01uF B12 C151 B13 0.01uFB14 B15 B16 B17 B18 B19 B20 AD31 B21 AD29 B22 B23 AD27 B24 AD25 B25 B26 C/BE3 B27 AD23 B28 B29 AD21 B30 AD19 B31 B32 AD17 B33 C/BE2 B34 B35 B36 B37 B38 B39 B40 B41 B42 SERR_L B43 B44 C/BE1 B45 AD14 B46 B47 AD12 B48 AD10 B49 M66EN B50 B51 B52 AD8 B53 AD7 B54 B55 AD5 AD3 B56 B57 AD1 B58 B59 B60 ACK64#1 B61 B62 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C149 B11 0.01uF B12 C152 B13 0.01uFB14 B15 B16 B17 B18 B19 B20 AD31 B21 AD29 B22 B23 AD27 B24 AD25 B25 B26 C/BE3 B27 AD23 B28 B29 AD21 B30 AD19 B31 B32 AD17 B33 C/BE2 B34 B35 B36 B37 B38 B39 B40 B41 B42 SERR_L B43 B44 C/BE1 B45 AD14 B46 B47 AD12 B48 AD10 B49 M66EN B50 B51 B52 AD8 B53 AD7 B54 B55 AD5 B56 AD3 B57 B58 AD1 B59 B60 ACK64#2 B61 B62 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C339 B11 0.01uF B12 C340 B13 0.01uFB14 B15 B16 B17 B18 B19 B20 AD31 B21 AD29 B22 B23 AD27 B24 AD25 B25 B26 C/BE3 B27 AD23 B28 B29 AD21 B30 AD19 B31 B32 AD17 B33 C/BE2 B34 B35 B36 B37 B38 B39 B40 B41 B42 SERR_L B43 B44 C/BE1 B45 AD14 B46 B47 AD12 B48 AD10 B49 M66EN B50 B51 B52 AD8 B53 AD7 B54 B55 AD5 B56 AD3 B57 B58 AD1 B59 B60 ACK64#3 B61 B62
R35 A1 1 TRST1_L 5.1K A2 R41 A3 TMS1 1 R44 1 5.1K A4 TDI1 5.1K A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 AD30 A21 A22 AD28 A23 AD26 A24 A25 AD24 A26 A27 A28 AD22 A29 AD20 A30 A31 AD18 A32 AD16 A33 A34 A35 A36 A37 A38 A39 A40 SDONE1 A41 SBO1_ L A42 A43 A44 AD15 A45 AD13 A46 A47 AD11 A48 A49 AD9 A50 A51 A52 C/BE0 A53 A54 AD6 A55 AD4 A56 A57 AD2 A58 AD0 A59 A60 REQ64#1 A61 A62
R46 A1 TRST3_L 1 5.1K A2 R47 A3 TMS3 1 R48 A4 TDI3 1 5.1K 5.1K A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 AD30 A21 A22 AD28 A23 AD26 A24 A25 AD24 A26 A27 A28 AD22 A29 AD20 A30 A31 AD18 A32 AD16 A33 A34 A35 A36 A37 A38 A39 A40 SDONE3 A41 SBO3_ L A42 A43 A44 AD15 A45 A46 AD13 A47 AD11 A48 A49 AD9 A50 A51 A52 C/BE0 A53 A54 AD6 A55 AD4 A56 A57 AD2 A58 AD0 A59 A60 REQ64#3 A61 A62
ADVANCE INFORMATION
765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
C/BE[3:0] C/BE[3:0] R51 2 SDONE0 SBO0_ L 5.1K 2 PERR_L 5.1K 2 SERR_L 1 R67 2 5.1K 2 STOP_ L 1 R73 2 5.1K +5V DEVSEL_L 1 IRDY_L 1 5.1K 2 5.1K 2 5.1K SBO3_ L 1 R72 SBO2_ L 1 R66 SBO1_ L 1 2 1 R60 R61 2 5.1K TRDY_L 1 5.1K 2 SDONE1 5.1K 2 SDONE2 5.1K 2 SDONE3 5.1K -12V +3.3V 1 R71 1 R65 1 R59 LOCK_L 1 2 1 2 1 2 +3.3V R52 R53 R54 +3.3V +3.3V +3.3V FRAME_L 1 R55 +3.3V 2 5.1K R62 2 5.1K R68 2 5.1K R74 2 5.1K 5.1K
2
C-5
AD[31:0] +3.3V 2 REQ64#0 1 2 REQ64#1 5.1K 2 REQ64#2 5.1K 2 REQ64#3 5.1K +12V 1 R70 1 R64 1 R58 C161 0.01uF C162 0.01uF C163 0.01uF C164 0.01uF C165 0.01uF C166 0.01uF C167 0.01uF C170 0.01uF C171 0.01uF C172 0.01uF C72 0.01uF C73 0.01uF +3.3V +5V C186 0.1uF C187 0.1uF C188 0.1uF C189 0.1uF C190 0.1uF C194 0.1uF C195 0.1uF C74 0.1uF C191 0.1uF C192 0.1uF +3.3V +5V C211 0.01uF C212 0.01uF C213 0.01uF C214 0.01uF C215 0.01uF C226 0.01uF C217 0.01uF C218 0.01uF C219 0.01uF C220 0.01uF
B C
PCISLOT
AD[31:0]
M66EN
ACK64#0
1
R50
2
M66EN
5.1K
ACK64#1
1
R57
5.1K
ACK64#2
1
R63
5.1K
ACK64#3
1
R69
5.1K
+3.3V
+5V
+
C156 10uF
+
C158 10uF
+12V
-12V
C184 0.01uF
C185 0.01uF
1
1
+3.3V
+5V
+12V
-12V
+
C204 10uF
+
C206 10uF
C209 0.01uF
C210 0.01uF
2380 Bering Dr., San Jose, CA
Title
Three Port PCI Bridge Evaluation Board
Size C Date:
D
Document Number PI7C7100
Secondary 1 PCI Bus
Friday, March 17, 2000
E
Rev 1.3 Sheet 3 of 5
Appendix C PI7C7100 3-Port PCI Bridge
A
04/18/00
A
B
C
D
E
+5V
+12V
-12V
+3.3V
+5V
+ C234 0.01uF C235 0.01uF C236 0.1uF C237 0.1uF C238 0.1uF C239 0.1uF C240 0.1uF C243 0.1uF C244 0.1uF C245 0.1uF C78 0.1uF C79 0.1uF
C232 10uF
U13 2 1 TCK1 2 2 INTB_L INTD_L INTD_L INTB_L INTA_L INTC_L INTC_L INTA_L 5.1K 2 2 2 2 5.1K TCK2 TCK3 2 2 INTA_L INTC_L INTC_L INTA_L 5.1K R80 2 1 2 1 2 5.1K R84 TMS2 1 R87 TDI2 1 5.1K 5.1K R81 R75 +3.3V 2 1 TRST2_L 2 2 +3.3V R78 +3.3V +3.3V
U14
U15
U12
1
R79
2
TCK0
5.1K
4
4
INTB_L INTD_L
INTD_L INTB_L
RESET_L CLK1 GNT0_L REQ1_L AD30 AD28 AD26 AD24 IDSEL2_L AD22 AD20 AD18 AD16 FRAME_L IRDY_L TRDY_L DEVSEL_L STOP_L SDONE2 SBO2_ L SERR_L AD15 AD13 AD11 AD9 C/BE0 AD6 AD4 AD2 AD0 REQ64#2 C321 0.01uF PAR LOCK_L PERR_L REQ2_L REQ3_L GNT1_L GNT2_L CLK2 CLK3
RESET_L
RESET_L
RESET_L GNT3_L
CLK0
REQ0_L
IDSEL0_L
IDSEL1_L
IDSEL3_L
FRAME_L IRDY_L TRDY_L DEVSEL_L STOP_ L LOCK_L PERR_L SERR_L PAR PAR SERR_L LOCK_L PERR_L STOP_ L DEVSEL_L TRDY_L IRDY_L
FRAME_L
FRAME_L TRDY_L STOP_ L
IRDY_L
DEVSEL_L
LOCK_L PERR_L
3
SERR_L
PAR
3
C258 0.01uF
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C252 B11 0.01uF B12 C255 B13 0.01uFB14 B15 B16 B17 B18 B19 B20 AD31 B21 AD29 B22 B23 AD27 B24 AD25 B25 B26 C/BE3 B27 AD23 B28 B29 AD21 B30 AD19 B31 B32 AD17 B33 C/BE2 B34 B35 B36 B37 B38 B39 B40 B41 B42 SERR_L B43 B44 C/BE1 B45 AD14 B46 B47 AD12 B48 AD10 B49 M66EN B50 B51 B52 AD8 B53 AD7 B54 B55 AD5 B56 AD3 B57 B58 AD1 B59 B60 ACK64#0 B61 B62 C259 0.01uF -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# NC PRSNT2# GND GND NC GND CLK GND REQ# +5V AD31 AD29 GND AD27 AD25 +3.3V C/BE3# AD23 GND AD21 AD19 +3.3V AD17 C/BE2# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 GND AD12 AD10 M66EN NC NC AD08 AD07 +3.3V AD05 AD03 GND AD01 +5V ACK64# +5V +5V C260 0.01uF PCISLOT PCISLOT PCISLOT TRST# +12V TMS TDI +5V INTA# INTC# +5V NC +5V NC GND GND NC RST# +5V GNT# GND NC AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3V AD22 AD20 GND AD18 AD16 +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD15 +3.3V AD13 AD11 GND AD09 NC NC C/BE0# +3.3V AD06 AD04 GND AD02 AD00 +5V REQ64# +5V +5V -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# NC PRSNT2# GND GND NC GND CLK GND REQ# +5V AD31 AD29 GND AD27 AD25 +3.3V C/BE3# AD23 GND AD21 AD19 +3.3V AD17 C/BE2# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 GND AD12 AD10 M66EN NC NC AD08 AD07 +3.3V AD05 AD03 GND AD01 +5V ACK64# +5V +5V TRST# +12V TMS TDI +5V INTA# INTC# +5V NC +5V NC GND GND NC RST# +5V GNT# GND NC AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3V AD22 AD20 GND AD18 AD16 +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD15 +3.3V AD13 AD11 GND AD09 NC NC C/BE0# +3.3V AD06 AD04 GND AD02 AD00 +5V REQ64# +5V +5V -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# NC PRSNT2# GND GND NC GND CLK GND REQ# +5V AD31 AD29 GND AD27 AD25 +3.3V C/BE3# AD23 GND AD21 AD19 +3.3V AD17 C/BE2# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 GND AD12 AD10 M66EN NC NC AD08 AD07 +3.3V AD05 AD03 GND AD01 +5V ACK64# +5V +5V TRST# +12V TMS TDI +5V INTA# INTC# +5V NC +5V NC GND GND NC RST# +5V GNT# GND NC AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3V AD22 AD20 GND AD18 AD16 +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD15 +3.3V AD13 AD11 GND AD09 NC NC C/BE0# +3.3V AD06 AD04 GND AD02 AD00 +5V REQ64# +5V +5V
-12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# NC PRSNT2# GND GND NC GND CLK GND REQ# +5V AD31 AD29 GND AD27 AD25 +3.3V C/BE3# AD23 GND AD21 AD19 +3.3V AD17 C/BE2# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 GND AD12 AD10 M66EN NC NC AD08 AD07 +3.3V AD05 AD03 GND AD01 +5V ACK64# +5V +5V
TRST# +12V TMS TDI +5V INTA# INTC# +5V NC +5V NC GND GND NC RST# +5V GNT# GND NC AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3V AD22 AD20 GND AD18 AD16 +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD15 +3.3V AD13 AD11 GND AD09 NC NC C/BE0# +3.3V AD06 AD04 GND AD02 AD00 +5V REQ64# +5V +5V
R76 A1 1 TRST0_L 5.1K A2 R82 A3 TMS0 1 R85 1 5.1K A4 TDI0 5.1K A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 AD30 A21 A22 AD28 A23 AD26 A24 A25 AD24 A26 A27 A28 AD22 A29 AD20 A30 A31 AD18 A32 AD16 A33 A34 A35 A36 A37 A38 A39 A40 SDONE0 A41 SBO0_ L A42 A43 A44 AD15 A45 A46 AD13 A47 AD11 A48 A49 AD9 A50 A51 A52 C/BE0 A53 A54 AD6 A55 AD4 A56 A57 AD2 A58 AD0 A59 A60 REQ64#0 A61 A62 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C253 B11 0.01uF B12 C256 B13 0.01uFB14 B15 B16 B17 B18 B19 B20 AD31 B21 AD29 B22 B23 AD27 B24 AD25 B25 B26 C/BE3 B27 AD23 B28 B29 AD21 B30 AD19 B31 B32 AD17 B33 C/BE2 B34 B35 B36 B37 B38 B39 B40 B41 B42 SERR_L B43 B44 C/BE1 B45 AD14 B46 B47 AD12 B48 AD10 B49 M66EN B50 B51 B52 AD8 B53 AD7 B54 B55 AD5 AD3 B56 B57 AD1 B58 B59 B60 ACK64#1 B61 B62 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C254 B11 0.01uF B12 C257 B13 0.01uFB14 B15 B16 B17 B18 B19 B20 AD31 B21 AD29 B22 B23 AD27 B24 AD25 B25 B26 C/BE3 B27 AD23 B28 B29 AD21 B30 AD19 B31 B32 AD17 B33 C/BE2 B34 B35 B36 B37 B38 B39 B40 B41 B42 SERR_L B43 B44 C/BE1 B45 AD14 B46 B47 AD12 B48 AD10 B49 M66EN B50 B51 B52 AD8 B53 AD7 B54 B55 AD5 B56 AD3 B57 B58 AD1 B59 B60 ACK64#2 B61 B62 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C330 B11 0.01uF B12 C331 B13 0.01uFB14 B15 B16 B17 B18 B19 B20 AD31 B21 AD29 B22 B23 AD27 B24 AD25 B25 B26 C/BE3 B27 AD23 B28 B29 AD21 B30 AD19 B31 B32 AD17 B33 C/BE2 B34 B35 B36 B37 B38 B39 B40 B41 B42 SERR_L B43 B44 C/BE1 B45 AD14 B46 B47 AD12 B48 AD10 B49 M66EN B50 B51 B52 AD8 B53 AD7 B54 B55 AD5 B56 AD3 B57 B58 AD1 B59 B60 ACK64#3 B61 B62
R77 A1 1 TRST1_L 5.1K A2 R83 A3 TMS1 1 R86 1 5.1K A4 TDI1 5.1K A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 AD30 A21 A22 AD28 A23 AD26 A24 A25 AD24 A26 A27 A28 AD22 A29 AD20 A30 A31 AD18 A32 AD16 A33 A34 A35 A36 A37 A38 A39 A40 SDONE1 A41 SBO1_ L A42 A43 A44 AD15 A45 AD13 A46 A47 AD11 A48 A49 AD9 A50 A51 A52 C/BE0 A53 A54 AD6 A55 AD4 A56 A57 AD2 A58 AD0 A59 A60 REQ64#1 A61 A62
R89 A1 TRST3_L 1 5.1K A2 R90 A3 TMS3 1 R88 A4 TDI3 1 5.1K 5.1K A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 AD30 A21 A22 AD28 A23 AD26 A24 A25 AD24 A26 A27 A28 AD22 A29 AD20 A30 A31 AD18 A32 AD16 A33 A34 A35 A36 A37 A38 A39 A40 SDONE3 A41 SBO3_ L A42 A43 A44 AD15 A45 A46 AD13 A47 AD11 A48 A49 AD9 A50 A51 A52 C/BE0 A53 A54 AD6 A55 AD4 A56 A57 AD2 A58 AD0 A59 A60 REQ64#3 A61 A62
ADVANCE INFORMATION
65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
C/BE[3:0] C/BE[3:0] 1 SDONE0 5.1K 2 SDONE1 5.1K 2 SDONE2 5.1K 2 SDONE3 5.1K -12V +3.3V 5.1K +5V 1 R113 2 SBO3_ L 1 2 R114 5.1K STOP_ L 1 1 R107 2 SBO2_ L 1 2 R108 5.1K SERR_L 1 PERR_L 1 R101 2 SBO1_ L 1 2 1 R102 5.1K 5.1K R103 2 5.1K R109 2 5.1K R115 2 5.1K DEVSEL_L 1 IRDY_L 1 TRDY_L 1 SBO0_ L LOCK_L 5.1K R93 2 1 2 1 2 1 2 +3.3V R94 R95 R96 +3.3V +3.3V +3.3V FRAME_L 1 R97 +3.3V 2 5.1K R104 2 5.1K R110 2 5.1K R116 2 5.1K
2
C-6
AD[31:0] +3.3V 2 REQ64#0 2 REQ64#1 5.1K 2 REQ64#2 5.1K 2 REQ64#3 5.1K +12V 1 R112 1 R106 1 R100 C266 0.01uF C267 0.01uF C268 0.01uF C269 0.01uF C270 0.01uF C271 0.01uF C272 0.01uF C275 0.01uF C276 0.01uF C277 0.01uF C80 0.01uF C81 0.01uF +3.3V +5V C291 0.1uF C292 0.1uF C293 0.1uF C294 0.1uF C295 0.1uF C298 0.1uF C299 0.1uF C300 0.1uF C82 0.1uF C83 0.1uF +3.3V +5V C316 0.01uF C317 0.01uF C318 0.01uF C319 0.01uF C320 0.01uF C323 0.01uF C324 0.01uF C325 0.01uF C84 0.01uF C85 0.01uF
B C
PCISLOT
AD[31:0]
M66EN
ACK64#0
1
R92
2
M66EN
5.1K
ACK64#1
1
R99
5.1K
ACK64#2
1
R105
5.1K
ACK64#3
1
R111
5.1K
+3.3V
+5V
+
C229 10uF
+
C263 10uF
+5V
+12V
-12V
+
C287 10uF
C289 0.01uF
C290 0.01uF
1
1
+3.3V
+5V
+12V
-12V
+
C284 10uF
+
C311 10uF
C314 0.01uF
C315 0.01uF
2380 Bering Dr., San Jose, CA
Title
Three Port PCI Bridge Evaluation Board
Size C Date:
D
Document Number PI7C7100
Secondary 2 PCI Bus
Friday, March 17, 2000
E
Rev 1.3 Sheet 4 of 5
Appendix C PI7C7100 3-Port PCI Bridge
04/18/00
A
A
B
C
D
E
Edge S1_AD[31:0] S1_AD20 S2_AD20 U17 TCK TMS TDI TDO TRST_L CLK S1_AD21 S2_AD21 S2_IDSEL1_L S1_IDSEL1_L P_CLK Test Point T RESET_L SERR_L PERR_L PAR REQ_L GNT_L 2 R199 5.1K INTD_L INTC_L INTB_L INTA_L INTD_L INTC_L INTB_L INTA_L 1 S1_AD23 S1_IDSEL3_L S2_AD23 S2_IDSEL3_L IDSEL_L LOCK_L STOP_ L DVSEL_L TRDY_L IRDY_L FRAME_L C/BE[3:0] AD[31:0] S1_AD22 S1_IDSEL2_L S2_AD22 S2_IDSEL2_L
4
S2_AD[31:0] S1_IDSEL0_L S2_IDSEL0_L
P_M66EN M66EN
TCK TMS TDI TDO TRST_L
P_RESET_L
P_SERR_L P_PERR_L P_PAR_L
4
P_REQ_L P_GNT_L
P_IDSEL_L P_LOCK_L P_STOP_ L P_DEVSEL_L P_TRDY_L P_IRDY_L P_FRAME_L P_C/BE[3:0] P_AD[31:0]
PCIEDGE S1_INTERFACE 1 1 1 1 1 22 R171 2 SCLKOUT6 22 22 R170 2 SCLKOUT5 22 R169 2 SCLKOUT4 22 R146 2 SCLKOUT3 22 R145 2 SCLKOUT2 S1_IDSEL0_L S1_IDSEL1_L S1_IDSEL2_L S1_IDSEL3_L S1_C/BE[3:0] S1_FRAME_L S1_IRDY_L S1_TRDY_L S1_DEVSEL_ L S1_STOP _L S1_LOCK_L 1 AD[31:0] IDSEL0_L IDSEL1_L IDSEL2_L IDSEL3_L C/BE[3:0] FRAME_L IRDY_L TRDY_L DEVSEL_L STOP_ L LOCK_L PAR PERR_L SERR_L RESET_L 22
3
1 CLK0 CLK1 CLK2 CLK3 SCLKOUT0/4 SCLKOUT1/5 SCLKOUT2/6 SCLKOUT3/7 22 R144 2 SCLKOUT1
R143 2 SCLKOUT0
CHIP PLL_PCLK PLL_SCLK SCLKOUT[15:0] S1_RESET_ L S1_GNTN0/4 S1_GNTN1/5 S1_GNTN2/6 S1_GNTN3/7 GNT0_L GNT1_L GNT2_L GNT3_L 1 2 SCLKOUT7 S_CLK SCLKOUT[15:0] R172 S1_PAR_L S1_PERR_L S1_SERR_L
3
P_AD[31:0] P_C/BE[3:0] P_FRAME_L P_IRDY_L P_TRDY_L P_DEVSEL_L P_STOP_ L P_LOCK_L P_IDSEL_L P_AD[31:0] P_CBE[3:0] P_FRAMEN P_IRDYN P_TRDYN P_DEVSELN P_STOPN P_LOCKN P_IDSEL P_GNTN P_REQN 1 1 1 22 1 1 1 22 S2_INTERFACE M66EN 1 SCLKOUT8/12 SCLKOUT9/13 SCLKOUT10/14 SCLKOUT11/15 1 R175 22 2 SCLKOUT14 22 R174 22 R152 R149 2 SCLKOUT9 2 SCLKOUT11 2 SCLKOUT13 22 R173 2 SCLKOUT12 22 R151 2 SCLKOUT10 R147 2 SCLKOUT8 S1_AD[31:0] S1_CBE[3:0] S1_FRAMEN S1_IRDYN S1_TRDYN S1_DEVSELN S1_STOPN S1_LOCKN S1_REQN0/4 S1_REQN1/5 S1_REQN2/6 S1_REQN3/7 REQ0_L REQ1_L REQ2_L REQ3_L S1_PAR S1_PERRN S1_SERRN S1_RESETN S1_GNTN[7:0] S1_REQN[7:0] 1 5.1K S_M66EN P_M66EN S_M66EN PCIBUS R49 2 +3.3V TRST_L TDO TDI TMS TCK S1_GNTN[7:0] S1_REQN[7:0] M66EN S1_RESET_ L INTA_L INTB_L INTC_L INTD_L INTA_L INTB_L INTC_L INTD_L S1_PAR_L S1_PERR_L S1_SERR_L S1_AD[31:0] S1_C/BE[3:0] S1_FRAME_L S1_IRDY_L S1_TRDY_L S1_DEVSEL_ L S1_STOP _L S1_LOCK_L
P_GNT_L P_REQ_L
P_PAR_L P_PERR_L P_SERR_L P_PAR P_PERRN P_SERRN P_RESETN
+3.3V +5V P1 1 2 3 4 5 6 HEADER 6
P_RESET_L
TRST_L TDO TDI TMS TCK
ADVANCE INFORMATION
765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
S2_AD[31:0] S2_C/BE[3:0] S2_FRAME_L S2_IRDY_L S2_TRDY_L S2_DEVSEL_ L S2_STOP _L S2_LOCK_L CLK0 CLK1 CLK2 CLK3 S2_PAR_L S2_PERR_L S2_SERR_L S2_RESET_L S2_GNTN[7:0] S2_REQN[7:0] S2_PAR_L S2_PERR_L S2_SERR_L PAR PERR_L SERR_L RESET_L S1_GNTN0/4 S1_GNTN1/5 S1_GNTN2/6 S1_GNTN3/7 1 1 1 1 T T T T U22 1header U23 1header U24 1header U25 1header S2_GNTN0/4 S2_GNTN1/5 S2_GNTN2/6 S2_GNTN3/7 REQ0_L REQ1_L REQ2_L REQ3_L INTA_L INTB_L INTC_L INTD_L S1_REQN0/4 S1_REQN1/5 S1_REQN2/6 S1_REQN3/7 1 1 1 1 T T T T PCIBUS2 U26 1header U27 1header U28 1header U29 1header 1 1 1 1 T T T T U30 1header U31 1header U32 1header U33 1header S2_RESET_L R176 22 2 SCLKOUT15 S2_IDSEL0_L S2_IDSEL1_L S2_IDSEL2_L S2_IDSEL3_L S2_C/BE[3:0] S2_FRAME_L S2_IRDY_L S2_TRDY_L S2_DEVSEL_L S2_STOP _L S2_LOCK_L AD[31:0] IDSEL0_L IDSEL1_L IDSEL2_L IDSEL3_L C/BE[3:0] FRAME_L IRDY_L TRDY_L DEVSEL_L STOP_ L LOCK_L
2
C-7
S2_AD[31:0] S2_CBE[3:0] S2_FRAMEN S2_IRDYN S2_TRDYN S2_DEVSELN S2_STOPN S2_LOCKN PLL_CAP1 S2_PAR S2_PERRN S2_SERRN S2_RESETN PLL_CAP2 S2_GNTN[7:0] S2_REQN[7:0] S2_GNTN0/4 S2_GNTN1/5 S2_GNTN2/6 S2_GNTN3/7 GNT0_L GNT1_L GNT2_L GNT3_L S2_REQN0/4 S2_REQN1/5 S2_REQN2/6 S2_REQN3/7 INTA_L INTB_L INTC_L INTD_L S1_REQN[7:0] S1_REQN7 S1_REQN3/7 S2_GNTN7 S2_GNTN[7:0] S2_GNTN3/7 S2_REQN[7:0] S2_REQN7 S2_REQN3/7 S1_REQN6 S1_REQN2/6 S2_GNTN6 S2_GNTN2/6 S2_REQN6 S2_REQN2/6 S1_GNTN1/5 S1_REQN3 1 S1_REQN1 1 0 0 R183 2 0 R181 2 S1_REQN5 1 S1_REQN1/5 R162 2 S2_GNTN5 1 S2_GNTN3 1 S2_GNTN1 1 R163 0 R185 0 R187 0 2 2 2 S2_GNTN1/5 S2_REQN5 1 S2_REQN3 1 S2_REQN1 1 R164 0 R189 0 R191 0 2 2 2 S2_REQN1/5 S1_GNTN0/4 S1_REQN2 1 S1_REQN0 1 0 0 R184 2 0 R182 2 S1_REQN4 1 2 R166 S1_REQN0/4 S2_GNTN4 1 S2_GNTN2 1 S2_GNTN0 1 R167 0 R186 0 R188 0 2 2 2 S2_GNTN0/4 S2_REQN4 1 S2_REQN2 1 S2_REQN0 1 R168 0 R190 0 R192 0 2 2 2 S2_REQN0/4
B C
P_M66EN
PLL_CAP1
R148 4.7k
PLL_CAP2
2
C349 47p
C350 100p
R150 4.7k
PCICHIP
C351 100p
C352 47p
Note: Those AGNDs are only connected to a small GND plane on the top signal layer
U19
Test Point T
S2_REQN0/4 S2_REQN1/5 S2_REQN2/6 S2_REQN3/7
1 1 1 1
S1_GNTN[7:0]
T T T T
U34 1header U35 1header U36 1header U37 1header
S1_GNTN7
S1_GNTN3/7
S1_GNTN6
S1_GNTN2/6
U20 Test Point T
1
1
S1_GNTN5 1
R161
2
S1_GNTN3 1
0 R177
2
S1_GNTN1 1
0 R179
2
0
S1_GNTN4 1
R165
2
S1_GNTN2 1
0 R178
2380 Bering Dr., San Jose, CA
Title
2
S1_GNTN0 1
0 R180
2
Three Port PCI Bridge Evaluation Board
Size C Date:
D
0
Document Number PI7C7100
Top View
Friday, March 17, 2000
E
Rev 1.3 Sheet 5 of 5
Appendix C PI7C7100 3-Port PCI Bridge
A
04/18/00
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ADVANCE INFORMATION
C-8
Appendix C PI7C7100 3-Port PCI Bridge
04/18/00
765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
ADVANCE INFORMATION
Representatives & Distributors
Appendix D
PI7C7100 3-Port PCI Bridge
D1
PI7C7100 3-Port PCI Bridge
09/18/00 Rev 1.1
ADVANCE INFORMATION
65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
Pericom Corporate Offices
Corporate Headquarters Pericom Semiconductor Corp. 2380 Bering Drive, San Jose, CA 95131-USA 1-800 435-2336 408 435-0800 408 435 1100 Fax nolimits@pericom.com Northern California, Western USA & British Columbia Pericom Semiconductor Corp. 2380 Bering Drive, San Jose, CA 95131-USA 1-800 435-2336 408 435-0800 408 435 1100 Fax rgorshe@pericom.com Southern California-USA Pericom Semiconductor Corp. 3455 Lebon Street, Suite 1536 San Diego, CA 92212-USA 858 558-6975 858 558 6685 Fax nsoo@pericom.com North Central & South Central USA Pericom Semiconductor Corp. 5068 West Plano Parkway, Suite 300 Plano, TX 75093-USA 972 381-4209 972 381 4208 mmorse@pericom.com Mid Atlantic and South East USA Pericom Semiconductor Corp 1143-B Executive Circle Cary, NC 27511-USA 919 460-3177 919 460 3179 Fax mward@pericom.com North East and Mid and Eastern Canada Pericom Semiconductor Corp Radnor Station Building #2 290 King of Prussia Road, Suite 104 Radnor, PA 19087 610.293.7400 610.293.7410 Fax gfrancisco@pericom.com Europe Pericom Semiconductor Corp. The Enterprise Center 1-2 Davy Road Gorse Lane Industrial Center Clacton On Sea, Essex, UK CO15 4XD 44 1255 479994 44 1255 223676 Fax johara@pericom.com China - Peoples Republic of China Pericom Technology Inc. 481 Gui Ping Road 3F, Building 20 Shanghai, 200233 86 21 6485 0576 86 21 6485 2181 Fax afock@pericom.com Hong Kong Pericom Technology Inc. 8 Wang Hoi Road, Unit 1517 Chevalier Commercial Center Kowloon Bay, Hong Kong 852 2243 3660 852 2243 3667 Fax qshuai@pti.com.cn Taiwan R.O.C. Pericom Semiconductor Corp. 11F, No. 18, Alley 1, Lane 768, Sec 4 Pa Te Road Taipei, Taiwan - R.O.C. 886 2 2651 5159 886 2 2653 0041 Fax mchiang@pericom.com Singapore Pericom Semiconductor Corp. 42 Mactaggart Road #04-01 Mactaggart Building Singapore 368086 65 287 9705 65 287 9706 Fax tctee@postone.com Japan Pericom Semiconductor Corp. Yamamasa Daiichi Building 5, 2-11-3 Kobuchi Sagamihara-shi, Kanagawa 229-0004-Japan 81 427 86 7266 81 427 86 7267 Fax ksato@pericom.com
D2
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ADVANCE INFORMATION
765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
North America Distributors
Company Name Street Address All American ................................... 4950 Corporate Drive, Suite 115D ............................................. Future ............................................. 6767 Old Madison Pike, Suite 400A ........................................... Nu Horizons ................................... 4825 University Square, Suite 8 ................................................ Pioneer-Standard Electronics .......... 4910 University Square, Suite 7 ................................................ FAI ................................................. 11219 Financial Centre Parkway, Financial Park Place, Ste 311 .. All American ................................... 4636 East University Drive, Suite 155 ........................................ Bell Microproducts .......................... 4926 East McDowell Road, Suite 102 ........................................ FAI ................................................. 4636 East University Drive, Suite 145 ........................................ Future ............................................. 4636 East University Drive, Suite 245 ........................................ Nu Horizons ................................... 1295 West Washington Street, Suite 212 ................................... Pioneer-Standard Electronics .......... 4908 East McDowell Road, Suite 103 ........................................ Aegis Electronics Group .................. 1015 Chestnut Avenue, Suite G2 ............................................... All American ................................... 10805 Holder Street, Suite 100 .................................................. All American ................................... 14192 Chambers Road ............................................................. All American ................................... 1545 East Acequia, Suite A ....................................................... All American ................................... 230 Devcon Drive ..................................................................... All American ................................... 26010 Mureau Road, Suite 120 ................................................. All American ................................... 6390 Greenwich Drive, Suite 170 ............................................... Bell Microproducts .......................... 1921 Ringwood Avenue ............................................................. Bell Microproducts .......................... 30 Fairbanks, Suite 114 ............................................................ Bell Microproducts .......................... 5090 Shoreham Place, Suite 206 ............................................... Bell Microproducts .......................... 29800 West Agoura Road, Suite 150 ......................................... FAI ................................................. 354 Bel Marin Keys Blvd., Suite D ............................................. FAI ................................................. 525 South Douglas Street ......................................................... FAI ................................................. 2220 O'Toole Ave. .................................................................... FAI ................................................. 6256 Greenwich Drive, Suite 200 .............................................. FAI ................................................. 25B Technology Drive, Suite 200 .............................................. FAI ................................................. 26570 Agoura Road ................................................................. FAI ................................................. 3009 Douglas Blvd., Suite 215 .................................................. FAI ................................................. 1370 Valley Vista Drive, Suite 265 ............................................. FAI ................................................. 2121 41st Avenue ..................................................................... Future ............................................. 2220 O'Toole Ave. .................................................................... Future ............................................. 26570 Agoura Road ................................................................. Future ............................................. 25B Technology Drive, Suite 200 .............................................. Future ............................................. 27489 West Agoura Road, Suite 300 ......................................... Future ............................................. 3009 Douglas Blvd., Suite 210 .................................................. Future ............................................. 5990 Stoneridge Drive .............................................................. Future ............................................. 6256 Greenwich Drive, Suite 200 .............................................. Nu Horizons ................................... 1220 Melody Lane, Suite 110 .................................................... Nu Horizons ................................... 13900 Alton Parkway, Suite 123 ................................................. Nu Horizons ................................... 2070 Ringwood Avenue ............................................................ Nu Horizons ................................... 4360 View Ridge Avenue, Suite B ............................................. Nu Horizons ................................... 850 Hampshire Road, Suite R .................................................. Pioneer-Standard Electronics .......... 217 Technology Drive, Suite 110 ............................................... Pioneer-Standard Electronics .......... 333 River Oaks Pkwy. ............................................................... Pioneer-Standard Electronics .......... 5126 Clareton Drive, Suite 100 ................................................. Pioneer-Standard Electronics .......... 9449 Balboa Ave., Suite 114 ...................................................... Pioneer-Standard Electronics .......... 431 Dixon Landing Road .......................................................... All American ................................... 7577 West 103rd Avenue, Suite 204 .......................................... All American ................................... 4090 Youngfield Street ............................................................. Bell Microproducts .......................... 4600 South Ulster Street, Suite 240 .......................................... Future ............................................. 1819 Denver West Drive, Bldg. 26, Suite 350 ............................ Pioneer-Standard Electronics .......... 5600 Greenwood Plaza Blvd. Suite 200 ..................................... All American ................................... 100 Mill Plain Road, Suite 360 .................................................. All American ................................... 83 Papermill Road ................................................................... Future ............................................. 700 West Johnson Avenue, Westgate Office Center .................. Pioneer-Standard Electronics .......... Two Trap Falls Road, Suite 100 ............................................... All American ................................... 600 Fairway Drive, Suite 101 .................................................... All American ................................... 528 South North Lake Blvd., Suite 1040 ..................................... All American ................................... 14450 46th Street North, Suite 116 ............................................ All American ................................... 16115 NW 52nd Avenue ............................................................ Bell Microproducts .......................... 17431 SW 18th Street ............................................................... Bell Microproducts .......................... 1110 Douglas Avenue, Suite 1018 ............................................. Bell Microproducts .......................... 1761 West Hillsboro Blvd., Suite 208 ......................................... Edge Electronics ............................. 100 Second Avenue South, Suite 200 ......................................... FAI ................................................. 525 Technology Park, Suites 125/126 ........................................ FAI ................................................. 348 SW Miracle Strip Pkwy., Suite 33 ........................................ FAI ................................................. 2200 Tall Pines Drive, Suite 109 ............................................... Future ............................................. 1400 East Newport Center Drive, Suite 200 ............................... Future ............................................. 237 South Westmonte Drive, Suite 307 ...................................... Future ............................................. 2200 Tall Pines Drive, Suite 108 ............................................... Nu Horizons ................................... 3421 N.W. 55th Street .............................................................. Nu Horizons ................................... 4500 140th Avenue North, Suites 214/215 .................................. Nu Horizons ................................... 600 South North Lake Blvd., Suite 210 ....................................... Pioneer-Standard Electronics .......... 337 South North Lake, Suite 1000 .............................................. Pioneer-Standard Electronics .......... 674 South Military Trail ............................................................ City State Zip Code Country Telephone Huntsville .................. AL ............. 35805 ............. USA ....... 800 382-5303 ....... Huntsville .................. AL ............. 35806 ............. USA ....... 256-971-2010 ...... Huntsville .................. AL ............. 35816 ............. USA ....... 256-722-9330 ...... Huntsville .................. AL ............. 35816 ............. USA ....... 256 837-9300 ....... Little Rock .................. AR ............ 72211 ............. USA ....... 501-219-1707 ...... Phoenix ...................... AZ ............ 85034 ............. USA ....... 480-966-0006 ...... Phoenix ...................... AZ ............ 85008 ............. USA ....... 602-267-9551 ...... Phoenix ...................... AZ ............ 85034 ............. USA ....... 480-731-4661 ...... Phoenix ...................... AZ ............ 85034 ............. USA ....... 602-968-7140 ...... Tempe ....................... AZ ............ 85281 ............. USA ....... 602 685-9000 ....... Phoenix ...................... AZ ............ 85008 ............. USA ....... 602-231-6400 ...... Carlsbad ................... CA ............ 92208 ............. USA ....... 760 729-2026 ....... Cypress ..................... CA ............ 90630 ............. USA ....... 714 229-8600 ....... Tustin ........................ CA ............ 92680 ............. USA ....... 714 573-5000 ....... Visalia ....................... CA ............ 93292 ............. USA ....... 209 734-8861 ....... San Jose ................... CA ............ 95112 ............. USA ....... 800-222-6001 ...... Calabasas ................. CA ............ 91302 ............. USA ....... 818 878-0555 ....... San Diego ................. CA ............ 92122 ............. USA ....... 800-382-3441 ...... San Jose ................... CA ............ 95131-1721 .... USA ....... 408 451-9400 ....... Irvine ......................... CA ............ 92618 ............. USA ....... 949 470-2900 ....... San Diego ................. CA ............ 92121 ............. USA ....... 858 597-3010 ....... Agoura Hills .............. CA ............ 91301 ............. USA ....... 818 865-0266 ....... Novato ....................... CA ............ 94949 ............. USA ....... 415 883-9446 ....... El Segundo ................ CA ............ 90245 ............. USA ....... 310 727-1754 ....... San Jose ................... CA ............ 95131 ............. USA ....... 408 434-0369 ....... San Diego ................. CA ............ 92122 ............. USA ....... 858-623-5859 ...... Irvine ......................... CA ............ 92618 ............. USA ....... 949-753-4778 ...... Calabasas ................. CA ............ 91302 ............. USA ....... 818 871-1700 ....... Roseville ................... CA ............ 95661 ............. USA ....... 916-782-7882 ...... Diamond Bar ............. CA ............ 91765 ............. USA ....... 909 612-0667 ....... Capitola ..................... CA ............ 95010 ............. USA ....... 831 465-7373 ....... San Jose ................... CA ............ 95131 ............. USA ....... 408 434-1122 ....... Calabasas ................. CA ............ 91302 ............. USA ....... 818 871-1740 ....... Irvine ......................... CA ............ 92618 ............. USA ....... 949-453-1515 ...... Agoura Hills .............. CA ............ 91301 ............. USA ....... 818 865-0040 ....... Roseville ................... CA ............ 95661 ............. USA ....... 916 783-7877 ....... Pleasanton ................. CA ............ 94588 ............. USA ....... 925 225-0294 ....... San Diego ................. CA ............ 92122 ............. USA ....... 858-625-2800 ...... Roseville ................... CA ............ 95678 ............. USA ....... 916 783-5500 ....... Irvine ......................... CA ............ 92718 ............. USA ....... 949 470-1011 ....... San Jose ................... CA ............ 95131 ............. USA ....... 408 434-0800 ....... San Diego ................. CA ............ 92123 ............. USA ....... 619 576-0088 ....... Thousand Oaks .......... CA ............ 91361 ............. USA ....... 805 370-1515 ....... Irvine ......................... CA ............ 92618 ............. USA ....... 949-753-5090 ...... San Jose ................... CA ............ 95134 ............. USA ....... 408 954-9100 ....... Agoura Hills .............. CA ............ 91301 ............. USA ....... 818 865-5800 ....... San Diego ................. CA ............ 92123 ............. USA ....... 858-514-7700 ...... Milpitas ..................... CA ............ 95035 ............. USA ....... 408 586-5600 ....... Westminster .............. CO ............ 80021 ............. USA ....... 303-222-0100 ...... Wheat Ridge ............. CO ............ 80033 ............. USA ....... 303 422-1701 ....... Denver ....................... CO ............ 80237 ............. USA ....... 303-846-3065 ...... Golden ....................... CO ............ 80401 ............. USA ....... 303 277-0023 ....... Englewood ................. CO ............ 80111 ............. USA ....... 303 773-8090 ....... Danbury ..................... CT ............ 06811 ............. USA ....... 203 791-3818 ....... Woodbury .................. CT ............ 6798 ............... USA ....... 203-266-0486 ...... Cheshire ................... CT ............ 06410 ............. USA ....... 203 250-0083 ....... Shelton ...................... CT ............ 06484 ............. USA ....... 203-929-5600 ...... Deerfield Beach ......... FL ............. 33441 ............. USA ....... 954 429-2800 ....... Altamonte Springs ..... FL ............. 32701 ............. USA ....... 407 261-1304 ....... Clearwater ................. FL ............. 33762 ............. USA ....... 813 532-9800 ....... Miami ........................ FL ............. 33014 ............. USA ....... 305 621-8282 ....... Miramar .................... FL ............. 33029 ............. USA ....... 954-450-1850 ...... Altamonte Springs ..... FL ............. 32714 ............. USA ....... 407 682-1199 ....... Deerfield Beach ......... FL ............. 33442 ............. USA ....... 954 429-1001 ....... St. Petersburg ........... FL ............. 33701 ............. USA ....... 727-894-3343 ...... Lake Mary .................. FL ............. 32746 ............. USA ....... 407 333-3177 ....... Fort Walton Beach ..... FL ............. 32548 ............. USA ....... 850 301-0766 ....... Largo ........................ FL ............. 34641 ............. USA ....... 727-530-1665 ...... Deerfield Beach ......... FL ............. 33442 ............. USA ....... 954 428-9494 ....... Altamonte Springs ..... FL ............. 32714 ............. USA ....... 407 444-6302 ....... Largo ........................ FL ............. 33771 ............. USA ....... 727-530-1222 ...... Ft. Lauderdale ............ FL ............. 33309 ............. USA ....... 954 735-2555 ....... Clearwater ................. FL ............. 33762 ............. USA ....... 727-536-5700 ...... Altamonte Springs ..... FL ............. 32701 ............. USA ....... 407 831-8008 ....... Alamonte Springs ...... FL ............. 32701 ............. USA ....... 407 834-9090 ....... Deerfield Beech ......... FL ............. 33442 ............. USA ....... 954 428-8877 ....... Fax Number 256-837-7733 256-922-0004 256-722-9348 256-837-9385 501-219-1747 480-966-0007 602-267-8911 480-731-9866 602-968-0334 602-685-9004 602-321-8877 714-229-8603 714-573-5047 408-437-8970 818-878-0533 619-658-0201 408-467-2734 949-470-2929 858-597-3015 818-865-0215 415-883-8336 310-727-1796 408-433-9599 858-623-5860 949-753-4778 818-871-1726 916-782-9388 909-612-0167 831-465-7299 408-433-0822 818-871-1764 949-453-1226 916-783-7988 925 225-9745 858-625-2810 916-783-3066 949-470-1104 408-434-0935 619-576-0990 805-370-1525 949-753-5074 818-865-5814 858-514-7799 408-586-5785 303-222-0110 303-846-3064 303-277-0722 303-773-8194 same 203-250-0081 203-929-9791 954-429-0391 407-261-1330 813-538-5567 305-620-7831 954-450-0223 407-682-1286 727-823-9030 407-333-3277 850-301-0773 727-530-7609 954-428-9477 407-444-6303 727-538-9598 954-735-2880 727-536-7799 407-931-8862 407-834-0865 954-481-2950
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ADVANCE INFORMATION
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PI7C7100 3-Port PCI Bridge
North America Distributors (continued)
Company Name Street Address City State Zip Code Country Telephone All American ................................... 6875 Jimmy Carter Blvd., Suite 3100 ......................................... Norcross ................... GA ............ 30071 ............. USA ....... 770 441-7500 ....... Bell Microproducts .......................... 1950 Spectrum Circle, Suite 400 ............................................... Marietta ..................... GA ............ 30067 ............. USA ....... 770-980-4922 ...... Future ............................................. 44000 River Green Parkway, Suite 220 ...................................... Duluth ....................... GA ............ 30096 ............. USA ....... 770 476-3900 ....... Future ............................................. 3150 Hocomb Bridge Rd. Holcolm Place, Suite 130 ................. Norcross ................... GA ............ 30071 ............. USA ....... 770 441-7676 ....... Nu Horizons ................................... 100 Pinnacle Way, Suite 155 ..................................................... Norcross ................... GA ............ 30071 ............. USA ....... 770 416-8666 ....... Pioneer-Standard Electronics .......... 4250-C Rivergreen Pkwy. ......................................................... Duluth ....................... GA ............ 30096 ............. USA ....... 770 623-1003 ....... FAI ................................................. 12438 West Bridger Street, Suite 110 ....................................... Boise ......................... ID ............. 83713 ............. USA ....... 208 376-8080 ....... All American ................................... 1930 North Thoreau Drive, Suite 200 ........................................ Schaumburg .............. IL .............. 60173 ............. USA ....... 847 303-1995 ....... Bell Microproducts .......................... 953 Plum Grove Road, Suite B .................................................. Schaumburg .............. IL .............. 60173 ............. USA ....... 847 413-8530 ....... FAI ................................................. 3100 West Higgins Road, Suite 115 ......................................... Hoffman Estates ........ IL .............. 60195 ............. USA ....... 847 843-0034 ....... Future ............................................. 3100 West Higgins Road, Suite 100 ......................................... Hoffman Estates ........ IL .............. 60195 ............. USA ....... 847 882-1255 ....... Nu Horizons ................................... Basswood Office Center, 500 East Remington Road, Suite 104 . Schaumburg .............. IL .............. 60173 ............. USA ....... 847 519-0700 ....... Pioneer-Standard Electronics .......... 2171 Executive Drive Suite 200 ................................................. Addison ..................... IL .............. 60101 ............. USA ....... 630 495-9680 ....... Future ............................................. 8520 Allison Pointe Blvd., Suite 310 .......................................... Indianapolis ............... IN ............. 46250 ............. USA ....... 317 913-1355 ....... Future ............................................. 8425 Woodfield Crossing, Suite 170 ......................................... Indianapolis ............... IN ............. 46240 ............. USA ....... 317 469-0447 ....... Pioneer-Standard Electronics .......... 237 Airport N. Office Park ......................................................... Fort Wayne ................ IN ............. 46285 ............. USA ....... 219 489-0283 ....... Pioneer-Standard Electronics .......... 9350 N. Priority Way W. Drive ................................................... Indianapolis ............... IN ............. 46240 ............. USA ....... 317 573-0880 ....... All American ................................... 7201 West 129th Street, Suite 150 ............................................. Overland Park ............ KS ............ 66213 ............. USA ....... 913 851 5900 ....... FAI ................................................. 10977 Granada Lane, Suite 210 ................................................ Overland Park ............ KS ............ 66211 ............. USA ....... 913 338-4400 ....... Pioneer-Standard Electronics .......... 8500 College Blvd., Suite 128 ................................................... Overland .................... KS ............ 66210 ............. USA ....... 913-338-7164 ...... All American ................................... 19-A Crosby Drive ................................................................... Bedford ...................... MA ............ 01730 ............. USA ....... 781-275-8888 ...... Bell Microproducts .......................... 2A Gill Street ........................................................................... Woburn ...................... MA ............ 1730 ............... USA ....... 781-933-9010 ...... Future ............................................. 41 Main Street ......................................................................... Bolton ........................ MA ............ 01740 ............. USA ....... 978 779-3000 ....... Interface Electronics ........................ 124 Grove Street, Suite 300 ...................................................... Franklin ..................... MA ............ 2038 ............... USA ....... 508-553-4200 ...... Interface Electronics ........................ 228 South Street ....................................................................... Hopkinton .................. MA ............ 1748 ............... USA ....... 508 435-0100 ....... Nu Horizons ................................... 2 Corporation Way, Suite 240 .................................................... Peabody ..................... MA ............ ,01960 ............ USA ....... 978 532-7666 ....... Pioneer-Standard Electronics .......... 299 Callardvale Street .............................................................. Wilmington ................ MA ............ ,01887 ............ USA ....... 978 988-6600 ....... All American ................................... 8310 Guilford Road, Suite A ..................................................... Columbia ................... MD ........... 21046 ............. USA ....... 410 309-6262 ....... Bell Microproducts .......................... 6925 R. Oakland Mills Road ..................................................... Columbia ................... MD ........... 21045 ............. USA ....... 410 720-5100 ....... Future ............................................. 857 Elkridge Landing Road, International Tower ....................... Linthicum ................... MD ........... 21090 ............. USA ....... 410 314-1111 ....... Future ............................................. 6716 Alexander Bell Drive, Suite 220 ......................................... Columbia ................... MD ........... 21046 ............. USA ....... 410 290-0600 ....... Nu Horizons ................................... 8965 Guilford Road, Suite 100 .................................................. Columbia ................... MD ........... 21046 ............. USA ....... 310-995-6330 ...... Pioneer-Standard Electronics .......... 9100 Gaither Road ................................................................... Gaithersburg ............. MD ........... 20877 ............. USA ....... 301 921-0660 ....... All American ................................... 39201 Schoolcraft Road, Suite B-2 ........................................... Livonia ....................... MI ............. 48150 ............. USA ....... 734-464-2202 ...... Future ............................................. 39340 Country Club Drive, Suite 100 ......................................... Famingron Hills ........ MI ............. 48331 ............. USA ....... 248 489-1179 ....... Future ............................................. 4595 Broadmoor SE., Suite 280 ................................................ Grand Rapids ............ MI ............. 49512 ............. USA ....... 616 534-3510 ....... Pioneer-Standard Electronics .......... 44190 Plymouth Oaks Blvd. ....................................................... Plymouth .................... MI ............. 48170 ............. USA ....... 734-416-2157 ...... Pioneer-Standard Electronics .......... 4476 Byron Center Road SW .................................................... Grand Rapids ............ MI ............. 49509 ............. USA ....... 616-534-3145 ...... All American ................................... 6608 Flying Cloud Drive ........................................................... Eden Prairie .............. MN ........... 55344 ............. USA ....... 612 944-2151 ....... Bell Microproducts .......................... Primetech Center 1, 6442 City West Parkway, Suite 200 ............ Eden Prairie .............. MN ........... 55344 ............. USA ....... 612 943-1122 ....... Future ............................................. 18882 Lake Drive East .............................................................. Chanhassen .............. MN ........... 55317 ............. USA ....... 612 934-9100 ....... Future ............................................. 10025 Valley View Road, Suite 196 ........................................... Eden Prairie .............. MN ........... 55344 ............. USA ....... 612 944-2200 ....... Nu Horizons ................................... 10907 Valley View Road ........................................................... Eden Prairie .............. MN ........... 55344 ............. USA ....... 612 942-9030 ....... Pioneer-Standard Electronics .......... 7625 Golden Triangle Drive, Suite G ........................................ Eden Prairie .............. MN ........... 55344 ............. USA ....... 612-944-3794 ...... FAI ................................................. 12125 Woodcrest Executive Drive, Suite 208 ............................. St. Louis .................... MO ........... 63141 ............. USA ....... 314-542-9922 ...... Future ............................................. 12125 Woodcrest Executive Drive, Suite 206 ............................. St. Louis .................... MO ........... 63141 ............. USA ....... 314-469-6805 ...... Pioneer-Standard Electronics .......... 4227 Earth City Expressway ...................................................... Earth City .................. MO ........... 63045 ............. USA ....... 314-209-3000 ...... All American ................................... 1121 Situs Court, Suite 370 ...................................................... Raleigh ..................... NC ............ 27606 ............. USA ....... 919 851-6566 ....... FAI ................................................. 5225 Capital Blvd., 1 North Commerce Center .......................... Raleigh ..................... NC ............ 27616 ............. USA ....... 919 790-7111 ....... FAI ................................................. 2800 Sumner Blvd., Suite 154 .................................................... Raleigh ..................... NC ............ 27616 ............. USA ....... 919 876-0088 ....... Future ............................................. 8401 University Executive Parkway, Suite 108 ............................ Charlotte ................... NC ............ 28262 ............. USA ....... 704-548-9503 ...... Interface Electronics ........................ 4601 Six Forks Road, Suite 133 ................................................ Raleigh ..................... NC ............ 27609 ............. USA ....... 919-787-8744 ...... Nu Horizons ................................... 2920 Highwood Boulevard, Suite 125 ........................................ Raleigh ..................... NC ............ 27604 ............. USA ....... 919 954-0500 ....... Pioneer-Standard Electronics .......... 5510 Six Forks Road, Suite 310 ................................................ Raleigh ..................... NC ............ 27609 ............. USA ....... 919-845-5100 ...... All American ................................... 8 East Stow Road, Suite 100 ..................................................... Marlton ...................... NJ ............ 8053 ............... USA ....... 609-596-6666 ...... Bell Microproducts .......................... 55 U.S. Highway 46 East, Suite 403 .......................................... Pine Brook ................. NJ ............ ,07058 ............ USA ....... 973-244-9668 ...... Bell Microproducts .......................... 23 Sebago Street ..................................................................... Clifton ....................... NJ ............ 7013 ............... USA ....... 201 777-4100 ....... FAI ................................................. 2000 Crawford Place, Suite 900 ................................................ Mt. Laurel .................. NJ ............ ,08054 ............ USA ....... 856 787-1000 ....... Future ............................................. 12 East Stow Road, Suite 200 ................................................... Marlton ...................... NJ ............ 08053 ............. USA ....... 609 596-4080 ....... Future ............................................. 1259 Route 46 East .................................................................. Parsippany ................. NJ ............ 07054 ............. USA ....... 973 299-0400 ....... Interface Electronics ........................ 20000 Horizon Way, Suite 300 .................................................. Mt. Laural .................. NJ ............ 8054 ............... USA ....... 609-439-0750 ...... Interface Electronics ........................ 1 Green Tree, Suite 201 ........................................................... Marlton ...................... NJ ............ 8053 ............... USA ....... 609 988-5448 ....... Nu Horizons ................................... 18000 Horizon Way, Suite 200 .................................................. Mt. Laural .................. NJ ............ 08054 ............. USA ....... 609 231-0900 ....... Nu Horizons ................................... 39 U.S. Route 46 ...................................................................... Pine Brook ................. NJ ............ 07058 ............. USA ....... 973-882-8300 ...... Pioneer-Standard Electronics .......... 271 Route 46W, Suite D206 ...................................................... Fairfield ..................... NJ ............ ,07004 ............ USA ....... 973 227-7760 ....... Pioneer-Standard Electronics .......... 14A Madison Road ................................................................... Fairfield ..................... NJ ............ 7004 ............... USA ....... 201 575-3510 ....... FAI ................................................. 5250 Neil Road, Suite 106 ........................................................ Reno ......................... NV ............ 89502 ............. USA ....... 715-826-2500 ...... All American ................................... 275B Marcus Blvd. ................................................................... Hauppauge ................ NY ............ 11788 ............. USA ....... 516 434-9000 ....... All American ................................... 333 Metro Park ........................................................................ Rochester .................. NY ............ 14623 ............. USA ....... 716 292-6700 ....... Bell Microproducts .......................... 1056 West Jericho Turnpike ..................................................... Smithtown .................. NY ............ 11787 ............. USA ....... 516 543-2000 ....... Edge Electronics ............................. 2271-7 Fifth Avenue .................................................................. Ronkonkoma .............. NY ............ 11779 ............. USA ....... 631-471-3343 ...... FAI ................................................. 6245 Sheridan Drive, Suite 216 ................................................. Williamsville .............. NY ............ 14221 ............. USA ....... 716 633-7188 ....... FAI ................................................. 251 Salina Meadows Parkway, Suite 230 ................................... Syracuse ................... NY ............ 13212 ............. USA ....... 315 451-4405 ....... Future ............................................. 251 Salina Meadows Parkway, Suite 210 ................................... Syracuse ................... NY ............ 13212 ............. USA ....... 315 451-2371 ....... Future ............................................. 300 Linden Oaks ....................................................................... Rochester .................. NY ............ 14625 ............. USA ....... 716 387-9600 ....... Future ............................................. 3033 Express Drive North ......................................................... Hauppauge ................ NY ............ 11788 ............. USA ....... 516-234-4000 ...... Fax Number 770-441-3660 770-857-4399 770-476-8662 770-416-9060 770-623-0665 208-376-6186 847-303-1996 847-413-8541 847-843-1163 847-490-9290 847-519-7710 630-495-9831 317-913-1375 317-49-0448
913-851-5905 913-338-3412 913-338-7185 617-275-1982 781-933-8336 978-779-3050 508-553-9575 978-532-7667 978-988-6620 410-309-6272 410-381-2172 410-314-1110 310-995-6332 301-670-6746 734-464-2433 248-489-1030 616-698-6821 734-416-2415 616-534-3922 612-944-9803 612-943-1110 612-934-6700 612-942-9144 612-829-2229 314-542-9655 314-469-7226 314-209-3054 919-851-8734 919-790-9022 919-876-8597 704-548-9469 919-787-9192 919-954-0545 919-845-5055 609-797-1700 973-244-9667 856-787-9626 973-299-1377 609-439-0519 609-231-9510 973-882-8398 973-227-3305 715-826-2664 516-434-9394 716-292-6755 516-543-2030 631-471-3405 716-633-7178 315 451-2621 315 451-7258 716-387-9596 516-234-6183
D4
09/18/00 Rev 1.1
ADVANCE INFORMATION
765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
North America Distributors (continued)
Company Name Street Address Nu Horizons ................................... 333 Metro Park ........................................................................ Nu Horizons ................................... 70 Maxess Road ...................................................................... Pioneer-Standard Electronics .......... 3125 Veterans Memorial Highway, Meridian Plaza III ................ Pioneer-Standard Electronics .......... 1249 UpperFront, Suite 201 ...................................................... Pioneer-Standard Electronics .......... 1250 Pittsford/Victor Road, Bldg. 200 ....................................... Pioneer-Standard Electronics .......... 60 Crossways Park West .......................................................... All American ................................... 26650 Renaissance Parkway .................................................... Bell Microproducts .......................... 13971 Placid Cove ................................................................... FAI ................................................. 6009-I Landerhaven Drive ........................................................ Future ............................................. 1430 Oak Court, Suite 203 ........................................................ Future ............................................. 6009-E Landerhaven Drive ........................................................ Future ............................................. 6565 Davis Industrial Parkway, Unit AA ..................................... Nu Horizons ................................... 2208 Enterprise E. Parkway ...................................................... Pioneer-Standard Electronics .......... 8741 Gander Creek Drive ......................................................... Pioneer-Standard Electronics .......... 6065 Parkland Boulevard .......................................................... Pioneer-Standard Electronics .......... 6675 Parkland Blvd. .................................................................. FAI ................................................. 7030 South Yale, Suite 606 ....................................................... Pioneer-Standard Electronics .......... 9717 East 42nd Street, Suite 105 ............................................... All American ................................... 1815 NW 169th Place, Suite 1040 ............................................. Bell Microproducts .......................... 14780 SW Osprey Drive, Suite 240 ........................................... FAI ................................................. 7204 SW Durham Road, Suite 900 ............................................ Future ............................................. 7204 SW Durham Road, Suite 800 ............................................ Nu Horizons ................................... 15455 NW Greenbrier Parkway, Suite 135 ................................. Pioneer-Standard Electronics .......... 5665 SW Meadows Road, Suite 150 .......................................... Future ............................................. 103 Bradford Road, Suite 100, Stonewood Commons II .............. Pioneer-Standard Electronics .......... 500 Enterprise Road, Kuth Valley Business Center ................... Pioneer-Standard Electronics .......... 259 Kappa Drive ....................................................................... All American ................................... 13706 Research Blvd., Suite 103 ............................................... All American ................................... 1771 International Parkway, Suite 101 ........................................ Bell Microproducts .......................... 12701 Research Blvd., Suite 360 ............................................... Bell Microproducts .......................... 833 East Araphho Road, Suite 205 ............................................ Bell Microproducts .......................... 2900 Wilcrest, Suite 138 ........................................................... Edge Electronics ............................. 1411 LeMay Drive, Suite 204 .................................................... FAI ................................................. The Courtyard, 7500 Viscount, Suite C75 .................................. Future ............................................. 7200 North Mopac, Suite 310 .................................................... Future ............................................. 2201 West Plano Parkway, Suite 150 ......................................... Future ............................................. 10737 Gateway West, Suite 330 ................................................ Future ............................................. 10333 Richmond Avenue, Suite 970 .......................................... Future ............................................. 7500 Viscount, Suite C75 ......................................................... Future ............................................. 800 East Campbell Road, Suite 130 .......................................... Nu Horizons ................................... 1313 Valwood Parkway, Suite 200 .............................................. Nu Horizons ................................... 2404 Rutland Drive, Suite 100 ................................................... Pioneer-Standard Electronics .......... 10707 Corporate Drive, Suite 106 ............................................. Pioneer-Standard Electronics .......... 13765 Beta Road ...................................................................... Pioneer-Standard Electronics .......... 4030 West Breaker Lane, Suite 175 ........................................... Pioneer-Standard Electronics .......... 959 East Collins Blvd., Suite 102 ............................................... All American ................................... 6955 South Union Park Center, Suite 110 .................................. Bell Microproducts .......................... 384 North Main Street .............................................................. Future ............................................. 3450 South Highland Drive, Suite 303 ....................................... Pioneer-Standard Electronics .......... 6925 Union Park Center, Suite 600-24 ...................................... Bell Microproducts .......................... 1039 Sterling Road, Suite 204 .................................................. FAI ................................................. 660 Hunters Place, Suite 202 .................................................... All American ................................... 11807 North Creek Pkwy South, Suite 112 ................................. FAI ................................................. 12100 NE 195th Street, Suite 150 .............................................. Future ............................................. 19102 North Creek Parkway, Suite 118 ...................................... Nu Horizons ................................... 8417 154th Avenue NE .............................................................. Pioneer-Standard Electronics .......... 2800 156th Avenue SE, Suite 205 .............................................. All American ................................... 18000 Sarah Lane, Suite 145 .................................................... FAI ................................................. 175 North Corporate Drive, Suite 150 ....................................... Future ............................................. 250 N. Patrick Blvd., Suite 170 .................................................. Pioneer-Standard Electronics .......... 120 Bishops Way, Suite 163 ...................................................... City State Zip Code Country Telephone Rochester .................. NY ............ 14623 ............. USA ....... 716 292-0777 ....... Mellville ..................... NY ............ 11747 ............. USA ....... 516 396-5000 ....... Ronkonkoma .............. NY ............ 11719 ............. USA ....... 516 738-1700 ....... Binghamton ............... NY ............ 13901 ............. USA ....... 607 722-9300 ....... Pittsford ..................... NY ............ 14534 ............. USA ....... 716 389-8200 ....... Woodbury .................. NY ............ 11797 ............. USA ....... 516 921-8700 ....... Warrenville Heights ... OH ............ 44128 ............. USA ....... 216 514-0625 ....... Strongsville ............... OH ............ 44136 ............. USA ....... 212 846-9156 ....... Mayfield Heights ........ OH ............ 44124 ............. USA ....... 440 446-0061 ....... Beavercreek ............... OH ............ 45430 ............. USA ....... 937 426-0090 ....... Mayfield Heights ........ OH ............ 44124 ............. USA ....... 440 449-6996 ....... Solon ......................... OH ............ 45430 ............. USA ....... 937 426-0090 ....... Townsburg ................ OH ............ 44087 ............. USA ....... 330 963-9933 ....... Miamisburg ............... OH ............ 45342 ............. USA ....... 937 428-6900 ....... Mayfield Heights ........ OH ............ 44124 ............. USA ....... 440 720 8500 ....... Solon ......................... OH ............ 44139 ............. USA ....... 440 519-6200 ....... Tulsa ......................... OK ............ 74136 ............. USA ....... 918 492-1500 ....... Tulsa ......................... OK ............ 74146 ............. USA ....... 918 665-7840 ....... Beaverton .................. OR ............ 97006 ............. USA ....... 503 531-3333 ....... Beaverton .................. OR ............ 97007 ............. USA ....... 503-524-0787 ...... Portland ..................... OR ............ 97224 ............. USA ....... 503 603-0866 ....... Portland ..................... OR ............ 97224 ............. USA ....... 503 603-0956 ....... Beaverton .................. OR ............ 97006 ............. USA ....... 503-439-1200 ...... Lake Oswego ............. OR ............ 97035 ............. USA ....... 503-968-6565 ...... Wexford ..................... PA ............ 15090 ............. USA ....... 724 935-9600 ....... Horsham ................... PA ............ 19044 ............. USA ....... 215 674-4000 ....... Pittsburgh .................. PA ............ 15238 ............. USA ....... 412 782-2300 ....... Austin ........................ TX ............ 78750 ............. USA ....... 512 335-2280 ....... Richardson ................ TX ............ 75081 ............. USA ....... 972 231-5300 ....... Austin ........................ TX ............ 78759 ............. USA ....... 512 258-0725 ....... Richardson ................ TX ............ 75081 ............. USA ....... 972 783-4191 ....... Houston ..................... TX ............ 77042 ............. USA ....... 713 917-0663 ....... Carrolton ................... TX ............ 75007 ............. USA ....... 972 323 7977 ....... El Paso ...................... TX ............ 79925 ............. USA ....... 915 779-7484 ....... Austin ........................ TX ............ 78731 ............. USA ....... 512-346-6426 ...... Plano ......................... TX ............ 75075 ............. USA ....... 469 467-0070 ....... El Paso ...................... TX ............ 79955 ............. USA ....... 915-592-3563 ...... Houston ..................... TX ............ 77042 ............. USA ....... 713-952-7088 ...... El Paso ...................... TX ............ 79925 ............. USA ....... 915 595-1000 ....... Richardson ................ TX ............ 75081 ............. USA ....... 972 437-2437 ....... Carrollton .................. TX ............ 75006 ............. USA ....... 972 488-2255 ....... Austin ........................ TX ............ 78758 ............. USA ....... 512 873-9300 ....... Stafford ...................... TX ............ 77477 ............. USA ....... 281-240-4882 ...... Dallas ....................... TX ............ 75244 ............. USA ....... 972-419-5500 ...... Austin ........................ TX ............ 78759 ............. USA ....... 512 340-9500 ....... Richardson ................ TX ............ 75081 ............. USA ....... 972-808-1900 ...... Midvale ...................... UT ............ 84047 ............. USA ....... 801-565-8300 ...... Centerville ................. UT ............ 84014 ............. USA ....... 801-295-3900 ...... Salt Lake City ............. UT ............ 84106 ............. USA ....... 801 467-9696 ....... Midvale ...................... UT ............ 84047 ............. USA ....... 801-566-8692 ...... Herndon .................... VA ............ 20170 ............. USA ....... 703 834-3696 ....... Charlottesville ............ VA ............ 22911 ............. USA ....... 804 984-5022 ....... Bothell ....................... WA ............ 98011 ............. USA ....... 425-806-4800 ...... Bothell ....................... WA ............ 98011 ............. USA ....... 425-485-6616 ...... Bothell ....................... WA ............ 98011 ............. USA ....... 425 489-3400 ....... Redmond ................... WA ............ 98052 ............. USA ....... 425-861-9200 ...... Bellevue ..................... WA ............ 98007 ............. USA ....... 425-644-7500 ...... Brookfield .................. WI ............. 53045 ............. USA ....... 414 792-0438 ....... Brookfield .................. WI ............. 53045 ............. USA ....... 414-792-9778 ...... Brookfield .................. WI ............. 53045 ............. USA ....... 414 879-0244 ....... Brookfield .................. WI ............. 53005 ............. USA ....... 414-780-3600 ...... Fax Number 716-292-0750 516-396-5050 516-738-1790 607-722-9562 716 389-8240 216-514-0822 212 846-9599 440-446-0062 937-426-8490 440-449-8987 937-426-8490 330 963-9944 937-428-6995 440 720 8501 440-519-6250 918-492-4848 918-665-1891 503-531-3695 503-524-1075 503-603-0960 503-603-0859 503-439-6286 503-598-2555 724-935-9695 215 674-3107 412-963-8255 512 335-2282 972 437-0353 512-258-6517 972-783-4192 713-917-0615 972-323-8530 512-346-6781 469-467-0071 915-592-3818 713-952-7098
972-488-2265 512-873-9800 281-240-7897 972-490-6419 512-340-9552 972-808-1940 801-565-9983 801-295-3377 801-467-9755 801-566-8719 703-834-3698 425-806-9900 425-483-6109 425-489-3411 425-861-9800 425-644-7300 414-792-9733 414-792-9779 414-780-3613
D5
09/18/00 Rev 1.1
ADVANCE INFORMATION
65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
North America Representatives
Company Name Street Address City State Zip Code Country Telephone Fax Number BITS, Inc. ..................................... 2705 Artie St., Suite 29 .................................... Huntsville ................. AL ....................... 35805 ....................... USA ......................... 256 534-4020 ........ 256 534-0410 Neutronics Components Ltd. ......... 206 2723-37th Avenue NE ................................ Calgary .................... Alberta ................ T1Y 5R8 .................. CANADA ................. 403 291 4994 ........ 403 291-4717 Schefler-Kahn Company, Inc. ........ 21639 North 12th Aveune, Suite 105 ................. Phoenix .................... AZ ...................... 85027 ....................... USA ......................... 623 581-0884 ........ 623 581-3522 DynaRep ...................................... 2985 E. Hillcrest Drive, Suite 201 .................... Thousand Oaks ........ CA ...................... 91362 ....................... USA ......................... 805 777 1185 ........ 805 777-9266 DynaRep ...................................... 3002 Dow Avenue, Suite 226 ............................ Tustin ....................... CA ...................... 92780 ....................... USA ......................... 714 573 1223 ........ 714 573-0778 Innovation Sales ........................... 6440 Lusk Blvd., Suite D200 ............................. San Diego ................ CA ...................... 92121 ....................... USA ......................... 858-535-9300 ...... 858-550-3707 NCTR ......................................... 46750 Fremont Blvd., Suite 110 ........................ Fremont ................... CA ...................... 94538 ....................... USA ......................... 510 624-8900 ........ 510 624-8905 Electrodyne .................................. 2620 South Park Road, Suite 395 ..................... Aurora ...................... CO ...................... 80014 ....................... USA ......................... 303-695-8903 ....... 303 745-8924 Component Design Marketing ...... 1803 Park Center Drive, Suite 200 ................... Orlando .................... FL ....................... 32835 ....................... USA ......................... 407-522-5808 ....... 407 522-0774 Component Design Marketing ...... 2240 Woolbright Road, Suite 317 .................... Boyton Beach ............ FL ....................... 33426 ....................... USA ......................... 561 740-3335 ........ 561 740-3635 BITS, Inc. ..................................... 5425 Sugarloaf Pkwy., Suite 2201 .................... Lawrenceville ............ GA ...................... 30043 ....................... USA ......................... 770-513-8610 ...... 770-513-8680 Luscombe Sales ........................... 6901 Emerald, Suite 206 .................................. Boise ....................... ID ....................... 83704 ....................... USA ......................... 208-377-1444 ....... 208 377-0282 Martan, Inc. .................................. 1100 Woodfield Road ...................................... Schaumburg ............. IL ........................ 60173 ....................... USA ......................... 847 330 3200 ............................ Oasis Sales Corporation .............. 1101 Tonne Road ............................................ Elk Grove Village ...... IL ........................ 60007 ....................... USA ......................... 847 640 1850 ....... 847-640-9432 Martan, Inc. .................................. 10820 Horton .................................................. Overland Park ........... KS ...................... 66211 ....................... USA ......................... 913 381 3652 ........ 913 381-3653 Universal Technology ................... 22 A Street ...................................................... Burlington ................ MA ...................... 3803 ........................ USA ......................... 781-890-8523 ....... 781 890-8589 Avtek Associates .......................... 10632 Little Patuxent Parkway, Suite 435 .......... Columbia .................. MD ..................... 21044 ....................... USA ......................... 410 740-5100 ....... 410-740-5103 Jay Marketing Assoc. Inc. ............. 44752 Helm Street .......................................... Plymouth .................. MI ....................... 48170 ....................... USA ......................... 734-459-1200 ...... 734-459-1697 Cahill, Schmitz & Cahill, Inc. ........ 897 St. Paul Avenue ........................................ St. Paul .................... MN ..................... 55116 ....................... USA ......................... 651 699 0200 ....... 651-699-0800 Martan, Inc. .................................. 257 Old Stone Court ....................................... O'Fallon ................... MO ..................... 63366 ....................... USA ......................... 314 939 3300 ....... 314-447-1371 BITS, Inc. ..................................... 940 Main Campus Drive, Suite 120 .................. Raleigh .................... NC ...................... 27606 ....................... USA ......................... 919 807 1000 ....... 919-807-1001 BITS, Inc. ..................................... 3320 Silver Pond Court ................................... Charlotte .................. NC ...................... 28810 ....................... USA ......................... 704-540-8185 ...... 704-540-8183 Matrix Sales ................................. 30 Washington Avenue Suite B-2 ..................... Haddonfield .............. NJ ...................... 8033 ........................ USA ......................... 856 795 8833 ........ 856 795 0038 Neptune Electronics/NECCO ....... 11 Oval Drive, Suite 169 .................................. Islandia .................... NY ...................... 11722 ....................... USA ......................... 631-234-2525 ...... 631-234-2707 NYCOM, Inc. ............................... 10 Adler Drive ................................................. East Syracuse .......... NY ...................... 13057 ....................... USA ......................... 315 437-8343 ....... 315-437-1208 Electronic Device Sales ................ 8000 Green Ridge Court ................................. Mentor ..................... OH ...................... 44060 ....................... USA ......................... 440 255-7040 ....... 440-255-7093 Electronic Device Sales ................ 6917 Rob Vern Drive ....................................... Cincinnati ................. OH ...................... 45239 ....................... USA ......................... 513 729-8440 ....... 513-729-8448 Nova Marketing Ltd. ..................... 3544 Adams Road ........................................... Mounds .................... OK ...................... 74074 ....................... USA ......................... 918-827-5560 ....... 918 827-5561 Neutronics Components Ltd. ......... 232 Herzberg Road, Suite 201 ........................ Kanata ...................... Ontario ................ K2K 2A1 .................. CANADA ................. 613-599-1263 ...... 613-599-4750 Neutronics Components Ltd. ......... 240 Terence Mathews Crescent, Suite 105 ...... Kanata ...................... Ontario ................ K2M 2C4 ................. CANADA ................. 613 599 1263 ............................ Neutronics Components Ltd. ......... 6271 Dorman Road, Suite 18 ........................... Mississauga ............ Ontario ................ L4V 1H1 .................. CANADA ................. 905 671 4001 ........ 905 671-4062 Electra ......................................... 6700 SW 105th Avenue, Suite 210 .................... Beaverton ................. OR ...................... 97008 ....................... USA ......................... 503 643 5074 ........ 503 526-2055 Astrorep Mid Atlantic Inc. ............. 65 West Street Road, Suite B-203 ................... Warminster .............. PA ...................... 18974 ....................... USA ......................... 215 957 9580 ............................ Neutronics Components Ltd. ......... 189 Hymus Blvd., Suite 604 ............................. Pointe Claire ............ Quebec ............... H9R 1E9 .................. CANADA ................. 514 428 5838 ....... 514-428-5837 Nova Marketing Ltd. ..................... 10701 Corporate Drive, Suite 370 .................... Stafford .................... TX ...................... 77477 ....................... USA ......................... 214-265-4600 ...... 214-265-4668 Nova Marketing Ltd. ..................... 127 Pioneer Plaza at 127 San Francisco ......... El Paso .................... TX ...................... 79901 ....................... USA ......................... 915 543-3212 ....... 915-543-3213 Nova Marketing Ltd. ..................... 3520 Executive Center Drive, Suite 159 ............ Austin ....................... TX ...................... 78731 ....................... USA ......................... 512 343-2321 ....... 512-343-2487 Nova Marketing Ltd. ..................... 508 Twilight Trail, Suite 203 ............................ Richardson .............. TX ...................... 75080 ....................... USA ......................... 214-570-3430 ...... 214-570-3435 Luscombe Sales ........................... 670 East 3900 South, Suite 103 ........................ Salt Lake City ............ UT ...................... 84107 ....................... USA ......................... 801 268-3434 ........ 801 266-9021 Electra ......................................... 11411 NE 124th Sreet, Suite 285 ..................... Kirkland .................... WA ...................... 98034 ....................... USA ......................... 425 821 7442 ........ 425 821-7289 Oasis Sales Corporation .............. 1305 N. Barker Road ....................................... Brookfield ................. WI ....................... 53045 ....................... USA ......................... 262 782 6660 ........ 262 782-7921
D6
09/18/00 Rev 1.1
ADVANCE INFORMATION
765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
International Distributors
Company Name ........................................... Address .............................................................................................................................................................. Country ......................... Telephone All American ................................................. Ave. Mariano Otero, #3431 Ber Pisco, Col. Verde Valle, Guadalajara, Jalisco, 44550 .............................................. MEXICO ................. 011 523 818 4302, All American ................................................. 6375 Dixie Road, Units 4,5,6, Mississuaga, ON, L5T 2E7 ...................................................................................... CANADA ...................... 905 670-5946 FAI ............................................................... 3689 East 1st Ave., Suite 200, Vancouver, Br. Colum., V5M 1C2 ............................................................................. CANADA ...................... 604 654-1050 FAI ............................................................... 1780 Wellington Avenue, Suite 504, Winnipeg, Manitoba, R3H 1B2 ........................................................................ CANADA ..................... 204-786-3075 FAI ............................................................... 1000 St. Charles Blvd., 10th Floor, Vaudreuil, Quebec, J7V 8P5 ............................................................................. CANADA ...................... 514 457-1487 FAI ............................................................... 1000 St. Charles Blvd., 1st Floor, Vaudreuil, Quebec, J7V 8P5 ............................................................................... CANADA ...................... 514 457 3004 FAI ............................................................... 1101 Prince of Wales, Suite 210, Ottawa, Ontario, K2C 3W7 ................................................................................... CANADA ...................... 613 727 8622 FAI ............................................................... 1144 29th Avenue NE, Suite 200, Calgary, Alberta, T2E 7P1 ................................................................................... CANADA ...................... 403 291 5333 FAI ............................................................... 5935 Airport Road, Suite 205/210, Mississauga, Ontario, L4V 1W5 ........................................................................ CANADA ...................... 905 612 9888 FAI ............................................................... 237 Hymus Blvd., Point Claire, Quebec, H9R 5C7 .................................................................................................. CANADA ...................... 514 694-7710 FAI ............................................................... 6029 103rd Street, Edmonton, Alberta, T6H 2H3 .................................................................................................... CANADA ...................... 708 438 5888 Future ........................................................... 1000 St. Jean Baptiste, Suite 201, Quebec, Quebec, G2E 5G5 ................................................................................ CANADA ...................... 418 877-1414 Future ........................................................... 1101 Prince of Wales, Suite 210, Ottawa, Ontario, K2C 3W7 ................................................................................... CANADA ...................... 613 727 1800 Future ........................................................... 1144 29th Avenue NE, Suite 200, Calgary, Alberta, T2E 7P1 ................................................................................... CANADA ..................... 403-219-3443 Future ........................................................... 26 Merchants Square, Ennis, Country Clare .......................................................................................................... IRELAND ....................... 353 6541330 Future ........................................................... 3689 East 1st Avenue, Suite 200, Vancouver, Br. Colum., V5M 1C2 ........................................................................ CANADA ...................... 604 294 1166 Future ........................................................... 5, Avenue Albert Durand, Aeropole 3, 31700 Blagnac, Toulouse ............................................................................. FRANCE .................. 33 5 62 74 72 40 Future ........................................................... Black and Decker Str. 17b, Idstein, 65510 ............................................................................................................... GERMANY ................... 06126 9321 0 Future ........................................................... Buschkamp 84, Langenhagen, 30853 ..................................................................................................................... GERMANY ................... 0511 72562 0 Future ........................................................... Europarc du chene/ 4 Rue Edison, 69674 Bron Cedex, Lyon .................................................................................... FRANCE .................. 44 3 72 15 86 00 Future ........................................................... Hauert 8, Dortmund, 44227 .................................................................................................................................... GERMANY .................. 0231 975048 0 Future ........................................................... Johannes-Daur Str. 1, Korntal-Munchigen, 70825 .................................................................................................. GERMANY .................... 0711 830830 Future ........................................................... Kanalvagen 10C, 184 61 Upplands Vasby .............................................................................................................. SWEDEN ................ 0046 5 590 041 83 Future ........................................................... Luxemburger Str. 35, Berlin, 13353 ........................................................................................................................ GERMANY ................... 030 469089 0 Future ........................................................... Max-Weber-Strabe 3, Quickborn, 25451 ................................................................................................................ GERMANY ................... 04106 7748 0 Future ........................................................... Munchner Strabe 18, Unterforhring, 85774 ............................................................................................................ GERMANY ..................... 089 95727 0 Future ........................................................... Parc Technolopolis/L.P. 854 les Ulis, 3, Ave. du Canada/ Bat Theta 2, Courtabeuf, Cedex, Paris, 91974 ................... FRANCE ................... 33 1 69 82 1111 Future ........................................................... Unit 4 Blair Court, Clydebank Bus. Park, Clydebank, Glasgow, G811 2RX ............................................................... UK ................................. 041 9511199 Future ........................................................... Urb. Belmonte Galicia #45, Mayaguez, 00680 ........................................................................................................ Puerto Rico ................... 787 289-7801 Future ........................................................... Via Fosse Ardeatine 4, 20092 Cinisello Balsamo, Milan ......................................................................................... ITALY .............................. 39 2 660941 Future ........................................................... Wilhelm-Wolff Str. 6, Erfurt, 99099 ......................................................................................................................... GERMANY ................... 0361 42087 0 Future Electronics OY ................................... Olarinluoma 7, Fon-02200, Espoo, Helsinki ............................................................................................................ FINLAND .............. 011 358 9 525 9950 Future Electronics ......................................... Distribution (Spain), S.L., Avenida D=dek, Oarebib 8-10, Madrid ............................................................................ SPAIN .......................... 34 1 72 10 762 Future Electronics ......................................... Faerch-Huset, L1/ Ostergade 5.4, DK-7500 Holstebro .......................................................................................... DENMARK ................... 45 961 00961 Future Electronics AS .................................... GPI Building, Karihaugveien 89, 1086 Oslo ............................................................................................................ NORWAY ................ 011 47 22 90 5800 Future Electronics B.V. .................................. Tinstaat 3, 4823AA Breda ...................................................................................................................................... Netherlands ........... 011 31 64 571 2497 Future Electronics Inc. ................................... 103 Medinat Hayeudim Street, P.O. Box 2219, Herzliya, 46120 ................................................................................ ISRAEL ...................... 972 999 586555 Future Electronics KFT- Hungary .................. Burok utca 34, J-1124, Budapest ............................................................................................................................ HUNGARY ............. 011 36 1 458 5690 Future Electronics Polska .............................. Spolka z.o.o U1 Panienska 9, 03-704 Warsaw ........................................................................................................ POLAND ............... 011 48 22 618 9202 Future Electronics SRL ................................. Galleria Camillo Ronzani 3/9, Casalecchio Di Reno, Bologna, 40033 .................................................................... ITALY ............................. 051 6136700 Future Electronics SRL ................................. Via Domenico Turazza, 30, 31528 Padova ............................................................................................................. ITALY ........................... 049 899 20111 Future Electronics De Mexico ........................ Calle Paplot #92 Bis, Col. San Martin, Xochinahuac, Mexico, D. F., 2210 ................................................................ MEXICO .......................... 5-382-4106 Future Electronics De Mexico ........................ Chimalhuacan #3569, 4 Piso, Suite 6 Ciudad Del Sol, Zapopan, Jalisco, 45050 ....................................................... MEXICO .................. 011523 122-0043 Future Electronics De Mexico ........................ Col. Bosques del Alba, Cuautitlan, Ixcalli, Estado De Mexico, 54769 ....................................................................... MEXICO ........................... 5 893 5764 Future Electronics De Mexico ........................ Futbol #173-11, Col. Country Club, Mexico, D.F., ,04220 ........................................................................................ MEXICO ........................... 5 689 3340 Future Electronics De Mexico ........................ Torre Gia Piso 8, Av. Morones Prieto , #2805 Pte., Col. Loma Larga, Monterrey, N.L., 64710 ................................... MEXICO .......................... 8-399-0027 Future-Birminham .......................................... 1st Floor 3 Hagley Court North, Waterfront East, Brierley Hill, W. Midlands, DY5 1XF ............................................ UK ............................... 01384 482 555 Future-Brazil ................................................ Rua Luzitana, 740 10 Andar, Conj 103/104, 13014-121, Compinas, SP .................................................................... BRAZIL ................. 011 55 19 232 1511 Future-Manchester ........................................ Adamson House, Throstle nest Lane, Pomona Strand, Manchester, M16 0TT ......................................................... UK ................................ 44 61 876000 Pioneer-Standard Canada .............................. 10711 Cambie Road, Suite 170, Richmond, BC, V6X 3G5 ....................................................................................... CANADA ...................... 604 273-5575 Pioneer-Standard Canada .............................. 223 Colonnade Road, Unit 100, Nepean, ON, K2E 7K3 ........................................................................................... CANADA ...................... 613 226-8840 Pioneer-Standard Canada .............................. 148 York Street, Suite 209, London, ON, N6A 1A9 .................................................................................................. CANADA ..................... 905-405-8300 Pioneer-Standard Canada .............................. 240 Graham Avenue, Suite 808, Winnipeg, Manitoba, R3C 0J7 ............................................................................... CANADA ...................... 204 989-1957 Pioneer-Standard Canada .............................. 3415 American Drive, Mississauga, ON, L4V 1T6 ................................................................................................. CANADA ...................... 905 405-8300 Pioneer-Standard Canada .............................. 520 McCaffrey Street, Ville St. Laurent, QC, H4T 1N1 ............................................................................................ CANADA ...................... 514 737-9700 Pioneer-Standard Canada .............................. Place Iberville IV, 2954 Blvd. Laurier, Suite 100, Ste. Foy, QC, G1V 4T2 .................................................................. CANADA ...................... 418 654-1078 Pioneer-Standard Electronics ........................ Kuth Valley Bus. Ctr, 500 Enterprise Road, Horsham, PA, 19044 ............................................................................ CANADA ...................... 215 674-4000
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09/18/00 Rev 1.1
ADVANCE INFORMATION
65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI7C7100 3-Port PCI Bridge
International Representatives
Company Name Address Acetronix ....................................................... 1st Floor Ashiville Palace 31-13 Hap-Dong, Sudaimoon-Ku, SEOUL, 120-030 ................................................ Alcom Electronics .......................................... Single 3, 2550 Kontich Belgium ..................................................................................................................... Alcom Electronics BV .................................... Rivian le straat 52, 2909 LE, Capelle aan den Yssel ........................................................................................ Ambar Cascom, Ltd. ...................................... The Gatehouse, Alton House Business Park, Gatehouse Way, Aylesbury Bucks, HP19 3DL ............................. Boran Technologies Ltd. ................................ Dynacom Division, P.O. Box 2627, Petach Tikva, 49125 ................................................................................... Braemac Pty. Ltd. ........................................... Unit 1, 59-61 Burrows Road, Alexandria NSW, 2015 ....................................................................................... Chin Shang Electronics Corp. ....................... 4F, No. 18, Alley 1, Lane 768, Sec 4, Pa Te Road, Taipei ................................................................................ Communica (PTY) Ltd. .................................. Sunnyside 0132 Pretoria 0002 ....................................................................................................................... Component Design Marketing ....................... Calle Huca #38 Bajos BO Sabanetas Mercedita Dr. 00715 ............................................................................. Deltek ........................................................... Block 1 Unit A3, Templeton Bus. Centre, Templeton St., Glasgow, G40 1DA ................................................... Desner Electronics Co. Ltd. ........................... 4th Floor, Na-Nakorn Building, 99/349 Changwattana Rd. 10210 Bangkok, Laksi, Bangkok, 10210 .................... Desner Electronics, Far East PTE, Ltd. .......... 42 Mactaggart Road, #04-01, Mactaggart Building, Singapore, 368086 ......................................................... Desner SDN BHD ......................................... No 9, Jalan PJS 8/9, Bandar Sunway, 46150 Selangor, Kuala Lumpur, 46150 ................................................... Desner SDNBHD ......................................... No.36B Jalan Tun Dr. Awang 11900 Pulau Pinang, Pulau Pinang, 11900 ........................................................ EEC International (HK) Ltd. ............................ Room 805 8/f Hunghom Comm. Ctr., Tower B, 37-39 Ma Tau Wai Road, Hunghom, Kowloon .......................... EEC Technology (S) Pte. Ltd. ........................ 10 Upper Aljunied Link , #04-01, York Intl Industrial Bldg., Singapore, 367904 ................................................. Elitetron Electronic Co. Ltd ............................ 4F, 70 Cheng Kung Road, Sec. 1 , Nankang, Taipei ....................................................................................... Elitetron Electronic Co. Ltd. ............................ 4F, 70 Cheng Kung Road, Section 1, Nankang, Taipei ................................................................................... EPCO Technology Co., Ltd. ........................... 10 F, 268, Sec. 2, Fu-Hsing S. Rd., Taipei ..................................................................................................... FMG Electronics Ltd. ..................................... Garden Row, William Street, Kilkenny ............................................................................................................ GD Technik ................................................... Tudor House, 24 High Street, Twyford Berks, RG10 9AG ............................................................................... GD Technik ................................................... Unit 20, Blackburn Technology Mgmt. Cntre, Challenge Way, Blackburn, BB1 5QB ......................................... Golden Rich Technologies ............................ Unit 1006, 10/F Tower II, Enterprise Square, 9 Sheung Yuet Road, Kowloon Bay ............................................. Heko Electronikk & Data a/s ............................ L-rdagsrudeveien 24, Fjellhamar, 1472 .......................................................................................................... Hy-Line Computer Components ...................... Inselkammerstrasse 10, Unterhaching, 82008 ................................................................................................ I&C Microsystems,Co.Ltd .............................. 8th Floor, Bethel Bldg., 324-1, Yangjae-Dong, Seocho-Ku , SEOUL ............................................................... Internix Inc. (Hachioji Branch) ........................ 59-10 Takakura-cho, Hachioji-shi, Tokyo, 192-0033 ........................................................................................ Internix Inc. (Head Office) .............................. Shinjuku Hamada Bldg., 3F 7-4-7, Nishishinjuku, Shinjuku-ku, Tokyo, 160-8388 ............................................... Leading Technologies ................................... 99 Route de Versailles, Champlan, 91160 ...................................................................................................... Leading Technologies Italia SRL ................... Via Flume 13, 1-20059 Vimercate (MI) .......................................................................................................... MCM Japan Ltd. ............................................ 2-11-2 Sun Tower Center Bldg., Sangenjaya, Setagaya-Ku, Tokyo, 154-8539 .................................................. Micro Summit K.K. ......................................... Premier KI Building, 1 Kanda, Mikura-cho, Chiyoda-ku, Tokyo, 101-0038 ......................................................... Micro Summit Singapore Pte. Ltd ................... Blk 13 Braddell Tech, #03-02 , Toa Payoh Lorong 8, Singapore, 319261 .......................................................... Microelectronic Visions Inc. ........................... 2812 Garden Creek Circle, Pleasanton, CA, 94588 ......................................................................................... Milgray Distribution GMBH ........................... Allmendstrasse 28, PO Box 68, 2562 Port Switzerland .................................................................................... Neutronics Components Ltd. .......................... 189 Hymus Components, Suite 604, Pointe Claire, Quebec, H9R 1ER ............................................................ Neutronics Components Ltd. .......................... 206 2723-37th Avenue NE, Calgary, Alberta, T1Y 5R8 .................................................................................... Neutronics Components Ltd. .......................... 240 Terence Matthew's Crescent, Suite 105, Kanata, Ontario, K2M 2C4 ......................................................... Neutronics Components Ltd. .......................... 6271 Dorman Road, Unit # 18, Mississauga, Ontario, L4V 1H1 ...................................................................... Newtek .......................................................... 8 Rue De L'Esterel, Silic 583, Rungis Cedex, 94663 ...................................................................................... Newtek Italia SpA ........................................... Via Cassiodoro 16, Milano, 20145 ................................................................................................................. Pan American Technical Sales ....................... Av. Avila Camacho No. 2275-1, Col. Country Club, C.P. 44610 , Zapopan, Jalisco ........................................... Pan American Technical Sales ....................... 6624 Cresta Bonita, El Paso, TX, 79912 ........................................................................................................ Pan American Technical Sales ....................... Av. Morones Prieto #2805 Pte. Col. Loma Largo, C.P. 64710, Monterrey, Nuevo Leon ...................................... Pan American Technical Sales ....................... 8100 Shoal Creek Blvd., Suite 250, Austin, TX, 78757 ..................................................................................... Pangaea International Trading Corp. ............. Unit 703, Alabang Business Center, Madrigal Business Park, Ayala Alabang, Muntinlupa City, 1780 ............... RTI Industries Co., Ltd. .................................. Room 402, Nan Fung Commercial Centre, No 19. Lam Lok Street, Kowloon Bay .............................................. Silicon Concepts ........................................... PBC LYNCHBOROUGH ROAD, PASSFIELD, LIPHOOK, Hampshire, HAMPSHIRE .................................. Silicon Highway ............................................. 4B Saturn House, Calieva Park, Aldermaston,, Berkshire, RG7 8HA ............................................................... Spectra Innovations Inc. ................................. 780 Montague Expressway, Suite 208, San Jose, CA, 95131-1316 .................................................................. Spectra Innovations Inc. ................................. S-822, Manipal Centre, 47, Dickenson Road, Bangalore, 560 042 ................................................................... Sunrise Corporation ...................................... Unit 802, Daesung Bldg. 775-3 Daerim-3dong, Youngdeungpo-Ku, SEOUL ................................................... Techmosa International Inc. ............................ 4F, No. 18, Alley 1, Lane 768, Sec 4, Pa Te Road, Taipei ................................................................................ Country Telephone KOREA ................................ 82-2-796-4561 BELGIUM .......................... 011 323 458 3033 Netherlands .......................... 31 10 28 82 500 UK ......................................... 01296-434141 ISRAEL ................................ 972-3927-4747 AUSTRALIA .......................... 612 9550 6600 TAIWAN ............................ 886-2-2-7885470 South Africa ..................... 011 27 12 3327613 Puerto Rico ............................ 787 844-3840 SCOTLAND ......................... 0141-556-7233 THAILAND ........................... 662-576 1500-1 SINGAPORE ............................. 65-2851566 MALAYSIA ........................... 603-7877 6211 MALAYSIA ............................. 604-641-1288 Hong Kong ...................... 011 852 2365 7775 SINGAPORE ............................. 65 283 0822 Taiwan, R.O.C. .............. 011 886 2 27893300 Taiwan, R.O.C. .............. 011 886 2 27893300 TAIWAN .............................. 886 2 2737 3507 IRELAND ............................... 353-56-64002 UK ................................... 011441189342277 UK .......................................... 01254 679831 HONG KONG ...................... 852 2751-8840 NORWAY ............................. 47-67-90-52-44 GERMANY ................ 011-49-89-614503-40 KOREA ................................ 82-2-577-9131 JAPAN ................................. 81-426-448786 JAPAN ............................... 81-3-3369-1105 FRANCE ............................ 33 01 69 79 9350 ITALY ................................... 39 39 66 13 108 JAPAN ................................ 81-3-3487-8477 JAPAN ................................... 03-3258-5531 SINGAPORE ............................. 65-2522677 UK .......................................... 510 485-0710 SWITZERLAND .............. 011 41 3233 12064 CANADA ................................. 514 428 5838 CANADA ................................. 403 291 4994 CANADA ................................. 613 599 1263 CANADA ................................. 905 671 4001 FRANCE .................................. 1-468-72200 ITALY ........................................ 02-4692156 Mexico .............................. 011 52 3 824 9999 USA ........................................ 915 532 1900 Mexico .............................. 011 52 8 399 0024 USA ........................................ 512 371 7272 PHILIPPINES .......................... 632 807 8429 HONG KONG ...................... 852-279-57421 UK .......................................... 01428 751617 UK ........................................... 01189816888 USA ..................................... (408) 954-8474 INDIA .................................. 91-80-558-8323 KOREA ................................... 822 844 2328 TAIWAN ............................ 886-2-2-7822288
D8
09/18/00 Rev 1.1
765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
ADVANCE INFORMATION
NOTES
D9
PI7C7100 3-Port PCI Bridge
09/18/00 Rev 1.1
65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 65432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
ADVANCE INFORMATION
NOTES
D10
PI7C7100 3-Port PCI Bridge
09/18/00 Rev 1.1

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