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Data Sheet July 1998
T8502 and T8503 Dual PCM Codecs with Filters
Features
s s s s s s s
+5 V only Two independent channels Pin-selectable receive gain control Pin-selectable -law or A-law companding Automatic powerdown mode Low-power, latch-up-free CMOS technology -- 40 mW/channel typical operating power dissipation -- 12.5 mW/channel typical standby power dissipation Automatic master clock frequency selection -- 2.048 MHz or 4.096 MHz Independent transmit and receive frame strobes 2.048 MHz or 4.096 MHz data rate On-chip sample and hold, autozero, and precision voltage reference Differential architecture for high noise immunity and power supply rejection
GSX0 VFXIN0 - + +2.4 V FILTER NETWORK
s
Meets or exceeds ITU-T G.711--G.714 requirements and VF characteristics of D3/D4 (as per Bellcore PUB43801) Operating temperature range: -40 C to +85 C
Description
The T8502 and T8503 devices are single-chip, twochannel, -law/A-law PCM codecs with filters. These integrated circuits provide analog-to-digital and digital-to-analog conversion. They provide the transmit and receive filtering necessary to interface a voice telephone circuit to a time-division multiplexed system. These devices are packaged in both 20-pin SOJs and 20-pin SOGs. The T8502 differs from the T8503 in its timing mode. The T8502 operates in the delayed timing mode (digital data is valid one clock cycle after frame sync goes high), and the T8503 operates in the nondelayed timing mode (digital data valid when frame sync goes high) (see Figures 5 and 6).
s
s s s
s
DX DR ENCODER PCM INTERFACE FSX0 FSR0 FSX1 FSR1 GNDD
CHANNEL 0
VFRO0
FILTER NETWORK
DECODER
GAIN CONTROL
GS0 GS1 MCLK ASEL
GSX1 VFXIN1 VFRO1
INTERNAL TIMING & CONTROL CHANNEL 1 BIAS CIRCUITRY & REFERENCE
VDD GNDA (2)
5-3579.b
Figure 1. Block Diagram
T8502 and T8503 Dual PCM Codecs with Filters
Data Sheet July 1998
Functional Description
Two channels of PCM data input and output are passed through only two ports, DX and DR, so some type of time-slot assignment is necessary. The scheme used here is to utilize a fixed-data rate mode of 32 or 64 time slots corresponding to master clock frequencies of either 2.048 MHz or 4.096 MHz, respectively. Each device has four frame sync (FSX and FSR) inputs, one pair for each channel. During a single 125 s frame, each frame sync input is supplied a single pulse. The timing of the respective frame sync pulse indicates the beginning of the time slot during which the data for that channel is clocked in or out of the device. FSX and FSR must be high for a minimum of one master clock cycle. They can be operated independently, or they can be tied together for coincident transmit and receive data transfer. During a frame, channel 0 and 1 transmit frame sync pulses must be separated from each other by one or more time slots. Likewise, channel 0 and 1 receive frame sync pulses must be separated from each other by one or more time slots. Both transmit and receive frame strobes must be derived from master clock, but they do not need to be byte aligned. A channel is placed in standby mode by removing both FSX and FSR for 500 s. Note, if any one of those pulses (per channel) is removed, operation is indeterminate. Standby mode reduces overall device power consumption by turning off nonessential circuitry. Critical circuits that ensure a fast, quiet powerup are kept active. Master clock need not be active when both channels are in standby mode. The frequency of the master clock must be either 2.048 MHz or 4.096 MHz. Internal circuitry determines the master clock frequency during the powerup reset interval. The analog input section in Figure 2 includes an onchip op amp that is used in conjunction with external, user-supplied resistors to vary encoder passband gain. The feedback resistance (RF) should range from 10 k to 200 k, and capacitance from GSX to ground should
be kept to less than 50 pF. The input signal at VFXIN should be ac coupled. For best performance, the maximum gain of this op amp should be limited to 20 dB or less. Gain in the receive path is selectable via the GS pins as either 0 dB or -3.5 dB.
RF GSX
CI
RI
VFXIN - + 2.4 V GAIN =
TO CODEC FILTERS
RF RI
5-3786.a
Figure 2. Typical Analog Input Section
Pin Information
VFXIN0 GSX0 GNDA0 VFRO0 GS0 VDD FSR0 FSX0 MCLK GNDD 1 2 3 4 5 6 7 8 9 10 T-8502 T-8503 20 19 18 17 16 15 14 13 12 11 VFXIN1 GSX1 GNDA1 VFRO1 GS1 ASEL FSR1 FSX1 DR DX
5-3788.b
Figure 3. Pin Diagram
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Lucent Technologies Inc.
Data Sheet July 1998
T8502 and T8503 Dual PCM Codecs with Filters
Pin Information (continued)
Table 1. Pin Descriptions Symbol VFXIN1 VFXIN0 GSX1 GSX0 VFRO1 VFRO0 VDD GNDA1 GNDA0 DR DX Pin 20 1 19 2 17 4 6 18 3 12 11 Type* Name/Function Voice Frequency Transmitter Input. Analog inverting input to the uncommitted operI ational amplifier at the transmit filter input. Connect the signal to be digitized to this pin through a resistor RI (see Figure 2). O Gain Set for Transmitter. Output of the transmit uncommitted operational amplifier. The pin is the input to the transmit differential filters. Connect the pin to its corresponding VFXIN through a resistor RF (see Figure 2). O Voice Frequency Receiver Output. This pin can drive 2000 (or greater) loads. -- -- I O +5 V Power Supply. This pin should be bypassed to ground with at least 0.1 F of capacitance as close to the device as possible. Analog Grounds. All ground pins must be connected on the circuit board. Receive PCM Data Input. The data on this pin is shifted into the device on the falling edges of MCLK. Data is only entered for valid time slots as defined by the FSR inputs. Transmit PCM Data Output. This pin remains in the high-impedance state except during active transmit time slots. An active transmit time slot is defined as one in which a pulse is present on one of the FSX inputs. Data is shifted out on the rising edge of MCLK. Master Clock Input. The frequency must be 2.048 MHz or 4.096 MHz. This clock serves as the bit clock for all PCM data transfer. Digital Ground. Ground connection for the digital circuitry. All ground pins must be connected on the circuit board. Transmit Frame Sync. This signal is an edge trigger and must be high for a minimum of one MCLK cycle. This signal must be derived from MCLK. The division ratio is 1:256 or 1:512 (FSX:MCLK). Each FSX input must have a pulse present at the start of the desired active output time slot. Pulses on FSX inputs must be separated by one or more integer multiples of time slots. If the device is to be used as an A/D converter only, FSX must be tied to FSR. An internal pull-down device is included on each FSX. Receive Frame Sync. This signal is an edge trigger and must be high for a minimum of one MCLK cycle. This signal must be derived from MCLK. The division ratio is 1:256 or 1:512 (FSR:MCLK). Each FSR input must have a pulse present at the start of the desired active input time slot. Pulses on FSR inputs must be separated by one or more integer multiples of time slots. If the device is to be used as a D/A converter only, FSR must be tied to FSX. An internal pull-down device is included on each FSR. Gain Selection. A high or floating state sets the receive path gain at 0 dB; a logic low sets the gain to -3.5 dB. A pull-up device is included. A-Law/-Law Select. A logic low selects -law coding. A logic high selects A-law coding. A pull-down device is included.
MCLK GNDD FSX1 FSX0
9 10 13 8
I -- Id
FSR1 FSR0
14 7
Id
GS1 GS0 ASEL
16 5 15
Iu Id
* Id indicates a pull-down device is included on this lead. Iu indicates a pull-up device is included on this lead.
Lucent Technologies Inc.
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T8502 and T8503 Dual PCM Codecs with Filters
Data Sheet July 1998
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter Storage Temperature Range Power Supply Voltage Voltage on Any Pin with Respect to Ground Maximum Power Dissipation (package limit) Symbol Tstg VDD -- PD Min -55 -- -0.5 -- Max 150 6.5 0.5 + VDD 600 Unit C V V mW
Handling Precautions
Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Lucent Technologies Microelectronics Group employs a human-body model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been adopted for CDM. However, a standard HBM (resistance = 1500 , capacitance = 100 pF) is widely used and, therefore, can be used for comparison purposes. The HBM ESD threshold presented here was obtained by using these circuit parameters: HBM ESD Threshold Voltage Device Rating T8502 >2000 T8503 >2000
Electrical Characteristics
Specifications apply for TA = -40 C to +85 C, VDD = 5 V 5%, MCLK = either 2.048 MHz or 4.096 MHz, and GND = 0 V, unless otherwise noted.
dc Characteristics
Table 2. Digital Interface Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Current, Pins 9, 12 Input Current, Pins 7, 8, 13, 14, 15 Input Current, Pins 5, 16 Output Current in High-impedance State Input Capacitance Symbol VIL VIH VOL VOH II II II IOZ CI Test Conditions All digital inputs All digital inputs DX, IL = 3.2 mA DX, IL = -3.2 mA DX, IL = -320 A GNDD < VIN < VDD GNDD < VIN < VDD GNDD < VIN < VDD DX -- Min -- 2.0 -- 2.4 3.5 -10 2 -120 -30 -- Typ -- -- -- -- -- -- -- -- <2 -- Max 0.8 -- 0.4 -- -- 10 150 -2 30 5 Unit V V V V V A A A A pF
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Lucent Technologies Inc.
Data Sheet July 1998
T8502 and T8503 Dual PCM Codecs with Filters
Electrical Characteristics (continued)
dc Characteristics (continued)
Table 3. Power Dissipation Power measurements are made at MCLK = 4.096 MHz with outputs unloaded and ASEL and GS[1:0] not connected. Clock and frame sync levels are +5 V and 0 V. Channels Parameter Operational 0 Standby Current 1 Partial Standby Current Symbol IDDS IDDP Test Conditions MCLK present; FSX[1:0] = FSR[1:0] = 0 V MCLK present; FS pulses present for one channel, FSX = FSR = 0 V for other channel MCLK, FS pulses present Min -- -- Typ 5 10 Max 8 16 Unit mA mA
2
Powerup Current
IDD1
--
16
23
mA
Transmission Characteristics
Table 4. Analog Interface Parameter Input Resistance, VFXIN Input Leakage Current, VFXIN dc Open-loop Voltage Gain, GSX Open-loop Unity Gain Bandwidth, GSX Load Capacitance, GSX Load Resistance, GSX Input Voltage, VFXIN Load Resistance, VFRO Load Capacitance, VFRO Output Resistance, VFRO Symbol RVFXI IBVFXI AVOL fO CLX1 RLX1 VIX RLVFRO CLVFRO ROVFRO Test Conditions 0.25 V < VFXI < 4.75 V 0.25 V < VFXI < 4.75 V -- -- -- -- Relative to ground -- -- 0 dBm0, 1020 Hz PCM code applied to DR Standby mode FSX = FSR = 0 V for channel under test VOR Alternating zero -law PCM code applied to DR VORPD Standby mode FSX = FSR = 0 V for channel under test, no load VSWR RL = 2000 Min Typ 1.0 60 -- 0.04 5000 -- 1 3 -- -- 10 -- 2.25 2.35 2000 -- -- -- -- -- 3000 -- Max -- 2.4 -- -- 50 -- 2.5 -- 100 20 10000 2.5 2.65 -- Unit M A -- MHz pF k V pF V V Vp-p
Output Voltage, VFRO Output Voltage, VFRO, Standby Output Voltage Swing, VFRO
2.25 2.38 2.0 3.2 2.35 --
Lucent Technologies Inc.
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T8502 and T8503 Dual PCM Codecs with Filters
Data Sheet July 1998
Transmission Characteristics (continued)
ac Transmission Characteristics
Unless otherwise noted, the analog input is a 0 dBm0, 1020 Hz sine wave; the input amplifier is set for unity gain. The digital input is a PCM bit stream equivalent to that obtained by passing a 0 dBm0, 1020 Hz sine wave through an ideal encoder. The output level is sin(x)/x-corrected. Table 5. Absolute Gain Parameter Encoder Milliwatt Response (transmit gain tolerance) Decoder Milliwatt Response (receive gain tolerance) Relative Decoder Gain Variation Referenced to DmW Table 6. Gain Tracking Parameter Transmit Gain Tracking Error Sinusoidal Input -Law/A-Law Receive Gain Tracking Error Sinusoidal Input -Law/A-Law Table 7. Distortion Parameter Transmit Signal to Distortion Symbol SDX Test Conditions -law 3 dBm0 VFXI -30 dBm0 A-law 3 dBm0 VFXI -30 dBm0 -law -30 dBm0 VFXI -40 dBm0 A-law -30 dBm0 VFXI -40 dBm0 -law -40 dBm0 VFXI -45 dBm0 A-law -40 dBm0 VFXI -45 dBm0 -law 3 dBm0 VFRO -30 dBm0 A-law 3 dBm0 VFRO -30 dBm0 -law -30 dBm0 VFRO -40 dBm0 A-law -30 dBm0 VFRO -40 dBm0 -law -40 dBm0 VFRO -45 dBm0 A-law -40 dBm0 VFRO -45 dBm0 200 Hz--3400 Hz, 0 dBm0 input, output any other single frequency 3400 Hz 200 Hz--3400 Hz, 0 dBm0 input, output any other single frequency 3400 Hz Transmit or receive, two frequencies in the range (300 Hz--3400 Hz) at -6 dBm0 Min 36 35 30 29 25 25 36 35 30 29 25 25 -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max Unit -- dB -- dB -- dB -- dB -- dB -- dB -- dB -- dB -- dB -- dB -- dB -- dB -38 dBm0 Symbol GTX GTR Test Conditions +3 dBm0 to -37 dBm0 -37 dBm0 to -50 dBm0 +3 dBm0 to -37 dBm0 -37 dBm0 to -50 dBm0 Min -0.25 -0.50 -0.25 -0.50 Typ -- -- -- -- Max 0.25 0.50 0.25 0.50 Unit dB dB dB dB Symbol EmW Test Conditions Min Typ Max Signal input of 0.775 Vrms, 0 C to 85 C -0.20 -- 0.20 -law or A-law -40 C to +85 C -0.25 -- 0.25 Measured relative to 0 C to 85 C -0.20 0.775 Vrms -law or A-law, -40 C to +85 C -0.25 PCM input of 0 dBm0 1020 Hz, RL = 10 k Decoder gain at -3.5 dB -40 C to +85 C -0.15 (GS = 0) -- -- -- 0.20 0.25 0.15 Unit dBm0 dBm0 dBm0 dBm0 dB
DmW
RGR
Receive Signal to Distortion
SDR
Single Frequency Distortion, Transmit Single Frequency Distortion, Receive Intermodulation Distortion
SFDX
SFDR
--
--
-40
dBm0
IMD
--
--
-42
dBm0
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Lucent Technologies Inc.
Data Sheet July 1998
T8502 and T8503 Dual PCM Codecs with Filters
Transmission Characteristics (continued)
ac Transmission Characteristics (continued)
Table 8. Envelope Delay Distortion Parameter TX Delay, Absolute TX Delay, Relative to 1600 Hz Symbol DXA DXR Test Conditions f = 1600 Hz f = 500 Hz--600 Hz f = 600 Hz--800 Hz f = 800 Hz--1000 Hz f = 1000 Hz--1600 Hz f = 1600 Hz--2600 Hz f = 2600 Hz--2800 Hz f = 2800 Hz--3000 Hz f = 1600 Hz f = 500 Hz--1000 Hz f = 1000 Hz--1600 Hz f = 1600 Hz--2600 Hz f = 2600 Hz--2800 Hz f = 2800 Hz--3000 Hz Any time slot/channel to any time slot/channel f = 1600 Hz Min -- -- -- -- -- -- -- -- -- -40 -30 -- -- -- -- Typ 280 -- -- -- -- -- -- -- 190 -- -- -- -- -- 470 Max 300 220 145 75 40 75 105 155 200 -- -- 90 125 175 600 Unit s s s s s s s s s s s s s s s
RX Delay, Absolute RX Delay, Relative to 1600 Hz
DRA DRR
Round-trip Delay, Absolute
DRTA
Overload Compression Figure 4 shows the region of operation for encoder signal levels above the reference input power (0 dBm0).
9 8
FUNDAMENTAL OUTPUT POWER (dBm)
7
6
5 ACCEPTABLE REGION 4
3
2
1
1
2
3
4
5
6
7
8
9
FUNDAMENTAL INPUT POWER (dBm)
5-3586C
Figure 4. Overload Compression
Lucent Technologies Inc.
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T8502 and T8503 Dual PCM Codecs with Filters
Data Sheet July 1998
Transmission Characteristics (continued)
ac Transmission Characteristics (continued)
Table 9. Noise Parameter Transmit Noise, -Law Transmit Noise, A-Law Receive Noise, -Law Receive Noise, A-Law Noise, Single Frequency, f = 0 kHz--100 kHz Power Supply Rejection Transmit Symbol NXC NXP NRC NRP NRS PSRX Test Conditions -- Input amplifier gain = 20 dB -- PCM code is alternating positive and negative zero PCM code is A-law positive one VFXIN = 0 Vrms, measurement at VFRO, DR = DX VDD = 5.0 Vdc + 100 mVrms: f = 0 kHz--4 kHz f = 4 kHz--50 kHz PCM code is positive one LSB VDD = 5.0 Vdc + 100 mVrms: f = 0 kHz--4 kHz f = 4 kHz--25 kHz f = 25 kHz--50 kHz 0 dBm0, 300 Hz--3400 Hz input PCM code applied: 4600 Hz--7600 Hz 7600 Hz--8400 Hz 8400 Hz--50 kHz Min -- -- -- -- -- -- Typ -- -- -- -- -- -- Max 18 19 -68 13 -75 -53 Unit dBrnC0 dBrnC0 dBm0p dBrnC0 dBm0p dBm0
36 30
-- --
-- --
dB dB
Power Supply Rejection Receive
PSRX
36 40 30
-- -- --
-- -- --
dB dB dB
Spurious Out-of-band Signals at VFRO Relative to Input
SOS
-- -- --
-- -- --
-30 -40 -30
dB dB dB
Table 10. Receive Gain Relative to Gain at 1.02 kHz Frequency (Hz) Below 3000 3140 3380 3860 4600 and above Min -0.150 -0.570 -0.735 -- -- Typ 0.04 0.04 -0.58 -10.7 -- Max 0.150 0.150 0.010 -9.4 -28 Unit dB dB dB dB dB
Table 11. Transmit Gain Relative to Gain at 1.02 kHz Frequency (Hz) 16.67 40 50 60 200 300 to 3000 3140 3380 3860 4600 and above 8 Min -- -- -- -- -1.8 -0.150 -0.570 -0.735 -- -- Typ -35 -34 -36 -50 -0.5 0.04 0.04 -0.58 -10.7 -- Max -30 -26 -30 -30 0 0.150 0.150 0.010 -9.4 -32 Unit dB dB dB dB dB dB dB dB dB dB Lucent Technologies Inc.
Data Sheet July 1998
T8502 and T8503 Dual PCM Codecs with Filters
Transmission Characteristics (continued)
ac Transmission Characteristics (continued)
Table 12. Interchannel Crosstalk (Between Channels) RF = 200 k (See Note.) Parameter Symbol Transmit to Receive CTXX-RY Crosstalk 0 dBm0 Transmit Levels Receive to Transmit CTRX-XY Crosstalk 0 dBm0 Receive Levels Transmit to TransCTXX-XY mit Crosstalk 0 dBm0 Transmit Levels Receive to Receive CTRX-RY Crosstalk 0 dBm0 Receive Levels Test Conditions f = 300 Hz--3400 Hz idle PCM code for channel under test; 0 dBm0 into other channel VFXIN f = 300 Hz--3400 Hz VFXIN = 0 Vrms for channel under test; 0 dBm0 code level on other channel DR f = 300 Hz--3400 Hz VFXIN = 0 Vrms for channel under test; 0 dBm0 into other channel VFXIN f = 300 Hz--3400 Hz idle PCM code for channel under test; 0 dBm0 code level on other channel DR Min -- Typ -100 Max -77 Unit dB
--
-92
-77
dB
--
-90
-77
dB
--
-102
-77
dB
Table 13. Intrachannel Crosstalk (Within Channels) RF = 200 k (See Note.) Parameter Symbol Transmit to Receive CTXX-RX Crosstalk 0 dBm0 Transmit Levels Receive to Transmit CTRX-XX Crosstalk 0 dBm0 Receive Levels Test Conditions f = 300 Hz--3400 Hz idle PCM code for channel under test; 0 dBm0 into VFXIN f = 300 Hz--3400 Hz VFXIN = 0 Vrms for channel under test; 0 dBm0 code level on DR Min -- Typ -80 Max -70 Unit dB
--
-88
-70
dB
Note: For Tables 12 and 13, crosstalk into the transmit channels (VFXIN) can be significantly affected by parasitic capacitive feeds from GSX and VFRO outputs. PWB layouts should be arranged to keep these parasitics low. The resistor value of RF (from GSX to VFXIN) should also be kept as low as possible (while maintaining the load on GSX above 10 k, per Table 4) to minimize crosstalk.
Lucent Technologies Inc.
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T8502 and T8503 Dual PCM Codecs with Filters
Data Sheet July 1998
Timing Characteristics
Table 14. Clock Section (See Figures 5 and 6.) Symbol Parameter tMCHMCL1 Clock Pulse Width tMCH1MCH2 Clock Rise and tMCL2MCL1 Fall Time Test Conditions -- -- Min 97 0 Typ -- -- Max -- 15 Unit ns ns
Table 15. T8502 Transmit Section (See Figure 5.) Symbol tMCHDV tMCHDV1 tMCLDZ* tFSHMCL tMCLFSH tFSLMCL tFSHFSL Parameter Data Enabled on TS Entry Data Delay from MC Data Float on TS Exit Frame-sync Hold Time Frame-sync High Setup Frame-sync Low Setup Frame-sync Pulse Width Test Conditions 0 < CLOAD < 100 pF 0 < CLOAD < 100 pF CLOAD = 0 -- -- -- -- Min 0 0 10 50 50 50 0.1 Typ -- -- -- -- -- -- -- Max 60 60 100 -- -- -- 125 - tMCHMCH Unit ns ns ns ns ns ns s
* Timing parameter tMCLDZ is referenced to a high-impedance state.
Table 16. T8503 Transmit Section (See Figure 6.) Symbol tFSHDV tMCHDV1 tMCHDZ* tFSHMCL tMCLFSH tFSLMCL tFSHFSL Parameter Data Enabled on TS Entry Data Delay from FSX Data Float on TS Exit Frame-sync Hold Time Frame-sync High Setup Frame-sync Low Setup Frame-sync Pulse Width Test Conditions 0 < CLOAD < 100 pF 0 < CLOAD < 100 pF CLOAD = 0 -- -- -- -- Min 0 0 0 50 50 50 0.1 Typ -- -- -- -- -- -- -- Max 80 60 30 -- -- -- 125 - tMCHMCH Unit ns ns ns ns ns ns s
* Timing parameter tMCHDZ is referenced to a high-impedance state.
Table 17. T8502 and T8503 Receive Section (See Figures 5 and 6.) Symbol tDVMCL tMCLDV Parameter Receive Data Setup Receive Data Hold Test Conditions -- -- Min 30 15 Typ -- -- Max -- -- Unit ns ns
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Lucent Technologies Inc.
Data Sheet July 1998
T8502 and T8503 Dual PCM Codecs with Filters
Timing Characteristics (continued)
TIME SLOT tMCHMCL1 MCLK tMCLFS H tFSHMCL FSXN 1 2 tMCH1MCH2 tFSLMCL 3 4 5 tMCL2MCL1 6 tFSLMCL 7 8 1
tFSHFSL tMCHDV Dx BIT 1 tMCHDV1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 tMCLDZ BIT 7 BIT 8
FSR N
tDV MCL DR BIT 1 BIT 2 DR STA BLE BIT 3 BIT 4 BIT 5
tMCLDV BIT 6 BIT 7 BIT 8
5-3581.I(C)
Note: FSX and FSR do not need to be coincident.
Figure 5. T8502 Transmit and Receive Timing
TIME SLOT tMCHMCL1 MCLK tMCLFSH tFSHMCL FSXN tMCH1MCH2 2 3 tFSLMCL 4 5 tMCL2MCL1 6 tFSLMCL 7 8 1
1
tFSHFSL tFSHDV DX BIT 1 tMCHDV1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 tMCHDZ BIT 7 BIT 8
FSRN
tDVMCL DR BIT 1 BIT 2 DR STABLE BIT 3 BIT 4 BIT 5
tMCLDV BIT 6 BIT 7 BIT 8
5-3581.R(C)
Note: FSX and FSR do not need to be coincident.
Figure 6. T8503 Transmit and Receive Timing
Lucent Technologies Inc.
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T8502 and T8503 Dual PCM Codecs with Filters
Data Sheet July 1998
Applications
RF
GSXn
ZT2 VTR 0.1 F VFXINn
SLIC
0.1 F ACIN RG
ZT1 ZRCV
ZHB
T8502 T8503
VFROn
5-3584.d
Figure 7. Typical T8502 and T8503/SLIC Interconnection
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Lucent Technologies Inc.
Data Sheet July 1998
T8502 and T8503 Dual PCM Codecs with Filters
Outline Diagrams
20-Pin SOJ
Dimensions are in millimeters.
L N
B
1 PIN #1 IDENTIFIER ZONE W
H SEATING PLANE 0.10 1.27 TYP 0.51 MAX 0.79 MAX
Number of Pins (N) 20
Maximum Length (L) 12.95
Maximum Width Without Leads (B) 7.62
Maximum Width Including Leads (W) 8.81
Maximum Height Above Board (H) 3.18
5-4413 (C)r4
Lucent Technologies Inc.
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T8502 and T8503 Dual PCM Codecs with Filters
Data Sheet July 1998
Outline Diagrams (continued)
20-Pin SOG
Dimensions are in millimeters.
L N
B
1 PIN #1 IDENTIFIER ZONE W
H SEATING PLANE 0.10 1.27 TYP 0.51 MAX 0.61 0.28 MAX
Number of Pins (N) 20
Maximum Length (L) 13.00
Maximum Width Without Leads (B) 7.62
Maximum Width Including Leads (W) 10.64
Maximum Height Above Board (H) 2.67
5-4414 (C)r.4
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Lucent Technologies Inc.
Data Sheet July 1998
T8502 and T8503 Dual PCM Codecs with Filters
Ordering Information
Device Part No. T-8502 - - EL2-D T-8502 - - EL2-DT T-8502 - - GL2-D T-8502 - - GL2-DT T-8503 - - EL2-D T-8503 - - EL2-DT T-8503 - - GL2-D T-8503 - - GL2-DT Package 20-Pin SOJ 20-Pin SOJ Tape & Reel 20-Pin SOG 20-Pin SOG Tape & Reel 20-Pin SOJ 20-Pin SOJ Tape & Reel 20-Pin SOG 20-Pin SOG Tape & Reel Temperature -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C Comcode 108295908 108295916 108295924 108295932 108295940 108295957 108295965 108295973
Note: All parts are shipped in dry bag.
Lucent Technologies Inc.
15
For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P. R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1189 324 299, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Bracknell), FRANCE: (33) 1 48 83 68 00 (Paris), SWEDEN: (46) 8 600 7070 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), ITALY: (39) 2 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information.
Copyright (c) 1998 Lucent Technologies Inc. All Rights Reserved
July 1998 DS98-342ALC (Replaces DS97-205ALC)

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